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authorJustin Chen <justin.chen@broadcom.com>2023-08-21 21:52:51 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2023-08-22 16:30:59 +0300
commit42a569cd0d774fd575395a84481f87a1aaa530df (patch)
treedfca86006a45ac3a8b007bca8e8af0971bac24ce /include
parentb4a778303ea0fcabcaff974721477a5743e1f8ec (diff)
downloadlinux-42a569cd0d774fd575395a84481f87a1aaa530df.tar.xz
serial: 8250_bcm7271: improve bcm7271 8250 port
The 8250 BCM7271 UART is not a direct match to PORT_16550A and other generic ports do not match its hardware capabilities. PORT_ALTR matches the rx trigger levels, but its vendor configurations are not compatible. Unfortunately this means we need to create another port to fully capture the hardware capabilities of the BCM7271 UART. To alleviate some latency pressures, we default the rx trigger level to 8. Signed-off-by: Justin Chen <justin.chen@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Acked-by: Doug Berger <opendmb@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/1692643978-16570-1-git-send-email-justin.chen@broadcom.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include')
-rw-r--r--include/uapi/linux/serial_core.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index d19dabd2c20d..add349889d0a 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -123,6 +123,9 @@
/* Xilinx uartlite */
#define PORT_UARTLITE 74
+/* Broadcom BCM7271 UART */
+#define PORT_BCM7271 76
+
/* Broadcom SB1250, etc. SOC */
#define PORT_SB1250_DUART 77