summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorZhenyu Wang <zhenyuw@linux.intel.com>2010-08-27 07:08:57 +0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-07 14:16:43 +0400
commitf8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337 (patch)
tree9211554f0542ce636aa1f14ffe58cfa832efa04d /include
parent93f5f7f1249e76a5e8afbdab53f90b10c41fdb61 (diff)
downloadlinux-f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337.tar.xz
agp/intel: Fix cache control for Sandybridge
Sandybridge GTT has new cache control bits in PTE, which controls graphics page cache in LLC or LLC/MLC, so we need to extend the mask function to respect the new bits. And set cache control to always LLC only by default on Gen6. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'include')
-rw-r--r--include/linux/intel-gtt.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/include/linux/intel-gtt.h b/include/linux/intel-gtt.h
new file mode 100644
index 000000000000..1d19ab2afa39
--- /dev/null
+++ b/include/linux/intel-gtt.h
@@ -0,0 +1,20 @@
+/*
+ * Common Intel AGPGART and GTT definitions.
+ */
+#ifndef _INTEL_GTT_H
+#define _INTEL_GTT_H
+
+#include <linux/agp_backend.h>
+
+/* This is for Intel only GTT controls.
+ *
+ * Sandybridge: AGP_USER_CACHED_MEMORY default to LLC only
+ */
+
+#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2)
+#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4)
+
+/* flag for GFDT type */
+#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
+
+#endif