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author | Palmer Dabbelt <palmer@rivosinc.com> | 2024-03-12 17:13:21 +0300 |
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committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-03-15 20:17:13 +0300 |
commit | 0fd283cb64c0ac526a71fe10bf6e164f4f472ff2 (patch) | |
tree | 2930c5fa6fcc591026f0aa41e555c5084f57929d /mm/pgalloc-track.h | |
parent | 3b6be8d235752c809f74ffd9ea38f1590a985ea3 (diff) | |
parent | f5102e31c209798cafd2d79463f5093771aadc12 (diff) | |
download | linux-0fd283cb64c0ac526a71fe10bf6e164f4f472ff2.tar.xz |
Merge patch series "Support Andes PMU extension"
Yu Chien Peter Lin <peterlin@andestech.com> says:
This patch series introduces the Andes PMU extension, which serves the
same purpose as Sscofpmf and Smcntrpmf. Its non-standard local interrupt
is assigned to bit 18 in the custom S-mode local interrupt enable and
pending registers (slie/slip), while the interrupt cause is (256 + 18).
* b4-shazam-merge:
riscv: andes: Support specifying symbolic firmware and hardware raw events
riscv: dts: renesas: Add Andes PMU extension for r9a07g043f
dt-bindings: riscv: Add Andes PMU extension description
perf: RISC-V: Introduce Andes PMU to support perf event sampling
perf: RISC-V: Eliminate redundant interrupt enable/disable operations
riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC
dt-bindings: riscv: Add Andes interrupt controller compatible string
riscv: errata: Rename defines for Andes
Link: https://lore.kernel.org/r/20240222083946.3977135-1-peterlin@andestech.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'mm/pgalloc-track.h')
0 files changed, 0 insertions, 0 deletions