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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2024-04-24 04:39:32 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-04-27 21:14:56 +0300 |
| commit | 615a292ee4d51303246278f3fa33cc38700fe00e (patch) | |
| tree | 5bf268ed779da5fe5ed1ff9a4bcb18fb4a82bb3c /net/mac80211/tkip.h | |
| parent | e90b5139da8465a15c3820b4b67ca9468dce93b4 (diff) | |
| download | linux-615a292ee4d51303246278f3fa33cc38700fe00e.tar.xz | |
clk: qcom: dispcc-sm8650: fix DisplayPort clocks
On SM8650 DisplayPort link clocks use frequency tables inherited from
the vendor kernel, it is not applicable in the upstream kernel. Drop
frequency tables and use clk_byte2_ops for those clocks.
This fixes frequency selection in the OPP core (which otherwise attempts
to use invalid 810 KHz as DP link rate), also fixing the following
message:
msm-dp-display af54000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22
Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240424-dispcc-dp-clocks-v2-4-b44038f3fa96@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'net/mac80211/tkip.h')
0 files changed, 0 insertions, 0 deletions