diff options
author | Charles Keepax <ckeepax@opensource.wolfsonmicro.com> | 2017-04-18 20:32:52 +0300 |
---|---|---|
committer | Mark Brown <broonie@kernel.org> | 2017-04-18 20:59:18 +0300 |
commit | fbeea237af65c6dceca00886aba30839bc986fd7 (patch) | |
tree | 49a8b5ac6bf4c10ba5304e8bc815b8fc0ba55fdd /sound/soc/codecs/cs35l35.c | |
parent | 0c67fb5544061cb990e07a73e1b7ba1f8ca22479 (diff) | |
download | linux-fbeea237af65c6dceca00886aba30839bc986fd7.tar.xz |
ASoC: cs35l35: Correct some register defaults
Correct some minor errors in the register defaults.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Acked-by: Brian Austin <brian.austin@cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/cs35l35.c')
-rw-r--r-- | sound/soc/codecs/cs35l35.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/sound/soc/codecs/cs35l35.c b/sound/soc/codecs/cs35l35.c index 6ecb7ddae9cf..dc6591adc96d 100644 --- a/sound/soc/codecs/cs35l35.c +++ b/sound/soc/codecs/cs35l35.c @@ -50,7 +50,7 @@ static const struct reg_default cs35l35_reg[] = { {CS35L35_PWRCTL2, 0x11}, {CS35L35_PWRCTL3, 0x00}, {CS35L35_CLK_CTL1, 0x04}, - {CS35L35_CLK_CTL2, 0x10}, + {CS35L35_CLK_CTL2, 0x12}, {CS35L35_CLK_CTL3, 0xCF}, {CS35L35_SP_FMT_CTL1, 0x20}, {CS35L35_SP_FMT_CTL2, 0x00}, @@ -70,7 +70,7 @@ static const struct reg_default cs35l35_reg[] = { {CS35L35_BST_RAMP_CTL, 0x85}, {CS35L35_BST_CONV_COEF_1, 0x24}, {CS35L35_BST_CONV_COEF_2, 0x24}, - {CS35L35_BST_CONV_SLOPE_COMP, 0x47}, + {CS35L35_BST_CONV_SLOPE_COMP, 0x4E}, {CS35L35_BST_CONV_SW_FREQ, 0x04}, {CS35L35_CLASS_H_CTL, 0x0B}, {CS35L35_CLASS_H_HEADRM_CTL, 0x0B}, @@ -78,9 +78,9 @@ static const struct reg_default cs35l35_reg[] = { {CS35L35_CLASS_H_FET_DRIVE_CTL, 0x41}, {CS35L35_CLASS_H_VP_CTL, 0xC5}, {CS35L35_VPBR_CTL, 0x0A}, - {CS35L35_VPBR_VOL_CTL, 0x09}, + {CS35L35_VPBR_VOL_CTL, 0x90}, {CS35L35_VPBR_TIMING_CTL, 0x6A}, - {CS35L35_VPBR_MODE_VOL_CTL, 0x40}, + {CS35L35_VPBR_MODE_VOL_CTL, 0x00}, {CS35L35_SPKR_MON_CTL, 0xC0}, {CS35L35_IMON_SCALE_CTL, 0x30}, {CS35L35_AUDIN_RXLOC_CTL, 0x00}, |