diff options
| author | Lucas Tanure <tanureal@opensource.cirrus.com> | 2021-05-25 12:08:19 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@sirena.org.uk> | 2021-05-25 18:45:03 +0300 |
| commit | 1c52825c38fc4e44c61ed75a8ae32f5fa580383b (patch) | |
| tree | afa3df527c85efca7aac5e4f53105ba59d48baf1 /sound/soc/codecs/cs42l42.h | |
| parent | d4e9889b02014a07c8dba3fbbae7205ea4084350 (diff) | |
| download | linux-1c52825c38fc4e44c61ed75a8ae32f5fa580383b.tar.xz | |
ASoC: cs42l42: Fix 1536000 Bit Clock instability
The 16 Bits, 2 channels, 48K sample rate use case needs
to configure a safer pll_divout during the start of PLL
After 800us from the start of PLL the correct pll_divout
can be set
Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com>
Reviewed-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Message-Id: <20210525090822.64577-1-tanureal@opensource.cirrus.com>
Signed-off-by: Mark Brown <broonie@sirena.org.uk>
Diffstat (limited to 'sound/soc/codecs/cs42l42.h')
| -rw-r--r-- | sound/soc/codecs/cs42l42.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sound/soc/codecs/cs42l42.h b/sound/soc/codecs/cs42l42.h index 24f7be228d5f..7bf05ff05f74 100644 --- a/sound/soc/codecs/cs42l42.h +++ b/sound/soc/codecs/cs42l42.h @@ -755,6 +755,7 @@ #define CS42L42_NUM_SUPPLIES 5 #define CS42L42_BOOT_TIME_US 3000 +#define CS42L42_PLL_DIVOUT_TIME_US 800 #define CS42L42_CLOCK_SWITCH_DELAY_US 150 #define CS42L42_PLL_LOCK_POLL_US 250 #define CS42L42_PLL_LOCK_TIMEOUT_US 1250 @@ -777,6 +778,7 @@ struct cs42l42_private { int bclk; u32 sclk; u32 srate; + u8 pll_divout; u8 plug_state; u8 hs_type; u8 ts_inv; |