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authorAxel Lin <axel.lin@gmail.com>2011-10-24 07:32:41 +0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2011-10-24 16:09:42 +0400
commit49fa4d9b5aeafb985abe8cb8cdf6432690c49ad3 (patch)
tree4c3aee893aa2818d83a1ff5f9691b5749b9cb1b9 /sound/soc/codecs/wm8940.c
parent753ddf52153b60be924109df3bebab0cd60b3297 (diff)
downloadlinux-49fa4d9b5aeafb985abe8cb8cdf6432690c49ad3.tar.xz
ASoC: wm8940: Fix setting PLL Output clock division ratio
According to the datasheet: The PLL Output clock division ratio is controlled by BIT[5:4] of WM8940_GPIO register(08h). Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong. Signed-off-by: Axel Lin <axel.lin@gmail.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/codecs/wm8940.c')
-rw-r--r--sound/soc/codecs/wm8940.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c
index a4abfdfb217b..3cc3bce61316 100644
--- a/sound/soc/codecs/wm8940.c
+++ b/sound/soc/codecs/wm8940.c
@@ -627,8 +627,8 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 5));
break;
case WM8940_OPCLKDIV:
- reg = snd_soc_read(codec, WM8940_ADDCNTRL) & 0xFFCF;
- ret = snd_soc_write(codec, WM8940_ADDCNTRL, reg | (div << 4));
+ reg = snd_soc_read(codec, WM8940_GPIO) & 0xFFCF;
+ ret = snd_soc_write(codec, WM8940_GPIO, reg | (div << 4));
break;
}
return ret;