diff options
| author | Mac Chiang <mac.chiang@intel.com> | 2022-01-20 08:40:12 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-01-24 16:31:59 +0300 |
| commit | dbf2f8e3fecd5b2197f406f26fed26042664044e (patch) | |
| tree | 8eb1ebb6ee84c45b379312a34412265ed2d56966 /sound/soc/intel/boards/sof_rt5682.c | |
| parent | 330dc18356e697eaf9796732b6acbdf948022136 (diff) | |
| download | linux-dbf2f8e3fecd5b2197f406f26fed26042664044e.tar.xz | |
ASoC: Intel: sof_rt5682: add 512FS MCLK clock configuration
codec system clock source support 512FS MCLK synchronous directly, so
no need to set PLL configuration when MCLK 24.576MHz.
Suggested-by: Shuming Fan <shumingf@realtek.com>
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20220120054012.15849-1-mac.chiang@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/intel/boards/sof_rt5682.c')
| -rw-r--r-- | sound/soc/intel/boards/sof_rt5682.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/sound/soc/intel/boards/sof_rt5682.c b/sound/soc/intel/boards/sof_rt5682.c index bd6d2e7dea53..f4e833cbffe1 100644 --- a/sound/soc/intel/boards/sof_rt5682.c +++ b/sound/soc/intel/boards/sof_rt5682.c @@ -369,11 +369,16 @@ static int sof_rt5682_hw_params(struct snd_pcm_substream *substream, pll_out = params_rate(params) * 512; - /* Configure pll for codec */ - ret = snd_soc_dai_set_pll(codec_dai, pll_id, pll_source, pll_in, - pll_out); - if (ret < 0) - dev_err(rtd->dev, "snd_soc_dai_set_pll err = %d\n", ret); + /* when MCLK is 512FS, no need to set PLL configuration additionally. */ + if (pll_in == pll_out) + clk_id = RT5682S_SCLK_S_MCLK; + else { + /* Configure pll for codec */ + ret = snd_soc_dai_set_pll(codec_dai, pll_id, pll_source, pll_in, + pll_out); + if (ret < 0) + dev_err(rtd->dev, "snd_soc_dai_set_pll err = %d\n", ret); + } /* Configure sysclk for codec */ ret = snd_soc_dai_set_sysclk(codec_dai, clk_id, |