diff options
| author | Sanyog Kale <sanyog.r.kale@intel.com> | 2018-03-13 06:32:25 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2018-03-13 19:29:14 +0300 |
| commit | fc9fdd61c4809b14faa9b84fe3d8f4167a836326 (patch) | |
| tree | 3b8c4b6397fc855bbf420b2785393865c0b65c0f /sound/soc/intel/skylake/skl.h | |
| parent | c22969d70fc9253112e88da55116e04074cdeac4 (diff) | |
| download | linux-fc9fdd61c4809b14faa9b84fe3d8f4167a836326.tar.xz | |
ASoC: Intel: Skylake: Disable clock and power gating during FW/LIB download
In order to achieve better DMA performance and reduce download time for
firmware and library, it is recommended to disable dynamic clock and
power gating. In some scenarios, DMA may wait to accumulate more data and
last chunk of data never gets completed if dynamic clock and power
gating is kept enabled.
This patch adds support to disable/enable dynamic clock and power gating
and use it during firmware and library download.
Signed-off-by: Rakesh Ughreja <rakesh.a.ughreja@intel.com>
Signed-off-by: Sanyog Kale <sanyog.r.kale@intel.com>
Signed-off-by: Guneshwor Singh <guneshwor.o.singh@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/intel/skylake/skl.h')
| -rw-r--r-- | sound/soc/intel/skylake/skl.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/sound/soc/intel/skylake/skl.h b/sound/soc/intel/skylake/skl.h index ca46ad1d0a08..0d5375cbcf6e 100644 --- a/sound/soc/intel/skylake/skl.h +++ b/sound/soc/intel/skylake/skl.h @@ -33,8 +33,10 @@ #define AZX_PCIREG_PGCTL 0x44 #define AZX_PGCTL_LSRMD_MASK (1 << 4) +#define AZX_PGCTL_ADSPPGD BIT(2) #define AZX_PCIREG_CGCTL 0x48 #define AZX_CGCTL_MISCBDCGE_MASK (1 << 6) +#define AZX_CGCTL_ADSPDCGE BIT(1) /* D0I3C Register fields */ #define AZX_REG_VS_D0I3C_CIP 0x1 /* Command in progress */ #define AZX_REG_VS_D0I3C_I3 0x4 /* D0i3 enable */ @@ -43,6 +45,8 @@ #define DMA_TRANSMITION_START 2 #define DMA_TRANSMITION_STOP 3 +#define AZX_REG_VS_EM2_L1SEN BIT(13) + struct skl_dsp_resource { u32 max_mcps; u32 max_mem; |