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authorSugar Zhang <sugar.zhang@rock-chips.com>2021-08-26 07:01:48 +0300
committerMark Brown <broonie@kernel.org>2021-08-26 15:59:31 +0300
commit6b76bcc004b046ea3c8eb66bbc6954f1d23cc2af (patch)
treee456bf342072a723076a8b77880a3c2281fbd217 /sound
parentebfea67125767a779af63ae6de176709713c8826 (diff)
downloadlinux-6b76bcc004b046ea3c8eb66bbc6954f1d23cc2af.tar.xz
ASoC: rockchip: i2s: Fixup clk div error
MCLK maybe not precise as required because of PLL, but which still can be used and no side effect. so, using DIV_ROUND_CLOSEST instead div. e.g. set mclk to 11289600 Hz, but get 11289598 Hz. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Link: https://lore.kernel.org/r/1629950520-14190-2-git-send-email-sugar.zhang@rock-chips.com Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/rockchip/rockchip_i2s.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c
index c9d5c524af6c..05fce2c61f1a 100644
--- a/sound/soc/rockchip/rockchip_i2s.c
+++ b/sound/soc/rockchip/rockchip_i2s.c
@@ -280,10 +280,10 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
if (i2s->is_master_mode) {
mclk_rate = clk_get_rate(i2s->mclk);
bclk_rate = i2s->bclk_ratio * params_rate(params);
- if (bclk_rate == 0 || mclk_rate % bclk_rate)
+ if (!bclk_rate)
return -EINVAL;
- div_bclk = mclk_rate / bclk_rate;
+ div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
div_lrck = bclk_rate / params_rate(params);
regmap_update_bits(i2s->regmap, I2S_CKR,
I2S_CKR_MDIV_MASK,