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| author | Dan Williams <dan.j.williams@intel.com> | 2022-05-19 02:34:48 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-05-19 18:50:41 +0300 |
| commit | 14d78874077442d1d0f08129f5a0ea5070984b4b (patch) | |
| tree | 4c80ac1f7f8fb934b3a430fdcdacee9d40e47f05 /tools/testing/cxl/test/mem.c | |
| parent | 2e4ba0ec978335b4b550bbed95cb198ac3a00745 (diff) | |
| download | linux-14d78874077442d1d0f08129f5a0ea5070984b4b.tar.xz | |
cxl/mem: Consolidate CXL DVSEC Range enumeration in the core
In preparation for fixing the setting of the 'mem_enabled' bit in CXL
DVSEC Control register, move all CXL DVSEC range enumeration into the
same source file.
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165291688886.1426646.15046138604010482084.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/testing/cxl/test/mem.c')
| -rw-r--r-- | tools/testing/cxl/test/mem.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c index c519ace17b41..6b9239b2afd4 100644 --- a/tools/testing/cxl/test/mem.c +++ b/tools/testing/cxl/test/mem.c @@ -242,14 +242,6 @@ static void label_area_release(void *lsa) vfree(lsa); } -static void mock_validate_dvsec_ranges(struct cxl_dev_state *cxlds) -{ - struct cxl_endpoint_dvsec_info *info; - - info = &cxlds->info; - info->mem_enabled = true; -} - static int cxl_mock_mem_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -286,8 +278,6 @@ static int cxl_mock_mem_probe(struct platform_device *pdev) if (rc) return rc; - mock_validate_dvsec_ranges(cxlds); - cxlmd = devm_cxl_add_memdev(cxlds); if (IS_ERR(cxlmd)) return PTR_ERR(cxlmd); |