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| author | Haibo Xu <haibo1.xu@intel.com> | 2024-01-22 12:58:42 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2024-03-06 18:23:29 +0300 |
| commit | d0b94bcbb04262b9ffe6e172223e8cbb663a2c9d (patch) | |
| tree | 7779a0ba757871823641275e7d742b19bdb52b88 /tools/testing/selftests/kvm/include/riscv/processor.h | |
| parent | 812806bd1e70f79cc69061f9fd9bb1d367990d37 (diff) | |
| download | linux-d0b94bcbb04262b9ffe6e172223e8cbb663a2c9d.tar.xz | |
KVM: riscv: selftests: Add sstc timer test
Add a KVM selftests to validate the Sstc timer functionality.
The test was ported from arm64 arch timer test.
Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'tools/testing/selftests/kvm/include/riscv/processor.h')
| -rw-r--r-- | tools/testing/selftests/kvm/include/riscv/processor.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h index 1b0a9e9d2d30..ce473fe251dd 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -193,4 +193,14 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, bool guest_sbi_probe_extension(int extid, long *out_val); +static inline void local_irq_enable(void) +{ + csr_set(CSR_SSTATUS, SR_SIE); +} + +static inline void local_irq_disable(void) +{ + csr_clear(CSR_SSTATUS, SR_SIE); +} + #endif /* SELFTEST_KVM_PROCESSOR_H */ |