summaryrefslogtreecommitdiff
path: root/tools
diff options
context:
space:
mode:
authorZhang Rui <rui.zhang@intel.com>2023-08-27 10:33:27 +0300
committerZhang Rui <rui.zhang@intel.com>2023-09-27 17:14:21 +0300
commit05ad96ff0fb9d1b16abb5022b9c62636c6780fc2 (patch)
treedcfd26e468fb9f04e7196a3bba3628902924f7e1 /tools
parent7ee39d8d593e3d28eced0fa1a8c8c6bdcbd4156e (diff)
downloadlinux-05ad96ff0fb9d1b16abb5022b9c62636c6780fc2.tar.xz
tools/power/turbostat: Enable MSR_CORE_C1_RES on recent Intel client platforms
All recent Intel client platforms have MSR_CORE_C1_RES. Enable the support on these platforms, including CNL/ICL/LKF/RKL/TGL/ADL/RPL/MTL. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'tools')
-rw-r--r--tools/power/x86/turbostat/turbostat.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index 607152b36c1a..9895f348b637 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -604,6 +604,7 @@ static const struct platform_features cnl_features = {
.supported_cstates = CC1 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7 | PC8 | PC9 | PC10,
.cst_limit = CST_LIMIT_HSW,
.has_irtl_msrs = 1,
+ .has_msr_core_c1_res = 1,
.has_ext_cst_msrs = 1,
.trl_msrs = TRL_BASE,
.tcc_offset_bits = 6,