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-rw-r--r--Documentation/devicetree/bindings/dma/altr,msgdma.yaml61
-rw-r--r--Documentation/devicetree/bindings/dma/arm-pl08x.txt59
-rw-r--r--Documentation/devicetree/bindings/dma/arm-pl08x.yaml136
-rw-r--r--Documentation/devicetree/bindings/dma/qcom,gpi.yaml1
-rw-r--r--Documentation/devicetree/bindings/dma/renesas,shdma.txt84
-rw-r--r--MAINTAINERS8
-rw-r--r--drivers/dma/altera-msgdma.c20
-rw-r--r--drivers/dma/fsl-qdma.c6
-rw-r--r--drivers/dma/hsu/hsu.c3
-rw-r--r--drivers/dma/idxd/cdev.c2
-rw-r--r--drivers/dma/idxd/init.c3
-rw-r--r--drivers/dma/imx-sdma.c56
-rw-r--r--drivers/dma/qcom/gpi.c1
-rw-r--r--drivers/dma/sf-pdma/sf-pdma.c5
-rw-r--r--drivers/dma/sh/Makefile2
-rw-r--r--drivers/dma/sh/shdma-of.c76
-rw-r--r--drivers/dma/sun4i-dma.c5
-rw-r--r--drivers/dma/ti/omap-dma.c3
-rw-r--r--drivers/dma/xilinx/xilinx_dpdma.c44
-rw-r--r--include/linux/dmaengine.h11
-rw-r--r--include/linux/platform_data/dma-imx-sdma.h60
21 files changed, 333 insertions, 313 deletions
diff --git a/Documentation/devicetree/bindings/dma/altr,msgdma.yaml b/Documentation/devicetree/bindings/dma/altr,msgdma.yaml
new file mode 100644
index 000000000000..a4f9fe23dcd9
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/altr,msgdma.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/altr,msgdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera mSGDMA IP core
+
+maintainers:
+ - Olivier Dautricourt <olivier.dautricourt@orolia.com>
+
+description: |
+ Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)
+ intellectual property (IP)
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+ const: altr,socfpga-msgdma
+
+ reg:
+ items:
+ - description: Control and Status Register Slave Port
+ - description: Descriptor Slave Port
+ - description: Response Slave Port
+
+ reg-names:
+ items:
+ - const: csr
+ - const: desc
+ - const: resp
+
+ interrupts:
+ maxItems: 1
+
+ "#dma-cells":
+ const: 1
+ description:
+ The cell identifies the channel id (must be 0)
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ msgdma_controller: dma-controller@ff200b00 {
+ compatible = "altr,socfpga-msgdma";
+ reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>;
+ reg-names = "csr", "desc", "resp";
+ interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/dma/arm-pl08x.txt b/Documentation/devicetree/bindings/dma/arm-pl08x.txt
deleted file mode 100644
index 0ba81f79266f..000000000000
--- a/Documentation/devicetree/bindings/dma/arm-pl08x.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-* ARM PrimeCells PL080 and PL081 and derivatives DMA controller
-
-Required properties:
-- compatible: "arm,pl080", "arm,primecell";
- "arm,pl081", "arm,primecell";
- "faraday,ftdmac020", "arm,primecell"
-- arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded
- in the hardware and must be specified here as <0x0003b080>. This number
- follows the PrimeCell standard numbering using the JEP106 vendor code 0x38
- for Faraday Technology.
-- reg: Address range of the PL08x registers
-- interrupt: The PL08x interrupt number
-- clocks: The clock running the IP core clock
-- clock-names: Must contain "apb_pclk"
-- lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
-- lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
-- mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
-- mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
-- #dma-cells: must be <2>. First cell should contain the DMA request,
- second cell should contain either 1 or 2 depending on
- which AHB master that is used.
-
-Optional properties:
-- dma-channels: contains the total number of DMA channels supported by the DMAC
-- dma-requests: contains the total number of DMA requests supported by the DMAC
-- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32
- 64, 128 or 256 bytes are legal values
-- memcpy-bus-width: the bus width used for memcpy in bits: 8, 16 or 32 are legal
- values, the Faraday FTDMAC020 can also accept 64 bits
-
-Clients
-Required properties:
-- dmas: List of DMA controller phandle, request channel and AHB master id
-- dma-names: Names of the aforementioned requested channels
-
-Example:
-
-dmac0: dma-controller@10130000 {
- compatible = "arm,pl080", "arm,primecell";
- reg = <0x10130000 0x1000>;
- interrupt-parent = <&vica>;
- interrupts = <15>;
- clocks = <&hclkdma0>;
- clock-names = "apb_pclk";
- lli-bus-interface-ahb1;
- lli-bus-interface-ahb2;
- mem-bus-interface-ahb2;
- memcpy-burst-size = <256>;
- memcpy-bus-width = <32>;
- #dma-cells = <2>;
-};
-
-device@40008000 {
- ...
- dmas = <&dmac0 0 2
- &dmac0 1 2>;
- dma-names = "tx", "rx";
- ...
-};
diff --git a/Documentation/devicetree/bindings/dma/arm-pl08x.yaml b/Documentation/devicetree/bindings/dma/arm-pl08x.yaml
new file mode 100644
index 000000000000..3bd9eea543ca
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/arm-pl08x.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM PrimeCells PL080 and PL081 and derivatives DMA controller
+
+maintainers:
+ - Vinod Koul <vkoul@kernel.org>
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+# We need a select here so we don't match all nodes with 'arm,primecell'
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - arm,pl080
+ - arm,pl081
+ required:
+ - compatible
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - arm,pl080
+ - arm,pl081
+ - const: arm,primecell
+ - items:
+ - const: faraday,ftdma020
+ - const: arm,pl080
+ - const: arm,primecell
+
+ reg:
+ maxItems: 1
+ description: Address range of the PL08x registers
+
+ interrupts:
+ minItems: 1
+ description: The PL08x interrupt number
+
+ clocks:
+ minItems: 1
+ description: The clock running the IP core clock
+
+ clock-names:
+ maxItems: 1
+
+ lli-bus-interface-ahb1:
+ type: boolean
+ description: if AHB master 1 is eligible for fetching LLIs
+
+ lli-bus-interface-ahb2:
+ type: boolean
+ description: if AHB master 2 is eligible for fetching LLIs
+
+ mem-bus-interface-ahb1:
+ type: boolean
+ description: if AHB master 1 is eligible for fetching memory contents
+
+ mem-bus-interface-ahb2:
+ type: boolean
+ description: if AHB master 2 is eligible for fetching memory contents
+
+ memcpy-burst-size:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 1
+ - 4
+ - 8
+ - 16
+ - 32
+ - 64
+ - 128
+ - 256
+ description: the size of the bursts for memcpy
+
+ memcpy-bus-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 8
+ - 16
+ - 32
+ - 64
+ description: bus width used for memcpy in bits. FTDMAC020 also accept 64 bits
+
+required:
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - "#dma-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ dmac0: dma-controller@10130000 {
+ compatible = "arm,pl080", "arm,primecell";
+ reg = <0x10130000 0x1000>;
+ interrupt-parent = <&vica>;
+ interrupts = <15>;
+ clocks = <&hclkdma0>;
+ clock-names = "apb_pclk";
+ lli-bus-interface-ahb1;
+ lli-bus-interface-ahb2;
+ mem-bus-interface-ahb2;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ #dma-cells = <2>;
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/reset/cortina,gemini-reset.h>
+ #include <dt-bindings/clock/cortina,gemini-clock.h>
+ dma-controller@67000000 {
+ compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
+ /* Faraday Technology FTDMAC020 variant */
+ arm,primecell-periphid = <0x0003b080>;
+ reg = <0x67000000 0x1000>;
+ interrupts = <9 IRQ_TYPE_EDGE_RISING>;
+ resets = <&syscon GEMINI_RESET_DMAC>;
+ clocks = <&syscon GEMINI_CLK_AHB>;
+ clock-names = "apb_pclk";
+ /* Bus interface AHB1 (AHB0) is totally tilted */
+ lli-bus-interface-ahb2;
+ mem-bus-interface-ahb2;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ #dma-cells = <2>;
+ };
diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
index e302147e53c6..e614fe3187bb 100644
--- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
+++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
@@ -21,6 +21,7 @@ properties:
enum:
- qcom,sdm845-gpi-dma
- qcom,sm8150-gpi-dma
+ - qcom,sm8250-gpi-dma
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/dma/renesas,shdma.txt b/Documentation/devicetree/bindings/dma/renesas,shdma.txt
deleted file mode 100644
index a91920a49433..000000000000
--- a/Documentation/devicetree/bindings/dma/renesas,shdma.txt
+++ /dev/null
@@ -1,84 +0,0 @@
-* SHDMA Device Tree bindings
-
-Sh-/r-mobile and R-Car systems often have multiple identical DMA controller
-instances, capable of serving any of a common set of DMA slave devices, using
-the same configuration. To describe this topology we require all compatible
-SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible
-DMAC instances have the same number of channels and use the same DMA
-descriptors. Therefore respective DMA DT bindings can also all be placed in the
-multiplexer node. Even if there is only one such DMAC instance on a system, it
-still has to be placed under such a multiplexer node.
-
-* DMA multiplexer
-
-Required properties:
-- compatible: should be "renesas,shdma-mux"
-- #dma-cells: should be <1>, see "dmas" property below
-
-Optional properties (currently unused):
-- dma-channels: number of DMA channels
-- dma-requests: number of DMA request signals
-
-* DMA controller
-
-Required properties:
-- compatible: should be of the form "renesas,shdma-<soc>", where <soc> should
- be replaced with the desired SoC model, e.g.
- "renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC
-
-Example:
- dmac: dma-multiplexer@0 {
- compatible = "renesas,shdma-mux";
- #dma-cells = <1>;
- dma-channels = <20>;
- dma-requests = <256>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- dma0: dma-controller@e6700020 {
- compatible = "renesas,shdma-r8a73a4";
- reg = <0 0xe6700020 0 0x89e0>;
- interrupt-parent = <&gic>;
- interrupts = <0 220 4
- 0 200 4
- 0 201 4
- 0 202 4
- 0 203 4
- 0 204 4
- 0 205 4
- 0 206 4
- 0 207 4
- 0 208 4
- 0 209 4
- 0 210 4
- 0 211 4
- 0 212 4
- 0 213 4
- 0 214 4
- 0 215 4
- 0 216 4
- 0 217 4
- 0 218 4
- 0 219 4>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19";
- };
- };
-
-* DMA client
-
-Required properties:
-- dmas: a list of <[DMA multiplexer phandle] [MID/RID value]> pairs,
- where MID/RID values are fixed handles, specified in the SoC
- manual
-- dma-names: a list of DMA channel names, one per "dmas" entry
-
-Example:
- dmas = <&dmac 0xd1
- &dmac 0xd2>;
- dma-names = "tx", "rx";
diff --git a/MAINTAINERS b/MAINTAINERS
index c06fcc41381c..cd61f99dff8e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -791,6 +791,14 @@ M: Ley Foon Tan <ley.foon.tan@intel.com>
S: Maintained
F: drivers/mailbox/mailbox-altera.c
+ALTERA MSGDMA IP CORE DRIVER
+M: Olivier Dautricourt <olivier.dautricourt@orolia.com>
+R: Stefan Roese <sr@denx.de>
+L: dmaengine@vger.kernel.org
+S: Odd Fixes
+F: Documentation/devicetree/bindings/dma/altr,msgdma.yaml
+F: drivers/dma/altera-msgdma.c
+
ALTERA PIO DRIVER
M: Joyce Ooi <joyce.ooi@intel.com>
L: linux-gpio@vger.kernel.org
diff --git a/drivers/dma/altera-msgdma.c b/drivers/dma/altera-msgdma.c
index 9a841ce5f0c5..0fe0676f8e1d 100644
--- a/drivers/dma/altera-msgdma.c
+++ b/drivers/dma/altera-msgdma.c
@@ -19,6 +19,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
+#include <linux/of_dma.h>
#include "dmaengine.h"
@@ -888,6 +889,13 @@ static int msgdma_probe(struct platform_device *pdev)
if (ret)
goto fail;
+ ret = of_dma_controller_register(pdev->dev.of_node,
+ of_dma_xlate_by_chan_id, dma_dev);
+ if (ret == -EINVAL)
+ dev_warn(&pdev->dev, "device was not probed from DT");
+ else if (ret && ret != -ENODEV)
+ goto fail;
+
dev_notice(&pdev->dev, "Altera mSGDMA driver probe success\n");
return 0;
@@ -908,6 +916,8 @@ static int msgdma_remove(struct platform_device *pdev)
{
struct msgdma_device *mdev = platform_get_drvdata(pdev);
+ if (pdev->dev.of_node)
+ of_dma_controller_free(pdev->dev.of_node);
dma_async_device_unregister(&mdev->dmadev);
msgdma_dev_remove(mdev);
@@ -916,9 +926,19 @@ static int msgdma_remove(struct platform_device *pdev)
return 0;
}
+#ifdef CONFIG_OF
+static const struct of_device_id msgdma_match[] = {
+ { .compatible = "altr,socfpga-msgdma", },
+ { }
+};
+
+MODULE_DEVICE_TABLE(of, msgdma_match);
+#endif
+
static struct platform_driver msgdma_driver = {
.driver = {
.name = "altera-msgdma",
+ .of_match_table = of_match_ptr(msgdma_match),
},
.probe = msgdma_probe,
.remove = msgdma_remove,
diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
index ed2ab46b15e7..045ead46ec8f 100644
--- a/drivers/dma/fsl-qdma.c
+++ b/drivers/dma/fsl-qdma.c
@@ -1235,7 +1235,11 @@ static int fsl_qdma_probe(struct platform_device *pdev)
fsl_qdma->dma_dev.device_synchronize = fsl_qdma_synchronize;
fsl_qdma->dma_dev.device_terminate_all = fsl_qdma_terminate_all;
- dma_set_mask(&pdev->dev, DMA_BIT_MASK(40));
+ ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40));
+ if (ret) {
+ dev_err(&pdev->dev, "dma_set_mask failure.\n");
+ return ret;
+ }
platform_set_drvdata(pdev, fsl_qdma);
diff --git a/drivers/dma/hsu/hsu.c b/drivers/dma/hsu/hsu.c
index 025d8ad5a63c..92caae55aece 100644
--- a/drivers/dma/hsu/hsu.c
+++ b/drivers/dma/hsu/hsu.c
@@ -201,6 +201,7 @@ EXPORT_SYMBOL_GPL(hsu_dma_get_status);
*/
int hsu_dma_do_irq(struct hsu_dma_chip *chip, unsigned short nr, u32 status)
{
+ struct dma_chan_percpu *stat;
struct hsu_dma_chan *hsuc;
struct hsu_dma_desc *desc;
unsigned long flags;
@@ -210,6 +211,7 @@ int hsu_dma_do_irq(struct hsu_dma_chip *chip, unsigned short nr, u32 status)
return 0;
hsuc = &chip->hsu->chan[nr];
+ stat = this_cpu_ptr(hsuc->vchan.chan.local);
spin_lock_irqsave(&hsuc->vchan.lock, flags);
desc = hsuc->desc;
@@ -221,6 +223,7 @@ int hsu_dma_do_irq(struct hsu_dma_chip *chip, unsigned short nr, u32 status)
} else {
vchan_cookie_complete(&desc->vdesc);
desc->status = DMA_COMPLETE;
+ stat->bytes_transferred += desc->length;
hsu_dma_start_transfer(hsuc);
}
}
diff --git a/drivers/dma/idxd/cdev.c b/drivers/dma/idxd/cdev.c
index d4419bf1fede..e9def577c697 100644
--- a/drivers/dma/idxd/cdev.c
+++ b/drivers/dma/idxd/cdev.c
@@ -296,9 +296,7 @@ int idxd_wq_add_cdev(struct idxd_wq *wq)
void idxd_wq_del_cdev(struct idxd_wq *wq)
{
struct idxd_cdev *idxd_cdev;
- struct idxd_cdev_context *cdev_ctx;
- cdev_ctx = &ictx[wq->idxd->data->type];
idxd_cdev = wq->idxd_cdev;
wq->idxd_cdev = NULL;
cdev_device_del(&idxd_cdev->cdev, &idxd_cdev->dev);
diff --git a/drivers/dma/idxd/init.c b/drivers/dma/idxd/init.c
index 442d55c11a5f..c8ae41d36040 100644
--- a/drivers/dma/idxd/init.c
+++ b/drivers/dma/idxd/init.c
@@ -351,7 +351,8 @@ static int idxd_setup_internals(struct idxd_device *idxd)
init_waitqueue_head(&idxd->cmd_waitq);
if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)) {
- idxd->int_handles = devm_kcalloc(dev, idxd->max_wqs, sizeof(int), GFP_KERNEL);
+ idxd->int_handles = kcalloc_node(idxd->max_wqs, sizeof(int), GFP_KERNEL,
+ dev_to_node(dev));
if (!idxd->int_handles)
return -ENOMEM;
}
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index d5590c08db51..48390ea3c91f 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -35,7 +35,6 @@
#include <linux/workqueue.h>
#include <asm/irq.h>
-#include <linux/platform_data/dma-imx-sdma.h>
#include <linux/platform_data/dma-imx.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
@@ -181,6 +180,61 @@
BIT(DMA_MEM_TO_DEV) | \
BIT(DMA_DEV_TO_DEV))
+/**
+ * struct sdma_script_start_addrs - SDMA script start pointers
+ *
+ * start addresses of the different functions in the physical
+ * address space of the SDMA engine.
+ */
+struct sdma_script_start_addrs {
+ s32 ap_2_ap_addr;
+ s32 ap_2_bp_addr;
+ s32 ap_2_ap_fixed_addr;
+ s32 bp_2_ap_addr;
+ s32 loopback_on_dsp_side_addr;
+ s32 mcu_interrupt_only_addr;
+ s32 firi_2_per_addr;
+ s32 firi_2_mcu_addr;
+ s32 per_2_firi_addr;
+ s32 mcu_2_firi_addr;
+ s32 uart_2_per_addr;
+ s32 uart_2_mcu_addr;
+ s32 per_2_app_addr;
+ s32 mcu_2_app_addr;
+ s32 per_2_per_addr;
+ s32 uartsh_2_per_addr;
+ s32 uartsh_2_mcu_addr;
+ s32 per_2_shp_addr;
+ s32 mcu_2_shp_addr;
+ s32 ata_2_mcu_addr;
+ s32 mcu_2_ata_addr;
+ s32 app_2_per_addr;
+ s32 app_2_mcu_addr;
+ s32 shp_2_per_addr;
+ s32 shp_2_mcu_addr;
+ s32 mshc_2_mcu_addr;
+ s32 mcu_2_mshc_addr;
+ s32 spdif_2_mcu_addr;
+ s32 mcu_2_spdif_addr;
+ s32 asrc_2_mcu_addr;
+ s32 ext_mem_2_ipu_addr;
+ s32 descrambler_addr;
+ s32 dptc_dvfs_addr;
+ s32 utra_addr;
+ s32 ram_code_start_addr;
+ /* End of v1 array */
+ s32 mcu_2_ssish_addr;
+ s32 ssish_2_mcu_addr;
+ s32 hdmi_dma_addr;
+ /* End of v2 array */
+ s32 zcanfd_2_mcu_addr;
+ s32 zqspi_2_mcu_addr;
+ s32 mcu_2_ecspi_addr;
+ /* End of v3 array */
+ s32 mcu_2_zqspi_addr;
+ /* End of v4 array */
+};
+
/*
* Mode/Count of data node descriptors - IPCv2
*/
diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c
index 43ac3ab23d4c..1a1b7d8458c9 100644
--- a/drivers/dma/qcom/gpi.c
+++ b/drivers/dma/qcom/gpi.c
@@ -2282,6 +2282,7 @@ static int gpi_probe(struct platform_device *pdev)
static const struct of_device_id gpi_of_match[] = {
{ .compatible = "qcom,sdm845-gpi-dma" },
{ .compatible = "qcom,sm8150-gpi-dma" },
+ { .compatible = "qcom,sm8250-gpi-dma" },
{ },
};
MODULE_DEVICE_TABLE(of, gpi_of_match);
diff --git a/drivers/dma/sf-pdma/sf-pdma.c b/drivers/dma/sf-pdma/sf-pdma.c
index c4c4e8575764..f12606aeff87 100644
--- a/drivers/dma/sf-pdma/sf-pdma.c
+++ b/drivers/dma/sf-pdma/sf-pdma.c
@@ -94,6 +94,7 @@ sf_pdma_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dest, dma_addr_t src,
{
struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan);
struct sf_pdma_desc *desc;
+ unsigned long iflags;
if (chan && (!len || !dest || !src)) {
dev_err(chan->pdma->dma_dev.dev,
@@ -109,10 +110,10 @@ sf_pdma_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dest, dma_addr_t src,
desc->dirn = DMA_MEM_TO_MEM;
desc->async_tx = vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
- spin_lock_irqsave(&chan->vchan.lock, flags);
+ spin_lock_irqsave(&chan->vchan.lock, iflags);
chan->desc = desc;
sf_pdma_fill_desc(desc, dest, src, len);
- spin_unlock_irqrestore(&chan->vchan.lock, flags);
+ spin_unlock_irqrestore(&chan->vchan.lock, iflags);
return desc->async_tx;
}
diff --git a/drivers/dma/sh/Makefile b/drivers/dma/sh/Makefile
index 112fbd22bb3f..abdf10341725 100644
--- a/drivers/dma/sh/Makefile
+++ b/drivers/dma/sh/Makefile
@@ -3,7 +3,7 @@
# DMA Engine Helpers
#
-obj-$(CONFIG_SH_DMAE_BASE) += shdma-base.o shdma-of.o
+obj-$(CONFIG_SH_DMAE_BASE) += shdma-base.o
#
# DMA Controllers
diff --git a/drivers/dma/sh/shdma-of.c b/drivers/dma/sh/shdma-of.c
deleted file mode 100644
index be89dd894328..000000000000
--- a/drivers/dma/sh/shdma-of.c
+++ /dev/null
@@ -1,76 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SHDMA Device Tree glue
- *
- * Copyright (C) 2013 Renesas Electronics Inc.
- * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
- */
-
-#include <linux/dmaengine.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_dma.h>
-#include <linux/of_platform.h>
-#include <linux/platform_device.h>
-#include <linux/shdma-base.h>
-
-#define to_shdma_chan(c) container_of(c, struct shdma_chan, dma_chan)
-
-static struct dma_chan *shdma_of_xlate(struct of_phandle_args *dma_spec,
- struct of_dma *ofdma)
-{
- u32 id = dma_spec->args[0];
- dma_cap_mask_t mask;
- struct dma_chan *chan;
-
- if (dma_spec->args_count != 1)
- return NULL;
-
- dma_cap_zero(mask);
- /* Only slave DMA channels can be allocated via DT */
- dma_cap_set(DMA_SLAVE, mask);
-
- chan = dma_request_channel(mask, shdma_chan_filter,
- (void *)(uintptr_t)id);
- if (chan)
- to_shdma_chan(chan)->hw_req = id;
-
- return chan;
-}
-
-static int shdma_of_probe(struct platform_device *pdev)
-{
- const struct of_dev_auxdata *lookup = dev_get_platdata(&pdev->dev);
- int ret;
-
- ret = of_dma_controller_register(pdev->dev.of_node,
- shdma_of_xlate, pdev);
- if (ret < 0)
- return ret;
-
- ret = of_platform_populate(pdev->dev.of_node, NULL, lookup, &pdev->dev);
- if (ret < 0)
- of_dma_controller_free(pdev->dev.of_node);
-
- return ret;
-}
-
-static const struct of_device_id shdma_of_match[] = {
- { .compatible = "renesas,shdma-mux", },
- { }
-};
-MODULE_DEVICE_TABLE(of, sh_dmae_of_match);
-
-static struct platform_driver shdma_of = {
- .driver = {
- .name = "shdma-of",
- .of_match_table = shdma_of_match,
- },
- .probe = shdma_of_probe,
-};
-
-module_platform_driver(shdma_of);
-
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("SH-DMA driver DT glue");
-MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c
index e8b6633ae661..93f1645ae928 100644
--- a/drivers/dma/sun4i-dma.c
+++ b/drivers/dma/sun4i-dma.c
@@ -1042,9 +1042,8 @@ handle_pending:
* Move the promise into the completed list now that
* we're done with it
*/
- list_del(&vchan->processing->list);
- list_add_tail(&vchan->processing->list,
- &contract->completed_demands);
+ list_move_tail(&vchan->processing->list,
+ &contract->completed_demands);
/*
* Cyclic DMA transfers are special:
diff --git a/drivers/dma/ti/omap-dma.c b/drivers/dma/ti/omap-dma.c
index 268a08058714..7cb577e6587b 100644
--- a/drivers/dma/ti/omap-dma.c
+++ b/drivers/dma/ti/omap-dma.c
@@ -1608,7 +1608,8 @@ static int omap_dma_context_notifier(struct notifier_block *nb,
return NOTIFY_BAD;
omap_dma_context_save(od);
break;
- case CPU_CLUSTER_PM_ENTER_FAILED:
+ case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
+ break;
case CPU_CLUSTER_PM_EXIT:
omap_dma_context_restore(od);
break;
diff --git a/drivers/dma/xilinx/xilinx_dpdma.c b/drivers/dma/xilinx/xilinx_dpdma.c
index 6c709803203a..b280a53e8570 100644
--- a/drivers/dma/xilinx/xilinx_dpdma.c
+++ b/drivers/dma/xilinx/xilinx_dpdma.c
@@ -531,7 +531,7 @@ static void xilinx_dpdma_sw_desc_set_dma_addrs(struct xilinx_dpdma_device *xdev,
for (i = 1; i < num_src_addr; i++) {
u32 *addr = &hw_desc->src_addr2;
- addr[i-1] = lower_32_bits(dma_addr[i]);
+ addr[i - 1] = lower_32_bits(dma_addr[i]);
if (xdev->ext_addr) {
u32 *addr_ext = &hw_desc->addr_ext_23;
@@ -703,8 +703,9 @@ xilinx_dpdma_chan_prep_interleaved_dma(struct xilinx_dpdma_chan *chan,
size_t stride = hsize + xt->sgl[0].icg;
if (!IS_ALIGNED(xt->src_start, XILINX_DPDMA_ALIGN_BYTES)) {
- dev_err(chan->xdev->dev, "buffer should be aligned at %d B\n",
- XILINX_DPDMA_ALIGN_BYTES);
+ dev_err(chan->xdev->dev,
+ "chan%u: buffer should be aligned at %d B\n",
+ chan->id, XILINX_DPDMA_ALIGN_BYTES);
return NULL;
}
@@ -917,7 +918,7 @@ static u32 xilinx_dpdma_chan_ostand(struct xilinx_dpdma_chan *chan)
}
/**
- * xilinx_dpdma_chan_no_ostand - Notify no outstanding transaction event
+ * xilinx_dpdma_chan_notify_no_ostand - Notify no outstanding transaction event
* @chan: DPDMA channel
*
* Notify waiters for no outstanding event, so waiters can stop the channel
@@ -936,7 +937,9 @@ static int xilinx_dpdma_chan_notify_no_ostand(struct xilinx_dpdma_chan *chan)
cnt = xilinx_dpdma_chan_ostand(chan);
if (cnt) {
- dev_dbg(chan->xdev->dev, "%d outstanding transactions\n", cnt);
+ dev_dbg(chan->xdev->dev,
+ "chan%u: %d outstanding transactions\n",
+ chan->id, cnt);
return -EWOULDBLOCK;
}
@@ -972,8 +975,8 @@ static int xilinx_dpdma_chan_wait_no_ostand(struct xilinx_dpdma_chan *chan)
return 0;
}
- dev_err(chan->xdev->dev, "not ready to stop: %d trans\n",
- xilinx_dpdma_chan_ostand(chan));
+ dev_err(chan->xdev->dev, "chan%u: not ready to stop: %d trans\n",
+ chan->id, xilinx_dpdma_chan_ostand(chan));
if (ret == 0)
return -ETIMEDOUT;
@@ -1007,8 +1010,8 @@ static int xilinx_dpdma_chan_poll_no_ostand(struct xilinx_dpdma_chan *chan)
return 0;
}
- dev_err(chan->xdev->dev, "not ready to stop: %d trans\n",
- xilinx_dpdma_chan_ostand(chan));
+ dev_err(chan->xdev->dev, "chan%u: not ready to stop: %d trans\n",
+ chan->id, xilinx_dpdma_chan_ostand(chan));
return -ETIMEDOUT;
}
@@ -1062,7 +1065,8 @@ static void xilinx_dpdma_chan_done_irq(struct xilinx_dpdma_chan *chan)
vchan_cyclic_callback(&active->vdesc);
else
dev_warn(chan->xdev->dev,
- "DONE IRQ with no active descriptor!\n");
+ "chan%u: DONE IRQ with no active descriptor!\n",
+ chan->id);
spin_unlock_irqrestore(&chan->lock, flags);
}
@@ -1094,8 +1098,12 @@ static void xilinx_dpdma_chan_vsync_irq(struct xilinx_dpdma_chan *chan)
/* If the retrigger raced with vsync, retry at the next frame. */
sw_desc = list_first_entry(&pending->descriptors,
struct xilinx_dpdma_sw_desc, node);
- if (sw_desc->hw.desc_id != desc_id)
+ if (sw_desc->hw.desc_id != desc_id) {
+ dev_dbg(chan->xdev->dev,
+ "chan%u: vsync race lost (%u != %u), retrying\n",
+ chan->id, sw_desc->hw.desc_id, desc_id);
goto out;
+ }
/*
* Complete the active descriptor, if any, promote the pending
@@ -1151,10 +1159,12 @@ static void xilinx_dpdma_chan_handle_err(struct xilinx_dpdma_chan *chan)
spin_lock_irqsave(&chan->lock, flags);
- dev_dbg(xdev->dev, "cur desc addr = 0x%04x%08x\n",
+ dev_dbg(xdev->dev, "chan%u: cur desc addr = 0x%04x%08x\n",
+ chan->id,
dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE),
dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR));
- dev_dbg(xdev->dev, "cur payload addr = 0x%04x%08x\n",
+ dev_dbg(xdev->dev, "chan%u: cur payload addr = 0x%04x%08x\n",
+ chan->id,
dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDRE),
dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDR));
@@ -1170,7 +1180,8 @@ static void xilinx_dpdma_chan_handle_err(struct xilinx_dpdma_chan *chan)
xilinx_dpdma_chan_dump_tx_desc(chan, active);
if (active->error)
- dev_dbg(xdev->dev, "repeated error on desc\n");
+ dev_dbg(xdev->dev, "chan%u: repeated error on desc\n",
+ chan->id);
/* Reschedule if there's no new descriptor */
if (!chan->desc.pending &&
@@ -1235,7 +1246,8 @@ static int xilinx_dpdma_alloc_chan_resources(struct dma_chan *dchan)
align, 0);
if (!chan->desc_pool) {
dev_err(chan->xdev->dev,
- "failed to allocate a descriptor pool\n");
+ "chan%u: failed to allocate a descriptor pool\n",
+ chan->id);
return -ENOMEM;
}
@@ -1588,7 +1600,7 @@ static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
struct of_dma *ofdma)
{
struct xilinx_dpdma_device *xdev = ofdma->of_dma_data;
- uint32_t chan_id = dma_spec->args[0];
+ u32 chan_id = dma_spec->args[0];
if (chan_id >= ARRAY_SIZE(xdev->chan))
return NULL;
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 004736b6a9c8..93c3ca5fdafd 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -230,12 +230,6 @@ enum sum_check_flags {
typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
/**
- * struct dma_chan_percpu - the per-CPU part of struct dma_chan
- * @memcpy_count: transaction counter
- * @bytes_transferred: byte counter
- */
-
-/**
* enum dma_desc_metadata_mode - per descriptor metadata mode types supported
* @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the
* client driver and it is attached (via the dmaengine_desc_attach_metadata()
@@ -291,6 +285,11 @@ enum dma_desc_metadata_mode {
DESC_METADATA_ENGINE = BIT(1),
};
+/**
+ * struct dma_chan_percpu - the per-CPU part of struct dma_chan
+ * @memcpy_count: transaction counter
+ * @bytes_transferred: byte counter
+ */
struct dma_chan_percpu {
/* stats */
unsigned long memcpy_count;
diff --git a/include/linux/platform_data/dma-imx-sdma.h b/include/linux/platform_data/dma-imx-sdma.h
deleted file mode 100644
index 725602d9df91..000000000000
--- a/include/linux/platform_data/dma-imx-sdma.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __MACH_MXC_SDMA_H__
-#define __MACH_MXC_SDMA_H__
-
-/**
- * struct sdma_script_start_addrs - SDMA script start pointers
- *
- * start addresses of the different functions in the physical
- * address space of the SDMA engine.
- */
-struct sdma_script_start_addrs {
- s32 ap_2_ap_addr;
- s32 ap_2_bp_addr;
- s32 ap_2_ap_fixed_addr;
- s32 bp_2_ap_addr;
- s32 loopback_on_dsp_side_addr;
- s32 mcu_interrupt_only_addr;
- s32 firi_2_per_addr;
- s32 firi_2_mcu_addr;
- s32 per_2_firi_addr;
- s32 mcu_2_firi_addr;
- s32 uart_2_per_addr;
- s32 uart_2_mcu_addr;
- s32 per_2_app_addr;
- s32 mcu_2_app_addr;
- s32 per_2_per_addr;
- s32 uartsh_2_per_addr;
- s32 uartsh_2_mcu_addr;
- s32 per_2_shp_addr;
- s32 mcu_2_shp_addr;
- s32 ata_2_mcu_addr;
- s32 mcu_2_ata_addr;
- s32 app_2_per_addr;
- s32 app_2_mcu_addr;
- s32 shp_2_per_addr;
- s32 shp_2_mcu_addr;
- s32 mshc_2_mcu_addr;
- s32 mcu_2_mshc_addr;
- s32 spdif_2_mcu_addr;
- s32 mcu_2_spdif_addr;
- s32 asrc_2_mcu_addr;
- s32 ext_mem_2_ipu_addr;
- s32 descrambler_addr;
- s32 dptc_dvfs_addr;
- s32 utra_addr;
- s32 ram_code_start_addr;
- /* End of v1 array */
- s32 mcu_2_ssish_addr;
- s32 ssish_2_mcu_addr;
- s32 hdmi_dma_addr;
- /* End of v2 array */
- s32 zcanfd_2_mcu_addr;
- s32 zqspi_2_mcu_addr;
- s32 mcu_2_ecspi_addr;
- /* End of v3 array */
- s32 mcu_2_zqspi_addr;
- /* End of v4 array */
-};
-
-#endif /* __MACH_MXC_SDMA_H__ */
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-28 02:06:34 +0300