summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--drivers/clk/rockchip/clk-cpu.c41
-rw-r--r--drivers/clk/rockchip/clk.h2
2 files changed, 43 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index 11aa2259b532..6ea7fba9f9e5 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -113,6 +113,42 @@ static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk,
}
}
+static void rockchip_cpuclk_set_pre_muxs(struct rockchip_cpuclk *cpuclk,
+ const struct rockchip_cpuclk_rate_table *rate)
+{
+ int i;
+
+ /* alternate parent is active now. set the pre_muxs */
+ for (i = 0; i < ARRAY_SIZE(rate->pre_muxs); i++) {
+ const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i];
+
+ if (!clksel->reg)
+ break;
+
+ pr_debug("%s: setting reg 0x%x to 0x%x\n",
+ __func__, clksel->reg, clksel->val);
+ writel(clksel->val, cpuclk->reg_base + clksel->reg);
+ }
+}
+
+static void rockchip_cpuclk_set_post_muxs(struct rockchip_cpuclk *cpuclk,
+ const struct rockchip_cpuclk_rate_table *rate)
+{
+ int i;
+
+ /* alternate parent is active now. set the muxs */
+ for (i = 0; i < ARRAY_SIZE(rate->post_muxs); i++) {
+ const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i];
+
+ if (!clksel->reg)
+ break;
+
+ pr_debug("%s: setting reg 0x%x to 0x%x\n",
+ __func__, clksel->reg, clksel->val);
+ writel(clksel->val, cpuclk->reg_base + clksel->reg);
+ }
+}
+
static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
struct clk_notifier_data *ndata)
{
@@ -165,6 +201,9 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
cpuclk->reg_base + reg_data->core_reg[i]);
}
}
+
+ rockchip_cpuclk_set_pre_muxs(cpuclk, rate);
+
/* select alternate parent */
if (reg_data->mux_core_reg)
writel(HIWORD_UPDATE(reg_data->mux_core_alt,
@@ -219,6 +258,8 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
reg_data->mux_core_shift),
cpuclk->reg_base + reg_data->core_reg[0]);
+ rockchip_cpuclk_set_post_muxs(cpuclk, rate);
+
/* remove dividers */
for (i = 0; i < reg_data->num_cores; i++) {
writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 6eb31d36c4cd..24d3e56d3f71 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -399,6 +399,8 @@ struct rockchip_cpuclk_clksel {
struct rockchip_cpuclk_rate_table {
unsigned long prate;
struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
+ struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
+ struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
};
/**