diff options
| -rw-r--r-- | drivers/soc/xilinx/xlnx_vcu.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/soc/xilinx/xlnx_vcu.c index 14daad4efc58..7da9643820a8 100644 --- a/drivers/soc/xilinx/xlnx_vcu.c +++ b/drivers/soc/xilinx/xlnx_vcu.c @@ -73,7 +73,6 @@ * @aclk: axi clock source * @logicore_reg_ba: logicore reg base address * @vcu_slcr_ba: vcu_slcr Register base address - * @coreclk: core clock frequency */ struct xvcu_device { struct device *dev; @@ -81,7 +80,6 @@ struct xvcu_device { struct clk *aclk; struct regmap *logicore_reg_ba; void __iomem *vcu_slcr_ba; - u32 coreclk; }; static struct regmap_config vcu_settings_regmap_config = { @@ -358,10 +356,10 @@ static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu) return -EINVAL; } - xvcu->coreclk = pll_clk / divisor_core; + coreclk = pll_clk / divisor_core; mcuclk = pll_clk / divisor_mcu; dev_dbg(xvcu->dev, "Actual Ref clock freq is %uHz\n", refclk); - dev_dbg(xvcu->dev, "Actual Core clock freq is %uHz\n", xvcu->coreclk); + dev_dbg(xvcu->dev, "Actual Core clock freq is %uHz\n", coreclk); dev_dbg(xvcu->dev, "Actual Mcu clock freq is %uHz\n", mcuclk); vcu_pll_ctrl &= ~(VCU_PLL_CTRL_FBDIV_MASK << VCU_PLL_CTRL_FBDIV_SHIFT); |