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-rw-r--r--Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml47
1 files changed, 37 insertions, 10 deletions
diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
index 8da99461e817..346eb7cf29a5 100644
--- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -27,18 +27,12 @@ properties:
- const: phy-pma
clocks:
- items:
- - description: PLL reference clock
- - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
- - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
- - description: symbol clock for output symbol ( tx0 symbol clock)
+ minItems: 1
+ maxItems: 4
clock-names:
- items:
- - const: ref_clk
- - const: rx1_symbol_clk
- - const: rx0_symbol_clk
- - const: tx0_symbol_clk
+ minItems: 1
+ maxItems: 4
samsung,pmu-syscon:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
@@ -62,6 +56,39 @@ required:
- clock-names
- samsung,pmu-syscon
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-ufs-phy
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: PLL reference clock
+ - description: symbol clock for input symbol (rx0-ch0 symbol clock)
+ - description: symbol clock for input symbol (rx1-ch1 symbol clock)
+ - description: symbol clock for output symbol (tx0 symbol clock)
+
+ clock-names:
+ items:
+ - const: ref_clk
+ - const: rx1_symbol_clk
+ - const: rx0_symbol_clk
+ - const: tx0_symbol_clk
+
+ else:
+ properties:
+ clocks:
+ items:
+ - description: PLL reference clock
+
+ clock-names:
+ items:
+ - const: ref_clk
+
additionalProperties: false
examples: