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Diffstat (limited to 'arch/arm/boot/dts/dra7.dtsi')
-rw-r--r--arch/arm/boot/dts/dra7.dtsi182
1 files changed, 114 insertions, 68 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index a0afce7ad482..5332b57b4950 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -102,17 +102,101 @@
interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- prm: prm@4ae06000 {
- compatible = "ti,dra7-prm";
- reg = <0x4ae06000 0x3000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ l4_cfg: l4@4a000000 {
+ compatible = "ti,dra7-l4-cfg", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4a000000 0x22c000>;
- prm_clocks: clocks {
+ scm: scm@2000 {
+ compatible = "ti,dra7-scm-core", "simple-bus";
+ reg = <0x2000 0x2000>;
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
+ ranges = <0 0x2000 0x2000>;
+
+ scm_conf: scm_conf@0 {
+ compatible = "syscon";
+ reg = <0x0 0x1400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pbias_regulator: pbias_regulator {
+ compatible = "ti,pbias-omap";
+ reg = <0xe00 0x4>;
+ syscon = <&scm_conf>;
+ pbias_mmc_reg: pbias_mmc_omap5 {
+ regulator-name = "pbias_mmc_omap5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ };
+ };
+
+ dra7_pmx_core: pinmux@1400 {
+ compatible = "ti,dra7-padconf",
+ "pinctrl-single";
+ reg = <0x1400 0x0464>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x3fffffff>;
+ };
+ };
+
+ cm_core_aon: cm_core_aon@5000 {
+ compatible = "ti,dra7-cm-core-aon";
+ reg = <0x5000 0x2000>;
+
+ cm_core_aon_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm_core_aon_clockdomains: clockdomains {
+ };
+ };
+
+ cm_core: cm_core@8000 {
+ compatible = "ti,dra7-cm-core";
+ reg = <0x8000 0x3000>;
+
+ cm_core_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm_core_clockdomains: clockdomains {
+ };
};
+ };
- prm_clockdomains: clockdomains {
+ l4_wkup: l4@4ae00000 {
+ compatible = "ti,dra7-l4-wkup", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4ae00000 0x3f000>;
+
+ counter32k: counter@4000 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x4000 0x40>;
+ ti,hwmods = "counter_32k";
+ };
+
+ prm: prm@6000 {
+ compatible = "ti,dra7-prm";
+ reg = <0x6000 0x3000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+
+ prm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ prm_clockdomains: clockdomains {
+ };
};
};
@@ -185,36 +269,16 @@
};
};
- cm_core_aon: cm_core_aon@4a005000 {
- compatible = "ti,dra7-cm-core-aon";
- reg = <0x4a005000 0x2000>;
-
- cm_core_aon_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- cm_core_aon_clockdomains: clockdomains {
- };
- };
-
- cm_core: cm_core@4a008000 {
- compatible = "ti,dra7-cm-core";
- reg = <0x4a008000 0x3000>;
-
- cm_core_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- cm_core_clockdomains: clockdomains {
- };
- };
-
- counter32k: counter@4ae04000 {
- compatible = "ti,omap-counter32k";
- reg = <0x4ae04000 0x40>;
- ti,hwmods = "counter_32k";
+ bandgap: bandgap@4a0021e0 {
+ reg = <0x4a0021e0 0xc
+ 0x4a00232c 0xc
+ 0x4a002380 0x2c
+ 0x4a0023C0 0x3c
+ 0x4a002564 0x8
+ 0x4a002574 0x50>;
+ compatible = "ti,dra752-bandgap";
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ #thermal-sensor-cells = <1>;
};
dra7_ctrl_core: ctrl_core@4a002000 {
@@ -227,28 +291,6 @@
reg = <0x4a002e00 0x7c>;
};
- pbias_regulator: pbias_regulator {
- compatible = "ti,pbias-omap";
- reg = <0 0x4>;
- syscon = <&dra7_ctrl_general>;
- pbias_mmc_reg: pbias_mmc_omap5 {
- regulator-name = "pbias_mmc_omap5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- };
- };
-
- dra7_pmx_core: pinmux@4a003400 {
- compatible = "ti,dra7-padconf", "pinctrl-single";
- reg = <0x4a003400 0x0464>;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x3fffffff>;
- };
-
sdma: dma-controller@4a056000 {
compatible = "ti,omap4430-sdma";
reg = <0x4a056000 0x1000>;
@@ -666,7 +708,6 @@
reg = <0x48820000 0x80>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer5";
- ti,timer-dsp;
};
timer6: timer@48822000 {
@@ -674,8 +715,6 @@
reg = <0x48822000 0x80>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer6";
- ti,timer-dsp;
- ti,timer-pwm;
};
timer7: timer@48824000 {
@@ -683,7 +722,6 @@
reg = <0x48824000 0x80>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer7";
- ti,timer-dsp;
};
timer8: timer@48826000 {
@@ -691,8 +729,6 @@
reg = <0x48826000 0x80>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer8";
- ti,timer-dsp;
- ti,timer-pwm;
};
timer9: timer@4803e000 {
@@ -714,7 +750,6 @@
reg = <0x48088000 0x80>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer11";
- ti,timer-pwm;
};
timer13: timer@48828000 {
@@ -1419,7 +1454,7 @@
compatible = "ti,dra7-d_can";
ti,hwmods = "dcan1";
reg = <0x4ae3c000 0x2000>;
- syscon-raminit = <&dra7_ctrl_core 0x558 0>;
+ syscon-raminit = <&scm_conf 0x558 0>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dcan1_sys_clk_mux>;
status = "disabled";
@@ -1429,12 +1464,23 @@
compatible = "ti,dra7-d_can";
ti,hwmods = "dcan2";
reg = <0x48480000 0x2000>;
- syscon-raminit = <&dra7_ctrl_core 0x558 1>;
+ syscon-raminit = <&scm_conf 0x558 1>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_clkin1>;
status = "disabled";
};
};
+
+ thermal_zones: thermal-zones {
+ #include "omap4-cpu-thermal.dtsi"
+ #include "omap5-gpu-thermal.dtsi"
+ #include "omap5-core-thermal.dtsi"
+ };
+
+};
+
+&cpu_thermal {
+ polling-delay = <500>; /* milliseconds */
};
/include/ "dra7xx-clocks.dtsi"