diff options
Diffstat (limited to 'arch/arm/boot/dts/mmp3.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/mmp3.dtsi | 50 |
1 files changed, 29 insertions, 21 deletions
diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/mmp3.dtsi index 59a108e49b41..57231d49d938 100644 --- a/arch/arm/boot/dts/mmp3.dtsi +++ b/arch/arm/boot/dts/mmp3.dtsi @@ -183,14 +183,14 @@ mrvl,intc-nr-irqs = <5>; }; - usb_otg_phy0: usb-otg-phy@d4207000 { + usb_otg_phy0: usb-phy@d4207000 { compatible = "marvell,mmp3-usb-phy"; reg = <0xd4207000 0x40>; #phy-cells = <0>; status = "disabled"; }; - usb_otg0: usb-otg@d4208000 { + usb_otg0: usb@d4208000 { compatible = "marvell,pxau2o-ehci"; reg = <0xd4208000 0x200>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; @@ -201,15 +201,14 @@ status = "disabled"; }; - hsic_phy0: hsic-phy@f0001800 { - compatible = "marvell,mmp3-hsic-phy", - "usb-nop-xceiv"; + hsic_phy0: usb-phy@f0001800 { + compatible = "marvell,mmp3-hsic-phy"; reg = <0xf0001800 0x40>; #phy-cells = <0>; status = "disabled"; }; - hsic0: hsic@f0001000 { + hsic0: usb@f0001000 { compatible = "marvell,pxau2o-ehci"; reg = <0xf0001000 0x200>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; @@ -223,15 +222,14 @@ status = "disabled"; }; - hsic_phy1: hsic-phy@f0002800 { - compatible = "marvell,mmp3-hsic-phy", - "usb-nop-xceiv"; + hsic_phy1: usb-phy@f0002800 { + compatible = "marvell,mmp3-hsic-phy"; reg = <0xf0002800 0x40>; #phy-cells = <0>; status = "disabled"; }; - hsic1: hsic@f0002000 { + hsic1: usb@f0002000 { compatible = "marvell,pxau2o-ehci"; reg = <0xf0002000 0x200>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; @@ -281,6 +279,16 @@ status = "disabled"; }; + mmc5: mmc@d4217000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4217000 0x120>; + clocks = <&soc_clocks MMP3_CLK_SDH4>; + clock-names = "io"; + interrupt-parent = <&hsi1_mux>; + interrupts = <0>; + status = "disabled"; + }; + camera0: camera@d420a000 { compatible = "marvell,mmp2-ccic"; reg = <0xd420a000 0x800>; @@ -318,8 +326,8 @@ clocks = <&soc_clocks MMP2_CLK_TIMER>; }; - uart1: uart@d4030000 { - compatible = "mrvl,mmp-uart"; + uart1: serial@d4030000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4030000 0x1000>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&soc_clocks MMP2_CLK_UART0>; @@ -328,8 +336,8 @@ status = "disabled"; }; - uart2: uart@d4017000 { - compatible = "mrvl,mmp-uart"; + uart2: serial@d4017000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4017000 0x1000>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&soc_clocks MMP2_CLK_UART1>; @@ -338,8 +346,8 @@ status = "disabled"; }; - uart3: uart@d4018000 { - compatible = "mrvl,mmp-uart"; + uart3: serial@d4018000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4018000 0x1000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&soc_clocks MMP2_CLK_UART2>; @@ -348,8 +356,8 @@ status = "disabled"; }; - uart4: uart@d4016000 { - compatible = "mrvl,mmp-uart"; + uart4: serial@d4016000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4016000 0x1000>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; clocks = <&soc_clocks MMP2_CLK_UART3>; @@ -474,7 +482,7 @@ rtc: rtc@d4010000 { compatible = "mrvl,mmp-rtc"; reg = <0xd4010000 0x1000>; - interrupts = <1 0>; + interrupts = <1>, <0>; interrupt-names = "rtc 1Hz", "rtc alarm"; interrupt-parent = <&rtc_mux>; clocks = <&soc_clocks MMP2_CLK_RTC>; @@ -523,7 +531,7 @@ }; }; - l2: l2-cache-controller@d0020000 { + l2: cache-controller@d0020000 { compatible = "marvell,tauros3-cache", "arm,pl310-cache"; reg = <0xd0020000 0x1000>; cache-unified; @@ -531,7 +539,7 @@ }; soc_clocks: clocks@d4050000 { - compatible = "marvell,mmp2-clock"; + compatible = "marvell,mmp3-clock"; reg = <0xd4050000 0x1000>, <0xd4282800 0x400>, <0xd4015000 0x1000>; |