diff options
Diffstat (limited to 'arch/arm/boot/dts/r8a7779.dtsi')
-rw-r--r-- | arch/arm/boot/dts/r8a7779.dtsi | 272 |
1 files changed, 264 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index b517c8e6b420..7cfba9aa1b41 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -11,6 +11,7 @@ /include/ "skeleton.dtsi" +#include <dt-bindings/clock/r8a7779-clock.h> #include <dt-bindings/interrupt-controller/irq.h> / { @@ -25,21 +26,25 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clock-frequency = <1000000000>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clock-frequency = <1000000000>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; + clock-frequency = <1000000000>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; + clock-frequency = <1000000000>; }; }; @@ -49,13 +54,13 @@ spi2 = &hspi2; }; - gic: interrupt-controller@f0001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xf0001000 0x1000>, - <0xf0000100 0x100>; - }; + gic: interrupt-controller@f0001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xf0001000 0x1000>, + <0xf0000100 0x100>; + }; gpio0: gpio@ffc40000 { compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; @@ -157,6 +162,7 @@ compatible = "renesas,i2c-r8a7779"; reg = <0xffc70000 0x1000>; interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_I2C0>; status = "disabled"; }; @@ -166,6 +172,7 @@ compatible = "renesas,i2c-r8a7779"; reg = <0xffc71000 0x1000>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_I2C1>; status = "disabled"; }; @@ -175,6 +182,7 @@ compatible = "renesas,i2c-r8a7779"; reg = <0xffc72000 0x1000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_I2C2>; status = "disabled"; }; @@ -184,6 +192,61 @@ compatible = "renesas,i2c-r8a7779"; reg = <0xffc73000 0x1000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_I2C3>; + status = "disabled"; + }; + + scif0: serial@ffe40000 { + compatible = "renesas,scif-r8a7779", "renesas,scif"; + reg = <0xffe40000 0x100>; + interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg_clocks R8A7779_CLK_P>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif1: serial@ffe41000 { + compatible = "renesas,scif-r8a7779", "renesas,scif"; + reg = <0xffe41000 0x100>; + interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg_clocks R8A7779_CLK_P>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif2: serial@ffe42000 { + compatible = "renesas,scif-r8a7779", "renesas,scif"; + reg = <0xffe42000 0x100>; + interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg_clocks R8A7779_CLK_P>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif3: serial@ffe43000 { + compatible = "renesas,scif-r8a7779", "renesas,scif"; + reg = <0xffe43000 0x100>; + interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg_clocks R8A7779_CLK_P>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif4: serial@ffe44000 { + compatible = "renesas,scif-r8a7779", "renesas,scif"; + reg = <0xffe44000 0x100>; + interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg_clocks R8A7779_CLK_P>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif5: serial@ffe45000 { + compatible = "renesas,scif-r8a7779", "renesas,scif"; + reg = <0xffe45000 0x100>; + interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg_clocks R8A7779_CLK_P>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -193,20 +256,64 @@ }; thermal@ffc48000 { - compatible = "renesas,rcar-thermal"; + compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; reg = <0xffc48000 0x38>; }; + tmu0: timer@ffd80000 { + compatible = "renesas,tmu-r8a7779", "renesas,tmu"; + reg = <0xffd80000 0x30>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, + <0 33 IRQ_TYPE_LEVEL_HIGH>, + <0 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_TMU0>; + clock-names = "fck"; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + tmu1: timer@ffd81000 { + compatible = "renesas,tmu-r8a7779", "renesas,tmu"; + reg = <0xffd81000 0x30>; + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, + <0 37 IRQ_TYPE_LEVEL_HIGH>, + <0 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_TMU1>; + clock-names = "fck"; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + tmu2: timer@ffd82000 { + compatible = "renesas,tmu-r8a7779", "renesas,tmu"; + reg = <0xffd82000 0x30>; + interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, + <0 41 IRQ_TYPE_LEVEL_HIGH>, + <0 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_TMU2>; + clock-names = "fck"; + + #renesas,channels = <3>; + + status = "disabled"; + }; + sata: sata@fc600000 { compatible = "renesas,rcar-sata"; reg = <0xfc600000 0x2000>; interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7779_CLK_SATA>; }; sdhi0: sd@ffe4c000 { compatible = "renesas,sdhi-r8a7779"; reg = <0xffe4c000 0x100>; interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -216,6 +323,7 @@ compatible = "renesas,sdhi-r8a7779"; reg = <0xffe4d000 0x100>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -225,6 +333,7 @@ compatible = "renesas,sdhi-r8a7779"; reg = <0xffe4e000 0x100>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -234,6 +343,7 @@ compatible = "renesas,sdhi-r8a7779"; reg = <0xffe4f000 0x100>; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -245,6 +355,7 @@ interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; + clocks = <&mstp0_clks R8A7779_CLK_HSPI>; status = "disabled"; }; @@ -254,6 +365,7 @@ interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; + clocks = <&mstp0_clks R8A7779_CLK_HSPI>; status = "disabled"; }; @@ -263,6 +375,150 @@ interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; + clocks = <&mstp0_clks R8A7779_CLK_HSPI>; status = "disabled"; }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* External root clock */ + extal_clk: extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overriden by the board. */ + clock-frequency = <0>; + clock-output-names = "extal"; + }; + + /* Special CPG clocks */ + cpg_clocks: clocks@ffc80000 { + compatible = "renesas,r8a7779-cpg-clocks"; + reg = <0xffc80000 0x30>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "plla", "z", "zs", "s", + "s1", "p", "b", "out"; + }; + + /* Fixed factor clocks */ + i_clk: i_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7779_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "i"; + }; + s3_clk: s3_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7779_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "s3"; + }; + s4_clk: s4_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7779_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <16>; + clock-mult = <1>; + clock-output-names = "s4"; + }; + g_clk: g_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7779_CLK_PLLA>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "g"; + }; + + /* Gate clocks */ + mstp0_clks: clocks@ffc80030 { + compatible = "renesas,r8a7779-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0xffc80030 4>; + clocks = <&cpg_clocks R8A7779_CLK_S>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_S>, + <&cpg_clocks R8A7779_CLK_S>, + <&cpg_clocks R8A7779_CLK_S1>, + <&cpg_clocks R8A7779_CLK_S1>, + <&cpg_clocks R8A7779_CLK_S1>, + <&cpg_clocks R8A7779_CLK_S1>, + <&cpg_clocks R8A7779_CLK_S1>, + <&cpg_clocks R8A7779_CLK_S1>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7779_CLK_HSPI R8A7779_CLK_TMU2 + R8A7779_CLK_TMU1 R8A7779_CLK_TMU0 + R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0 + R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4 + R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 + R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0 + R8A7779_CLK_I2C3 R8A7779_CLK_I2C2 + R8A7779_CLK_I2C1 R8A7779_CLK_I2C0 + >; + clock-output-names = + "hspi", "tmu2", "tmu1", "tmu0", "hscif1", + "hscif0", "scif5", "scif4", "scif3", "scif2", + "scif1", "scif0", "i2c3", "i2c2", "i2c1", + "i2c0"; + }; + mstp1_clks: clocks@ffc80034 { + compatible = "renesas,r8a7779-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0xffc80034 4>, <0xffc80044 4>; + clocks = <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_S>, + <&cpg_clocks R8A7779_CLK_S>, + <&cpg_clocks R8A7779_CLK_S>, + <&cpg_clocks R8A7779_CLK_S>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_S>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7779_CLK_USB01 R8A7779_CLK_USB2 + R8A7779_CLK_DU R8A7779_CLK_VIN2 + R8A7779_CLK_VIN1 R8A7779_CLK_VIN0 + R8A7779_CLK_ETHER R8A7779_CLK_SATA + R8A7779_CLK_PCIE R8A7779_CLK_VIN3 + >; + clock-output-names = + "usb01", "usb2", + "du", "vin2", + "vin1", "vin0", + "ether", "sata", + "pcie", "vin3"; + }; + mstp3_clks: clocks@ffc8003c { + compatible = "renesas,r8a7779-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0xffc8003c 4>; + clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, + <&s4_clk>, <&s4_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2 + R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 + R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 + >; + clock-output-names = + "sdhi3", "sdhi2", "sdhi1", "sdhi0", + "mmc1", "mmc0"; + }; + }; }; |