diff options
Diffstat (limited to 'arch/arm/boot')
461 files changed, 19012 insertions, 4893 deletions
diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore index ce1c5ff746e7..8c759326baf4 100644 --- a/arch/arm/boot/.gitignore +++ b/arch/arm/boot/.gitignore @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only Image zImage xipImage diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore index 86b2f5d28240..db05c6ef3e31 100644 --- a/arch/arm/boot/compressed/.gitignore +++ b/arch/arm/boot/compressed/.gitignore @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only ashldi3.S bswapsdi2.S font.c diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index da599c3a1193..9c11e7490292 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -101,7 +101,6 @@ clean-files += piggy_data lib1funcs.S ashldi3.S bswapsdi2.S \ $(libfdt) $(libfdt_hdrs) hyp-stub.S KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING -KBUILD_CFLAGS += $(DISABLE_ARM_SSP_PER_TASK_PLUGIN) ifeq ($(CONFIG_FUNCTION_TRACER),y) ORIG_CFLAGS := $(KBUILD_CFLAGS) @@ -117,7 +116,8 @@ CFLAGS_fdt_ro.o := $(nossp-flags-y) CFLAGS_fdt_rw.o := $(nossp-flags-y) CFLAGS_fdt_wip.o := $(nossp-flags-y) -ccflags-y := -fpic $(call cc-option,-mno-single-pic-base,) -fno-builtin -I$(obj) +ccflags-y := -fpic $(call cc-option,-mno-single-pic-base,) -fno-builtin \ + -I$(obj) $(DISABLE_ARM_SSP_PER_TASK_PLUGIN) asflags-y := -DZIMAGE # Supply kernel BSS size to the decompressor via a linker symbol. diff --git a/arch/arm/boot/compressed/efi-header.S b/arch/arm/boot/compressed/efi-header.S index a5983588f96b..62286da318e7 100644 --- a/arch/arm/boot/compressed/efi-header.S +++ b/arch/arm/boot/compressed/efi-header.S @@ -60,7 +60,7 @@ optional_header: .long __pecoff_code_size @ SizeOfCode .long __pecoff_data_size @ SizeOfInitializedData .long 0 @ SizeOfUninitializedData - .long efi_stub_entry - start @ AddressOfEntryPoint + .long efi_entry - start @ AddressOfEntryPoint .long start_offset @ BaseOfCode .long __pecoff_data_start - start @ BaseOfData @@ -70,8 +70,8 @@ extra_header_fields: .long SZ_512 @ FileAlignment .short 0 @ MajorOsVersion .short 0 @ MinorOsVersion - .short 0 @ MajorImageVersion - .short 0 @ MinorImageVersion + .short LINUX_EFISTUB_MAJOR_VERSION @ MajorImageVersion + .short LINUX_EFISTUB_MINOR_VERSION @ MinorImageVersion .short 0 @ MajorSubsystemVersion .short 0 @ MinorSubsystemVersion .long 0 @ Win32VersionValue diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 088b0a060876..e8e1c866e413 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -151,6 +151,25 @@ .L_\@: .endm + /* + * The kernel build system appends the size of the + * decompressed kernel at the end of the compressed data + * in little-endian form. + */ + .macro get_inflated_image_size, res:req, tmp1:req, tmp2:req + adr \res, .Linflated_image_size_offset + ldr \tmp1, [\res] + add \tmp1, \tmp1, \res @ address of inflated image size + + ldrb \res, [\tmp1] @ get_unaligned_le32 + ldrb \tmp2, [\tmp1, #1] + orr \res, \res, \tmp2, lsl #8 + ldrb \tmp2, [\tmp1, #2] + ldrb \tmp1, [\tmp1, #3] + orr \res, \res, \tmp2, lsl #16 + orr \res, \res, \tmp1, lsl #24 + .endm + .section ".start", "ax" /* * sort out different calling conventions @@ -268,15 +287,15 @@ not_angel: */ mov r0, pc cmp r0, r4 - ldrcc r0, LC0+32 + ldrcc r0, LC0+28 addcc r0, r0, pc cmpcc r4, r0 orrcc r4, r4, #1 @ remember we skipped cache_on blcs cache_on restart: adr r0, LC0 - ldmia r0, {r1, r2, r3, r6, r10, r11, r12} - ldr sp, [r0, #28] + ldmia r0, {r1, r2, r3, r6, r11, r12} + ldr sp, [r0, #24] /* * We might be running at a different address. We need @@ -284,20 +303,8 @@ restart: adr r0, LC0 */ sub r0, r0, r1 @ calculate the delta offset add r6, r6, r0 @ _edata - add r10, r10, r0 @ inflated kernel size location - /* - * The kernel build system appends the size of the - * decompressed kernel at the end of the compressed data - * in little-endian form. - */ - ldrb r9, [r10, #0] - ldrb lr, [r10, #1] - orr r9, r9, lr, lsl #8 - ldrb lr, [r10, #2] - ldrb r10, [r10, #3] - orr r9, r9, lr, lsl #16 - orr r9, r9, r10, lsl #24 + get_inflated_image_size r9, r10, lr #ifndef CONFIG_ZBOOT_ROM /* malloc space is above the relocated stack (64k max) */ @@ -521,11 +528,8 @@ dtb_check_done: /* Preserve offset to relocated code. */ sub r6, r9, r6 -#ifndef CONFIG_ZBOOT_ROM - /* cache_clean_flush may use the stack, so relocate it */ - add sp, sp, r6 -#endif - + mov r0, r9 @ start of relocated zImage + add r1, sp, r6 @ end of relocated zImage bl cache_clean_flush badr r0, restart @@ -622,6 +626,11 @@ not_relocated: mov r0, #0 add r2, sp, #0x10000 @ 64k max mov r3, r7 bl decompress_kernel + + get_inflated_image_size r1, r2, r3 + + mov r0, r4 @ start of inflated image + add r1, r1, r0 @ end of inflated image bl cache_clean_flush bl cache_off @@ -652,13 +661,15 @@ LC0: .word LC0 @ r1 .word __bss_start @ r2 .word _end @ r3 .word _edata @ r6 - .word input_data_end - 4 @ r10 (inflated size location) .word _got_start @ r11 .word _got_end @ ip .word .L_user_stack_end @ sp .word _end - restart + 16384 + 1024*1024 .size LC0, . - LC0 +.Linflated_image_size_offset: + .long (input_data_end - 4) - . + #ifdef CONFIG_ARCH_RPC .globl params params: ldr r0, =0x10000100 @ params_phys for RPC @@ -668,6 +679,24 @@ params: ldr r0, =0x10000100 @ params_phys for RPC #endif /* + * dcache_line_size - get the minimum D-cache line size from the CTR register + * on ARMv7. + */ + .macro dcache_line_size, reg, tmp +#ifdef CONFIG_CPU_V7M + movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR + movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR + ldr \tmp, [\tmp] +#else + mrc p15, 0, \tmp, c0, c0, 1 @ read ctr +#endif + lsr \tmp, \tmp, #16 + and \tmp, \tmp, #0xf @ cache line size encoding + mov \reg, #4 @ bytes per word + mov \reg, \reg, lsl \tmp @ actual cache line size + .endm + +/* * Turn on the cache. We need to setup some page tables so that we * can have both the I and D caches on. * @@ -1159,8 +1188,6 @@ __armv7_mmu_cache_off: bic r0, r0, #0x000c #endif mcr p15, 0, r0, c1, c0 @ turn MMU and cache off - mov r12, lr - bl __armv7_mmu_cache_flush mov r0, #0 #ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB @@ -1168,11 +1195,14 @@ __armv7_mmu_cache_off: mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC mcr p15, 0, r0, c7, c10, 4 @ DSB mcr p15, 0, r0, c7, c5, 4 @ ISB - mov pc, r12 + mov pc, lr /* * Clean and flush the cache to maintain consistency. * + * On entry, + * r0 = start address + * r1 = end address (exclusive) * On exit, * r1, r2, r3, r9, r10, r11, r12 corrupted * This routine must preserve: @@ -1181,6 +1211,7 @@ __armv7_mmu_cache_off: .align 5 cache_clean_flush: mov r3, #16 + mov r11, r1 b call_cache_fn __armv4_mpu_cache_flush: @@ -1231,51 +1262,16 @@ __armv7_mmu_cache_flush: mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D b iflush hierarchical: - mcr p15, 0, r10, c7, c10, 5 @ DMB - stmfd sp!, {r0-r7, r9-r11} - mrc p15, 1, r0, c0, c0, 1 @ read clidr - ands r3, r0, #0x7000000 @ extract loc from clidr - mov r3, r3, lsr #23 @ left align loc bit field - beq finished @ if loc is 0, then no need to clean - mov r10, #0 @ start clean at cache level 0 -loop1: - add r2, r10, r10, lsr #1 @ work out 3x current cache level - mov r1, r0, lsr r2 @ extract cache type bits from clidr - and r1, r1, #7 @ mask of the bits for current cache only - cmp r1, #2 @ see what cache we have at this level - blt skip @ skip if no cache, or just i-cache - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr - mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr - mrc p15, 1, r1, c0, c0, 0 @ read the new csidr - and r2, r1, #7 @ extract the length of the cache lines - add r2, r2, #4 @ add 4 (line length offset) - ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 @ find maximum number on the way size - clz r5, r4 @ find bit position of way size increment - ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 @ extract max number of the index size -loop2: - mov r9, r4 @ create working copy of max way size -loop3: - ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 - ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 - THUMB( lsl r6, r9, r5 ) - THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 - THUMB( lsl r6, r7, r2 ) - THUMB( orr r11, r11, r6 ) @ factor index number into r11 - mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way - subs r9, r9, #1 @ decrement the way - bge loop3 - subs r7, r7, #1 @ decrement the index - bge loop2 -skip: - add r10, r10, #2 @ increment cache number - cmp r3, r10 - bgt loop1 -finished: - ldmfd sp!, {r0-r7, r9-r11} - mov r10, #0 @ switch back to cache level 0 - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + dcache_line_size r1, r2 @ r1 := dcache min line size + sub r2, r1, #1 @ r2 := line size mask + bic r0, r0, r2 @ round down start to line size + sub r11, r11, #1 @ end address is exclusive + bic r11, r11, r2 @ round down end to line size +0: cmp r0, r11 @ finished? + bgt iflush + mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA + add r0, r0, r1 + b 0b iflush: mcr p15, 0, r10, c7, c10, 4 @ DSB mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB @@ -1437,29 +1433,26 @@ __enter_kernel: reloc_code_end: #ifdef CONFIG_EFI_STUB - .align 2 -_start: .long start - . - -ENTRY(efi_stub_entry) - @ allocate space on stack for passing current zImage address - @ and for the EFI stub to return of new entry point of - @ zImage, as EFI stub may copy the kernel. Pointer address - @ is passed in r2. r0 and r1 are passed through from the - @ EFI firmware to efi_entry - adr ip, _start - ldr r3, [ip] - add r3, r3, ip - stmfd sp!, {r3, lr} - mov r2, sp @ pass zImage address in r2 - bl efi_entry - - @ Check for error return from EFI stub. r0 has FDT address - @ or error code. - cmn r0, #1 - beq efi_load_fail - - @ Preserve return value of efi_entry() in r4 - mov r4, r0 +ENTRY(efi_enter_kernel) + mov r7, r0 @ preserve image base + mov r4, r1 @ preserve DT pointer + + mov r0, r4 @ DT start + add r1, r4, r2 @ DT end + bl cache_clean_flush + + mov r0, r7 @ relocated zImage + ldr r1, =_edata @ size of zImage + add r1, r1, r0 @ end of zImage + bl cache_clean_flush + + @ The PE/COFF loader might not have cleaned the code we are + @ running beyond the PoU, and so calling cache_off below from + @ inside the PE/COFF loader allocated region is unsafe unless + @ we explicitly clean it to the PoC. + ARM( adrl r0, call_cache_fn ) + THUMB( adr r0, call_cache_fn ) @ region of code we will + adr r1, 0f @ run with MMU off bl cache_clean_flush bl cache_off @@ -1469,18 +1462,10 @@ ENTRY(efi_stub_entry) mov r0, #0 mov r1, #0xFFFFFFFF mov r2, r4 - - @ Branch to (possibly) relocated zImage that is in [sp] - ldr lr, [sp] - ldr ip, =start_offset - add lr, lr, ip - mov pc, lr @ no mode switch - -efi_load_fail: - @ Return EFI_LOAD_ERROR to EFI firmware on error. - ldr r0, =0x80000001 - ldmfd sp!, {ip, pc} -ENDPROC(efi_stub_entry) + add r7, r7, #(__efi_start - start) + mov pc, r7 @ no mode switch +ENDPROC(efi_enter_kernel) +0: #endif .align diff --git a/arch/arm/boot/compressed/vmlinux.lds.S b/arch/arm/boot/compressed/vmlinux.lds.S index fc7ed03d8b93..b247f399de71 100644 --- a/arch/arm/boot/compressed/vmlinux.lds.S +++ b/arch/arm/boot/compressed/vmlinux.lds.S @@ -36,7 +36,6 @@ SECTIONS *(.start) *(.text) *(.text.*) - *(.fixup) *(.gnu.warning) *(.glue_7t) *(.glue_7) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d6546d2676b9..e6a1cac0bfc7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -55,6 +55,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-nattis-2-natte-2.dtb \ at91-sama5d27_som1_ek.dtb \ at91-sama5d27_wlsom1_ek.dtb \ + at91-sama5d2_icp.dtb \ at91-sama5d2_ptc_ek.dtb \ at91-sama5d2_xplained.dtb \ at91-sama5d3_xplained.dtb \ @@ -181,6 +182,7 @@ dtb-$(CONFIG_ARCH_EXYNOS3) += \ exynos3250-monk.dtb \ exynos3250-rinato.dtb dtb-$(CONFIG_ARCH_EXYNOS4) += \ + exynos4210-i9100.dtb \ exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-trats.dtb \ @@ -237,6 +239,7 @@ dtb-$(CONFIG_ARCH_HIX5HD2) += \ hisi-x5hd2-dkb.dtb dtb-$(CONFIG_ARCH_INTEGRATOR) += \ integratorap.dtb \ + integratorap-im-pd1.dtb \ integratorcp.dtb dtb-$(CONFIG_ARCH_IXP4XX) += \ intel-ixp42x-linksys-nslu2.dtb \ @@ -279,6 +282,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-iomega_ix2_200.dtb \ kirkwood-is2.dtb \ kirkwood-km_kirkwood.dtb \ + kirkwood-l-50.dtb \ kirkwood-laplug.dtb \ kirkwood-linkstation-lsqvl.dtb \ kirkwood-linkstation-lsvl.dtb \ @@ -412,6 +416,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ imx6dl-colibri-eval-v3.dtb \ + imx6dl-colibri-v1_1-eval-v3.dtb \ imx6dl-cubox-i.dtb \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ @@ -446,6 +451,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-nitrogen6x.dtb \ imx6dl-phytec-mira-rdk-nand.dtb \ imx6dl-phytec-pbab01.dtb \ + imx6dl-pico-dwarf.dtb \ + imx6dl-pico-hobbit.dtb \ + imx6dl-pico-nymph.dtb \ + imx6dl-pico-pi.dtb \ imx6dl-rex-basic.dtb \ imx6dl-riotboard.dtb \ imx6dl-sabreauto.dtb \ @@ -529,6 +538,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-phytec-mira-rdk-emmc.dtb \ imx6q-phytec-mira-rdk-nand.dtb \ imx6q-phytec-pbab01.dtb \ + imx6q-pico-dwarf.dtb \ + imx6q-pico-hobbit.dtb \ + imx6q-pico-nymph.dtb \ + imx6q-pico-pi.dtb \ imx6q-pistachio.dtb \ imx6q-rex-pro.dtb \ imx6q-sabreauto.dtb \ @@ -594,6 +607,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-kontron-n6310-s-43.dtb \ imx6ul-liteboard.dtb \ imx6ul-opos6uldev.dtb \ + imx6ul-pico-dwarf.dtb \ imx6ul-pico-hobbit.dtb \ imx6ul-pico-pi.dtb \ imx6ul-phytec-segin-ff-rdk-nand.dtb \ @@ -610,12 +624,16 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ulz-14x14-evk.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ + imx7d-colibri-aster.dtb \ + imx7d-colibri-emmc-aster.dtb \ imx7d-colibri-emmc-eval-v3.dtb \ imx7d-colibri-eval-v3.dtb \ imx7d-mba7.dtb \ imx7d-meerkat96.dtb \ imx7d-nitrogen7.dtb \ + imx7d-pico-dwarf.dtb \ imx7d-pico-hobbit.dtb \ + imx7d-pico-nymph.dtb \ imx7d-pico-pi.dtb \ imx7d-sbc-imx7.dtb \ imx7d-sdb.dtb \ @@ -623,6 +641,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb-sht11.dtb \ imx7d-zii-rmu2.dtb \ imx7d-zii-rpu2.dtb \ + imx7s-colibri-aster.dtb \ imx7s-colibri-eval-v3.dtb \ imx7s-mba7.dtb \ imx7s-warp.dtb @@ -818,6 +837,7 @@ dtb-$(CONFIG_SOC_DRA7XX) += \ am57xx-beagle-x15.dtb \ am57xx-beagle-x15-revb1.dtb \ am57xx-beagle-x15-revc.dtb \ + am5729-beagleboneai.dtb \ am57xx-cl-som-am57x.dtb \ am57xx-sbc-am57x.dtb \ am572x-idk.dtb \ @@ -882,6 +902,9 @@ dtb-$(CONFIG_ARCH_QCOM) += \ dtb-$(CONFIG_ARCH_RDA) += \ rda8810pl-orangepi-2g-iot.dtb \ rda8810pl-orangepi-i96.dtb +dtb-$(CONFIG_ARCH_REALTEK) += \ + rtd1195-horseradish.dtb \ + rtd1195-mele-x1000.dtb dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-pb1176.dtb \ arm-realview-pb11mp.dtb \ @@ -903,6 +926,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r7s9210-rza2mevb.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ + r8a7742-iwg21d-q7.dtb \ r8a7743-iwg20d-q7.dtb \ r8a7743-iwg20d-q7-dbcm-ca.dtb \ r8a7743-sk-rzg1m.dtb \ @@ -1015,10 +1039,15 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-eval.dtb \ stm32h743i-disco.dtb \ stm32mp157a-avenger96.dtb \ + stm32mp157a-dhcor-avenger96.dtb \ stm32mp157a-dk1.dtb \ + stm32mp157a-iot-box.dtb \ + stm32mp157a-stinger96.dtb \ + stm32mp157c-dhcom-pdk2.dtb \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ - stm32mp157c-ev1.dtb + stm32mp157c-ev1.dtb \ + stm32mp157c-lxa-mc1.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ sun4i-a10-ba10-tvbox.dtb \ @@ -1056,6 +1085,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a13-licheepi-one.dtb \ sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino-micro.dtb \ + sun5i-a13-pocketbook-touch-lux-3.dtb \ sun5i-a13-q8-tablet.dtb \ sun5i-a13-utoo-p66.dtb \ sun5i-gr8-chip-pro.dtb \ @@ -1086,6 +1116,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-i12-tvbox.dtb \ sun7i-a20-icnova-swac.dtb \ sun7i-a20-lamobo-r1.dtb \ + sun7i-a20-linutronix-testbox-v2.dtb \ sun7i-a20-m3.dtb \ sun7i-a20-mk808c.dtb \ sun7i-a20-olimex-som-evb.dtb \ @@ -1093,6 +1124,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-olimex-som204-evb.dtb \ sun7i-a20-olimex-som204-evb-emmc.dtb \ sun7i-a20-olinuxino-lime.dtb \ + sun7i-a20-olinuxino-lime-emmc.dtb \ sun7i-a20-olinuxino-lime2.dtb \ sun7i-a20-olinuxino-lime2-emmc.dtb \ sun7i-a20-olinuxino-micro.dtb \ @@ -1202,7 +1234,8 @@ dtb-$(CONFIG_ARCH_U8500) += \ ste-hrefv60plus-stuib.dtb \ ste-hrefv60plus-tvk.dtb \ ste-href520-tvk.dtb \ - ste-ux500-samsung-golden.dtb + ste-ux500-samsung-golden.dtb \ + ste-ux500-samsung-skomer.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ld4-ref.dtb \ uniphier-ld6b-ref.dtb \ @@ -1321,6 +1354,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-wedge40.dtb \ aspeed-bmc-facebook-wedge100.dtb \ aspeed-bmc-facebook-yamp.dtb \ + aspeed-bmc-facebook-yosemitev2.dtb \ aspeed-bmc-ibm-rainier.dtb \ aspeed-bmc-intel-s2600wf.dtb \ aspeed-bmc-inspur-fp5280g2.dtb \ @@ -1329,6 +1363,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-microsoft-olympus.dtb \ aspeed-bmc-opp-lanyang.dtb \ aspeed-bmc-opp-mihawk.dtb \ + aspeed-bmc-opp-nicole.dtb \ aspeed-bmc-opp-palmetto.dtb \ aspeed-bmc-opp-romulus.dtb \ aspeed-bmc-opp-swift.dtb \ diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index 81e0f63e94d3..0ebe9e2c150e 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -105,6 +105,7 @@ ti,timers = <&timer7>; pinctrl-names = "default"; pinctrl-0 = <&dmtimer7_pins>; + ti,clock-source = <0x01>; }; vmmcsd_fixed: regulator-3v3 { diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 4e2986f0c604..5ed7f3c58c0f 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -759,12 +759,27 @@ ranges = <0x0 0x200000 0x80000>; }; - target-module@300000 { /* 0x4a300000, ap 9 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; + pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */ + compatible = "ti,sysc-pruss", "ti,sysc"; + reg = <0x326000 0x4>, + <0x326004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | + SYSC_PRUSS_SUB_MWAIT)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_per 1>; + reset-names = "rstctrl"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x300000 0x80000>; + status = "disabled"; }; }; }; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 41dcfb37155a..a35f5052d76f 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -47,6 +47,7 @@ #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a8"; + enable-method = "ti,am3352"; device_type = "cpu"; reg = <0>; @@ -56,6 +57,17 @@ clock-names = "cpu"; clock-latency = <300000>; /* From omap-cpufreq driver */ + cpu-idle-states = <&mpu_gate>; + }; + + idle-states { + mpu_gate: mpu_gate { + compatible = "arm,idle-state"; + entry-latency-us = <40>; + exit-latency-us = <90>; + min-residency-us = <300>; + ti,idle-wkup-m3; + }; }; }; @@ -193,45 +205,100 @@ reg = <0x48200000 0x1000>; }; - edma: edma@49000000 { - compatible = "ti,edma3-tpcc"; - ti,hwmods = "tpcc"; - reg = <0x49000000 0x10000>; - reg-names = "edma3_cc"; - interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, - <&edma_tptc2 0>; - - ti,edma-memcpy-channels = <20 21>; + target-module@49000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49000000 0x4>; + reg-names = "rev"; + clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49000000 0x10000>; + + edma: dma@0 { + compatible = "ti,edma3-tpcc"; + reg = <0 0x10000>; + reg-names = "edma3_cc"; + interrupts = <12 13 14>; + interrupt-names = "edma3_ccint", "edma3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, + <&edma_tptc2 0>; + + ti,edma-memcpy-channels = <20 21>; + }; }; - edma_tptc0: tptc@49800000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc0"; - reg = <0x49800000 0x100000>; - interrupts = <112>; - interrupt-names = "edma3_tcerrint"; + target-module@49800000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49800000 0x4>, + <0x49800010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_SMART>; + clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49800000 0x100000>; + + edma_tptc0: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <112>; + interrupt-names = "edma3_tcerrint"; + }; }; - edma_tptc1: tptc@49900000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc1"; - reg = <0x49900000 0x100000>; - interrupts = <113>; - interrupt-names = "edma3_tcerrint"; + target-module@49900000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49900000 0x4>, + <0x49900010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_SMART>; + clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49900000 0x100000>; + + edma_tptc1: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <113>; + interrupt-names = "edma3_tcerrint"; + }; }; - edma_tptc2: tptc@49a00000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc2"; - reg = <0x49a00000 0x100000>; - interrupts = <114>; - interrupt-names = "edma3_tcerrint"; + target-module@49a00000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49a00000 0x4>, + <0x49a00010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_SMART>; + clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49a00000 0x100000>; + + edma_tptc2: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <114>; + interrupt-names = "edma3_tcerrint"; + }; }; target-module@47810000 { diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index a1fd3e63e86e..92466b9eb6ba 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -156,6 +156,7 @@ pinctrl-0 = <&pwm_pins>; ti,timers = <&timer11>; #pwm-cells = <3>; + ti,clock-source = <0x01>; }; /* HS USB Host PHY on PORT 1 */ diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index faa14dc0faff..dba87bfaf33e 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -45,6 +45,7 @@ #size-cells = <0>; cpu: cpu@0 { compatible = "arm,cortex-a9"; + enable-method = "ti,am4372"; device_type = "cpu"; reg = <0>; @@ -54,6 +55,17 @@ operating-points-v2 = <&cpu0_opp_table>; clock-latency = <300000>; /* From omap-cpufreq driver */ + cpu-idle-states = <&mpu_gate>; + }; + + idle-states { + mpu_gate: mpu_gate { + compatible = "arm,idle-state"; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <300>; + local-timer-stop; + }; }; }; @@ -185,47 +197,102 @@ &pm_sram_data>; }; - edma: edma@49000000 { - compatible = "ti,edma3-tpcc"; - ti,hwmods = "tpcc"; - reg = <0x49000000 0x10000>; - reg-names = "edma3_cc"; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, - <&edma_tptc2 0>; - - ti,edma-memcpy-channels = <58 59>; + target-module@49000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49000000 0x4>; + reg-names = "rev"; + clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49000000 0x10000>; + + edma: dma@0 { + compatible = "ti,edma3-tpcc"; + reg = <0 0x10000>; + reg-names = "edma3_cc"; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma3_ccint", "edma3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, + <&edma_tptc2 0>; + + ti,edma-memcpy-channels = <58 59>; + }; }; - edma_tptc0: tptc@49800000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc0"; - reg = <0x49800000 0x100000>; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma3_tcerrint"; + target-module@49800000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49800000 0x4>, + <0x49800010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_SMART>; + clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49800000 0x100000>; + + edma_tptc0: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma3_tcerrint"; + }; }; - edma_tptc1: tptc@49900000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc1"; - reg = <0x49900000 0x100000>; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma3_tcerrint"; + target-module@49900000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49900000 0x4>, + <0x49900010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_SMART>; + clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49900000 0x100000>; + + edma_tptc1: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma3_tcerrint"; + }; }; - edma_tptc2: tptc@49a00000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc2"; - reg = <0x49a00000 0x100000>; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma3_tcerrint"; + target-module@49a00000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49a00000 0x4>, + <0x49a00010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_SMART>; + clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49a00000 0x100000>; + + edma_tptc2: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma3_tcerrint"; + }; }; target-module@47810000 { @@ -344,6 +411,28 @@ }; }; + pruss_tm: target-module@54400000 { + compatible = "ti,sysc-pruss", "ti,sysc"; + reg = <0x54426000 0x4>, + <0x54426004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | + SYSC_PRUSS_SUB_MWAIT)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>; + clock-names = "fck"; + resets = <&prm_per 1>; + reset-names = "rstctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x54400000 0x80000>; + }; + gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; @@ -394,38 +483,6 @@ }; }; - dss: dss@4832a000 { - compatible = "ti,omap3-dss"; - reg = <0x4832a000 0x200>; - status = "disabled"; - ti,hwmods = "dss_core"; - clocks = <&disp_clk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dispc: dispc@4832a400 { - compatible = "ti,omap3-dispc"; - reg = <0x4832a400 0x400>; - interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "dss_dispc"; - clocks = <&disp_clk>; - clock-names = "fck"; - - max-memory-bandwidth = <230000000>; - }; - - rfbi: rfbi@4832a800 { - compatible = "ti,omap3-rfbi"; - reg = <0x4832a800 0x100>; - ti,hwmods = "dss_rfbi"; - clocks = <&disp_clk>; - clock-names = "fck"; - status = "disabled"; - }; - }; - ocmcram: sram@40300000 { compatible = "mmio-sram"; reg = <0x40300000 0x40000>; /* 256k */ diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index f3ced6df0c9b..9f66f96d09c9 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -526,11 +526,11 @@ * Supply voltage supervisor on board will not allow opp50 so * disable it and set opp100 as suspend OPP. */ - opp50@300000000 { + opp50-300000000 { status = "disabled"; }; - opp100@600000000 { + opp100-600000000 { opp-suspend; }; }; diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index e18e17d31272..49c6a872052e 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -2117,7 +2117,6 @@ target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "dss_core"; reg = <0x2a000 0x4>, <0x2a010 0x4>, <0x2a014 0x4>; @@ -2135,6 +2134,82 @@ <0x00000800 0x0002a800 0x00000400>, <0x00000c00 0x0002ac00 0x00000400>, <0x00001000 0x0002b000 0x00001000>; + + dss: dss@0 { + compatible = "ti,omap3-dss"; + reg = <0 0x200>; + status = "disabled"; + clocks = <&disp_clk>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x00000400>, + <0x00000400 0x00000400 0x00000400>, + <0x00000800 0x00000800 0x00000400>, + <0x00000c00 0x00000c00 0x00000400>, + <0x00001000 0x00001000 0x00001000>; + + target-module@400 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x400 0x4>, + <0x410 0x4>, + <0x414 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x400 0x400>; + + dispc: dispc@0 { + compatible = "ti,omap3-dispc"; + reg = <0 0x400>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&disp_clk>; + clock-names = "fck"; + + max-memory-bandwidth = <230000000>; + }; + }; + + target-module@800 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x800 0x4>, + <0x810 0x4>, + <0x814 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x800 0x400>; + + rfbi: rfbi@0 { + compatible = "ti,omap3-rfbi"; + reg = <0 0x100>; + clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; + clock-names = "fck"; + status = "disabled"; + }; + }; + }; }; target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */ diff --git a/arch/arm/boot/dts/am57-pruss.dtsi b/arch/arm/boot/dts/am57-pruss.dtsi new file mode 100644 index 000000000000..b1c583dee10b --- /dev/null +++ b/arch/arm/boot/dts/am57-pruss.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * + * Common PRUSS data for TI AM57xx platforms + */ + +&ocp { + pruss1_tm: target-module@4b226000 { + compatible = "ti,sysc-pruss", "ti,sysc"; + reg = <0x4b226000 0x4>, + <0x4b226004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | + SYSC_PRUSS_SUB_MWAIT)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + /* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4b200000 0x80000>; + }; + + pruss2_tm: target-module@4b2a6000 { + compatible = "ti,sysc-pruss", "ti,sysc"; + reg = <0x4b2a6000 0x4>, + <0x4b2a6004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | + SYSC_PRUSS_SUB_MWAIT)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + /* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4b280000 0x80000>; + }; +}; diff --git a/arch/arm/boot/dts/am5718.dtsi b/arch/arm/boot/dts/am5718.dtsi index d51007c3e8c4..a80c2e3eee2e 100644 --- a/arch/arm/boot/dts/am5718.dtsi +++ b/arch/arm/boot/dts/am5718.dtsi @@ -4,6 +4,7 @@ */ #include "dra72x.dtsi" +#include "am57-pruss.dtsi" / { compatible = "ti,am5718", "ti,dra7"; diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts index 669559c9c95b..62eb2b6ff10b 100644 --- a/arch/arm/boot/dts/am571x-idk.dts +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -10,6 +10,7 @@ #include "dra7-mmc-iodelay.dtsi" #include "dra72x-mmc-iodelay.dtsi" #include "am57xx-idk-common.dtsi" +#include "dra7-ipu-dsp-common.dtsi" / { model = "TI AM5718 IDK"; @@ -20,6 +21,33 @@ reg = <0x0 0x80000000 0x0 0x40000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + leds { compatible = "gpio-leds"; cpu0-led { @@ -148,21 +176,19 @@ load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; }; -&mailbox5 { +&ipu2 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; + memory-region = <&ipu2_memory_region>; }; -&mailbox6 { +&ipu1 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; }; &pcie1_rc { diff --git a/arch/arm/boot/dts/am5728.dtsi b/arch/arm/boot/dts/am5728.dtsi index 82e5427ef6a9..9a3810f5adcc 100644 --- a/arch/arm/boot/dts/am5728.dtsi +++ b/arch/arm/boot/dts/am5728.dtsi @@ -4,6 +4,7 @@ */ #include "dra74x.dtsi" +#include "am57-pruss.dtsi" / { compatible = "ti,am5728", "ti,dra7"; diff --git a/arch/arm/boot/dts/am5729-beagleboneai.dts b/arch/arm/boot/dts/am5729-beagleboneai.dts new file mode 100644 index 000000000000..9877d7709d41 --- /dev/null +++ b/arch/arm/boot/dts/am5729-beagleboneai.dts @@ -0,0 +1,731 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; + +#include "dra74x.dtsi" +#include "am57xx-commercial-grade.dtsi" +#include "dra74x-mmc-iodelay.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/dra.h> + +/ { + model = "BeagleBoard.org BeagleBone AI"; + compatible = "beagle,am5729-beagleboneai", "ti,am5728", + "ti,dra742", "ti,dra74", "ti,dra7"; + + aliases { + rtc0 = &tps659038_rtc; + rtc1 = &rtc; + display0 = &hdmi_conn; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_memory_region: dsp2-memory@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + + }; + + vdd_adc: gpioregulator-vdd_adc { + compatible = "regulator-gpio"; + regulator-name = "vdd_adc"; + vin-supply = <&vdd_5v>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + states = <1800000 0 + 3300000 1>; + }; + + vdd_5v: fixedregulator-vdd_5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vtt_fixed: fixedregulator-vtt { + /* TPS51200 */ + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + vin-supply = <&vdd_ddr>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "beaglebone:green:usr0"; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led1 { + label = "beaglebone:green:usr1"; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led2 { + label = "beaglebone:green:usr2"; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu"; + default-state = "off"; + }; + + led3 { + label = "beaglebone:green:usr3"; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "beaglebone:green:usr4"; + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + default-state = "off"; + }; + }; + + hdmi_conn: connector@0 { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_encoder_out>; + }; + }; + }; + + hdmi_enc: encoder@0 { + /* "ti,tpd12s016" software compatible with "ti,tpd12s015" + * no need for individual driver + */ + compatible = "ti,tpd12s015"; + gpios = <0>, + <0>, + <&gpio7 12 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + + port@0 { + reg = <0x0>; + + hdmi_encoder_in: endpoint@0 { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <0x1>; + + hdmi_encoder_out: endpoint@0 { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + emmc_pwrseq: emmc_pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; + }; + + brcmf_pwrseq: brcmf_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>, /* BT-REG-ON */ + <&gpio3 18 GPIO_ACTIVE_LOW>; /* WL-REG-ON */ + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + ti,enable-id-detection; + id-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + ti,palmas-override-powerhold; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + + smps12-in-supply = <&vdd_5v>; + smps3-in-supply = <&vdd_5v>; + smps45-in-supply = <&vdd_5v>; + smps6-in-supply = <&vdd_5v>; + smps7-in-supply = <&vdd_5v>; + mps3-in-supply = <&vdd_5v>; + smps8-in-supply = <&vdd_5v>; + smps9-in-supply = <&vdd_5v>; + ldo1-in-supply = <&vdd_5v>; + ldo2-in-supply = <&vdd_5v>; + ldo3-in-supply = <&vdd_5v>; + ldo4-in-supply = <&vdd_5v>; + ldo9-in-supply = <&vdd_5v>; + ldoln-in-supply = <&vdd_5v>; + ldousb-in-supply = <&vdd_5v>; + ldortc-in-supply = <&vdd_5v>; + + regulators { + vdd_mpu: smps12 { + /* VDD_MPU */ + regulator-name = "smps12"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ddr: smps3 { + /* VDD_DDR EMIF1 EMIF2 */ + regulator-name = "smps3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_dspeve: smps45 { + /* VDD_DSPEVE on AM572 */ + regulator-name = "smps45"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_gpu: smps6 { + /* VDD_GPU */ + regulator-name = "smps6"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_core: smps7 { + /* VDD_CORE */ + regulator-name = "smps7"; + regulator-min-microvolt = < 850000>; /*** 1.15V */ + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_iva: smps8 { + /* VDD_IVAHD */ /*** 1.06V */ + regulator-name = "smps8"; + }; + + vdd_3v3: smps9 { + /* VDD_3V3 */ + regulator-name = "smps9"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_sd: ldo1 { + /* VDDSHV8 - VSDMMC */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_1v8: ldo2 { + /* VDDSH18V */ + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8_phy_ldo3: ldo3 { + /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8_phy_ldo4: ldo4 { + /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* LDO5-8 unused */ + + vdd_rtc: ldo9 { + /* VDD_RTC */ + regulator-name = "ldo9"; + regulator-min-microvolt = < 840000>; + regulator-max-microvolt = <1160000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8_pll: ldoln { + /* VDDA_1V8_PLL */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldortc_reg: ldortc { + /* VDDA_RTC */ + regulator-name = "ldortc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + regen1: regen1 { + /* VDD_3V3_ON */ + regulator-name = "regen1"; + regulator-boot-on; + regulator-always-on; + }; + + regen2: regen2 { + /* Needed for PMIC internal resource */ + regulator-name = "regen2"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659038_rtc: tps659038_rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&tps659038>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + tps659038_pwr_button: tps659038_pwr_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps659038>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + ti,palmas-long-press-seconds = <12>; + }; + + tps659038_gpio: tps659038_gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + /* STMPE811 touch screen controller */ + stmpe811@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio2>; + interrupt-controller; + id = <0>; + blocks = <0x5>; + irq-trigger = <0x1>; + st,mod-12b = <1>; /* 12-bit ADC */ + st,ref-sel = <0>; /* internal ADC reference */ + st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ + st,sample-time = <4>; /* ADC converstion time: 80 clocks */ + + stmpe_adc { + compatible = "st,stmpe-adc"; + st,norequest-mask = <0x00>; /* mask any channels to be used by touchscreen */ + adc0: iio-device@0 { + #io-channel-cells = <1>; + iio-channels = <&adc0 4>, <&adc0 1>, <&adc0 2>, <&adc0 3>, <&adc0 4>, <&adc0 5>, <&adc0 6>; + iio-channel-names = "AIN0_P9_39", "AIN1_P9_40", "AIN2_P9_37", "AIN3_P9_38", + "AIN4_P9_33", "AIN5_P9_36", "AIN6_P9_35"; + }; + }; + + stmpe_touchscreen { + status = "disabled"; + compatible = "st,stmpe-ts"; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + + stmpe_gpio { + compatible = "st,stmpe-gpio"; + }; + + stmpe_pwm { + compatible = "st,stmpe-pwm"; + #pwm-cells = <2>; + }; + }; +}; + +&mcspi3 { + status = "okay"; + ti,pindir-d0-out-d1-in; + + sn65hvs882: sn65hvs882@0 { + compatible = "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + }; +}; + +&cpu0 { + vdd-supply = <&vdd_mpu>; + voltage-tolerance = <1>; +}; + +&uart1 { + status = "okay"; +}; + +&davinci_mdio { + reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; + + phy0: ethernet-phy@1 { + reg = <4>; + eee-broken-100tx; + eee-broken-1000t; + }; +}; + +&mac { + slaves = <1>; + status = "okay"; +}; + +&cpsw_emac0 { + phy-handle = <&phy0>; + phy-mode = "rgmii"; +}; + +&ocp { + pruss1_shmem: pruss_shmem@4b200000 { + status = "okay"; + compatible = "ti,pruss-shmem"; + reg = <0x4b200000 0x020000>; + }; + + pruss2_shmem: pruss_shmem@4b280000 { + status = "okay"; + compatible = "ti,pruss-shmem"; + reg = <0x4b280000 0x020000>; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&vdd_sd>; + bus-width = <4>; + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ + + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&vdd_1v8>; + vqmmc-supply = <&vdd_1v8>; + bus-width = <8>; + ti,non-removable; + non-removable; + mmc-pwrseq = <&emmc_pwrseq>; + + ti,needs-special-reset; + dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; + dma-names = "tx", "rx"; + +}; + +&mmc4 { + /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */ + /* HS: High speed up to 50 MHz (3.3 V signaling). */ + /* SDR12: SDR up to 25 MHz (1.8 V signaling). */ + /* SDR25: SDR up to 50 MHz (1.8 V signaling). */ + /* SDR50: SDR up to 100 MHz (1.8 V signaling). */ + /* SDR104: SDR up to 208 MHz (1.8 V signaling) */ + /* DDR50: DDR up to 50 MHz (1.8 V signaling). */ + status = "okay"; + + ti,needs-special-reset; + vmmc-supply = <&vdd_3v3>; + cap-power-off-card; + keep-power-in-suspend; + bus-width = <4>; + ti,non-removable; + non-removable; + no-1-8-v; + max-frequency = <24000000>; + + #address-cells = <1>; + #size-cells = <0>; + mmc-pwrseq = <&brcmf_pwrseq>; + + brcmf: wifi@1 { + status = "okay"; + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + + brcm,sd-head-align = <4>; + brcm,sd_head_align = <4>; + brcm,sd_sgentry_align = <512>; + + interrupt-parent = <&gpio3>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; + +&usb1 { + status = "okay"; + dr_mode = "otg"; +}; + +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&usb2 { + status = "okay"; + dr_mode = "host"; +}; + +&dss { + status = "okay"; + vdda_video-supply = <&vdd_1v8_pll>; +}; + +&hdmi { + status = "okay"; + vdda-supply = <&vdd_1v8_phy_ldo4>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&hdmi_encoder_in>; + }; + }; +}; + +&bandgap { + status = "okay"; +}; + +&mailbox1 { + status = "okay"; +}; + +&mailbox2 { + status = "okay"; +}; + +&mailbox3 { + status = "okay"; +}; + +&mailbox4 { + status = "okay"; +}; + +&mailbox5 { + status = "okay"; +}; + +&mailbox6 { + status = "okay"; +}; + +&mailbox7 { + status = "okay"; +}; + +&mailbox8 { + status = "okay"; +}; + +&mailbox9 { + status = "okay"; +}; + +&mailbox10 { + status = "okay"; +}; + +&mailbox11 { + status = "okay"; +}; + +&mailbox12 { + status = "okay"; +}; + +&mailbox13 { + status = "okay"; +}; + +&cpu_alert0 { + temperature = <55000>; /* milliCelsius */ +}; + +&cpu_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&gpu_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&core_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&dspeve_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&iva_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&sata { + status = "disabled"; +}; + +&sata_phy { + status = "disabled"; +}; + +/* bluetooth */ +&uart6 { + status = "okay"; +}; + +/* cape header stuff */ +&i2c4 { + status = "okay"; + clock-frequency = <100000>; +}; + +&cpu0_opp_table { + opp_slow-500000000 { + opp-shared; + }; +}; diff --git a/arch/arm/boot/dts/am572x-idk-common.dtsi b/arch/arm/boot/dts/am572x-idk-common.dtsi index ddf123620e96..37ce2d7c4173 100644 --- a/arch/arm/boot/dts/am572x-idk-common.dtsi +++ b/arch/arm/boot/dts/am572x-idk-common.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include "am57xx-idk-common.dtsi" +#include "dra74-ipu-dsp-common.dtsi" / { memory@0 { @@ -13,6 +14,40 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_memory_region: dsp2-memory@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + status-leds { compatible = "gpio-leds"; cpu0-led { @@ -147,22 +182,22 @@ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; }; -&mailbox5 { +&ipu2 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; + memory-region = <&ipu2_memory_region>; }; -&mailbox6 { +&ipu1 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_memory_region>; }; diff --git a/arch/arm/boot/dts/am5748.dtsi b/arch/arm/boot/dts/am5748.dtsi index 5e129759d04a..2b65317b1513 100644 --- a/arch/arm/boot/dts/am5748.dtsi +++ b/arch/arm/boot/dts/am5748.dtsi @@ -4,6 +4,7 @@ */ #include "dra76x.dtsi" +#include "am57-pruss.dtsi" / { compatible = "ti,am5748", "ti,dra762", "ti,dra7"; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi index a813a0cf3ff3..9cfdc29c283d 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi @@ -7,6 +7,7 @@ #include "am5728.dtsi" #include "am57xx-commercial-grade.dtsi" #include "dra74x-mmc-iodelay.dtsi" +#include "dra74-ipu-dsp-common.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -50,6 +51,40 @@ regulator-boot-on; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_memory_region: dsp2-memory@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + vdd_3v3: fixedregulator-vdd_3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; @@ -584,22 +619,22 @@ rx-num-evt = <32>; }; -&mailbox5 { +&ipu2 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; + memory-region = <&ipu2_memory_region>; }; -&mailbox6 { +&ipu1 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_memory_region>; }; diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi index aa5e55f98179..8ec71342f289 100644 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi @@ -35,6 +35,16 @@ regulator-boot-on; }; + v1_2d: fixedregulator-v1_2d { + compatible = "regulator-fixed"; + regulator-name = "V1_2D"; + vin-supply = <&vmain>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + vtt_fixed: fixedregulator-vtt { /* TPS51200 */ compatible = "regulator-fixed"; @@ -139,6 +149,12 @@ }; }; }; + + src_clk_x1: src_clk_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; }; &dra7_pmx_core { @@ -378,6 +394,32 @@ gpio-controller; #gpio-cells = <2>; }; + + dsi_bridge: tc358778@e { + compatible = "toshiba,tc358778", "toshiba,tc358768"; + reg = <0xe>; + status = "disabled"; + + clocks = <&src_clk_x1>; + clock-names = "refclk"; + + vddc-supply = <&v1_2d>; + vddmipi-supply = <&v1_2d>; + vddio-supply = <&v3_3d>; + + dsi_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rgb_in: endpoint { + remote-endpoint = <&dpi_out>; + data-lines = <24>; + }; + }; + }; + }; }; &mcspi3 { @@ -543,4 +585,20 @@ &dss { status = "okay"; + + vdda_video-supply = <&ldoln_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_out: endpoint { + remote-endpoint = <&rgb_in>; + data-lines = <24>; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi index 09f3f544f3a7..f61bd59ae5ba 100644 --- a/arch/arm/boot/dts/arm-realview-pbx.dtsi +++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi @@ -210,7 +210,7 @@ }; }; - soc: soc@0 { + soc: soc { compatible = "arm,realview-pbx-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index c15f5e92f97f..0b8c2a64b36f 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -114,7 +114,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <31>; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -124,7 +123,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <32>; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 2932a29ae272..9805e507c695 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -236,7 +236,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -247,7 +246,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index e038abc0c6b4..348116501aa2 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -153,7 +153,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -164,7 +163,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index b1b86934c688..e0b7c2099831 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -108,7 +108,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -119,7 +118,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -130,7 +128,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -141,7 +138,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 4afa8662c4e8..8d0f4656aa05 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -213,3 +213,7 @@ &i2c15 { status = "okay"; }; + +&fsim0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index 5d7cbd9164d4..2d44d9ad4e40 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -5,6 +5,7 @@ #include "aspeed-g5.dtsi" #include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/i2c/i2c.h> / { model = "Facebook TiogaPass BMC"; @@ -112,13 +113,76 @@ &kcs2 { // BMC KCS channel 2 status = "okay"; - kcs_addr = <0xca8>; + aspeed,lpc-io-reg = <0xca8>; }; &kcs3 { // BMC KCS channel 3 status = "okay"; - kcs_addr = <0xca2>; + aspeed,lpc-io-reg = <0xca2>; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "BMC_CPLD_FPGA_SEL","","","","","","","", + /*B0-B7*/ "","BMC_DEBUG_EN","","","","BMC_PPIN","PS_PWROK", + "IRQ_PVDDQ_GHJ_VRHOT_LVT3", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "BIOS_MRC_DEBUG_MSG_DIS","BOARD_REV_ID0","", + "BOARD_REV_ID1","IRQ_DIMM_SAVE_LVT3","BOARD_REV_ID2", + "CPU_ERR0_LVT3_BMC","CPU_ERR1_LVT3_BMC", + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON", + "POWER_OUT","NMI_BUTTON","","CPU0_PROCHOT_LVT3_ BMC", + "CPU1_PROCHOT_LVT3_ BMC", + /*F0-F7*/ "IRQ_PVDDQ_ABC_VRHOT_LVT3","", + "IRQ_PVCCIN_CPU0_VRHOT_LVC3", + "IRQ_PVCCIN_CPU1_VRHOT_LVC3", + "IRQ_PVDDQ_KLM_VRHOT_LVT3","","P3VBAT_BRIDGE_EN","", + /*G0-G7*/ "CPU_ERR2_LVT3","CPU_CATERR_LVT3","PCH_BMC_THERMTRIP", + "CPU0_SKTOCC_LVT3","","","","BIOS_SMI_ACTIVE", + /*H0-H7*/ "LED_POST_CODE_0","LED_POST_CODE_1","LED_POST_CODE_2", + "LED_POST_CODE_3","LED_POST_CODE_4","LED_POST_CODE_5", + "LED_POST_CODE_6","LED_POST_CODE_7", + /*I0-I7*/ "CPU0_FIVR_FAULT_LVT3","CPU1_FIVR_FAULT_LVT3", + "FORCE_ADR","UV_ADR_TRIGGER_EN","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "IRQ_UV_DETECT","IRQ_OC_DETECT","HSC_TIMER_EXP","", + "MEM_THERM_EVENT_PCH","PMBUS_ALERT_BUF_EN","","", + /*M0-M7*/ "CPU0_RC_ERROR","CPU1_RC_ERROR","","OC_DETECT_EN", + "CPU0_THERMTRIP_LATCH_LVT3", + "CPU1_THERMTRIP_LATCH_LVT3","","", + /*N0-N7*/ "","","","CPU_MSMI_LVT3","","BIOS_SPI_BMC_CTRL","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "BOARD_SKU_ID0","BOARD_SKU_ID1","BOARD_SKU_ID2", + "BOARD_SKU_ID3","BOARD_SKU_ID4","BMC_PREQ", + "BMC_PWR_DEBUG","RST_RSMRST", + /*Q0-Q7*/ "","","","","UARTSW_LSB","UARTSW_MSB", + "POST_CARD_PRES_BMC","PE_BMC_WAKE", + /*R0-R7*/ "","","BMC_TCK_MUX_SEL","BMC_PRDY", + "BMC_XDP_PRSNT_IN","RST_BMC_PLTRST_BUF","SLT_CFG0", + "SLT_CFG1", + /*S0-S7*/ "THROTTLE","BMC_READY","","HSC_SMBUS_SWITCH_EN","", + "","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","BMC_FAULT","","", + /*V0-V7*/ "","","","FAST_PROCHOT_EN","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","GLOBAL_RST_WARN", + "CPU0_MEMABC_MEMHOT_LVT3_BMC", + "CPU0_MEMDEF_MEMHOT_LVT3_BMC", + "CPU1_MEMGHJ_MEMHOT_LVT3_BMC", + "CPU1_MEMKLM_MEMHOT_LVT3_BMC", + /*Y0-Y7*/ "SIO_S3","SIO_S5","BMC_JTAG_SEL","SIO_ONCONTROL","", + "","","", + /*Z0-Z7*/ "","SIO_POWER_GOOD","IRQ_PVDDQ_DEF_VRHOT_LVT3","", + "","","","", + /*AA0-AA7*/ "CPU1_SKTOCC_LVT3","IRQ_SML1_PMBUS_ALERT", + "SERVER_POWER_LED","","PECI_MUX_SELECT","UV_HIGH_SET", + "","POST_COMPLETE", + /*AB0-AB7*/ "IRQ_HSC_FAULT","OCP_MEZZA_PRES","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; }; &mac0 { @@ -368,6 +432,11 @@ &i2c4 { status = "okay"; // BMC Debug Header + ipmb0@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; }; &i2c5 { @@ -449,6 +518,11 @@ &i2c9 { status = "okay"; //USB Debug Connector + ipmb0@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; }; &pwm_tacho { diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts new file mode 100644 index 000000000000..8864e9c312a8 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (c) 2018 Facebook Inc. +/dts-v1/; +#include "aspeed-g5.dtsi" +#include <dt-bindings/i2c/i2c.h> + +/ { + model = "Facebook Yosemitev2 BMC"; + compatible = "facebook,yosemitev2-bmc", "aspeed,ast2500"; + aliases { + serial4 = &uart5; + }; + chosen { + stdout-path = &uart5; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + iio-hwmon { + // VOLATAGE SENSOR + compatible = "iio-hwmon"; + io-channels = <&adc 0> , <&adc 1> , <&adc 2> , <&adc 3> , + <&adc 4> , <&adc 5> , <&adc 6> , <&adc 7> , + <&adc 8> , <&adc 9> , <&adc 10>, <&adc 11> , + <&adc 12> , <&adc 13> , <&adc 14> , <&adc 15> ; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + }; +}; +&uart1 { + // Host1 Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart2 { + // Host2 Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; + +}; + +&uart3 { + // Host3 Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart4 { + // Host4 Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; +}; + +&uart5 { + // BMC Console + status = "okay"; +}; + +&vuart { + // Virtual UART + status = "okay"; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + use-ncsi; + mlx,multi-host; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&i2c1 { + //Host1 IPMB bus + status = "okay"; + multi-master; + ipmb1@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c3 { + //Host2 IPMB bus + status = "okay"; + multi-master; + ipmb3@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c5 { + //Host3 IPMB bus + status = "okay"; + multi-master; + ipmb5@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c7 { + //Host4 IPMB bus + status = "okay"; + multi-master; + ipmb7@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c8 { + status = "okay"; + //FRU EEPROM + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&i2c9 { + status = "okay"; + tmp421@4e { + //INLET TEMP + compatible = "ti,tmp421"; + reg = <0x4e>; + }; + //OUTLET TEMP + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; +}; + +&i2c10 { + status = "okay"; + //HSC + adm1278@40 { + compatible = "adi,adm1278"; + reg = <0x40>; + }; +}; + +&i2c11 { + status = "okay"; + //MEZZ_TEMP_SENSOR + tmp421@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; +}; + +&i2c12 { + status = "okay"; + //MEZZ_FRU + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&pwm_tacho { + status = "okay"; + //FSC + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 6232cd726a7f..bdfe342bf7c5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -4,6 +4,7 @@ #include "aspeed-g6.dtsi" #include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/leds/leds-pca955x.h> / { model = "Rainier"; @@ -32,6 +33,11 @@ no-map; reg = <0xB8000000 0x04000000>; /* 64M */ }; + + vga_memory: region@bf000000 { + no-map; + reg = <0xbf000000 0x01000000>; /* 16M */ + }; }; gpio-keys { @@ -64,6 +70,40 @@ }; +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "cfam-reset","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "presence-ps0","presence-ps1","presence-ps2","presence-ps3", + "","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + &emmc_controller { status = "okay"; }; @@ -72,6 +112,88 @@ status = "okay"; }; +&fsim0 { + status = "okay"; + + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ0: occ { + compatible = "ibm,p9-occ"; + }; + }; + + fsi_hub0: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +&fsi_hub0 { + cfam@1,0 { + reg = <1 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <1>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ1: occ { + compatible = "ibm,p9-occ"; + }; + }; + + fsi_hub1: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +/* Legacy OCC numbering (to get rid of when userspace is fixed) */ +&fsi_occ0 { + reg = <1>; +}; + +&fsi_occ1 { + reg = <2>; +}; + &ibt { status = "okay"; }; @@ -269,66 +391,82 @@ gpio@0 { reg = <0>; + type = <PCA955X_TYPE_GPIO>; }; gpio@1 { reg = <1>; + type = <PCA955X_TYPE_GPIO>; }; gpio@2 { reg = <2>; + type = <PCA955X_TYPE_GPIO>; }; gpio@3 { reg = <3>; + type = <PCA955X_TYPE_GPIO>; }; gpio@4 { reg = <4>; + type = <PCA955X_TYPE_GPIO>; }; gpio@5 { reg = <5>; + type = <PCA955X_TYPE_GPIO>; }; gpio@6 { reg = <6>; + type = <PCA955X_TYPE_GPIO>; }; gpio@7 { reg = <7>; + type = <PCA955X_TYPE_GPIO>; }; gpio@8 { reg = <8>; + type = <PCA955X_TYPE_GPIO>; }; gpio@9 { reg = <9>; + type = <PCA955X_TYPE_GPIO>; }; gpio@10 { reg = <10>; + type = <PCA955X_TYPE_GPIO>; }; gpio@11 { reg = <11>; + type = <PCA955X_TYPE_GPIO>; }; gpio@12 { reg = <12>; + type = <PCA955X_TYPE_GPIO>; }; gpio@13 { reg = <13>; + type = <PCA955X_TYPE_GPIO>; }; gpio@14 { reg = <14>; + type = <PCA955X_TYPE_GPIO>; }; gpio@15 { reg = <15>; + type = <PCA955X_TYPE_GPIO>; }; }; @@ -386,21 +524,6 @@ &i2c9 { status = "okay"; - ir35221@42 { - compatible = "infineon,ir35221"; - reg = <0x42>; - }; - - ir35221@43 { - compatible = "infineon,ir35221"; - reg = <0x43>; - }; - - ir35221@44 { - compatible = "infineon,ir35221"; - reg = <0x44>; - }; - tmp423a@4c { compatible = "ti,tmp423"; reg = <0x4c>; @@ -411,21 +534,6 @@ reg = <0x4d>; }; - ir35221@72 { - compatible = "infineon,ir35221"; - reg = <0x72>; - }; - - ir35221@73 { - compatible = "infineon,ir35221"; - reg = <0x73>; - }; - - ir35221@74 { - compatible = "infineon,ir35221"; - reg = <0x74>; - }; - eeprom@50 { compatible = "atmel,24c128"; reg = <0x50>; @@ -435,21 +543,6 @@ &i2c10 { status = "okay"; - ir35221@42 { - compatible = "infineon,ir35221"; - reg = <0x42>; - }; - - ir35221@43 { - compatible = "infineon,ir35221"; - reg = <0x43>; - }; - - ir35221@44 { - compatible = "infineon,ir35221"; - reg = <0x44>; - }; - tmp423a@4c { compatible = "ti,tmp423"; reg = <0x4c>; @@ -460,21 +553,6 @@ reg = <0x4d>; }; - ir35221@72 { - compatible = "infineon,ir35221"; - reg = <0x72>; - }; - - ir35221@73 { - compatible = "infineon,ir35221"; - reg = <0x73>; - }; - - ir35221@74 { - compatible = "infineon,ir35221"; - reg = <0x74>; - }; - eeprom@50 { compatible = "atmel,24c128"; reg = <0x50>; @@ -540,6 +618,10 @@ status = "okay"; }; +&vuart2 { + status = "okay"; +}; + &lpc_ctrl { status = "okay"; memory-region = <&flash_memory>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts index f7e935ede919..60e545b6396f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts @@ -8,6 +8,52 @@ model = "Mihawk BMC"; compatible = "ibm,mihawk-bmc", "aspeed,ast2500"; + aliases { + i2c215 = &bus6_mux215; + i2c216 = &bus6_mux216; + i2c217 = &bus6_mux217; + i2c218 = &bus6_mux218; + i2c219 = &bus6_mux219; + i2c220 = &bus6_mux220; + i2c221 = &bus6_mux221; + i2c222 = &bus6_mux222; + i2c223 = &bus7_mux223; + i2c224 = &bus7_mux224; + i2c225 = &bus7_mux225; + i2c226 = &bus7_mux226; + i2c227 = &bus7_mux227; + i2c228 = &bus7_mux228; + i2c229 = &bus7_mux229; + i2c230 = &bus7_mux230; + i2c231 = &bus9_mux231; + i2c232 = &bus9_mux232; + i2c233 = &bus9_mux233; + i2c234 = &bus9_mux234; + i2c235 = &bus9_mux235; + i2c236 = &bus9_mux236; + i2c237 = &bus9_mux237; + i2c238 = &bus9_mux238; + i2c239 = &bus10_mux239; + i2c240 = &bus10_mux240; + i2c241 = &bus10_mux241; + i2c242 = &bus10_mux242; + i2c243 = &bus10_mux243; + i2c244 = &bus10_mux244; + i2c245 = &bus10_mux245; + i2c246 = &bus10_mux246; + i2c247 = &bus12_mux247; + i2c248 = &bus12_mux248; + i2c249 = &bus12_mux249; + i2c250 = &bus12_mux250; + i2c251 = &bus13_mux251; + i2c252 = &bus13_mux252; + i2c253 = &bus13_mux253; + i2c254 = &bus13_mux254; + i2c255 = &bus13_mux255; + i2c256 = &bus13_mux256; + i2c257 = &bus13_mux257; + i2c258 = &bus13_mux258; + }; chosen { stdout-path = &uart5; @@ -120,35 +166,24 @@ leds { compatible = "gpio-leds"; - fault { + front-fault { retain-state-shutdown; default-state = "keep"; gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; }; - power { + power-button { retain-state-shutdown; default-state = "keep"; gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>; }; - rear-id { + front-id { retain-state-shutdown; default-state = "keep"; gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; }; - rear-g { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_LOW>; - }; - - rear-ok { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(Y, 0) GPIO_ACTIVE_LOW>; - }; fan0 { retain-state-shutdown; @@ -630,6 +665,54 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + + bus7_mux223: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus7_mux224: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus7_mux225: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus7_mux226: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + bus7_mux227: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + bus7_mux228: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + bus7_mux229: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + bus7_mux230: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; }; }; @@ -644,6 +727,54 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + + bus6_mux215: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus6_mux216: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus6_mux217: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus6_mux218: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + bus6_mux219: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + bus6_mux220: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + bus6_mux221: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + bus6_mux222: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; }; }; @@ -684,6 +815,30 @@ i2c-mux-idle-disconnect; interrupt-controller; #interrupt-cells = <2>; + + bus9_mux231: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus9_mux232: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus9_mux233: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus9_mux234: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; }; pca9545@71 { @@ -695,6 +850,30 @@ i2c-mux-idle-disconnect; interrupt-controller; #interrupt-cells = <2>; + + bus9_mux235: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus9_mux236: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus9_mux237: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus9_mux238: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; }; }; @@ -725,6 +904,30 @@ i2c-mux-idle-disconnect; interrupt-controller; #interrupt-cells = <2>; + + bus10_mux239: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus10_mux240: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus10_mux241: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus10_mux242: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; }; pca9545@71 { @@ -736,6 +939,30 @@ i2c-mux-idle-disconnect; interrupt-controller; #interrupt-cells = <2>; + + bus10_mux243: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus10_mux244: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus10_mux245: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus10_mux246: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; }; }; @@ -796,7 +1023,7 @@ interrupt-controller; #interrupt-cells = <2>; - i2c@0 { + bus12_mux247: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; @@ -807,7 +1034,7 @@ }; }; - i2c@1 { + bus12_mux248: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; @@ -818,7 +1045,7 @@ }; }; - i2c@2 { + bus12_mux249: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; @@ -829,7 +1056,7 @@ }; }; - i2c@3 { + bus12_mux250: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; @@ -857,6 +1084,53 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + bus13_mux251: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus13_mux252: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus13_mux253: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus13_mux254: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + bus13_mux255: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + bus13_mux256: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + bus13_mux257: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + bus13_mux258: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; }; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts new file mode 100644 index 000000000000..91dced7e7849 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2019 YADRO +/dts-v1/; +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> + +/ { + model = "Nicole BMC"; + compatible = "yadro,nicole-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + + coldfire_memory: codefire_memory@9ef00000 { + reg = <0x9ef00000 0x00100000>; + no-map; + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + power { + label = "platform:green:power"; + gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>; + }; + + identify { + label = "platform:blue:indicator"; + gpios = <&gpio ASPEED_GPIO(AA, 7) GPIO_ACTIVE_HIGH>; + }; + + fault { + label = "platform:red:fault"; + gpios = <&gpio ASPEED_GPIO(AA, 3) GPIO_ACTIVE_HIGH>; + }; + + attention { + label = "platform:yellow:alarm"; + gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_HIGH>; + }; + }; + + fsi: gpio-fsi { + compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + no-gpio-delays; + + memory-region = <&coldfire_memory>; + aspeed,sram = <&sram>; + aspeed,cvic = <&cvic>; + + clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(J, 2)>; + }; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + use-ncsi; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; +}; + +&i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + }; +}; + +&i2c2 { + status = "okay"; + /* CPU0 characterization connector */ +}; + +&i2c3 { + status = "okay"; + /* CLK GEN SI5338 */ +}; + +&i2c4 { + status = "okay"; + /* Voltage regulators for CPU0 */ +}; + +&i2c5 { + status = "okay"; + /* Voltage regulators for CPU1 */ +}; + +&i2c6 { + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&i2c7 { + status = "okay"; + /* CPLD */ +}; + +&gpio { + gpio-line-names = + /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "fsi-enable","bmc_power_up","sys_pwrok_buf", + "func_mode0","func_mode1","func_mode2","","", + /*E0-E7*/ "","ncsi_cfg","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","checkstop","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","power-button","","","","","", + /*P0-P7*/ "","fsi-trans","pm_rtc_adc_en","","","","","", + /*Q0-Q7*/ "","","","","","","","id-button", + /*R0-R7*/ "","software_pwrgood","","","","","","", + /*S0-S7*/ "","","","","","","","seq_cont", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "fsi-clock","led-attention","fsi-data","led-fault", + "led-power","","","led-identify", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; + + func_mode0 { + gpio-hog; + gpios = <ASPEED_GPIO(D, 3) GPIO_ACTIVE_HIGH>; + output-low; + }; + func_mode1 { + gpio-hog; + gpios = <ASPEED_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + output-low; + }; + func_mode2 { + gpio-hog; + gpios = <ASPEED_GPIO(D, 5) GPIO_ACTIVE_HIGH>; + output-low; + }; + seq_cont { + gpio-hog; + gpios = <ASPEED_GPIO(S, 7) GPIO_ACTIVE_HIGH>; + output-low; + }; + ncsi_cfg { + gpio-hog; + input; + gpios = <ASPEED_GPIO(E, 1) GPIO_ACTIVE_HIGH>; + }; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&ibt { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&adc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index edfa44fe1f75..fd2e014dae75 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -231,23 +231,52 @@ }; &gpio { + gpio-line-names = + /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "fsi-enable","","","nic_func_mode0","nic_func_mode1","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","power-button","","","","", + /*J0-J7*/ "","","checkstop","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","led-fault","", + "led-identify","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","id-button", + /*R0-R7*/ "","","fsi-trans","","","led-power","","", + /*S0-S7*/ "","","","","","","","seq_cont", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "fsi-clock","","fsi-data","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; + nic_func_mode0 { gpio-hog; gpios = <ASPEED_GPIO(D, 3) GPIO_ACTIVE_HIGH>; output-low; - line-name = "nic_func_mode0"; }; nic_func_mode1 { gpio-hog; gpios = <ASPEED_GPIO(D, 4) GPIO_ACTIVE_HIGH>; output-low; - line-name = "nic_func_mode1"; }; seq_cont { gpio-hog; gpios = <ASPEED_GPIO(S, 7) GPIO_ACTIVE_HIGH>; output-low; - line-name = "seq_cont"; }; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index ff49ec76fa7c..13c4aa02f4de 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -34,6 +34,59 @@ gpio-keys { compatible = "gpio-keys"; + checkstop { + label = "checkstop"; + gpios = <&gpio0 ASPEED_GPIO(E, 3) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(E, 3)>; + }; + + ps0-presence { + label = "ps0-presence"; + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(H, 3)>; + }; + + ps1-presence { + label = "ps1-presence"; + gpios = <&gpio0 ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(E, 5)>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&pca0 4 GPIO_ACTIVE_LOW>; + linux,code = <4>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&pca0 5 GPIO_ACTIVE_LOW>; + linux,code = <5>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&pca0 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&pca0 7 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + air-water { label = "air-water"; gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_LOW>; @@ -89,6 +142,49 @@ linux,code = <7>; }; }; + + iio-hwmon-dps310 { + compatible = "iio-hwmon"; + io-channels = <&dps 0>; + }; + + iio-hwmon-bmp280 { + compatible = "iio-hwmon"; + io-channels = <&bmp 1>; + }; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "fsi-mux","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "power-button","","","checkstop","","presence-ps1","","led-rear-fault", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","presence-ps0","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "led-rear-power","led-rear-id","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "cfam-reset","","","","","","","fsi-routing", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; }; &fmc { @@ -132,6 +228,10 @@ use-ncsi; }; +&emmc_controller { + status = "okay"; +}; + &emmc { status = "okay"; }; @@ -142,6 +242,9 @@ #address-cells = <2>; #size-cells = <0>; + fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; + fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; + cfam@0,0 { reg = <0 0>; #address-cells = <1>; @@ -394,6 +497,11 @@ &i2c1 { status = "okay"; + + tpm: tpm@2e { + compatible = "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; }; &i2c2 { @@ -774,6 +882,10 @@ status = "okay"; }; +&vuart2 { + status = "okay"; +}; + &lpc_ctrl { status = "okay"; memory-region = <&flash_memory>; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index 421aa600148b..a0f99e34ac8e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -191,6 +191,40 @@ }; +&gpio { + gpio-line-names = + /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", + /*B0-B7*/ "","","","","","air-water","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "fsi-enable","","","","","","","", + /*E0-E7*/ "fsi-data","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","checkstop","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "presence-ps1","","led-rear-fault","led-rear-power", + "led-rear-id","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","presence-ps0", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","fsi-trans","","","power-button","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "fsi-clock","","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + &fmc { status = "okay"; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts index bc60ec291681..4bcc82046362 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -478,32 +478,61 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpioh_unbiased>; + gpio-line-names = + /*A0-A7*/ "","cfam-reset","","","","","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "fsi-enable","","","","","led-sys-boot-status","led-attention", + "led-fault", + /*E0-E7*/ "","","","","","","","presence-pcie-e2b", + /*F0-F7*/ "","","","","","","","checkstop", + /*G0-G7*/ "fsi-clock","fsi-data","","","","","","", + /*H0-H7*/ "onewire0","onewire1","onewire2","onewire3","","","","", + /*I0-I7*/ "","","","power-button","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","iso_u164_en","","fsi-trans","", + /*P0-P7*/ "ncsi_mux_en_n","bmc_i2c2_sw_rst_n","","bmc_i2c5_sw_rst_n","", + "","fsi-mux","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","led-hdd-fault","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; + line_iso_u146_en { gpio-hog; gpios = <ASPEED_GPIO(O, 4) GPIO_ACTIVE_HIGH>; output-high; - line-name = "iso_u164_en"; }; ncsi_mux_en_n { gpio-hog; gpios = <ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>; output-low; - line-name = "ncsi_mux_en_n"; }; line_bmc_i2c2_sw_rst_n { gpio-hog; gpios = <ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>; output-high; - line-name = "bmc_i2c2_sw_rst_n"; }; line_bmc_i2c5_sw_rst_n { gpio-hog; gpios = <ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>; output-high; - line-name = "bmc_i2c5_sw_rst_n"; }; }; diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 807a0fc20670..82f0213e3a3c 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -164,6 +164,8 @@ reg = <0x1e6a0000 0x300>; interrupts = <5>; clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + aspeed,vhub-downstream-ports = <5>; + aspeed,vhub-generic-endpoints = <15>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2d_default>; status = "disabled"; @@ -217,6 +219,16 @@ reg = <0x1e720000 0x8000>; // 32K }; + video: video@1e700000 { + compatible = "aspeed,ast2400-video-engine"; + reg = <0x1e700000 0x1000>; + clocks = <&syscon ASPEED_CLK_GATE_VCLK>, + <&syscon ASPEED_CLK_GATE_ECLK>; + clock-names = "vclk", "eclk"; + interrupts = <7>; + status = "disabled"; + }; + sdmmc: sd-controller@1e740000 { compatible = "aspeed,ast2400-sd-controller"; reg = <0x1e740000 0x100>; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index ebec0fa8baa7..de7fd80b022a 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -195,6 +195,8 @@ reg = <0x1e6a0000 0x300>; interrupts = <5>; clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + aspeed,vhub-downstream-ports = <5>; + aspeed,vhub-generic-endpoints = <15>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2ad_default>; status = "disabled"; @@ -222,6 +224,14 @@ #clock-cells = <1>; #reset-cells = <1>; + scu_ic: interrupt-controller@18 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2500-scu-ic"; + reg = <0x18 0x4>; + interrupts = <21>; + interrupt-controller; + }; + p2a: p2a-control@2c { compatible = "aspeed,ast2500-p2a-ctrl"; reg = <0x2c 0x4>; @@ -252,6 +262,17 @@ interrupts = <0x19>; }; + xdma: xdma@1e6e7000 { + compatible = "aspeed,ast2500-xdma"; + reg = <0x1e6e7000 0x100>; + clocks = <&syscon ASPEED_CLK_GATE_BCLK>; + resets = <&syscon ASPEED_RESET_XDMA>; + interrupts-extended = <&vic 6>, <&scu_ic 2>; + pcie-device = "bmc"; + aspeed,scu = <&syscon>; + status = "disabled"; + }; + adc: adc@1e6e9000 { compatible = "aspeed,ast2500-adc"; reg = <0x1e6e9000 0xb0>; @@ -424,22 +445,22 @@ #size-cells = <1>; ranges = <0x0 0x0 0x80>; - kcs1: kcs1@0 { - compatible = "aspeed,ast2500-kcs-bmc"; + kcs1: kcs@24 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; interrupts = <8>; - kcs_chan = <1>; status = "disabled"; }; - kcs2: kcs2@0 { - compatible = "aspeed,ast2500-kcs-bmc"; + kcs2: kcs@28 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; interrupts = <8>; - kcs_chan = <2>; status = "disabled"; }; - kcs3: kcs3@0 { - compatible = "aspeed,ast2500-kcs-bmc"; + kcs3: kcs@2c { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; interrupts = <8>; - kcs_chan = <3>; status = "disabled"; }; }; @@ -453,10 +474,10 @@ #size-cells = <1>; ranges = <0x0 0x80 0x1e0>; - kcs4: kcs4@0 { - compatible = "aspeed,ast2500-kcs-bmc"; + kcs4: kcs@94 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>; interrupts = <8>; - kcs_chan = <4>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi index 045ce66ca876..7028e21bdd98 100644 --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi @@ -1112,6 +1112,31 @@ groups = "UART9"; }; + pinctrl_usb2ah_default: usb2ah_default { + function = "USB2AH"; + groups = "USBA"; + }; + + pinctrl_usb2ad_default: usb2ad_default { + function = "USB2AD"; + groups = "USBA"; + }; + + pinctrl_usb2bh_default: usb2bh_default { + function = "USB2BH"; + groups = "USBB"; + }; + + pinctrl_usb2bd_default: usb2bd_default { + function = "USB2BD"; + groups = "USBB"; + }; + + pinctrl_usb11bhid_default: usb11bhid_default { + function = "USB11BHID"; + groups = "USBB"; + }; + pinctrl_vb_default: vb_default { function = "VB"; groups = "VB"; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 796976d275e1..9d8d8e18bc90 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -65,6 +65,7 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; clocks = <&syscon ASPEED_CLK_HPLL>; arm,cpu-registers-not-fw-configured; + always-on; }; ahb { @@ -245,6 +246,51 @@ status = "disabled"; }; + ehci0: usb@1e6a1000 { + compatible = "aspeed,ast2600-ehci", "generic-ehci"; + reg = <0x1e6a1000 0x100>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2ah_default>; + status = "disabled"; + }; + + ehci1: usb@1e6a3000 { + compatible = "aspeed,ast2600-ehci", "generic-ehci"; + reg = <0x1e6a3000 0x100>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2bh_default>; + status = "disabled"; + }; + + uhci: usb@1e6b0000 { + compatible = "aspeed,ast2600-uhci", "generic-uhci"; + reg = <0x1e6b0000 0x100>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #ports = <2>; + clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; + status = "disabled"; + /* + * No default pinmux, it will follow EHCI, use an + * explicit pinmux override if EHCI is not enabled. + */ + }; + + vhub: usb-vhub@1e6a0000 { + compatible = "aspeed,ast2600-usb-vhub"; + reg = <0x1e6a0000 0x350>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; + aspeed,vhub-downstream-ports = <7>; + aspeed,vhub-generic-endpoints = <21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2ad_default>; + status = "disabled"; + }; + apb { compatible = "simple-bus"; #address-cells = <1>; @@ -268,6 +314,22 @@ compatible = "aspeed,ast2600-smpmem"; reg = <0x180 0x40>; }; + + scu_ic0: interrupt-controller@560 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2600-scu-ic0"; + reg = <0x560 0x4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + }; + + scu_ic1: interrupt-controller@570 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2600-scu-ic1"; + reg = <0x570 0x4>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + }; }; rng: hwrng@1e6e2524 { @@ -277,6 +339,29 @@ quality = <100>; }; + xdma: xdma@1e6e7000 { + compatible = "aspeed,ast2600-xdma"; + reg = <0x1e6e7000 0x100>; + clocks = <&syscon ASPEED_CLK_GATE_BCLK>; + resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>; + reset-names = "device", "root-complex"; + interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <&scu_ic0 2>; + pcie-device = "bmc"; + aspeed,scu = <&syscon>; + status = "disabled"; + }; + + video: video@1e700000 { + compatible = "aspeed,ast2600-video-engine"; + reg = <0x1e700000 0x1000>; + clocks = <&syscon ASPEED_CLK_GATE_VCLK>, + <&syscon ASPEED_CLK_GATE_ECLK>; + clock-names = "vclk", "eclk"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + gpio0: gpio@1e780000 { #gpio-cells = <2>; gpio-controller; @@ -323,6 +408,7 @@ <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&syscon ASPEED_CLK_APB1>; clock-names = "PCLK"; + status = "disabled"; }; uart1: serial@1e783000 { @@ -388,22 +474,23 @@ #size-cells = <1>; ranges = <0x0 0x0 0x80>; - kcs1: kcs1@0 { - compatible = "aspeed,ast2600-kcs-bmc"; + kcs1: kcs@24 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; kcs_chan = <1>; status = "disabled"; }; - kcs2: kcs2@0 { - compatible = "aspeed,ast2600-kcs-bmc"; + kcs2: kcs@28 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; - kcs_chan = <2>; status = "disabled"; }; - kcs3: kcs3@0 { - compatible = "aspeed,ast2600-kcs-bmc"; + kcs3: kcs@2c { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; - kcs_chan = <3>; status = "disabled"; }; }; @@ -417,10 +504,10 @@ #size-cells = <1>; ranges = <0x0 0x80 0x1e0>; - kcs4: kcs4@0 { - compatible = "aspeed,ast2600-kcs-bmc"; + kcs4: kcs@94 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; - kcs_chan = <4>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi index 21876da7c442..c1c8650dafce 100644 --- a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi +++ b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi @@ -62,7 +62,7 @@ wm8904: wm8904@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - clocks = <&pck2>; + clocks = <&pmc PMC_TYPE_SYSTEM 10>; clock-names = "mclk"; }; }; diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi b/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi index df0f0cc575c1..bea920b192b6 100644 --- a/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi +++ b/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi @@ -17,7 +17,7 @@ }; panel: panel { - compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92", "simple-panel"; + compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92"; backlight = <&backlight>; power-supply = <&vcc_lcd_reg>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/at91-kizbox3-hs.dts b/arch/arm/boot/dts/at91-kizbox3-hs.dts index 8734e7f8939e..0da1f0557eaf 100644 --- a/arch/arm/boot/dts/at91-kizbox3-hs.dts +++ b/arch/arm/boot/dts/at91-kizbox3-hs.dts @@ -283,7 +283,7 @@ &flx3 { status = "okay"; - uart6: serial@200 { + uart8: serial@200 { status = "okay"; }; }; @@ -291,7 +291,7 @@ &flx4 { status = "okay"; - i2c2: i2c@600 { + i2c6: i2c@600 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91-kizbox3_common.dtsi b/arch/arm/boot/dts/at91-kizbox3_common.dtsi index 299e74d23184..7c3076e245ef 100644 --- a/arch/arm/boot/dts/at91-kizbox3_common.dtsi +++ b/arch/arm/boot/dts/at91-kizbox3_common.dtsi @@ -28,7 +28,7 @@ serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; - serial6 = &uart6; + serial6 = &uart8; }; chosen { @@ -207,7 +207,7 @@ }; }; - pinctrl_flx4_default: flx4_i2c2_default { + pinctrl_flx4_default: flx4_i2c6_default { pinmux = <PIN_PD12__FLEXCOM4_IO0>, //DATA <PIN_PD13__FLEXCOM4_IO1>; //CLK bias-disable; @@ -299,21 +299,8 @@ status = "disabled"; uart5: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x400>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(11))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(12))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "usart"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx0_default>; - atmel,fifo-size = <32>; atmel,use-dma-rx; atmel,use-dma-tx; status = "disabled"; @@ -324,22 +311,9 @@ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; status = "disabled"; - uart6: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x400>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(17))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(18))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "usart"; + uart8: serial@200 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx3_default>; - atmel,fifo-size = <32>; atmel,use-dma-rx; atmel,use-dma-tx; status = "disabled"; @@ -350,23 +324,9 @@ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; status = "disabled"; - i2c2: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(19))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(20))>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + i2c6: i2c@600 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <16>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index 9f30132d7d7b..a5f5718c711a 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -542,6 +542,18 @@ }; }; + sdmmc1 { + pinctrl_sdmmc1_default: sdmmc1 { + atmel,pins = + <AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */ + AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */ + AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */ + AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */ + AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */ + AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */ + }; + }; + gpio_keys { pinctrl_key_gpio_default: pinctrl_key_gpio { atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; @@ -568,6 +580,15 @@ disable-wp; }; +&sdmmc1 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + no-1-8-v; + non-removable; + status = "disabled"; /* Conflict with flx4. */ +}; + &qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; @@ -579,6 +600,8 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; m25p,fast-read; at91bootstrap@0 { @@ -645,3 +668,8 @@ &usb2 { status = "okay"; }; + +&watchdog { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi index 6281590150c8..b1f994c0ae79 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi @@ -13,6 +13,10 @@ model = "Atmel SAMA5D27 SoM1"; compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + aliases { + i2c0 = &i2c0; + }; + clocks { slow_xtal { clock-frequency = <32768>; @@ -34,12 +38,44 @@ pinctrl-0 = <&pinctrl_qspi1_default>; flash@0 { + #address-cells = <1>; + #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <80000000>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; m25p,fast-read; + + at91bootstrap@00000000 { + label = "at91bootstrap"; + reg = <0x00000000 0x00040000>; + }; + + bootloader@00040000 { + label = "bootloader"; + reg = <0x00040000 0x000c0000>; + }; + + bootloaderenvred@00100000 { + label = "bootloader env redundant"; + reg = <0x00100000 0x00040000>; + }; + + bootloaderenv@00140000 { + label = "bootloader env"; + reg = <0x00140000 0x00040000>; + }; + + dtb@00180000 { + label = "device tree"; + reg = <0x00180000 0x00080000>; + }; + + kernel@00200000 { + label = "kernel"; + reg = <0x00200000 0x00600000>; + }; }; }; @@ -57,7 +93,25 @@ }; }; + i2c0: i2c@f8028000 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + status = "okay"; + + at24@50 { + compatible = "24c02"; + reg = <0x50>; + pagesize = <8>; + }; + }; + pinctrl@fc038000 { + pinctrl_i2c0_default: i2c0_default { + pinmux = <PIN_PD21__TWD0>, + <PIN_PD22__TWCK0>; + bias-disable; + }; pinctrl_qspi1_default: qspi1_default { sck_cs { diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index b0853bf7901c..0e159f879c15 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -21,7 +21,7 @@ serial1 = &uart4; /* mikro BUS 1 */ serial2 = &uart2; /* mikro BUS 2 */ i2c1 = &i2c1; - i2c2 = &i2c2; + i2c2 = &i2c3; }; chosen { @@ -125,21 +125,13 @@ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; status = "okay"; - i2c2: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + i2c3: i2c@600 { dmas = <0>, <0>; - dma-names = "tx", "rx"; i2c-analog-filter; i2c-digital-filter; i2c-digital-filter-width-ns = <35>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus_i2c>; - atmel,fifo-size = <16>; status = "okay"; }; }; @@ -178,27 +170,17 @@ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>; status = "disabled"; - uart7: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "usart"; + uart8: serial@200 { + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx3_default>; - atmel,fifo-size = <32>; status = "disabled"; /* Conflict with isc. */ }; - spi2: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "spi_clk"; + spi5: spi@400 { + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx3_default>; - atmel,fifo-size = <16>; status = "disabled"; /* Conflict with isc. */ }; }; @@ -207,43 +189,25 @@ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>; status = "okay"; - uart6: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "usart"; + uart9: serial@200 { + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <32>; - status = "disabled"; /* Conflict with spi3 and i2c3. */ + status = "disabled"; /* Conflict with spi6 and i2c6. */ }; - spi3: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "spi_clk"; + spi6: spi@400 { + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>; - atmel,fifo-size = <16>; - status = "okay"; /* Conflict with uart6 and i2c3. */ + status = "okay"; /* Conflict with uart5 and i2c6. */ }; - i2c3: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + i2c6: i2c@600 { dmas = <0>, <0>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <16>; - status = "disabled"; /* Conflict with uart6 and spi3. */ + status = "disabled"; /* Conflict with uart5 and spi6. */ }; }; diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi index db3e2239eee8..a06700e53e4c 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi @@ -17,6 +17,10 @@ model = "Microchip SAMA5D27 WLSOM1"; compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + aliases { + i2c0 = &i2c0; + }; + clocks { slow_xtal { clock-frequency = <32768>; @@ -32,18 +36,6 @@ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; uart6: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(13))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(14))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - clock-names = "usart"; pinctrl-0 = <&pinctrl_flx1_default>; pinctrl-names = "default"; }; diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts index 0b9fa2942dff..6b38fa3f5568 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts @@ -77,18 +77,6 @@ status = "okay"; uart5: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(11))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(12))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "usart"; pinctrl-0 = <&pinctrl_flx0_default>; pinctrl-names = "default"; atmel,use-dma-rx; @@ -186,6 +174,11 @@ pinmux = <PIN_PA10__GPIO>; bias-disable; }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = <PIN_PA16__GPIO>; + bias-disable; + }; }; &pwm0 { @@ -248,6 +241,13 @@ status = "okay"; }; +&usb0 { + atmel,vbus-gpio = <&pioA PIN_PA16 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + &usb1 { num-ports = <3>; atmel,vbus-gpio = <0 diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts new file mode 100644 index 000000000000..8d19925fc09e --- /dev/null +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -0,0 +1,767 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama5d2_icp.dts - Device Tree file for SAMA5D2-ICP board + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Radu Pirea & Razvan Stefanescu, + * Codrin Ciubotariu <codrin.ciubotariu@microchip.com>, + * Cristian Birsan <cristian.birsan@microchip.com> + */ +/dts-v1/; +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/mfd/atmel-flexcom.h> + +/ { + model = "Microchip SAMA5D2-ICP"; + compatible = "microchip,sama5d2-icp", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + + aliases { + serial0 = &uart0; /* debug uart0 + mikro BUS 1 */ + serial1 = &uart1; /* mikro BUS 3 */ + serial3 = &uart3; /* mikro BUS 2 */ + serial5 = &uart7; /* flx2 */ + i2c0 = &i2c0; + i2c1 = &i2c1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + status = "okay"; + + sw4 { + label = "USER_PB1"; + gpios = <&pioA PIN_PD0 GPIO_ACTIVE_LOW>; + linux,code = <0x104>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + status = "okay"; /* conflict with pwm0 */ + + red { + label = "red"; + gpios = <&pioA PIN_PB0 GPIO_ACTIVE_HIGH>; + }; + + green { + label = "green"; + gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; + }; + + blue { + label = "blue"; + gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&adc { + vddana-supply = <&vdd_io_reg>; + vref-supply = <&vdd_io_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; + status = "okay"; +}; + +&flx0 { /* mikrobus2 spi */ + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>; + status = "okay"; + + spi2: spi@400 { + dmas = <0>, <0>; + cs-gpios = <&pioA PIN_PC0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus2_spi &pinctrl_ksz_spi_cs>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + switch0: ksz8563@0 { + compatible = "microchip,ksz8563"; + reg = <0>; + phy-mode = "mii"; + reset-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_LOW>; + + spi-max-frequency = <500000>; + spi-cpha; + spi-cpol; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "cpu"; + ethernet = <&macb0>; + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&flx2 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; + status = "okay"; + + uart7: serial@200 { + pinctrl-0 = <&pinctrl_flx2_default>; + pinctrl-names = "default"; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; /* Conflict w/ qspi1. */ + }; +}; + +&flx3 { /* mikrobus1 spi */ + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>; + status = "okay"; + + spi5: spi@400 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>; + status = "okay"; + }; +}; + +&flx4 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; + status = "okay"; + + i2c6: i2c@600 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx4_default>; + status = "okay"; + + mcp16502@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + status = "okay"; + lpm-gpios = <&pioBU 7 GPIO_ACTIVE_LOW>; + + regulators { + vdd_io_reg: VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1850000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1850000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1850000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + }; + }; + }; +}; + +&i2c0 { /* mikrobus i2c */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus_i2c>; + status = "okay"; +}; + +&i2c1 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <16>; + status = "okay"; + }; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <16>; + status = "disabled"; + }; + + eeprom@53 { + compatible = "atmel,24c32"; + reg = <0x53>; + pagesize = <16>; + status = "disabled"; + }; +}; + +&macb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq &pinctrl_macb0_rst>; + phy-mode = "mii"; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +&pioA { + pinctrl_adc_default: adc_default { + pinmux = <PIN_PD24__GPIO>, + <PIN_PD25__GPIO>, + <PIN_PD26__GPIO>; + bias-disable; + }; + + /* + * The ADTRG pin can work on any edge type. + * In here it's being pulled up, so need to + * connect it to ground to get an edge e.g. + * Trigger can be configured on falling, rise + * or any edge, and the pull-up can be changed + * to pull-down or left floating according to + * needs. + */ + pinctrl_adtrg_default: adtrg_default { + pinmux = <PIN_PD31__ADTRG>; + bias-pull-up; + }; + + pinctrl_flx4_default: flx4_default { + pinmux = <PIN_PC28__FLEXCOM4_IO0>, + <PIN_PC29__FLEXCOM4_IO1>; + bias-disable; + }; + + pinctrl_can0_default: can0_default { + pinmux = <PIN_PC10__CANTX0>, + <PIN_PC11__CANRX0>; + bias-disable; + }; + + pinctrl_can1_default: can1_default { + pinmux = <PIN_PC26__CANTX1>, + <PIN_PC27__CANRX1>; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PD19__TWD1>, + <PIN_PD20__TWCK1>; + bias-disable; + }; + + pinctrl_key_gpio_default: key_gpio_default { + pinmux = <PIN_PD0__GPIO>; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led_gpio_default { + pinmux = <PIN_PB0__GPIO>, + <PIN_PB1__GPIO>, + <PIN_PA31__GPIO>; + bias-pull-up; + }; + + pinctrl_qspi1_default: qspi1_default { + pinmux = <PIN_PA6__QSPI1_SCK>, + <PIN_PA7__QSPI1_IO0>, + <PIN_PA8__QSPI1_IO1>, + <PIN_PA9__QSPI1_IO2>, + <PIN_PA10__QSPI1_IO3>, + <PIN_PA11__QSPI1_CS>; + bias-disable; + }; + + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_data { + pinmux = <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_DAT0>, + <PIN_PA3__SDMMC0_DAT1>, + <PIN_PA4__SDMMC0_DAT2>, + <PIN_PA5__SDMMC0_DAT3>; + bias-disable; + }; + + ck_cd { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA13__SDMMC0_CD>; + bias-disable; + }; + }; + + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_data { + pinmux = <PIN_PA18__SDMMC1_DAT0>, + <PIN_PA19__SDMMC1_DAT1>, + <PIN_PA20__SDMMC1_DAT2>, + <PIN_PA21__SDMMC1_DAT3>; + bias-disable; + }; + + ck_cd { + pinmux = <PIN_PA22__SDMMC1_CK>, + <PIN_PA28__SDMMC1_CMD>; + bias-disable; + }; + }; + + pinctrl_mikrobus_i2c: mikrobus_i2c { + pinmux = <PIN_PD22__TWCK0>, + <PIN_PD21__TWD0>; + bias-disable; + }; + + pinctrl_mikrobus1_an: mikrobus1_an { + pinmux = <PIN_PD26__GPIO>; + bias-disable; + }; + + pinctrl_mikrobus1_rst: mikrobus1_rst { + pinmux = <PIN_PC5__GPIO>; + bias-disable; + }; + + pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { + pinmux = <PIN_PC21__FLEXCOM3_IO3>; + bias-disable; + }; + + pinctrl_mikrobus1_spi: mikrobus1_spi { + pinmux = <PIN_PC20__FLEXCOM3_IO0>, + <PIN_PC19__FLEXCOM3_IO1>, + <PIN_PC18__FLEXCOM3_IO2>; + bias-disable; + }; + + pinctrl_mikrobus1_pwm: mikrobus1_pwm { + pinmux = <PIN_PC4__TIOB1>; + bias-disable; + }; + + pinctrl_mikrobus1_int: mikrobus1_int { + pinmux = <PIN_PC3__GPIO>; + bias-disable; + }; + + pinctrl_mikrobus1_uart: mikrobus1_uart { + pinmux = <PIN_PB26__URXD0>, + <PIN_PB27__UTXD0>; + bias-disable; + }; + + pinctrl_mikrobus2_an: mikrobus2_an { + pinmux = <PIN_PD25__GPIO>; + bias-disable; + }; + + pinctrl_mikrobus2_rst: mikrobus2_rst { + pinmux = <PIN_PB24__GPIO>; + bias-disable; + }; + + pinctrl_mikrobus2_spi_cs: mikrobus2_spi_cs { + pinmux = <PIN_PB31__FLEXCOM0_IO3>; + bias-disable; + }; + + pinctrl_mikrobus2_spi: mikrobus2_spi { + pinmux = <PIN_PB28__FLEXCOM0_IO0>, + <PIN_PB29__FLEXCOM0_IO1>, + <PIN_PB30__FLEXCOM0_IO2>; + bias-disable; + }; + + pinctrl_ksz_spi_cs: ksz_spi_cs { + pinmux = <PIN_PC0__GPIO>; + bias-disable; + }; + + pinctrl_mikrobus2_pwm: mikrobus2_pwm { + pinmux = <PIN_PB23__TIOB2>; + bias-disable; + }; + + pinctrl_mikrobus2_int: mikrobus2_int { + pinmux = <PIN_PB22__GPIO>; + bias-disable; + }; + + pinctrl_mikrobus2_uart: mikrobus2_uart { + pinmux = <PIN_PC12__URXD3>, + <PIN_PC13__UTXD3>; + bias-disable; + }; + + pinctrl_mikrobus3_an: mikrobus3_an { + pinmux = <PIN_PD24__GPIO>; + bias-disable; + }; + + pinctrl_mikrobus3_rst: mikrobus3_rst { + pinmux = <PIN_PB21__GPIO>; + bias-disable; + }; + + pinctrl_mikrobus3_spi_cs: mikrobus3_spi_cs { + pinmux = <PIN_PA17__SPI0_NPCS0>; + bias-disable; + }; + + pinctrl_mikrobus3_spi: mikrobus3_spi { + pinmux = <PIN_PA14__SPI0_SPCK>, + <PIN_PA16__SPI0_MISO>, + <PIN_PA15__SPI0_MOSI>; + bias-disable; + }; + + pinctrl_mikrobus3_pwm: mikrobus3_pwm { + pinmux = <PIN_PB20__TIOB3>; + bias-disable; + }; + + pinctrl_mikrobus3_int: mikrobus3_int { + pinmux = <PIN_PB18__GPIO>; + bias-disable; + }; + + pinctrl_mikrobus3_uart: mikrobus3_uart { + pinmux = <PIN_PC7__URXD1>, + <PIN_PC8__UTXD1>; + bias-disable; + }; + + pinctrl_usb_default: usb_default { + pinmux = <PIN_PC17__GPIO>; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = <PIN_PD23__GPIO>; + bias-disable; + }; + + pinctrl_pwm0_pwm2_default: pwm0_pwm2_default { + pinmux = <PIN_PB5__PWMH2>, + <PIN_PB6__PWML2>; + bias-pull-up; + }; + + pinctrl_macb0_default: macb0_default { + pinmux = <PIN_PD1__GRXCK>, + <PIN_PD2__GTXER>, + <PIN_PD5__GRX2>, + <PIN_PD6__GRX3>, + <PIN_PD7__GTX2>, + <PIN_PD8__GTX3>, + <PIN_PD9__GTXCK>, + <PIN_PD10__GTXEN>, + <PIN_PD11__GRXDV>, + <PIN_PD12__GRXER>, + <PIN_PD13__GRX0>, + <PIN_PD14__GRX1>, + <PIN_PD15__GTX0>, + <PIN_PD16__GTX1>, + <PIN_PD17__GMDC>, + <PIN_PD18__GMDIO>; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PD3__GPIO>; + bias-disable; + }; + + pinctrl_macb0_rst: macb0_sw_rst { + pinmux = <PIN_PD4__GPIO>; + bias-disable; + }; + + pinctrl_flx2_default: flx2_default { + pinmux = <PIN_PA6__FLEXCOM2_IO0>, + <PIN_PA7__FLEXCOM2_IO1>, + <PIN_PA9__FLEXCOM2_IO3>, + <PIN_PA10__FLEXCOM2_IO4>; + bias-disable; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm2_default>; + status = "disabled"; /* conflict with leds, HSIC */ +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_default>; + status = "disabled"; /* Conflict with wilc_pwrseq, flx2 */ + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + + at91bootstrap@0 { + label = "qspi: at91bootstrap"; + reg = <0x00000000 0x00040000>; + }; + + bootloader@40000 { + label = "qspi: bootloader"; + reg = <0x00040000 0x000c0000>; + }; + + bootloaderenvred@100000 { + label = "qspi: bootloader env redundant"; + reg = <0x00100000 0x00040000>; + }; + + bootloaderenv@140000 { + label = "qspi: bootloader env"; + reg = <0x00140000 0x00040000>; + }; + + dtb@180000 { + label = "qspi: device tree"; + reg = <0x00180000 0x00080000>; + }; + + kernel@200000 { + label = "qspi: kernel"; + reg = <0x00200000 0x00600000>; + }; + }; +}; + +&sdmmc0 { + no-1-8-v; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + status = "okay"; +}; + +&shutdown_controller { + atmel,shdwc-debouncer = <976>; + atmel,wakeup-rtc-timer; + + input@0 { + reg = <0>; + atmel,wakeup-type = "low"; + }; +}; + +&spi0 { /* mikrobus3 spi */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus3_spi &pinctrl_mikrobus3_spi_cs>; + status = "okay"; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus3_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus2_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&usb0 { + atmel,vbus-gpio = <&pioA PIN_PD23 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + +&usb1 { + num-ports = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + phy_type = "hsic"; + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts index ba7f3e646c26..c894c7c788a9 100644 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts @@ -18,9 +18,9 @@ compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5"; aliases { - serial0 = &uart0; - i2c0 = &i2c0; - i2c1 = &i2c1; + serial0 = &uart0; /* DBGU */ + i2c0 = &i2c0; /* mikroBUS 1 */ + i2c1 = &i2c1; /* XPRO EXT1 */ i2c2 = &i2c2; }; @@ -40,7 +40,7 @@ ahb { usb0: gadget@300000 { - atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>; + atmel,vbus-gpio = <&pioA PIN_PB11 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; @@ -125,8 +125,6 @@ bus-width = <8>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdmmc0_default>; - non-removable; - mmc-ddr-1_8v; status = "okay"; }; @@ -180,8 +178,11 @@ i2c0: i2c@f8028000 { dmas = <0>, <0>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -190,17 +191,12 @@ status = "okay"; i2c2: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <0>, <0>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_flx0_default>; - atmel,fifo-size = <16>; + pinctrl-1 = <&pinctrl_flx0_gpio>; + sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PB29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; }; @@ -226,8 +222,11 @@ i2c1: i2c@fc028000 { dmas = <0>, <0>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&pioA PIN_PC6 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PC7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; at24@50 { @@ -244,18 +243,36 @@ bias-disable; }; + pinctrl_flx0_gpio: flx0_gpio { + pinmux = <PIN_PB28__GPIO>, + <PIN_PB29__GPIO>; + bias-disable; + }; + pinctrl_i2c0_default: i2c0_default { pinmux = <PIN_PD21__TWD0>, <PIN_PD22__TWCK0>; bias-disable; }; + pinctrl_i2c0_gpio: i2c0_gpio { + pinmux = <PIN_PD21__GPIO>, + <PIN_PD22__GPIO>; + bias-disable; + }; + pinctrl_i2c1_default: i2c1_default { pinmux = <PIN_PC6__TWD1>, <PIN_PC7__TWCK1>; bias-disable; }; + pinctrl_i2c1_gpio: i2c1_gpio { + pinmux = <PIN_PC6__GPIO>, + <PIN_PC7__GPIO>; + bias-disable; + }; + pinctrl_key_gpio_default: key_gpio_default { pinmux = <PIN_PA10__GPIO>; bias-pull-up; @@ -387,6 +404,7 @@ label = "PB_USER"; gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>; linux,code = <0x104>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 9d0a7fbea725..a927165ea7c2 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -16,6 +16,13 @@ model = "Atmel SAMA5D2 Xplained"; compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5"; + aliases { + serial0 = &uart1; /* DBGU */ + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; /* XPRO EXT2 */ + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -72,6 +79,58 @@ }; apb { + qspi0: spi@f0020000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0_default>; + status = "disabled"; /* conflict with sdmmc1 */ + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + + at91bootstrap@00000000 { + label = "at91bootstrap"; + reg = <0x00000000 0x00040000>; + }; + + bootloader@00040000 { + label = "bootloader"; + reg = <0x00040000 0x000c0000>; + }; + + bootloaderenvred@00100000 { + label = "bootloader env redundant"; + reg = <0x00100000 0x00040000>; + }; + + bootloaderenv@00140000 { + label = "bootloader env"; + reg = <0x00140000 0x00040000>; + }; + + dtb@00180000 { + label = "device tree"; + reg = <0x00180000 0x00080000>; + }; + + kernel@00200000 { + label = "kernel"; + reg = <0x00200000 0x00600000>; + }; + + misc@00800000 { + label = "misc"; + reg = <0x00800000 0x00000000>; + }; + }; + }; + spi0: spi@f8000000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; @@ -129,8 +188,11 @@ i2c0: i2c@f8028000 { dmas = <0>, <0>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-sda-hold-time-ns = <350>; status = "okay"; @@ -272,16 +334,25 @@ status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */ uart5: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "usart"; + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx0_default>; - atmel,fifo-size = <32>; status = "okay"; }; + + i2c2: i2c@600 { + dmas = <0>, <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_flx0_default>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PB29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-sda-hold-time-ns = <350>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */ + }; }; shdwc@f8048010 { @@ -322,18 +393,13 @@ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; status = "okay"; - i2c2: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + i2c6: i2c@600 { dmas = <0>, <0>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <16>; + pinctrl-1 = <&pinctrl_flx4_gpio>; + sda-gpios = <&pioA PIN_PD12 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-analog-filter; i2c-digital-filter; i2c-digital-filter-width-ns = <35>; @@ -343,11 +409,14 @@ i2c1: i2c@fc028000 { dmas = <0>, <0>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; i2c-analog-filter; i2c-digital-filter; i2c-digital-filter-width-ns = <35>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; at24@54 { @@ -441,18 +510,42 @@ bias-disable; }; + pinctrl_flx4_gpio: flx4_gpio { + pinmux = <PIN_PD12__GPIO>, + <PIN_PD13__GPIO>; + bias-disable; + }; + pinctrl_i2c0_default: i2c0_default { pinmux = <PIN_PD21__TWD0>, <PIN_PD22__TWCK0>; bias-disable; }; + pinctrl_i2c0_gpio: i2c0_gpio { + pinmux = <PIN_PD21__GPIO>, + <PIN_PD22__GPIO>; + bias-disable; + }; + pinctrl_i2c1_default: i2c1_default { pinmux = <PIN_PD4__TWD1>, <PIN_PD5__TWCK1>; bias-disable; }; + pinctrl_i2c1_gpio: i2c1_gpio { + pinmux = <PIN_PD4__GPIO>, + <PIN_PD5__GPIO>; + bias-disable; + }; + + pinctrl_i2c2_gpio: i2c2_gpio { + pinmux = <PIN_PB28__GPIO>, + <PIN_PB29__GPIO>; + bias-disable; + }; + pinctrl_i2s0_default: i2s0_default { pinmux = <PIN_PC1__I2SC0_CK>, <PIN_PC2__I2SC0_MCK>, @@ -508,6 +601,22 @@ bias-disable; }; + pinctrl_qspi0_default: qspi0_default { + sck_cs { + pinmux = <PIN_PA22__QSPI0_SCK>, + <PIN_PA23__QSPI0_CS>; + bias-disable; + }; + + data { + pinmux = <PIN_PA24__QSPI0_IO0>, + <PIN_PA25__QSPI0_IO1>, + <PIN_PA26__QSPI0_IO2>, + <PIN_PA27__QSPI0_IO3>; + bias-pull-up; + }; + }; + pinctrl_sdmmc0_default: sdmmc0_default { cmd_data { pinmux = <PIN_PA1__SDMMC0_CMD>, diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts index af4969485c88..4d7cee569ff2 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts @@ -136,7 +136,7 @@ panel: panel { /* Actually Ampire 800480R2 */ - compatible = "foxlink,fl500wvr00-a0t", "simple-panel"; + compatible = "foxlink,fl500wvr00-a0t"; backlight = <&backlight>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/at91-wb50n.dtsi b/arch/arm/boot/dts/at91-wb50n.dtsi index 4ed8500a5cb8..1487b893cfa7 100644 --- a/arch/arm/boot/dts/at91-wb50n.dtsi +++ b/arch/arm/boot/dts/at91-wb50n.dtsi @@ -46,10 +46,6 @@ atmel,osc-bypass; }; -&usart1_clk { - atmel,clk-output-range = <0 132000000>; -}; - &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 44385718d9d4..a5040f5ea641 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -101,259 +101,9 @@ compatible = "atmel,at91rm9200-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - clocks = <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <80000000 160000000 0>, - <150000000 180000000 2>; - }; - - pllb: pllbck { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKB>; - clocks = <&main>; - reg = <1>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <80000000 160000000 0>, - <150000000 180000000 2>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - atmel,clk-output-range = <0 80000000>; - atmel,clk-divisors = <1 2 3 4>; - }; - - usb: usbck { - compatible = "atmel,at91rm9200-clk-usb"; - #clock-cells = <0>; - atmel,clk-divisors = <1 2 0 0>; - clocks = <&pllb>; - }; - - prog: progck { - compatible = "atmel,at91rm9200-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = <AT91_PMC_PCKRDY(0)>; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = <AT91_PMC_PCKRDY(1)>; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = <AT91_PMC_PCKRDY(2)>; - }; - - prog3: prog3 { - #clock-cells = <0>; - reg = <3>; - interrupts = <AT91_PMC_PCKRDY(3)>; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - udpck: udpck { - #clock-cells = <0>; - reg = <2>; - clocks = <&usb>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <4>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - - pck3: pck3 { - #clock-cells = <0>; - reg = <11>; - clocks = <&prog3>; - }; - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <4>; - }; - - pioD_clk: pioD_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <8>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <9>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <10>; - }; - - udc_clk: udc_clk { - #clock-cells = <0>; - reg = <11>; - }; - - twi0_clk: twi0_clk { - reg = <12>; - #clock-cells = <0>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <13>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <15>; - }; - - ssc2_clk: ssc2_clk { - #clock-cells = <0>; - reg = <16>; - }; - - tc0_clk: tc0_clk { - #clock-cells = <0>; - reg = <17>; - }; - - tc1_clk: tc1_clk { - #clock-cells = <0>; - reg = <18>; - }; - - tc2_clk: tc2_clk { - #clock-cells = <0>; - reg = <19>; - }; - - tc3_clk: tc3_clk { - #clock-cells = <0>; - reg = <20>; - }; - - tc4_clk: tc4_clk { - #clock-cells = <0>; - reg = <21>; - }; - - tc5_clk: tc5_clk { - #clock-cells = <0>; - reg = <22>; - }; - - ohci_clk: ohci_clk { - #clock-cells = <0>; - reg = <23>; - }; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <24>; - }; - }; + #clock-cells = <2>; + clocks = <&slow_xtal>, <&main_xtal>; + clock-names = "slow_xtal", "main_xtal"; }; st: timer@fffffd00 { @@ -383,7 +133,7 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 18 IRQ_TYPE_LEVEL_HIGH 0 19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -395,7 +145,7 @@ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 21 IRQ_TYPE_LEVEL_HIGH 0 22 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&slow_xtal>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&slow_xtal>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -405,7 +155,7 @@ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_twi>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -415,7 +165,7 @@ compatible = "atmel,hsmci"; reg = <0xfffb4000 0x4000>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; clock-names = "mci_clk"; #address-cells = <1>; #size-cells = <0>; @@ -429,7 +179,7 @@ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "pclk"; status = "disabled"; }; @@ -440,7 +190,7 @@ interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; clock-names = "pclk"; status = "disabled"; }; @@ -451,7 +201,7 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; - clocks = <&ssc2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; clock-names = "pclk"; status = "disabled"; }; @@ -463,7 +213,7 @@ phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&macb0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; clock-names = "ether_clk"; status = "disabled"; }; @@ -803,7 +553,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioA_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioB: gpio@fffff600 { @@ -814,7 +564,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; pioC: gpio@fffff800 { @@ -825,7 +575,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioC_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; }; pioD: gpio@fffffa00 { @@ -836,7 +586,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioD_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; }; }; @@ -846,7 +596,7 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; clock-names = "usart"; status = "disabled"; }; @@ -859,7 +609,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; clock-names = "usart"; status = "disabled"; }; @@ -872,7 +622,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "usart"; status = "disabled"; }; @@ -885,7 +635,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "usart"; status = "disabled"; }; @@ -898,7 +648,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - clocks = <&usart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; clock-names = "usart"; status = "disabled"; }; @@ -907,7 +657,7 @@ compatible = "atmel,at91rm9200-udc"; reg = <0xfffb0000 0x4000>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udc_clk>, <&udpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 2>; clock-names = "pclk", "hclk"; status = "disabled"; }; @@ -920,7 +670,7 @@ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names = "spi_clk"; status = "disabled"; }; @@ -947,7 +697,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00300000 0x100000>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 4>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index fd179097a4bf..3034c23e697d 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -103,14 +103,14 @@ ramc0: ramc@ffffe400 { compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe400 0x200>; - clocks = <&ddrck>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>; clock-names = "ddrck"; }; ramc1: ramc@ffffe600 { compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe600 0x200>; - clocks = <&ddrck>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>; clock-names = "ddrck"; }; @@ -128,271 +128,9 @@ compatible = "atmel,at91sam9g45-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - clocks = <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <745000000 800000000 0 0 - 695000000 750000000 1 0 - 645000000 700000000 2 0 - 595000000 650000000 3 0 - 545000000 600000000 0 1 - 495000000 555000000 1 1 - 445000000 500000000 2 1 - 400000000 450000000 3 1>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKU>; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; - atmel,clk-output-range = <0 133333333>; - atmel,clk-divisors = <1 2 4 3>; - }; - - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - prog: progck { - compatible = "atmel,at91sam9g45-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = <AT91_PMC_PCKRDY(0)>; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = <AT91_PMC_PCKRDY(1)>; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <4>; - }; - - pioDE_clk: pioDE_clk { - #clock-cells = <0>; - reg = <5>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <8>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <9>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <10>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <11>; - }; - - twi0_clk: twi0_clk { - #clock-cells = <0>; - reg = <12>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <13>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <15>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <16>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <17>; - }; - - tcb0_clk: tcb0_clk { - #clock-cells = <0>; - reg = <18>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <19>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <20>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <21>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <22>; - }; - - lcd_clk: lcd_clk { - #clock-cells = <0>; - reg = <23>; - }; - - ac97_clk: ac97_clk { - #clock-cells = <0>; - reg = <24>; - }; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <25>; - }; - - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <26>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <27>; - }; - - aestdessha_clk: aestdessha_clk { - #clock-cells = <0>; - reg = <28>; - }; - - mci1_clk: mci1_clk { - #clock-cells = <0>; - reg = <29>; - }; - - vdec_clk: vdec_clk { - #clock-cells = <0>; - reg = <30>; - }; - }; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; }; rstc@fffffd00 { @@ -405,7 +143,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; @@ -421,7 +159,7 @@ #size-cells = <0>; reg = <0xfff7c000 0x100>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -431,7 +169,7 @@ #size-cells = <0>; reg = <0xfffd4000 0x100>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -440,7 +178,7 @@ reg = <0xffffec00 0x200>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; - clocks = <&dma0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; clock-names = "dma_clk"; }; @@ -883,7 +621,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioA_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioB: gpio@fffff400 { @@ -894,7 +632,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; pioC: gpio@fffff600 { @@ -905,7 +643,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioC_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; }; pioD: gpio@fffff800 { @@ -916,7 +654,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioDE_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; }; pioE: gpio@fffffa00 { @@ -927,7 +665,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioDE_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; }; }; @@ -937,7 +675,7 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; clock-names = "usart"; status = "disabled"; }; @@ -950,7 +688,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "usart"; status = "disabled"; }; @@ -963,7 +701,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "usart"; status = "disabled"; }; @@ -976,7 +714,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; clock-names = "usart"; status = "disabled"; }; @@ -989,7 +727,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; clock-names = "usart"; status = "disabled"; }; @@ -1000,7 +738,7 @@ interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&macb0_clk>, <&macb0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_PERIPHERAL 25>; clock-names = "hclk", "pclk"; status = "disabled"; }; @@ -1009,7 +747,7 @@ compatible = "atmel,at91sam9g45-trng"; reg = <0xfffcc000 0x100>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&trng_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; }; i2c0: i2c@fff84000 { @@ -1020,7 +758,7 @@ pinctrl-0 = <&pinctrl_i2c0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; status = "disabled"; }; @@ -1032,7 +770,7 @@ pinctrl-0 = <&pinctrl_i2c1>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; status = "disabled"; }; @@ -1042,7 +780,7 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; clock-names = "pclk"; status = "disabled"; }; @@ -1053,7 +791,7 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; clock-names = "pclk"; status = "disabled"; }; @@ -1064,7 +802,7 @@ interrupts = <24 IRQ_TYPE_LEVEL_HIGH 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ac97>; - clocks = <&ac97_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; clock-names = "ac97_clk"; status = "disabled"; }; @@ -1075,7 +813,7 @@ compatible = "atmel,at91sam9g45-adc"; reg = <0xfffb0000 0x100>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&adc_clk>, <&adc_op_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>; clock-names = "adc_clk", "adc_op_clk"; atmel,adc-channels-used = <0xff>; atmel,adc-vref = <3300>; @@ -1111,7 +849,7 @@ compatible = "atmel,at91sam9g45-isi"; reg = <0xfffb4000 0x4000>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&isi_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; clock-names = "isi_clk"; status = "disabled"; port { @@ -1125,7 +863,7 @@ reg = <0xfffb8000 0x300>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; #pwm-cells = <3>; - clocks = <&pwm_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; status = "disabled"; }; @@ -1138,7 +876,7 @@ dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; clock-names = "mci_clk"; status = "disabled"; }; @@ -1152,7 +890,7 @@ dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; clock-names = "mci_clk"; status = "disabled"; }; @@ -1176,7 +914,7 @@ interrupts = <14 4 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "spi_clk"; status = "disabled"; }; @@ -1189,7 +927,7 @@ interrupts = <15 4 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; clock-names = "spi_clk"; status = "disabled"; }; @@ -1201,7 +939,7 @@ reg = <0x00600000 0x80000 0xfff78000 0x400>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&udphs_clk>, <&utmi>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_CORE PMC_UTMI>; clock-names = "pclk", "hclk"; status = "disabled"; @@ -1294,7 +1032,7 @@ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fb>; - clocks = <&lcd_clk>, <&lcd_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "hclk", "lcdc_clk"; status = "disabled"; }; @@ -1303,7 +1041,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -1312,7 +1050,7 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00800000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; clock-names = "usb_clk", "ehci_clk"; status = "disabled"; }; @@ -1330,7 +1068,7 @@ 0x3 0x0 0x40000000 0x10000000 0x4 0x0 0x50000000 0x10000000 0x5 0x0 0x60000000 0x10000000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; status = "disabled"; nand_controller: nand-controller { diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 84bed6f55fcd..a3a5c82d9f29 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -72,9 +72,9 @@ pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>; pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>; - clocks = <&pck1>; + clocks = <&pmc PMC_TYPE_SYSTEM 9>; clock-names = "xvclk"; - assigned-clocks = <&pck1>; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; assigned-clock-rates = <25000000>; port { diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index ea675174432e..a994d076dc7e 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -104,7 +104,7 @@ ramc0: ramc@ffffe800 { compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe800 0x200>; - clocks = <&ddrck>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>; clock-names = "ddrck"; }; @@ -116,278 +116,10 @@ pmc: pmc@fffffc00 { compatible = "atmel,at91sam9n12-pmc", "syscon"; reg = <0xfffffc00 0x200>; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; - clock-frequency = <12000000>; - clock-accuracy = <50000000>; - }; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; - clocks = <&main_rc_osc>, <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, - <695000000 750000000 1 0>, - <645000000 700000000 2 0>, - <595000000 650000000 3 0>, - <545000000 600000000 0 1>, - <495000000 555000000 1 1>, - <445000000 500000000 2 1>, - <400000000 450000000 3 1>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - pllb: pllbck { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKB>; - clocks = <&main>; - reg = <1>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <30000000 100000000 0>; - }; - - mck: masterck { - compatible = "atmel,at91sam9x5-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>; - atmel,clk-output-range = <0 133333333>; - atmel,clk-divisors = <1 2 4 3>; - atmel,master-clk-have-div3-pres; - }; - - usb: usbck { - compatible = "atmel,at91sam9n12-clk-usb"; - #clock-cells = <0>; - clocks = <&pllb>; - }; - - prog: progck { - compatible = "atmel,at91sam9x5-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = <AT91_PMC_PCKRDY(0)>; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = <AT91_PMC_PCKRDY(1)>; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - lcdck: lcdck { - #clock-cells = <0>; - reg = <3>; - clocks = <&mck>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - }; - - periphck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioAB_clk: pioAB_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioCD_clk: pioCD_clk { - #clock-cells = <0>; - reg = <3>; - }; - - fuse_clk: fuse_clk { - #clock-cells = <0>; - reg = <4>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <8>; - }; - - twi0_clk: twi0_clk { - reg = <9>; - #clock-cells = <0>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <10>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <12>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <13>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <14>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <15>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <16>; - }; - - tcb_clk: tcb_clk { - #clock-cells = <0>; - reg = <17>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <18>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <19>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <20>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <22>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <23>; - }; - - lcdc_clk: lcdc_clk { - #clock-cells = <0>; - reg = <25>; - }; - - sha_clk: sha_clk { - #clock-cells = <0>; - reg = <27>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <28>; - }; - - aes_clk: aes_clk { - #clock-cells = <0>; - reg = <29>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <30>; - }; - }; }; rstc@fffffe00 { @@ -400,7 +132,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; shdwc@fffffe10 { @@ -439,7 +171,7 @@ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "mci_clk"; #address-cells = <1>; #size-cells = <0>; @@ -452,7 +184,7 @@ #size-cells = <0>; reg = <0xf8008000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; @@ -462,7 +194,7 @@ #size-cells = <0>; reg = <0xf800c000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; @@ -470,7 +202,7 @@ compatible = "atmel,at91sam9n12-hlcdc"; reg = <0xf8038000 0x2000>; interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; clock-names = "periph_clk", "sys_clk", "slow_clk"; status = "disabled"; @@ -499,7 +231,7 @@ reg = <0xffffec00 0x200>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; - clocks = <&dma0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; clock-names = "dma_clk"; }; @@ -817,7 +549,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioAB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioB: gpio@fffff600 { @@ -828,7 +560,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioAB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioC: gpio@fffff800 { @@ -839,7 +571,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioCD_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; pioD: gpio@fffffa00 { @@ -850,7 +582,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioCD_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; }; @@ -860,7 +592,7 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; clock-names = "usart"; status = "disabled"; }; @@ -874,7 +606,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; clock-names = "pclk"; status = "disabled"; }; @@ -885,7 +617,7 @@ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; clock-names = "usart"; status = "disabled"; }; @@ -896,7 +628,7 @@ interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; clock-names = "usart"; status = "disabled"; }; @@ -907,7 +639,7 @@ interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "usart"; status = "disabled"; }; @@ -918,7 +650,7 @@ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "usart"; status = "disabled"; }; @@ -934,7 +666,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; status = "disabled"; }; @@ -949,7 +681,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&twi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; status = "disabled"; }; @@ -964,7 +696,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names = "spi_clk"; status = "disabled"; }; @@ -980,7 +712,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "spi_clk"; status = "disabled"; }; @@ -1009,7 +741,7 @@ reg = <0xf8034000 0x300>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; #pwm-cells = <3>; - clocks = <&pwm_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; status = "disabled"; }; @@ -1017,7 +749,7 @@ compatible = "atmel,at91sam9260-udc"; reg = <0xf803c000 0x4000>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udphs_clk>, <&udpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 7>; clock-names = "pclk", "hclk"; status = "disabled"; }; @@ -1027,7 +759,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x00100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -1045,7 +777,7 @@ 0x3 0x0 0x40000000 0x10000000 0x4 0x0 0x50000000 0x10000000 0x5 0x0 0x60000000 0x10000000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; status = "disabled"; nand_controller: nand-controller { diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index ea5cef0b0974..870b83ff6b97 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -59,7 +59,7 @@ wm8904: codec@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - clocks = <&pck0>; + clocks = <&pmc PMC_TYPE_SYSTEM 8>; clock-names = "mclk"; }; @@ -238,7 +238,7 @@ }; panel: panel { - compatible = "qiaodian,qd43003c0-40", "simple-panel"; + compatible = "qiaodian,qd43003c0-40"; backlight = <&backlight>; power-supply = <&panel_reg>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/at91sam9x5dm.dtsi b/arch/arm/boot/dts/at91sam9x5dm.dtsi index 7f00c1f57b90..a9278038af3b 100644 --- a/arch/arm/boot/dts/at91sam9x5dm.dtsi +++ b/arch/arm/boot/dts/at91sam9x5dm.dtsi @@ -27,7 +27,7 @@ }; panel: panel { - compatible = "foxlink,fl500wvr00-a0t", "simple-panel"; + compatible = "foxlink,fl500wvr00-a0t"; backlight = <&backlight>; power-supply = <&panel_reg>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index 1b5a835f66bd..c7f1d97e69bb 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -20,7 +20,9 @@ }; aliases { + emmc2bus = &emmc2bus; ethernet0 = &genet; + pcie0 = &pcie0; }; leds { @@ -31,6 +33,8 @@ pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; }; }; @@ -52,6 +56,16 @@ 3300000 0x0>; status = "okay"; }; + + sd_vcc_reg: sd_vcc_reg { + compatible = "regulator-fixed"; + regulator-name = "vcc-sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>; + }; }; &firmware { @@ -65,12 +79,85 @@ "GLOBAL_RESET", "VDD_SD_IO_SEL", "CAM_GPIO", - "", + "SD_PWR_ON", ""; status = "okay"; }; }; +&gpio { + /* + * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD1", + "RXD1", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "RGMII_MDIO", + "RGMIO_MDC", + /* Used by BT module */ + "CTS0", + "RTS0", + "TXD0", + "RXD0", + /* Used by Wifi */ + "SD1_CLK", + "SD1_CMD", + "SD1_DATA0", + "SD1_DATA1", + "SD1_DATA2", + "SD1_DATA3", + /* Shared with SPI flash */ + "PWM0_MISO", + "PWM1_MOSI", + "STATUS_LED_G_CLK", + "SPIFLASH_CE_N", + "SDA0", + "SCL0", + "RGMII_RXCLK", + "RGMII_RXCTL", + "RGMII_RXD0", + "RGMII_RXD1", + "RGMII_RXD2", + "RGMII_RXD3", + "RGMII_TXCLK", + "RGMII_TXCTL", + "RGMII_TXD0", + "RGMII_TXD1", + "RGMII_TXD2", + "RGMII_TXD3"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>; @@ -97,6 +184,7 @@ /* EMMC2 is used to drive the SD card */ &emmc2 { vqmmc-supply = <&sd_io_1v8_reg>; + vmmc-supply = <&sd_vcc_reg>; broken-cd; status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index d1e684d0acfd..a91cf68e3c4c 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -241,17 +241,32 @@ status = "disabled"; }; + hvs@7e400000 { + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + /* + * emmc2 has different DMA constraints based on SoC revisions. It was + * moved into its own bus, so as for RPi4's firmware to update them. + * The firmware will find whether the emmc2bus alias is defined, and if + * so, it'll edit the dma-ranges property below accordingly. + */ + emmc2bus: emmc2bus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; + dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; + emmc2: emmc2@7e340000 { compatible = "brcm,bcm2711-emmc2"; - reg = <0x7e340000 0x100>; + reg = <0x0 0x7e340000 0x100>; interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clocks BCM2711_CLOCK_EMMC2>; status = "disabled"; }; - - hvs@7e400000 { - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; - }; }; arm-pmu { diff --git a/arch/arm/boot/dts/bcm2835-common.dtsi b/arch/arm/boot/dts/bcm2835-common.dtsi index 2b1d9d4c0cde..4119271c979d 100644 --- a/arch/arm/boot/dts/bcm2835-common.dtsi +++ b/arch/arm/boot/dts/bcm2835-common.dtsi @@ -130,7 +130,6 @@ compatible = "brcm,bcm2835-v3d"; reg = <0x7ec00000 0x1000>; interrupts = <1 10>; - power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; }; vc4: gpu { diff --git a/arch/arm/boot/dts/bcm2835-rpi-common.dtsi b/arch/arm/boot/dts/bcm2835-rpi-common.dtsi new file mode 100644 index 000000000000..8a55b6cded59 --- /dev/null +++ b/arch/arm/boot/dts/bcm2835-rpi-common.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This include file covers the common peripherals and configuration between + * bcm2835, bcm2836 and bcm2837 implementations that interact with RPi's + * firmware interface. + */ + +#include <dt-bindings/power/raspberrypi-power.h> + +&v3d { + power-domains = <&power RPI_POWER_DOMAIN_V3D>; +}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts index b75af21069f9..4c3f606e5b8d 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts @@ -112,6 +112,7 @@ &sdhci { #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; bus-width = <4>; mmc-pwrseq = <&wifi_pwrseq>; diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index 394c8a71b13b..f7ae5a4530b8 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -14,7 +14,11 @@ soc { firmware: firmware { compatible = "raspberrypi,bcm2835-firmware", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + mboxes = <&mailbox>; + dma-ranges; }; power: power { diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index 53bf4579cc22..0549686134ea 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "bcm283x.dtsi" #include "bcm2835-common.dtsi" +#include "bcm2835-rpi-common.dtsi" / { compatible = "brcm,bcm2835"; diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi index 82d6c4662ae4..b390006aef79 100644 --- a/arch/arm/boot/dts/bcm2836.dtsi +++ b/arch/arm/boot/dts/bcm2836.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "bcm283x.dtsi" #include "bcm2835-common.dtsi" +#include "bcm2835-rpi-common.dtsi" / { compatible = "brcm,bcm2836"; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts index 66ab35eccba7..28be0332c1c8 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts @@ -26,6 +26,8 @@ pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; }; }; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index 74ed6d047807..37343148643d 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -27,6 +27,8 @@ pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; }; }; diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi index 9e95fee78e19..0199ec98cd61 100644 --- a/arch/arm/boot/dts/bcm2837.dtsi +++ b/arch/arm/boot/dts/bcm2837.dtsi @@ -1,5 +1,6 @@ #include "bcm283x.dtsi" #include "bcm2835-common.dtsi" +#include "bcm2835-rpi-common.dtsi" / { compatible = "brcm,bcm2837"; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index e1abe8c730ce..b83a864e2e8b 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -372,6 +372,7 @@ "dsi0_ddr2", "dsi0_ddr"; + status = "disabled"; }; aux: aux@7e215000 { diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index d2f7d984bba5..3ab3cd250da7 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -77,7 +77,7 @@ ranges = <0 0xf7000000 0x1000000>; - sdhci0: sdhci@ab0000 { + sdhci0: mmc@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; @@ -86,7 +86,7 @@ status = "disabled"; }; - sdhci1: sdhci@ab0800 { + sdhci1: mmc@ab0800 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0800 0x200>; clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>; @@ -95,7 +95,7 @@ status = "disabled"; }; - sdhci2: sdhci@ab1000 { + sdhci2: mmc@ab1000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab1000 0x200>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index e5c1f4213ff9..7cf3e6302d75 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -62,7 +62,7 @@ ranges = <0 0xf7000000 0x1000000>; - sdhci0: sdhci@ab0000 { + sdhci0: mmc@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 99d6872a6dfc..c44a32e873f4 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -122,7 +122,7 @@ ranges = <0 0xf7000000 0x1000000>; interrupt-parent = <&gic>; - sdhci0: sdhci@ab0000 { + sdhci0: mmc@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; @@ -131,7 +131,7 @@ status = "disabled"; }; - sdhci1: sdhci@ab0800 { + sdhci1: mmc@ab0800 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0800 0x200>; clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; @@ -140,7 +140,7 @@ status = "disabled"; }; - sdhci2: sdhci@ab1000 { + sdhci2: mmc@ab1000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab1000 0x200>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts index 3931fb068ff0..91d1018ab75f 100644 --- a/arch/arm/boot/dts/dm8148-evm.dts +++ b/arch/arm/boot/dts/dm8148-evm.dts @@ -24,12 +24,12 @@ &cpsw_emac0 { phy-handle = <ðphy0>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; &cpsw_emac1 { phy-handle = <ðphy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; &davinci_mdio { diff --git a/arch/arm/boot/dts/dm8148-t410.dts b/arch/arm/boot/dts/dm8148-t410.dts index 9e43d5ec0bb2..79ccdd4470f4 100644 --- a/arch/arm/boot/dts/dm8148-t410.dts +++ b/arch/arm/boot/dts/dm8148-t410.dts @@ -33,12 +33,12 @@ &cpsw_emac0 { phy-handle = <ðphy0>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; &cpsw_emac1 { phy-handle = <ðphy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; &davinci_mdio { diff --git a/arch/arm/boot/dts/dm814x-clocks.dtsi b/arch/arm/boot/dts/dm814x-clocks.dtsi index e5e4d0affefa..f7939f43413b 100644 --- a/arch/arm/boot/dts/dm814x-clocks.dtsi +++ b/arch/arm/boot/dts/dm814x-clocks.dtsi @@ -362,4 +362,18 @@ #clock-cells = <2>; }; }; + + alwon_ethernet_cm: alwon_ethernet_cm@15d4 { + compatible = "ti,omap4-cm"; + reg = <0x15d4 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x15d4 0x4>; + + alwon_ethernet_clkctrl: clk@0 { + compatible = "ti,clkctrl"; + reg = <0 0x4>; + #clock-cells = <2>; + }; + }; }; diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 95de9f214c14..44ed5a798164 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -4,6 +4,8 @@ * kind, whether express or implied. */ +#include <dt-bindings/bus/ti-sysc.h> +#include <dt-bindings/clock/dm814.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/dm814x.h> @@ -519,53 +521,123 @@ reg = <0x47810000 0x1000>; }; - edma: edma@49000000 { - compatible = "ti,edma3-tpcc"; - ti,hwmods = "tpcc"; - reg = <0x49000000 0x10000>; - reg-names = "edma3_cc"; - interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, - <&edma_tptc2 3>, <&edma_tptc3 0>; - - ti,edma-memcpy-channels = <20 21>; + target-module@49000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49000000 0x4>; + reg-names = "rev"; + clocks = <&alwon_clkctrl DM814_TPCC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49000000 0x10000>; + + edma: dma@0 { + compatible = "ti,edma3-tpcc"; + reg = <0 0x10000>; + reg-names = "edma3_cc"; + interrupts = <12 13 14>; + interrupt-names = "edma3_ccint", "edma3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, + <&edma_tptc2 3>, <&edma_tptc3 0>; + + ti,edma-memcpy-channels = <20 21>; + }; }; - edma_tptc0: tptc@49800000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc0"; - reg = <0x49800000 0x100000>; - interrupts = <112>; - interrupt-names = "edma3_tcerrint"; + target-module@49800000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49800000 0x4>, + <0x49800010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_SMART>; + clocks = <&alwon_clkctrl DM814_TPTC0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49800000 0x100000>; + + edma_tptc0: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <112>; + interrupt-names = "edma3_tcerrint"; + }; }; - edma_tptc1: tptc@49900000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc1"; - reg = <0x49900000 0x100000>; - interrupts = <113>; - interrupt-names = "edma3_tcerrint"; + target-module@49900000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49900000 0x4>, + <0x49900010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_SMART>; + clocks = <&alwon_clkctrl DM814_TPTC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49900000 0x100000>; + + edma_tptc1: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <113>; + interrupt-names = "edma3_tcerrint"; + }; }; - edma_tptc2: tptc@49a00000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc2"; - reg = <0x49a00000 0x100000>; - interrupts = <114>; - interrupt-names = "edma3_tcerrint"; + target-module@49a00000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49a00000 0x4>, + <0x49a00010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_SMART>; + clocks = <&alwon_clkctrl DM814_TPTC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49a00000 0x100000>; + + edma_tptc2: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <114>; + interrupt-names = "edma3_tcerrint"; + }; }; - edma_tptc3: tptc@49b00000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc3"; - reg = <0x49b00000 0x100000>; - interrupts = <115>; - interrupt-names = "edma3_tcerrint"; + target-module@49b00000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49b00000 0x4>, + <0x49b00010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_SMART>; + clocks = <&alwon_clkctrl DM814_TPTC3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49b00000 0x100000>; + + edma_tptc3: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <115>; + interrupt-names = "edma3_tcerrint"; + }; }; /* See TRM "Table 1-318. L4HS Instance Summary" */ @@ -574,57 +646,73 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x4a000000 0x1b4040>; - }; - /* REVISIT: Move to live under l4hs once driver is fixed */ - mac: ethernet@4a100000 { - compatible = "ti,cpsw"; - ti,hwmods = "cpgmac0"; - clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; - clock-names = "fck", "cpts"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x80000000>; - cpts_clock_shift = <29>; - reg = <0x4a100000 0x800 - 0x4a100900 0x100>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - /* - * c0_rx_thresh_pend - * c0_rx_pend - * c0_tx_pend - * c0_misc_pend - */ - interrupts = <40 41 42 43>; - ranges; - syscon = <&scm_conf>; - - davinci_mdio: mdio@4a100800 { - compatible = "ti,davinci_mdio"; + target-module@100000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x100900 0x4>, + <0x100908 0x4>, + <0x100904 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <0>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>; + ti,syss-mask = <1>; + clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "davinci_mdio"; - bus_freq = <1000000>; - reg = <0x4a100800 0x100>; - }; - - cpsw_emac0: slave@4a100200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 1>; + #size-cells = <1>; + ranges = <0 0x100000 0x8000>; + + mac: ethernet@0 { + compatible = "ti,cpsw"; + clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; + clock-names = "fck", "cpts"; + cpdma_channels = <8>; + ale_entries = <1024>; + bd_ram_size = <0x2000>; + mac_control = <0x20>; + slaves = <2>; + active_slave = <0>; + cpts_clock_mult = <0x80000000>; + cpts_clock_shift = <29>; + reg = <0 0x800>, + <0x900 0x100>; + #address-cells = <1>; + #size-cells = <1>; + /* + * c0_rx_thresh_pend + * c0_rx_pend + * c0_tx_pend + * c0_misc_pend + */ + interrupts = <40 41 42 43>; + ranges = <0 0 0x8000>; + syscon = <&scm_conf>; + + davinci_mdio: mdio@800 { + compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; + clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + reg = <0x800 0x100>; + }; - }; + cpsw_emac0: slave@200 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1>; + }; - cpsw_emac1: slave@4a100300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 2>; + cpsw_emac1: slave@300 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index 1edc2b48b254..2a4934b60ded 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -4,6 +4,8 @@ * kind, whether express or implied. */ +#include <dt-bindings/bus/ti-sysc.h> +#include <dt-bindings/clock/dm816.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/omap.h> @@ -138,13 +140,123 @@ }; }; - edma: edma@49000000 { - compatible = "ti,edma3"; - ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3"; - reg = <0x49000000 0x10000>, - <0x44e10f90 0x40>; - interrupts = <12 13 14>; - #dma-cells = <1>; + target-module@49000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49000000 0x4>; + reg-names = "rev"; + clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49000000 0x10000>; + + edma: dma@0 { + compatible = "ti,edma3-tpcc"; + reg = <0 0x10000>; + reg-names = "edma3_cc"; + interrupts = <12 13 14>; + interrupt-names = "edma3_ccint", "edma3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, + <&edma_tptc2 3>, <&edma_tptc3 0>; + + ti,edma-memcpy-channels = <20 21>; + }; + }; + + target-module@49800000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49800000 0x4>, + <0x49800010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_SMART>; + clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49800000 0x100000>; + + edma_tptc0: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <112>; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@49900000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49900000 0x4>, + <0x49900010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_SMART>; + clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49900000 0x100000>; + + edma_tptc1: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <113>; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@49a00000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49a00000 0x4>, + <0x49a00010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_SMART>; + clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49a00000 0x100000>; + + edma_tptc2: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <114>; + interrupt-names = "edma3_tcerrint"; + }; + }; + + target-module@49b00000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x49b00000 0x4>, + <0x49b00010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_SMART>; + clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49b00000 0x100000>; + + edma_tptc3: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <115>; + interrupt-names = "edma3_tcerrint"; + }; }; elm: elm@48080000 { @@ -185,7 +297,7 @@ #address-cells = <2>; #size-cells = <1>; interrupts = <100>; - dmas = <&edma 52>; + dmas = <&edma 52 0>; dma-names = "rxtx"; gpmc,num-cs = <6>; gpmc,num-waitpins = <2>; @@ -202,7 +314,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <70>; - dmas = <&edma 58 &edma 59>; + dmas = <&edma 58 0 &edma 59 0>; dma-names = "tx", "rx"; }; @@ -213,7 +325,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <71>; - dmas = <&edma 60 &edma 61>; + dmas = <&edma 60 0 &edma 61 0>; dma-names = "tx", "rx"; }; @@ -311,10 +423,10 @@ interrupts = <65>; ti,spi-num-cs = <4>; ti,hwmods = "mcspi1"; - dmas = <&edma 16 &edma 17 - &edma 18 &edma 19 - &edma 20 &edma 21 - &edma 22 &edma 23>; + dmas = <&edma 16 0 &edma 17 0 + &edma 18 0 &edma 19 0 + &edma 20 0 &edma 21 0 + &edma 22 0 &edma 23 0>; dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3"; }; @@ -324,7 +436,7 @@ reg = <0x48060000 0x11000>; ti,hwmods = "mmc1"; interrupts = <64>; - dmas = <&edma 24 &edma 25>; + dmas = <&edma 24 0 &edma 25 0>; dma-names = "tx", "rx"; }; @@ -392,7 +504,7 @@ reg = <0x48020000 0x2000>; clock-frequency = <48000000>; interrupts = <72>; - dmas = <&edma 26 &edma 27>; + dmas = <&edma 26 0 &edma 27 0>; dma-names = "tx", "rx"; }; @@ -402,7 +514,7 @@ reg = <0x48022000 0x2000>; clock-frequency = <48000000>; interrupts = <73>; - dmas = <&edma 28 &edma 29>; + dmas = <&edma 28 0 &edma 29 0>; dma-names = "tx", "rx"; }; @@ -412,7 +524,7 @@ reg = <0x48024000 0x2000>; clock-frequency = <48000000>; interrupts = <74>; - dmas = <&edma 30 &edma 31>; + dmas = <&edma 30 0 &edma 31 0>; dma-names = "tx", "rx"; }; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 3081b04e8c08..89e0bdaf3a85 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -175,7 +175,6 @@ #size-cells = <0>; interrupts = <11>; clock-frequency = <400000>; - timeout-ms = <1000>; clocks = <&core_clk 0>; status = "okay"; }; @@ -248,7 +247,7 @@ marvell,#interrupts = <5>; }; - intc: main-interrupt-ctrl@20200 { + intc: interrupt-controller@20200 { compatible = "marvell,orion-intc"; interrupt-controller; #interrupt-cells = <1>; diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/dra62x-j5eco-evm.dts index 861ab90a3f3a..c16e183822be 100644 --- a/arch/arm/boot/dts/dra62x-j5eco-evm.dts +++ b/arch/arm/boot/dts/dra62x-j5eco-evm.dts @@ -24,12 +24,12 @@ &cpsw_emac0 { phy-handle = <ðphy0>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; &cpsw_emac1 { phy-handle = <ðphy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; }; &davinci_mdio { diff --git a/arch/arm/boot/dts/dra62x.dtsi b/arch/arm/boot/dts/dra62x.dtsi index d3cbb4ea35a8..cc4878aaa8ea 100644 --- a/arch/arm/boot/dts/dra62x.dtsi +++ b/arch/arm/boot/dts/dra62x.dtsi @@ -12,12 +12,12 @@ /* Compared to dm814x, dra62x has different offsets for Ethernet */ &mac { - reg = <0x4a100000 0x800 - 0x4a101200 0x100>; + reg = <0 0x800>, + <0x1200 0x100>; }; &davinci_mdio { - reg = <0x4a101000 0x100>; + reg = <0x1000 0x100>; }; #include "dra62x-clocks.dtsi" diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi index 23244b5a9942..f89a64cbcd53 100644 --- a/arch/arm/boot/dts/dra7-evm-common.dtsi +++ b/arch/arm/boot/dts/dra7-evm-common.dtsi @@ -3,6 +3,7 @@ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ */ +#include "dra74-ipu-dsp-common.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/ti-dra7-atl.h> #include <dt-bindings/input/input.h> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index de7f85efaa51..7aeb30daf3b8 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -35,6 +35,40 @@ regulator-max-microvolt = <1800000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_memory_region: dsp2-memory@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + evm_3v3_sd: fixedregulator-sd { compatible = "regulator-fixed"; regulator-name = "evm_3v3_sd"; @@ -61,10 +95,10 @@ regulator-max-microvolt = <1800000>; }; - evm_3v3: fixedregulator-evm3v3 { + vsys_3v3: fixedregulator-vsys3v3 { /* Output of Cntlr A of TPS43351-Q1 on dra7-evm */ compatible = "regulator-fixed"; - regulator-name = "evm_3v3"; + regulator-name = "vsys_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&evm_12v0>; @@ -537,3 +571,23 @@ pinctrl-1 = <&dcan1_pins_sleep>; pinctrl-2 = <&dcan1_pins_default>; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_memory_region>; +}; diff --git a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi new file mode 100644 index 000000000000..a25749a1c365 --- /dev/null +++ b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common IPU and DSP data for TI DRA7xx/AM57xx platforms + */ + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; +}; + +&ipu2 { + mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; + ti,timers = <&timer3>; + ti,watchdog-timers = <&timer4>, <&timer9>; +}; + +&ipu1 { + mboxes = <&mailbox5 &mbox_ipu1_ipc3x>; + ti,timers = <&timer11>; + ti,watchdog-timers = <&timer7>, <&timer8>; +}; + +&dsp1 { + mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; + ti,timers = <&timer5>; + ti,watchdog-timers = <&timer10>; +}; diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index fc418834890d..1abd455cf15a 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -1163,8 +1163,8 @@ timer2: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -1191,8 +1191,8 @@ timer3: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -1210,8 +1210,9 @@ <SYSC_IDLE_SMART>, <SYSC_IDLE_SMART_WKUP>; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>; - clock-names = "fck"; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>, + <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x36000 0x1000>; @@ -1219,8 +1220,8 @@ timer4: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -1246,8 +1247,8 @@ timer9: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -1853,8 +1854,8 @@ timer10: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -1880,8 +1881,8 @@ timer11: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -3354,8 +3355,8 @@ <SYSC_IDLE_SMART>, <SYSC_IDLE_SMART_WKUP>; /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>; - clock-names = "fck"; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; @@ -3381,8 +3382,9 @@ <SYSC_IDLE_SMART>, <SYSC_IDLE_SMART_WKUP>; /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>; - clock-names = "fck"; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>, + <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x22000 0x1000>; @@ -3417,8 +3419,8 @@ timer7: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -3444,8 +3446,8 @@ timer8: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -3471,9 +3473,10 @@ timer13: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-pwm; }; }; @@ -3501,6 +3504,7 @@ clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>; clock-names = "fck"; interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-pwm; }; }; @@ -3528,6 +3532,7 @@ clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>; clock-names = "fck"; interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-pwm; }; }; @@ -3555,6 +3560,7 @@ clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>; clock-names = "fck"; interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; + ti,timer-pwm; }; }; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index d78b684e7fca..8f4e4941984f 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -143,11 +143,12 @@ * the moment, just use a fake OCP bus entry to represent the whole bus * hierarchy. */ - ocp { + ocp: ocp { compatible = "ti,dra7-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0xc0000000>; + dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; ti,hwmods = "l3_main_1", "l3_main_2"; reg = <0x0 0x44000000 0x0 0x1000000>, <0x0 0x45000000 0x0 0x1000>; @@ -184,6 +185,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0x03000 0 0x00010000 0x82000000 0 0x20013000 0x13000 0 0xffed000>; + dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>; bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>; @@ -238,6 +240,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0x03000 0 0x00010000 0x82000000 0 0x30013000 0x13000 0 0xffed000>; + dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>; bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>; @@ -331,43 +334,73 @@ #pinctrl-cells = <2>; }; - edma: edma@43300000 { - compatible = "ti,edma3-tpcc"; - ti,hwmods = "tpcc"; - reg = <0x43300000 0x100000>; - reg-names = "edma3_cc"; - interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma3_ccint", "edma3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; + target-module@43300000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x43300000 0x4>; + reg-names = "rev"; + clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x43300000 0x100000>; + + edma: dma@0 { + compatible = "ti,edma3-tpcc"; + reg = <0 0x100000>; + reg-names = "edma3_cc"; + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma3_ccint", "edma3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; + + /* + * memcpy is disabled, can be enabled with: + * ti,edma-memcpy-channels = <20 21>; + * for example. Note that these channels need to be + * masked in the xbar as well. + */ + }; + }; - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; + target-module@43400000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x43400000 0x4>; + reg-names = "rev"; + clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x43400000 0x100000>; - /* - * memcpy is disabled, can be enabled with: - * ti,edma-memcpy-channels = <20 21>; - * for example. Note that these channels need to be - * masked in the xbar as well. - */ + edma_tptc0: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma3_tcerrint"; + }; }; - edma_tptc0: tptc@43400000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc0"; - reg = <0x43400000 0x100000>; - interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma3_tcerrint"; - }; + target-module@43500000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x43500000 0x4>; + reg-names = "rev"; + clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x43500000 0x100000>; - edma_tptc1: tptc@43500000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc1"; - reg = <0x43500000 0x100000>; - interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma3_tcerrint"; + edma_tptc1: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma3_tcerrint"; + }; }; dmm@4e000000 { @@ -377,6 +410,42 @@ ti,hwmods = "dmm"; }; + ipu1: ipu@58820000 { + compatible = "ti,dra7-ipu"; + reg = <0x58820000 0x10000>; + reg-names = "l2ram"; + iommus = <&mmu_ipu1>; + status = "disabled"; + resets = <&prm_ipu 0>, <&prm_ipu 1>; + clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; + firmware-name = "dra7-ipu1-fw.xem4"; + }; + + ipu2: ipu@55020000 { + compatible = "ti,dra7-ipu"; + reg = <0x55020000 0x10000>; + reg-names = "l2ram"; + iommus = <&mmu_ipu2>; + status = "disabled"; + resets = <&prm_core 0>, <&prm_core 1>; + clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; + firmware-name = "dra7-ipu2-fw.xem4"; + }; + + dsp1: dsp@40800000 { + compatible = "ti,dra7-dsp"; + reg = <0x40800000 0x48000>, + <0x40e00000 0x8000>, + <0x40f00000 0x8000>; + reg-names = "l2ram", "l1pram", "l1dram"; + ti,bootreg = <&scm_conf 0x55c 10>; + iommus = <&mmu0_dsp1>, <&mmu1_dsp1>; + status = "disabled"; + resets = <&prm_dsp1 0>; + clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; + firmware-name = "dra7-dsp1-fw.xe66"; + }; + target-module@40d01000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x40d01000 0x4>, @@ -705,44 +774,99 @@ ti,irqs-safe-map = <0>; }; - dss: dss@58000000 { - compatible = "ti,dra7-dss"; - /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ - /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ - status = "disabled"; - ti,hwmods = "dss_core"; - /* CTRL_CORE_DSS_PLL_CONTROL */ - syscon-pll-ctrl = <&scm_conf 0x538>; + target-module@58000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x58000000 4>, + <0x58000014 4>; + reg-names = "rev", "syss"; + ti,syss-mask = <1>; + clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>, + <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>, + <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>; + clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; #address-cells = <1>; #size-cells = <1>; - ranges; - - dispc@58001000 { - compatible = "ti,dra7-dispc"; - reg = <0x58001000 0x1000>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "dss_dispc"; - clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - /* CTRL_CORE_SMA_SW_1 */ - syscon-pol = <&scm_conf 0x534>; - }; + ranges = <0 0x58000000 0x800000>; - hdmi: encoder@58060000 { - compatible = "ti,dra7-hdmi"; - reg = <0x58040000 0x200>, - <0x58040200 0x80>, - <0x58040300 0x80>, - <0x58060000 0x19000>; - reg-names = "wp", "pll", "phy", "core"; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + dss: dss@0 { + compatible = "ti,dra7-dss"; + /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ + /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ status = "disabled"; - ti,hwmods = "dss_hdmi"; - clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - dmas = <&sdma_xbar 76>; - dma-names = "audio_tx"; + /* CTRL_CORE_DSS_PLL_CONTROL */ + syscon-pll-ctrl = <&scm_conf 0x538>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x800000>; + + target-module@1000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x1000 0x4>, + <0x1010 0x4>, + <0x1014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000 0x1000>; + + dispc@0 { + compatible = "ti,dra7-dispc"; + reg = <0 0x1000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; + clock-names = "fck"; + /* CTRL_CORE_SMA_SW_1 */ + syscon-pol = <&scm_conf 0x534>; + }; + }; + + target-module@40000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x40000 0x4>, + <0x40010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; + clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; + clock-names = "fck", "dss_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000 0x40000>; + + hdmi: encoder@0 { + compatible = "ti,dra7-hdmi"; + reg = <0 0x200>, + <0x200 0x80>, + <0x300 0x80>, + <0x20000 0x19000>; + reg-names = "wp", "pll", "phy", "core"; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>; + clock-names = "fck", "sys_clk"; + dmas = <&sdma_xbar 76>; + dma-names = "audio_tx"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts index fabeb7704753..a5d275ea7bd3 100644 --- a/arch/arm/boot/dts/dra71-evm.dts +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -17,6 +17,33 @@ reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + vpo_sd_1v8_3v3: gpio-regulator-TPS74801 { compatible = "regulator-gpio"; @@ -270,3 +297,18 @@ &extcon_usb2 { vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index 01558a86af82..c84b63bf0fc8 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -5,6 +5,7 @@ /dts-v1/; #include "dra72x.dtsi" +#include "dra7-ipu-dsp-common.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/ti-dra7-atl.h> @@ -583,23 +584,6 @@ rx-num-evt = <32>; }; -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; -}; - &pcie1_rc { status = "okay"; }; diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts index 2bb2e8be6276..6e70858f6313 100644 --- a/arch/arm/boot/dts/dra72-evm-revc.dts +++ b/arch/arm/boot/dts/dra72-evm-revc.dts @@ -14,6 +14,33 @@ reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_cma_pool: ipu2_cma@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_cma_pool: dsp1_cma@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_cma_pool: ipu1_cma@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + evm_1v8_sw: fixedregulator-evm_1v8 { compatible = "regulator-fixed"; regulator-name = "evm_1v8"; @@ -113,3 +140,18 @@ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; vmmc-supply = <&evm_1v8_sw>; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_cma_pool>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_cma_pool>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_cma_pool>; +}; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 9adb77585ef1..951152fe206a 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -12,6 +12,33 @@ reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + evm_1v8_sw: fixedregulator-evm_1v8 { compatible = "regulator-fixed"; regulator-name = "evm_1v8"; @@ -78,3 +105,18 @@ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>; vmmc-supply = <&evm_1v8_sw>; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index 82b57a35abc0..ae23ec14e8fa 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -10,6 +10,12 @@ / { compatible = "ti,dra722", "ti,dra72", "ti,dra7"; + aliases { + rproc0 = &ipu1; + rproc1 = &ipu2; + rproc2 = &dsp1; + }; + pmu { compatible = "arm,cortex-a15-pmu"; interrupt-parent = <&wakeupgen>; @@ -60,9 +66,9 @@ }; &dss { - reg = <0x58000000 0x80>, - <0x58004054 0x4>, - <0x58004300 0x20>; + reg = <0 0x80>, + <0x4054 0x4>, + <0x4300 0x20>; reg-names = "dss", "pll1_clkctrl", "pll1"; clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>, diff --git a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi new file mode 100644 index 000000000000..b1147a4b77f9 --- /dev/null +++ b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common IPU and DSP data for TI DRA74x/DRA76x/AM572x/AM574x platforms + */ + +#include "dra7-ipu-dsp-common.dtsi" + +&mailbox6 { + mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + status = "okay"; + }; +}; + +&dsp2 { + mboxes = <&mailbox6 &mbox_dsp2_ipc3x>; + ti,timers = <&timer6>; + ti,watchdog-timers = <&timer13>; +}; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index c5abc436ca1f..46d8e7615180 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -29,6 +29,13 @@ }; }; + aliases { + rproc0 = &ipu1; + rproc1 = &ipu2; + rproc2 = &dsp1; + rproc3 = &dsp2; + }; + pmu { compatible = "arm,cortex-a15-pmu"; interrupt-parent = <&wakeupgen>; @@ -124,6 +131,20 @@ ti,syscon-mmuconfig = <&dsp2_system 0x1>; }; }; + + dsp2: dsp@41000000 { + compatible = "ti,dra7-dsp"; + reg = <0x41000000 0x48000>, + <0x41600000 0x8000>, + <0x41700000 0x8000>; + reg-names = "l2ram", "l1pram", "l1dram"; + ti,bootreg = <&scm_conf 0x560 10>; + iommus = <&mmu0_dsp2>, <&mmu1_dsp2>; + status = "disabled"; + resets = <&prm_dsp2 0>; + clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; + firmware-name = "dra7-dsp2-fw.xe66"; + }; }; }; @@ -132,11 +153,11 @@ }; &dss { - reg = <0x58000000 0x80>, - <0x58004054 0x4>, - <0x58004300 0x20>, - <0x58009054 0x4>, - <0x58009300 0x20>; + reg = <0 0x80>, + <0x4054 0x4>, + <0x4300 0x20>, + <0x9054 0x4>, + <0x9300 0x20>; reg-names = "dss", "pll1_clkctrl", "pll1", "pll2_clkctrl", "pll2"; diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index e958cb3d1b31..820a0ece20d4 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -25,6 +25,40 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_cma_pool: ipu2_cma@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_cma_pool: dsp1_cma@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_cma_pool: ipu1_cma@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_cma_pool: dsp2_cma@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + vsys_12v0: fixedregulator-vsys12v0 { /* main supply */ compatible = "regulator-fixed"; @@ -548,3 +582,23 @@ data-lanes = <1 2>; }; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_cma_pool>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_cma_pool>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_cma_pool>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_cma_pool>; +}; diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi index 2f7539afef2b..42b8a205b64f 100644 --- a/arch/arm/boot/dts/dra76x.dtsi +++ b/arch/arm/boot/dts/dra76x.dtsi @@ -128,3 +128,8 @@ &usb4_tm { status = "disabled"; }; + +&mmc3 { + /* dra76x is not affected by i887 */ + max-frequency = <96000000>; +}; diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 55cef4cac5f1..dc0a93bccbf1 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -796,16 +796,6 @@ clock-div = <1>; }; - ipu1_gfclk_mux: ipu1_gfclk_mux@520 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>; - ti,bit-shift = <24>; - reg = <0x0520>; - assigned-clocks = <&ipu1_gfclk_mux>; - assigned-clock-parents = <&dpll_core_h22x2_ck>; - }; - dummy_ck: dummy_ck { #clock-cells = <0>; compatible = "fixed-clock"; @@ -1564,6 +1554,8 @@ compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; + assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>; + assigned-clock-parents = <&dpll_core_h22x2_ck>; }; ipu_clkctrl: ipu-clkctrl@50 { diff --git a/arch/arm/boot/dts/e60k02.dtsi b/arch/arm/boot/dts/e60k02.dtsi index ce50c4dc6f2a..3af1ab4458ef 100644 --- a/arch/arm/boot/dts/e60k02.dtsi +++ b/arch/arm/boot/dts/e60k02.dtsi @@ -117,6 +117,8 @@ ricoh619: pmic@32 { compatible = "ricoh,rc5t619"; reg = <0x32>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; system-power-controller; regulators { diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts index 5651ae6dc969..f6eb71553b95 100644 --- a/arch/arm/boot/dts/ecx-2000.dts +++ b/arch/arm/boot/dts/ecx-2000.dts @@ -13,7 +13,6 @@ compatible = "calxeda,ecx-2000"; #address-cells = <2>; #size-cells = <2>; - clock-ranges; cpus { #address-cells = <1>; @@ -83,8 +82,7 @@ intc: interrupt-controller@fff11000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <1>; + #address-cells = <0>; interrupt-controller; interrupts = <1 9 0xf04>; reg = <0xfff11000 0x1000>, @@ -95,7 +93,7 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; + interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>; }; }; }; diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi index 66ee1d34f72b..57a028a69373 100644 --- a/arch/arm/boot/dts/ecx-common.dtsi +++ b/arch/arm/boot/dts/ecx-common.dtsi @@ -27,10 +27,11 @@ reg = <0xffe08000 0x10000>; interrupts = <0 83 4>; dma-coherent; - calxeda,port-phys = <&combophy5 0 &combophy0 0 - &combophy0 1 &combophy0 2 - &combophy0 3>; - calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>; + calxeda,port-phys = < &combophy5 0>, <&combophy0 0>, + <&combophy0 1>, <&combophy0 2>, + <&combophy0 3>; + calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, + <&gpioh 7 1>; calxeda,led-order = <4 0 1 2 3>; }; @@ -114,8 +115,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xfff36000 0x1000>; interrupts = <0 20 4>; - clocks = <&pclk>; - clock-names = "apb_pclk"; + clocks = <&pclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; }; smic@fff3a000 { @@ -202,14 +203,14 @@ ethernet@fff50000 { compatible = "calxeda,hb-xgmac"; reg = <0xfff50000 0x1000>; - interrupts = <0 77 4 0 78 4 0 79 4>; + interrupts = <0 77 4>, <0 78 4>, <0 79 4>; dma-coherent; }; ethernet@fff51000 { compatible = "calxeda,hb-xgmac"; reg = <0xfff51000 0x1000>; - interrupts = <0 80 4 0 81 4 0 82 4>; + interrupts = <0 80 4>, <0 81 4>, <0 82 4>; dma-coherent; }; diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index dee35e3a5c4b..b27a82072365 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -23,7 +23,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x1ff00000>; + reg = <0x40000000 0x1f800000>; }; firmware@205f000 { diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index 248bd372fe70..ca29d7ed8216 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -57,7 +57,8 @@ i2c_max77836: i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&gpd0 2 GPIO_ACTIVE_HIGH>, <&gpd0 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpd0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpd0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 86c26a4edfd7..aba8350cfdaf 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -50,9 +50,15 @@ }; }; + wlan_pwrseq: mshc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; + }; + i2c_max77836: i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&gpd0 2 GPIO_ACTIVE_HIGH>, <&gpd0 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpd0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpd0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; @@ -605,8 +611,6 @@ }; &mshc_0 { - #address-cells = <1>; - #size-cells = <0>; broken-cd; non-removable; cap-mmc-highspeed; @@ -625,10 +629,48 @@ status = "okay"; }; +&mshc_1 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus1 &sd1_bus4>; + bus-width = <4>; + + mmc-pwrseq = <&wlan_pwrseq>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4334-fmac"; + reg = <1>; + + interrupt-parent = <&gpx1>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + &serial_0 { assigned-clocks = <&cmu CLK_SCLK_UART0>; assigned-clock-rates = <100000000>; status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpe0 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + clocks = <&s2mps14_osc S2MPS11_CLK_BT>; + }; }; &serial_1 { diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts new file mode 100644 index 000000000000..6d0c04d77a39 --- /dev/null +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -0,0 +1,768 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2020 Stenkin Evgeniy <stenkinevgeniy@gmail.com> + * Copyright (c) 2020 Paul Cercueil <paul@crapouillou.net> + */ + +/dts-v1/; +#include "exynos4210.dtsi" +#include "exynos4412-ppmu-common.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> + +/ { + model = "Samsung Galaxy S2 (GT-I9100)"; + compatible = "samsung,i9100", "samsung,exynos4210", "samsung,exynos4"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + vemmc_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + tsp_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "TSP_FIXED_VOLTAGES"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpl0 3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + cam_af_28v_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "8M_AF_2.8V_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + cam_io_en_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "CAM_IO_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpe2 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + cam_io_12v_reg: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "8M_1.2V_EN"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpe2 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vt_core_15v_reg: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "VT_CORE_1.5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpe2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + gpio-keys { + compatible = "gpio-keys"; + + vol-down { + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + label = "volume down"; + debounce-interval = <10>; + }; + + vol-up { + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + label = "volume up"; + debounce-interval = <10>; + }; + + power { + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + label = "power"; + debounce-interval = <10>; + wakeup-source; + }; + + ok { + gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; + linux,code = <KEY_OK>; + label = "ok"; + debounce-interval = <10>; + }; + }; + + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpl1 2 GPIO_ACTIVE_LOW>; + }; + + i2c_max17042_fuel: i2c-gpio { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sda-gpios = <&gpy4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + + battery@36 { + compatible = "maxim,max17042"; + + interrupt-parent = <&gpx2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&max17042_fuel_irq>; + pinctrl-names = "default"; + + reg = <0x36>; + maxim,over-heat-temp = <700>; + maxim,over-volt = <4500>; + }; + }; + + spi-lcd { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + num-chipselects = <1>; + cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>; + sck-gpios = <&gpy3 1 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpy3 3 GPIO_ACTIVE_HIGH>; + + lcd@0 { + compatible = "samsung,ld9040"; + reg = <0>; + + spi-max-frequency = <1200000>; + + vdd3-supply = <&vmipi_reg>; + vci-supply = <&vcclcd_reg>; + + reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; + power-on-delay = <10>; + reset-delay = <10>; + + panel-width-mm = <90>; + panel-height-mm = <154>; + + display-timings { + timing { + clock-frequency = <23492370>; + hactive = <480>; + vactive = <800>; + hback-porch = <16>; + hfront-porch = <16>; + vback-porch = <2>; + vfront-porch = <28>; + hsync-len = <2>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + lcd_ep: endpoint { + remote-endpoint = <&fimd_dpi_ep>; + }; + }; + }; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz */ + cooling-device = <&cpu0 2 2>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 4 4>; + }; + }; + }; + }; +}; + +&camera { + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&varm_breg>; +}; + +&ehci { + status = "okay"; + + phys = <&exynos_usbphy 1>; + phy-names = "host"; +}; + +&exynos_usbphy { + status = "okay"; + + vbus-supply = <&safe1_sreg>; +}; + +&fimc_0 { + status = "okay"; + + assigned-clocks = <&clock CLK_MOUT_FIMC0>, <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_1 { + status = "okay"; + + assigned-clocks = <&clock CLK_MOUT_FIMC1>, <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_2 { + status = "okay"; + + assigned-clocks = <&clock CLK_MOUT_FIMC2>, <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_3 { + status = "okay"; + + assigned-clocks = <&clock CLK_MOUT_FIMC3>, <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimd { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + samsung,invert-vden; + samsung,invert-vclk; + + pinctrl-0 = <&lcd_clk>, <&lcd_data24>; + pinctrl-names = "default"; + + port@3 { + reg = <3>; + + fimd_dpi_ep: endpoint { + remote-endpoint = <&lcd_ep>; + }; + }; +}; + +&gpu { + status = "okay"; + + mali-supply = <&vg3d_breg>; + regulator-microvolt-offset = <50000>; + regulator-microsecs-delay = <50>; +}; + +&hsotg { + status = "okay"; + + dr_mode = "otg"; + vusb_d-supply = <&vusb_reg>; + vusb_a-supply = <&vusbdac_reg>; +}; + +&i2c_3 { + status = "okay"; + + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + + mxt224-touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + + interrupt-parent = <&gpx0>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c_5 { + status = "okay"; + + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + + pinctrl-0 = <&i2c5_bus>; + pinctrl-names = "default"; + + max8997_pmic@66 { + compatible = "maxim,max8997-pmic"; + reg = <0x66>; + + interrupts-extended = <&gpx0 7 IRQ_TYPE_NONE>, + <&gpx2 3 IRQ_TYPE_EDGE_FALLING>; + + max8997,pmic-buck1-uses-gpio-dvs; + max8997,pmic-buck2-uses-gpio-dvs; + max8997,pmic-buck5-uses-gpio-dvs; + + max8997,pmic-ignore-gpiodvs-side-effect; + max8997,pmic-buck125-default-dvs-idx = <0>; + + max8997,pmic-buck125-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, + <&gpx0 6 GPIO_ACTIVE_HIGH>, + <&gpl0 0 GPIO_ACTIVE_HIGH>; + + max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; + + max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>, + <950000>, <900000>, + <1100000>, <1000000>, + <950000>, <900000>; + + max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + pinctrl-0 = <&max8997_irq>, <&otg_gp>, <&usb_sel>; + pinctrl-names = "default"; + + regulators { + vadc_reg: LDO1 { + regulator-name = "VADC_3.3V_C210"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + }; + valive_reg: LDO2 { + regulator-name = "VALIVE_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + + }; + + vusb_reg: LDO3 { + regulator-name = "VUSB_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vmipi_reg: LDO4 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vhsic_reg: LDO5 { + regulator-name = "VHSIC_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vpda_reg: LDO6 { + regulator-name = "VCC_1.8V_PDA"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcam_reg: LDO7 { + regulator-name = "CAM_ISP_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vusbdac_reg: LDO8 { + regulator-name = "VUSB+VDAC_3.3V_C210"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccpda_reg: LDO9 { + regulator-name = "VCC_2.8V_PDA"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vtouch_reg: LDO11 { + regulator-name = "TOUCH_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vpll_reg: LDO10 { + regulator-name = "VPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vtcam_reg: LDO12 { + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcclcd_reg: LDO13 { + regulator-name = "VCC_3.0V_LCD"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + vmotor_reg: LDO14 { + regulator-name = "VCC_2.8V_MOTOR"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vled_reg: LDO15 { + regulator-name = "LED_A_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + camsensor_reg: LDO16 { + regulator-name = "CAM_SENSOR_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vtf_reg: LDO17 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vtouchled_reg: LDO18 { + regulator-name = "TOUCH_LED_3.3V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + vddq_reg: LDO21 { + regulator-name = "VDDQ_M1M2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + varm_breg: BUCK1 { + regulator-name = "VARM_1.2V_C210"; + regulator-min-microvolt = <65000>; + regulator-max-microvolt = <2225000>; + regulator-always-on; + }; + + vint_breg: BUCK2 { + regulator-name = "VINT_1.1V_C210"; + regulator-min-microvolt = <65000>; + regulator-max-microvolt = <2225000>; + regulator-always-on; + }; + + vg3d_breg: BUCK3 { + regulator-name = "G3D_1.1V"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + camisp_breg: BUCK4 { + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vmem_breg: BUCK5 { + regulator-name = "VMEM_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vccsub_breg: BUCK7 { + regulator-name = "VCC_SUB_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + safe1_sreg: ESAFEOUT1 { + regulator-name = "SAFEOUT1"; + }; + + safe2_sreg: ESAFEOUT2 { + regulator-name = "SAFEOUT2"; + regulator-boot-on; + }; + + charger_reg: CHARGER { + regulator-name = "CHARGER"; + regulator-min-microamp = <60000>; + regulator-max-microamp = <2580000>; + regulator-always-on; + }; + + chargercv_reg: CHARGER_CV { + regulator-name = "CHARGER_CV"; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <4100000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c_7 { + status = "okay"; + + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + + pinctrl-0 = <&i2c7_bus>; + pinctrl-names = "default"; + + ak8975@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + + gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + sleep0: sleep-states { + gpa0-0 { + samsung,pins = "gpa0-0"; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; + + gpa0-1 { + samsung,pins = "gpa0-1"; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT0>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; + + gpa0-2 { + samsung,pins = "gpa0-2"; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; + + gpa0-3 { + samsung,pins = "gpa0-3"; + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>; + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + }; + }; +}; + +&pinctrl_1 { + mhl_int: mhl-int { + samsung,pins = "gpf3-5"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + i2c_mhl_bus: i2c-mhl-bus { + samsung,pins = "gpf0-4", "gpf0-6"; + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + usb_sel: usb-sel { + samsung,pins = "gpl0-6"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-val = <0>; + }; + + bt_en: bt-en { + samsung,pins = "gpl0-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-val = <0>; + }; + + bt_res: bt-res { + samsung,pins = "gpl1-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-val = <0>; + }; + + otg_gp: otg-gp { + samsung,pins = "gpx3-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-val = <0>; + }; + + mag_mhl_gpio: mag-mhl-gpio { + samsung,pins = "gpd0-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + max8997_irq: max8997-irq { + samsung,pins = "gpx0-7"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + max17042_fuel_irq: max17042-fuel-irq { + samsung,pins = "gpx2-3"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + tsp224_irq: tsp224-irq { + samsung,pins = "gpx0-4"; + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; + }; +}; + +&sdhci_0 { + status = "okay"; + + bus-width = <8>; + non-removable; + vmmc-supply = <&vemmc_reg>; + + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_bus8>; + pinctrl-names = "default"; +}; + +&sdhci_2 { + status = "okay"; + + bus-width = <4>; + cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vtf_reg>; + + pinctrl-0 = <&sd2_clk>, <&sd2_cmd>, <&sd2_bus4>; + pinctrl-names = "default"; +}; + +&sdhci_3 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wlan_pwrseq>; + vmmc-supply = <&vtf_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4330-fmac"; + reg = <1>; + + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&serial_0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&bt_en>, <&bt_res>, <&uart0_data>, <&uart0_fctl>; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + + shutdown-gpios = <&gpl0 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpl1 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&tmu { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 0d1e1a9c2f6e..890525b10d22 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -251,12 +251,7 @@ }; buck1_reg: BUCK1 { - /* - * HACK: The real name is VDD_ARM_1.2V, - * but exynos-cpufreq does not support - * DT-based regulator lookup yet. - */ - regulator-name = "vdd_arm"; + regulator-name = "VDD_ARM_1.2V"; regulator-min-microvolt = <950000>; regulator-max-microvolt = <1350000>; regulator-always-on; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 7c39dd1c4d3a..3d791db6095c 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -121,6 +121,11 @@ }; }; + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpl1 2 GPIO_ACTIVE_LOW>; + }; + fixed-rate-clocks { xxti { compatible = "samsung,clock-xxti"; @@ -280,11 +285,10 @@ max8997_pmic@66 { compatible = "maxim,max8997-pmic"; - interrupts-extended = <&gpx0 7 0>, <&gpx2 3 0>; reg = <0x66>; - interrupt-parent = <&gpx0>; - interrupts = <7 IRQ_TYPE_NONE>; + interrupts-extended = <&gpx0 7 IRQ_TYPE_LEVEL_LOW>, + <&gpx2 3 IRQ_TYPE_EDGE_FALLING>; max8997,pmic-buck1-uses-gpio-dvs; max8997,pmic-buck2-uses-gpio-dvs; @@ -403,12 +407,7 @@ }; varm_breg: BUCK1 { - /* - * HACK: The real name is VARM_1.2V_C210, - * but exynos-cpufreq does not support - * DT-based regulator lookup yet. - */ - regulator-name = "vdd_arm"; + regulator-name = "VARM_1.2V_C210"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -471,6 +470,30 @@ status = "okay"; }; +&sdhci_3 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wlan_pwrseq>; + vmmc-supply = <&tflash_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4330-fmac"; + reg = <1>; + + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + &serial_0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index a1bdf7830a87..02fde1a75ebd 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -50,6 +50,11 @@ enable-active-high; }; + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpe3 1 GPIO_ACTIVE_LOW>; + }; + gpio-keys { compatible = "gpio-keys"; @@ -115,7 +120,7 @@ gpio-sck = <&gpy3 1 GPIO_ACTIVE_HIGH>; gpio-mosi = <&gpy3 3 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; - cs-gpios = <&gpy4 3 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>; lcd@0 { compatible = "samsung,ld9040"; @@ -124,8 +129,6 @@ vci-supply = <&ldo17_reg>; reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; spi-max-frequency = <1200000>; - spi-cpol; - spi-cpha; power-on-delay = <10>; reset-delay = <10>; panel-width-mm = <90>; @@ -166,7 +169,8 @@ hdmi_ddc: i2c-ddc { compatible = "i2c-gpio"; - gpios = <&gpe4 2 GPIO_ACTIVE_HIGH &gpe4 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpe4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpe4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <100>; #address-cells = <1>; #size-cells = <0>; @@ -319,7 +323,7 @@ max8952,sync-freq = <0>; max8952,ramp-speed = <0>; - regulator-name = "vdd_arm"; + regulator-name = "VARM_1.2V_C210"; regulator-min-microvolt = <770000>; regulator-max-microvolt = <1400000>; regulator-always-on; @@ -565,6 +569,29 @@ status = "okay"; }; +&sdhci_3 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wlan_pwrseq>; + vmmc-supply = <&ldo5_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4330-fmac"; + reg = <1>; + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + &serial_0 { status = "okay"; /delete-property/dmas; diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi index 31719c079d67..53b3ca3effab 100644 --- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi +++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi @@ -33,7 +33,7 @@ }; }; - lcd_vdd3_reg: voltage-regulator-6 { + lcd_vdd3_reg: voltage-regulator-7 { compatible = "regulator-fixed"; regulator-name = "LCD_VDD_2.2V"; regulator-min-microvolt = <2200000>; @@ -42,7 +42,7 @@ enable-active-high; }; - ps_als_reg: voltage-regulator-7 { + ps_als_reg: voltage-regulator-8 { compatible = "regulator-fixed"; regulator-name = "LED_A_3.0V"; regulator-min-microvolt = <3000000>; @@ -53,7 +53,8 @@ i2c_ak8975: i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&gpy2 4 GPIO_ACTIVE_HIGH>, <&gpy2 5 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpy2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; @@ -68,7 +69,8 @@ i2c_cm36651: i2c-gpio-2 { compatible = "i2c-gpio"; - gpios = <&gpf0 0 GPIO_ACTIVE_LOW>, <&gpf0 1 GPIO_ACTIVE_LOW>; + sda-gpios = <&gpf0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpf0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 3023bc3b68ce..2c8111c6b065 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -140,7 +140,8 @@ i2c_max77693: i2c-gpio-1 { compatible = "i2c-gpio"; - gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpm2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpm2 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; @@ -188,7 +189,8 @@ i2c_max77693_fuel: i2c-gpio-3 { compatible = "i2c-gpio"; - gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>, <&gpf1 4 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpf1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpf1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; @@ -228,7 +230,8 @@ i2c-mhl { compatible = "i2c-gpio"; - gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpf0 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpf0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <100>; #address-cells = <1>; #size-cells = <0>; @@ -820,7 +823,7 @@ }; buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; + regulator-name = "VDD_MIF"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1100000>; regulator-always-on; @@ -831,7 +834,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; + regulator-name = "VDD_ARM"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -842,7 +845,7 @@ }; buck3_reg: BUCK3 { - regulator-name = "vdd_int"; + regulator-name = "VDD_INT"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1150000>; regulator-always-on; @@ -853,7 +856,7 @@ }; buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; + regulator-name = "VDD_G3D"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1150000>; regulator-boot-on; diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/exynos4412-n710x.dts index 98cd1284cd90..4189e1fb204c 100644 --- a/arch/arm/boot/dts/exynos4412-n710x.dts +++ b/arch/arm/boot/dts/exynos4412-n710x.dts @@ -13,7 +13,7 @@ /* bootargs are passed in by bootloader */ - cam_vdda_reg: voltage-regulator-6 { + cam_vdda_reg: voltage-regulator-7 { compatible = "regulator-fixed"; regulator-name = "CAM_SENSOR_CORE_1.2V"; regulator-min-microvolt = <1200000>; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 9c39e82e4ecb..a5c1ce1e396c 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -165,6 +165,15 @@ cpu0-supply = <&buck2_reg>; }; +&cpu0_opp_table { + opp-1000000000 { + opp-suspend; + }; + opp-800000000 { + /delete-property/opp-suspend; + }; +}; + &pinctrl_1 { gpio_power_key: power_key { samsung,pins = "gpx1-3"; @@ -421,7 +430,7 @@ }; buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; + regulator-name = "VDD_MIF"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1100000>; regulator-always-on; @@ -429,7 +438,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; + regulator-name = "VDD_ARM"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -437,7 +446,7 @@ }; buck3_reg: BUCK3 { - regulator-name = "vdd_int"; + regulator-name = "VDD_INT"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1050000>; regulator-always-on; @@ -445,7 +454,7 @@ }; buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; + regulator-name = "VDD_G3D"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1100000>; regulator-microvolt-offset = <50000>; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index ecd14b283a6b..dc865be40751 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -363,7 +363,7 @@ }; buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; + regulator-name = "VDD_MIF"; regulator-min-microvolt = <950000>; regulator-max-microvolt = <1100000>; regulator-always-on; @@ -372,7 +372,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; + regulator-name = "VDD_ARM"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -381,7 +381,7 @@ }; buck3_reg: BUCK3 { - regulator-name = "vdd_int"; + regulator-name = "VDD_INT"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1200000>; regulator-always-on; @@ -390,7 +390,7 @@ }; buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; + regulator-name = "VDD_G3D"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -399,7 +399,7 @@ }; buck5_reg: BUCK5 { - regulator-name = "vdd_m12"; + regulator-name = "VDD_M12"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -408,7 +408,7 @@ }; buck6_reg: BUCK6 { - regulator-name = "vdd12_5m"; + regulator-name = "VDD12_5M"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -417,7 +417,7 @@ }; buck9_reg: BUCK9 { - regulator-name = "vddf28_emmc"; + regulator-name = "VDDF28_EMMC"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <3000000>; regulator-always-on; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index f8ebc620f42d..c4cc7611898c 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -93,22 +93,23 @@ compatible = "regulator-fixed"; reg = <0>; regulator-name = "MAIN_DC"; + regulator-always-on; }; mmc_reg: regulator@1 { compatible = "regulator-fixed"; reg = <1>; - regulator-name = "VDD_33ON_2.8V"; + regulator-name = "VDD_MMC"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; + regulator-always-on; }; reg_hdmi_en: regulator@2 { compatible = "regulator-fixed"; reg = <2>; regulator-name = "hdmi-en"; + regulator-always-on; }; vcc_1v2_reg: regulator@3 { @@ -117,6 +118,7 @@ regulator-name = "VCC_1V2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + regulator-always-on; }; vcc_1v8_reg: regulator@4 { @@ -125,6 +127,7 @@ regulator-name = "VCC_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; }; vcc_3v3_reg: regulator@5 { @@ -133,6 +136,7 @@ regulator-name = "VCC_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; }; @@ -450,7 +454,7 @@ }; buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; + regulator-name = "VDD_MIF"; regulator-min-microvolt = <950000>; regulator-max-microvolt = <1200000>; regulator-always-on; @@ -459,7 +463,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; + regulator-name = "VDD_ARM"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1300000>; regulator-always-on; @@ -468,7 +472,7 @@ }; buck3_reg: BUCK3 { - regulator-name = "vdd_int"; + regulator-name = "VDD_INT"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1200000>; regulator-always-on; @@ -477,7 +481,7 @@ }; buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; + regulator-name = "VDD_G3D"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1300000>; regulator-always-on; @@ -637,9 +641,8 @@ pinctrl-0 = <&i2c2_gpio_bus>; status = "okay"; compatible = "i2c-gpio"; - gpios = <&gpa0 6 0 /* sda */ - &gpa0 7 0 /* scl */ - >; + sda-gpios = <&gpa0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpa0 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index ee28d30f5476..dd7f8385d81e 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -584,6 +584,7 @@ regulator-name = "PVDD_G3DS_1V0"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1100000>; + regulator-always-on; regulator-state-mem { regulator-on-in-suspend; @@ -672,7 +673,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; + regulator-name = "PVDD_ARM_1V0"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -697,6 +698,7 @@ regulator-name = "PVDD_G3D_1V0"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; + regulator-always-on; regulator-state-mem { regulator-off-in-suspend; diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi index 1b8605cf2407..4b641b9b8179 100644 --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -31,6 +31,7 @@ operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <539>; + dynamic-power-coefficient = <90>; }; cpu1: cpu@101 { @@ -43,6 +44,7 @@ operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <539>; + dynamic-power-coefficient = <90>; }; cpu2: cpu@102 { @@ -55,6 +57,7 @@ operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <539>; + dynamic-power-coefficient = <90>; }; cpu3: cpu@103 { @@ -67,6 +70,7 @@ operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <539>; + dynamic-power-coefficient = <90>; }; cpu4: cpu@0 { @@ -79,6 +83,7 @@ operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <310>; }; cpu5: cpu@1 { @@ -91,6 +96,7 @@ operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <310>; }; cpu6: cpu@2 { @@ -103,6 +109,7 @@ operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <310>; }; cpu7: cpu@3 { @@ -115,6 +122,7 @@ operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <310>; }; }; }; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 5cf1aed20490..ab27ff8bc3dc 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -901,6 +901,7 @@ regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; regulator-boot-on; + regulator-always-on; regulator-state-mem { regulator-off-in-suspend; diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts index f163206265bb..812659260278 100644 --- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts +++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts @@ -215,6 +215,36 @@ }; }; }; + gpu_thermal: gpu-thermal { + thermal-sensors = <&tmu_gpu 0>; + trips { + gpu_alert0: gpu-alert-0 { + temperature = <70000>; + hysteresis = <10000>; + type = "active"; + }; + gpu_alert1: gpu-alert-1 { + temperature = <85000>; + hysteresis = <10000>; + type = "active"; + }; + gpu_crit0: gpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&gpu 0 2>; + }; + map1 { + trip = <&gpu_alert1>; + cooling-device = <&gpu 3 6>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 1865a708b49f..5da2d81e3be2 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -357,6 +357,65 @@ }; }; }; + gpu_thermal: gpu-thermal { + thermal-sensors = <&tmu_gpu 0>; + polling-delay-passive = <250>; + polling-delay = <0>; + trips { + gpu_alert0: gpu-alert-0 { + temperature = <50000>; + hysteresis = <5000>; + type = "active"; + }; + gpu_alert1: gpu-alert-1 { + temperature = <60000>; + hysteresis = <5000>; + type = "active"; + }; + gpu_alert2: gpu-alert-2 { + temperature = <70000>; + hysteresis = <5000>; + type = "active"; + }; + gpu_crit0: gpu-crit-0 { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + gpu_alert3: gpu-alert-3 { + temperature = <70000>; + hysteresis = <10000>; + type = "passive"; + }; + gpu_alert4: gpu-alert-4 { + temperature = <85000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&fan0 0 1>; + }; + map1 { + trip = <&gpu_alert1>; + cooling-device = <&fan0 1 2>; + }; + map2 { + trip = <&gpu_alert2>; + cooling-device = <&fan0 2 3>; + }; + map3 { + trip = <&gpu_alert3>; + cooling-device = <&gpu 0 2>; + }; + map4 { + trip = <&gpu_alert4>; + cooling-device = <&gpu 3 6>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts index e2030ba16512..cc39289e99dd 100644 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts @@ -119,13 +119,11 @@ /* * This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM. - * Since the platform has no temperature sensor, this is controlled - * from userspace by using the hard disks S.M.A.R.T. temperature * sensor. It is turned on when the temperature exceeds 46 degrees * and turned off when the temperatures goes below 41 degrees * (celsius). */ - gpio-fan { + fan0: gpio-fan { compatible = "gpio-fan"; /* Collides with IDE */ gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; @@ -133,6 +131,40 @@ #cooling-cells = <2>; }; + thermal-zones { + chassis-thermal { + /* Poll every 20 seconds */ + polling-delay = <20000>; + /* Poll every 2nd second when cooling */ + polling-delay-passive = <2000>; + /* Use the thermal sensor in the hard drive */ + thermal-sensors = <&drive0>; + + /* Tripping points from the fan.script in the rootfs */ + trips { + alert: chassis-alert { + /* At 43 degrees turn on the fan */ + temperature = <43000>; + hysteresis = <3000>; + type = "active"; + }; + crit: chassis-crit { + /* Just shut down at 60 degrees */ + temperature = <60000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&alert>; + cooling-device = <&fan0 1 1>; + }; + }; + }; + }; + /* * The touchpad input is connected to a GPIO bit-banged * I2C bus. @@ -443,8 +475,18 @@ }; }; - ata@63000000 { + ide@63000000 { status = "okay"; + + /* + * This drive may have a temperature sensor with a + * thermal zone we can use for thermal control of the + * chassis temperature using the fan. + */ + drive0: ide-port@0 { + reg = <0>; + #thermal-sensor-cells = <0>; + }; }; display-controller@6a000000 { diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini-dlink-dns-313.dts index 360642a02a48..c6f3d90e3e90 100644 --- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts +++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts @@ -297,7 +297,7 @@ }; }; - ata@63000000 { + ide@63000000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts index 521714f38eed..43c45f7e1e0a 100644 --- a/arch/arm/boot/dts/gemini-nas4220b.dts +++ b/arch/arm/boot/dts/gemini-nas4220b.dts @@ -170,11 +170,11 @@ }; }; - ata@63000000 { + ide@63000000 { status = "okay"; }; - ata@63400000 { + ide@63400000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/gemini-sl93512r.dts b/arch/arm/boot/dts/gemini-sl93512r.dts index a98af0351906..a0916d3c1059 100644 --- a/arch/arm/boot/dts/gemini-sl93512r.dts +++ b/arch/arm/boot/dts/gemini-sl93512r.dts @@ -293,11 +293,11 @@ }; }; - ata@63000000 { + ide@63000000 { status = "okay"; }; - ata@63400000 { + ide@63400000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts index 239dfacaae4d..0c6e6d35bfaa 100644 --- a/arch/arm/boot/dts/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini-sq201.dts @@ -289,7 +289,7 @@ }; }; - ata@63000000 { + ide@63000000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index 8cf67b11751f..065ed10a79fa 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -356,7 +356,7 @@ }; }; - ata@63000000 { + ide@63000000 { compatible = "cortina,gemini-pata", "faraday,ftide010"; reg = <0x63000000 0x1000>; interrupts = <4 IRQ_TYPE_EDGE_RISING>; @@ -365,9 +365,11 @@ clock-names = "PCLK"; sata = <&sata>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; - ata@63400000 { + ide@63400000 { compatible = "cortina,gemini-pata", "faraday,ftide010"; reg = <0x63400000 0x1000>; interrupts = <5 IRQ_TYPE_EDGE_RISING>; @@ -376,6 +378,8 @@ clock-names = "PCLK"; sata = <&sata>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; dma-controller@67000000 { diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts index f4e4dca6f7e7..b6b0225a769e 100644 --- a/arch/arm/boot/dts/highbank.dts +++ b/arch/arm/boot/dts/highbank.dts @@ -13,7 +13,6 @@ compatible = "calxeda,highbank"; #address-cells = <1>; #size-cells = <1>; - clock-ranges; cpus { #address-cells = <1>; @@ -96,7 +95,7 @@ }; }; - memory { + memory@0 { name = "memory"; device_type = "memory"; reg = <0x00000000 0xff900000>; @@ -128,14 +127,12 @@ intc: interrupt-controller@fff11000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <1>; interrupt-controller; reg = <0xfff11000 0x1000>, <0xfff10100 0x100>; }; - L2: l2-cache { + L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0xfff12000 0x1000>; interrupts = <0 70 4>; @@ -145,14 +142,14 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; + interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>; }; sregs@fff3c200 { compatible = "calxeda,hb-sregs-l2-ecc"; reg = <0xfff3c200 0x100>; - interrupts = <0 71 4 0 72 4>; + interrupts = <0 71 4>, <0 72 4>; }; }; diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index 4c9aafe00b5d..0729e72f2283 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts @@ -23,7 +23,7 @@ ssp0: spi@80010000 { compatible = "fsl,imx23-mmc"; pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; bus-width = <4>; broken-cd; status = "okay"; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 8257630f7a49..c5edff381213 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -267,6 +267,14 @@ fsl,pull-up = <MXS_PULL_DISABLE>; }; + mmc0_sck_cfg: mmc0-sck-cfg@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_SSP1_SCK__SSP1_SCK + >; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + mmc1_4bit_pins_a: mmc1-4bit@0 { reg = <0>; fsl,pinmux-ids = < @@ -422,7 +430,7 @@ clocks = <&clks 16>; }; - dcp@80028000 { + dcp: crypto@80028000 { compatible = "fsl,imx23-dcp"; reg = <0x80028000 0x2000>; interrupts = <53 54>; diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h index f4516ccf2c1a..111bfdcbe552 100644 --- a/arch/arm/boot/dts/imx25-pinfunc.h +++ b/arch/arm/boot/dts/imx25-pinfunc.h @@ -82,6 +82,7 @@ #define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x00 0x000 #define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x04 0x000 #define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x05 0x000 +#define MX25_PAD_EB0__CSPI3_SS0 0x040 0x258 0x4bc 0x06 0x000 #define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x00 0x000 #define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x04 0x000 @@ -102,11 +103,13 @@ #define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000 #define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x03 0x000 #define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x05 0x000 +#define MX25_PAD_CS4__CSPI3_MOSI 0x054 0x264 0x4b8 0x06 0x000 #define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x00 0x000 #define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000 #define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x03 0x000 #define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x05 0x000 +#define MX25_PAD_CS5__CSPI3_MISO 0x058 0x268 0x4b4 0x06 0x000 #define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x00 0x000 #define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x05 0x000 @@ -114,6 +117,7 @@ #define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x00 0x000 #define MX25_PAD_ECB__UART5_TXD 0x060 0x270 0x000 0x03 0x000 #define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x05 0x000 +#define MX25_PAD_ECB__CSPI3_SCLK 0x060 0x270 0x4ac 0x06 0x000 #define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x00 0x000 #define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x03 0x000 @@ -251,10 +255,12 @@ #define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x00 0x000 #define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000 +#define MX25_PAD_LD12__KPP_ROW6 0x0f8 0x2f0 0x544 0x04 0x000 #define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x05 0x001 #define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x00 0x000 #define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000 +#define MX25_PAD_LD13__KPP_ROW7 0x0fc 0x2f4 0x548 0x04 0x000 #define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x05 0x000 #define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x00 0x000 @@ -512,9 +518,11 @@ #define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x00 0x000 #define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x05 0x000 +#define MX25_PAD_FEC_TX_EN__KPP_ROW4 0x1d8 0x3d0 0x53c 0x06 0x000 #define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x00 0x000 #define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x05 0x000 +#define MX25_PAD_FEC_RDATA0__KPP_ROW5 0x1dc 0x3d4 0x540 0x06 0x000 #define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x00 0x000 /* diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 40b95a290bd6..1123e683025c 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -75,7 +75,7 @@ interrupt-parent = <&asic>; ranges; - aips@43f00000 { /* AIPS1 */ + bus@43f00000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -332,7 +332,7 @@ }; }; - aips@53f00000 { /* AIPS2 */ + bus@53f00000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index f3464cf52e49..002cd223f22d 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -525,7 +525,7 @@ reg = <0x10024600 0x200>; }; - sahara2: sahara@10025000 { + sahara2: crypto@10025000 { compatible = "fsl,imx27-sahara"; reg = <0x10025000 0x1000>; interrupts = <59>; diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index 3a184d13887b..c5acc19c982d 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -183,10 +183,20 @@ pinctrl-0 = <&auart2_2pins_a>; status = "okay"; }; + + usbphy1: usbphy@8007e000 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_a>; + status = "okay"; + }; }; }; ahb@80080000 { + usb1: usb@80090000 { + status = "okay"; + }; + mac0: ethernet@800f0000 { phy-mode = "rmii"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index e14d8ef0158b..a1cbbeb39a4f 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -998,7 +998,7 @@ clocks = <&clks 26>; }; - dcp: dcp@80028000 { + dcp: crypto@80028000 { compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; reg = <0x80028000 0x2000>; interrupts = <52 53 54>; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 6b62f0745b82..18270ec648fe 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -63,7 +63,7 @@ ranges = <0 0x1fffc000 0x4000>; }; - aips@43f00000 { /* AIPS1 */ + bus@43f00000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -225,7 +225,7 @@ }; }; - aips@53f00000 { /* AIPS2 */ + bus@53f00000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 9cbdc1a15cda..2ebf2c1fa682 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -66,7 +66,7 @@ cache-level = <2>; }; - aips1: aips@43f00000 { + aips1: bus@43f00000 { compatible = "fsl,aips", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -199,7 +199,7 @@ }; }; - aips2: aips@53f00000 { + aips2: bus@53f00000 { compatible = "fsl,aips", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 0bfe7c91d0eb..1f4ecbca5225 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -101,7 +101,7 @@ interrupt-parent = <&tzic>; ranges; - aips@50000000 { /* AIPS1 */ + bus@50000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -288,11 +288,6 @@ reg = <0x53fa8000 0x4000>; }; - gpr: iomuxc-gpr@53fa8000 { - compatible = "fsl,imx50-iomuxc-gpr", "syscon"; - reg = <0x53fa8000 0xc>; - }; - pwm1: pwm@53fb4000 { #pwm-cells = <2>; compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; @@ -333,9 +328,10 @@ status = "disabled"; }; - src: src@53fd0000 { + src: reset-controller@53fd0000 { compatible = "fsl,imx50-src", "fsl,imx51-src"; reg = <0x53fd0000 0x4000>; + interrupts = <75>; #reset-cells = <1>; }; @@ -389,7 +385,7 @@ }; }; - aips@60000000 { /* AIPS2 */ + bus@60000000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index 3596060f52e7..e559ab0c3645 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -217,8 +217,8 @@ simple-audio-card,widgets = "Headphone", "Headphone Jack"; simple-audio-card,routing = - "Headphone Jack", "HPLEFT", - "Headphone Jack", "HPRIGHT"; + "Headphone Jack", "TPA6130A2 HPLEFT", + "Headphone Jack", "TPA6130A2 HPRIGHT"; simple-audio-card,aux-devs = <&hpa1>; sound_cpu: simple-audio-card,cpu { @@ -470,6 +470,7 @@ compatible = "ti,tpa6130a2"; reg = <0x60>; Vdd-supply = <®_3p3v>; + sound-name-prefix = "TPA6130A2"; }; ds1341: rtc@68 { diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index dea86b98e9c3..d3583aad8323 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -104,6 +104,11 @@ #phy-cells = <0>; }; + capture-subsystem { + compatible = "fsl,imx-capture-subsystem"; + ports = <&ipu_csi0>, <&ipu_csi1>; + }; + display-subsystem { compatible = "fsl,imx-display-subsystem"; ports = <&ipu_di0>, <&ipu_di1>; @@ -143,6 +148,14 @@ clock-names = "bus", "di0", "di1"; resets = <&src 2>; + ipu_csi0: port@0 { + reg = <0>; + }; + + ipu_csi1: port@1 { + reg = <1>; + }; + ipu_di0: port@2 { reg = <2>; @@ -158,7 +171,7 @@ }; }; - aips@70000000 { /* AIPS1 */ + bus@70000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -426,9 +439,10 @@ status = "disabled"; }; - src: src@73fd0000 { + src: reset-controller@73fd0000 { compatible = "fsl,imx51-src"; reg = <0x73fd0000 0x4000>; + interrupts = <75>; #reset-cells = <1>; }; @@ -440,7 +454,7 @@ }; }; - aips@80000000 { /* AIPS2 */ + bus@80000000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx53-cx9020.dts b/arch/arm/boot/dts/imx53-cx9020.dts index 0a475c234054..cfb18849a92b 100644 --- a/arch/arm/boot/dts/imx53-cx9020.dts +++ b/arch/arm/boot/dts/imx53-cx9020.dts @@ -59,23 +59,26 @@ }; dvi-converter { - #address-cells = <1>; - #size-cells = <0>; compatible = "ti,tfp410"; - port@0 { - reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; - tfp410_in: endpoint { - remote-endpoint = <&display0_out>; + tfp410_in: endpoint { + remote-endpoint = <&display0_out>; + }; }; - }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; }; }; }; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index ed341cfd9d09..afa57bf7b0ed 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -222,7 +222,7 @@ clock-names = "core_clk", "mem_iface_clk"; }; - aips@50000000 { /* AIPS1 */ + bus@50000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -588,9 +588,10 @@ status = "disabled"; }; - src: src@53fd0000 { + src: reset-controller@53fd0000 { compatible = "fsl,imx53-src", "fsl,imx51-src"; reg = <0x53fd0000 0x4000>; + interrupts = <75>; #reset-cells = <1>; }; @@ -654,7 +655,7 @@ }; }; - aips@60000000 { /* AIPS2 */ + bus@60000000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index cd075621de52..65359aece950 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2014-2016 Toradex AG + * Copyright 2014-2020 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -275,7 +239,7 @@ /* SRAM on Colibri nEXT_CS0 */ sram@0,0 { - compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram"; + compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram"; reg = <0 0 0x00010000>; #address-cells = <1>; #size-cells = <1>; @@ -286,7 +250,7 @@ /* SRAM on Colibri nEXT_CS1 */ sram@1,0 { - compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram"; + compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram"; reg = <1 0 0x00010000>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts new file mode 100644 index 000000000000..223275f028f1 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +/dts-v1/; + +#include "imx6dl-colibri-eval-v3.dts" +#include "imx6qdl-colibri-v1_1-uhs.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S V1.1 on Colibri Evaluation Board V3"; + compatible = "toradex,colibri_imx6dl-v1_1-eval-v3", + "toradex,colibri_imx6dl-v1_1", + "toradex,colibri_imx6dl-eval-v3", + "toradex,colibri_imx6dl", + "fsl,imx6dl"; +}; + +/* Colibri MMC */ +&usdhc1 { + status = "okay"; + /* + * Please make sure your carrier board does not pull-up any of + * the MMC/SD signals to 3.3 volt before attempting to activate + * UHS-I support. + * To let signaling voltage be changed to 1.8V, please + * delete no-1-8-v property (example below): + * /delete-property/no-1-8-v; + */ +}; diff --git a/arch/arm/boot/dts/imx6dl-pico-dwarf.dts b/arch/arm/boot/dts/imx6dl-pico-dwarf.dts new file mode 100644 index 000000000000..659a8e8714ea --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-pico-dwarf.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng <wig.cheng@technexion.com> +// Richard Hu <richard.hu@technexion.com> +// Tapani Utriainen <tapani@technexion.com> + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-pico-pi.dtsi" + +/ { + model = "TechNexion PICO-IMX6 DualLite/Solo Board and Dwarf baseboard"; + compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-pico-hobbit.dts b/arch/arm/boot/dts/imx6dl-pico-hobbit.dts new file mode 100644 index 000000000000..d7403c5c4337 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-pico-hobbit.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng <wig.cheng@technexion.com> +// Richard Hu <richard.hu@technexion.com> +// Tapani Utriainen <tapani@technexion.com> + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-pico-hobbit.dtsi" + +/ { + model = "TechNexion PICO-IMX6 DualLite/Solo Board and Hobbit baseboard"; + compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-pico-nymph.dts b/arch/arm/boot/dts/imx6dl-pico-nymph.dts new file mode 100644 index 000000000000..b282dbf953aa --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-pico-nymph.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng <wig.cheng@technexion.com> +// Richard Hu <richard.hu@technexion.com> +// Tapani Utriainen <tapani@technexion.com> + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-pico-pi.dtsi" + +/ { + model = "TechNexion PICO-IMX6 DualLite/Solo Board and Nymph baseboard"; + compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-pico-pi.dts b/arch/arm/boot/dts/imx6dl-pico-pi.dts new file mode 100644 index 000000000000..b7b1c07f96f3 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-pico-pi.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng <wig.cheng@technexion.com> +// Richard Hu <richard.hu@technexion.com> +// Tapani Utriainen <tapani@technexion.com> + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-pico-pi.dtsi" + +/ { + model = "TechNexion PICO-IMX6 DualLite/Solo Board and PI baseboard"; + compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 829654e1835a..065d3ab0f50a 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -89,11 +89,25 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + phy-handle = <&rgmii_phy>; interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; fsl,err006687-workaround-present; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Atheros AR8035 PHY */ + rgmii_phy: ethernet-phy@4 { + reg = <4>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <1000>; + }; + }; }; &gpio1 { diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index 80ed5f16a76e..2b9423d55c37 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -562,6 +562,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh1>; vbus-supply = <®_usb_h1_vbus>; + over-current-active-low; status = "disabled"; }; @@ -569,6 +570,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; vbus-supply = <®_usb_otg_vbus>; + over-current-active-low; srp-disable; hnp-disable; adp-disable; diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 008312ee0c31..77b65a402e19 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -44,6 +44,8 @@ arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; }; cpu@1 { @@ -85,8 +87,8 @@ clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips1: aips-bus@2000000 { - iomuxc: iomuxc@20e0000 { + aips1: bus@2000000 { + iomuxc: pinctrl@20e0000 { compatible = "fsl,imx6dl-iomuxc"; }; @@ -101,7 +103,7 @@ }; }; - aips2: aips-bus@2100000 { + aips2: bus@2100000 { i2c4: i2c@21f8000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts index 4665e15b196d..fab83abb6466 100644 --- a/arch/arm/boot/dts/imx6q-apalis-eval.dts +++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2014-2017 Toradex AG + * Copyright 2014-2020 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts index a3fa04a97d81..1614b1ae501d 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2014-2017 Toradex AG + * Copyright 2014-2020 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts index 5ba49d0f4880..fa9f98dd15ac 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2014-2017 Toradex AG + * Copyright 2014-2020 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts index bb74fc62d913..a2dd7e549568 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts +++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts @@ -22,6 +22,53 @@ clock-frequency = <24000000>; }; + display_bl: display-bl { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel { + compatible = "edt,etm0700g0edh6"; + ddc-i2c-bus = <&i2c2>; + backlight = <&display_bl>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + sound { compatible = "fsl,imx-audio-sgtl5000"; model = "imx-sgtl5000"; @@ -65,6 +112,15 @@ VDDA-supply = <®_3p3v>; VDDIO-supply = <&sw2_reg>; }; + + touchscreen@38 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ + }; }; &iomuxc { @@ -77,9 +133,7 @@ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0 MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x120b0 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0 - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x120b0 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0 @@ -132,6 +186,52 @@ >; }; + pinctrl_ipu1_lcdif: ipu1-lcdif-grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0 + >; + }; + + pinctrl_pwm1: pwm1-grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_touchscreen: touchscreen-grp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1 + >; + }; + pinctrl_pcie: pcie-grp { fsl,pins = < MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 @@ -139,6 +239,10 @@ }; }; +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; @@ -146,6 +250,13 @@ status = "okay"; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + #pwm-cells = <3>; + status = "okay"; +}; + &ssi1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts index 84b30bd6908f..05ee28388229 100644 --- a/arch/arm/boot/dts/imx6q-marsboard.dts +++ b/arch/arm/boot/dts/imx6q-marsboard.dts @@ -111,8 +111,22 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + phy-handle = <&rgmii_phy>; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Atheros AR8035 PHY */ + rgmii_phy: ethernet-phy@4 { + reg = <4>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <1000>; + }; + }; }; &hdmi { diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts index 61347a545d6c..69f170ff31c5 100644 --- a/arch/arm/boot/dts/imx6q-novena.dts +++ b/arch/arm/boot/dts/imx6q-novena.dts @@ -107,7 +107,7 @@ }; panel: panel { - compatible = "innolux,n133hse-ea1", "simple-panel"; + compatible = "innolux,n133hse-ea1"; backlight = <&backlight>; }; diff --git a/arch/arm/boot/dts/imx6q-pico-dwarf.dts b/arch/arm/boot/dts/imx6q-pico-dwarf.dts new file mode 100644 index 000000000000..618d2743e1e9 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-pico-dwarf.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng <wig.cheng@technexion.com> +// Richard Hu <richard.hu@technexion.com> +// Tapani Utriainen <tapani@technexion.com> + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-pico-pi.dtsi" + +/ { + model = "TechNexion PICO-IMX6 Quad Board and Dwarf baseboard"; + compatible = "technexion,imx6q-pico", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-pico-hobbit.dts b/arch/arm/boot/dts/imx6q-pico-hobbit.dts new file mode 100644 index 000000000000..7a666507b456 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-pico-hobbit.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng <wig.cheng@technexion.com> +// Richard Hu <richard.hu@technexion.com> +// Tapani Utriainen <tapani@technexion.com> + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-pico-hobbit.dtsi" + +/ { + model = "TechNexion PICO-IMX6 Quad Board and Hobbit baseboard"; + compatible = "technexion,imx6q-pico", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-pico-nymph.dts b/arch/arm/boot/dts/imx6q-pico-nymph.dts new file mode 100644 index 000000000000..fe5a7becc9e5 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-pico-nymph.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng <wig.cheng@technexion.com> +// Richard Hu <richard.hu@technexion.com> +// Tapani Utriainen <tapani@technexion.com> + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-pico-pi.dtsi" + +/ { + model = "TechNexion PICO-IMX6 Quad Board and Nymph baseboard"; + compatible = "technexion,imx6q-pico", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q-pico-pi.dts b/arch/arm/boot/dts/imx6q-pico-pi.dts new file mode 100644 index 000000000000..9413f0a68f54 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-pico-pi.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng <wig.cheng@technexion.com> +// Richard Hu <richard.hu@technexion.com> +// Tapani Utriainen <tapani@technexion.com> + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-pico-pi.dtsi" + +/ { + model = "TechNexion PICO-IMX6 Quad Board and PI baseboard"; + compatible = "technexion,imx6q-pico", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 9d3be1cc6b64..78a4d64929f3 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -49,6 +49,8 @@ arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; }; cpu1: cpu@1 { @@ -164,7 +166,7 @@ clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips-bus@2000000 { /* AIPS1 */ + bus@2000000 { /* AIPS1 */ spba-bus@2000000 { ecspi5: spi@2018000 { #address-cells = <1>; @@ -181,7 +183,7 @@ }; }; - iomuxc: iomuxc@20e0000 { + iomuxc: pinctrl@20e0000 { compatible = "fsl,imx6q-iomuxc"; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 1b5bc6b5e806..e34be8fabd93 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2014-2017 Toradex AG + * Copyright 2014-2020 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/gpio/gpio.h> @@ -180,7 +144,7 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy>; phy-reset-duration = <10>; phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi b/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi new file mode 100644 index 000000000000..7672fbfc29be --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +&iomuxc { + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 + >; + }; +}; + +/* Colibri MMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; + vmmc-supply = <®_module_3v3>; + vqmmc-supply = <&vgen3_reg>; + wakeup-source; + keep-power-in-suspend; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index d03dff23863d..240b86d2eb71 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2014-2016 Toradex AG + * Copyright 2014-2020 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/gpio/gpio.h> @@ -229,7 +193,16 @@ regulator-always-on; }; - /* vgen3: unused */ + /* + * +V3.3_1.8_SD1 coming off VGEN3 and supplying + * the i.MX 6 NVCC_SD1. + */ + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; vgen4_reg: vgen4 { regulator-min-microvolt = <1800000>; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 1a9a9d98f284..60563ff0b7ce 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -313,6 +313,11 @@ interrupts = <12 2>; wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; }; + + accel@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + }; }; &ldb { diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 54b2beadd7a2..8942bec65c5c 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -304,6 +304,11 @@ interrupts = <11 2>; wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; + + accel@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + }; }; &ldb { diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 1b6c1331c220..c40583dbd96d 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -361,6 +361,11 @@ interrupts = <12 2>; wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; }; + + accel@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + }; }; &ldb { diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi index dc646b72b59a..bb3597132c62 100644 --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi @@ -258,6 +258,14 @@ status = "okay"; }; +&usbotg { + vbus-supply = <®_5p0v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; @@ -359,6 +367,12 @@ >; }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi index a1066897be18..ee85031c3916 100644 --- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi @@ -173,6 +173,25 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + magn@1c { + compatible = "st,lsm9ds1-magn"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + }; + + imu@6a { + compatible = "st,lsm9ds1-imu"; + reg = <0x6a>; + st,drdy-int-pin = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imu>; + interrupt-parent = <&gpio7>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + }; + ltc3676: pmic@3c { compatible = "lltc,ltc3676"; reg = <0x3c>; @@ -426,6 +445,12 @@ >; }; + pinctrl_imu: imugrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + >; + }; + pinctrl_ipu1_csi0: ipu1csi0grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 @@ -449,6 +474,12 @@ >; }; + pinctrl_mag: maggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi index e8e36dfd0a6b..69ca70d3baa8 100644 --- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi @@ -295,6 +295,15 @@ VDDIO-supply = <®_3p3v>; }; + magn@1c { + compatible = "st,lsm9ds1-magn"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; + }; + tca8418: keypad@34 { compatible = "ti,tca8418"; pinctrl-names = "default"; @@ -389,6 +398,16 @@ }; }; }; + + imu@6a { + compatible = "st,lsm9ds1-imu"; + reg = <0x6a>; + st,drdy-int-pin = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imu>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + }; }; &i2c3 { @@ -609,6 +628,12 @@ >; }; + pinctrl_imu: imugrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0 + >; + }; + pinctrl_keypad: keypadgrp { fsl,pins = < MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */ @@ -616,6 +641,12 @@ >; }; + pinctrl_mag: maggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */ diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi index 6d21cc6a9d4b..76d6cf57f1c3 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi @@ -248,6 +248,15 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + magn@1c { + compatible = "st,lsm9ds1-magn"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + }; + ltc3676: pmic@3c { compatible = "lltc,ltc3676"; reg = <0x3c>; @@ -320,6 +329,16 @@ }; }; }; + + imu@6a { + compatible = "st,lsm9ds1-imu"; + reg = <0x6a>; + st,drdy-int-pin = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imu>; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + }; }; &i2c3 { @@ -501,6 +520,18 @@ >; }; + pinctrl_imu: imugrp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 + >; + }; + + pinctrl_mag: maggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi index be1af7482f89..0857de505192 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi @@ -81,20 +81,6 @@ enable-active-high; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_bt: regulator-bt { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_bt>; - compatible = "regulator-fixed"; - regulator-name = "bt"; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100>; - enable-active-high; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; }; }; @@ -220,12 +206,25 @@ status = "okay"; }; +/* cc1352 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + /* Sterling-LWB Bluetooth */ &uart4 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; + pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>; uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; }; /* GPS */ @@ -251,7 +250,7 @@ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; + vmmc-supply = <®_wl>; non-removable; bus-width = <4>; status = "okay"; @@ -280,6 +279,12 @@ >; }; + pinctrl_bten: btengrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 + >; + }; + pinctrl_ecspi3: escpi3grp { fsl,pins = < MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 @@ -385,12 +390,6 @@ >; }; - pinctrl_reg_bt: regbtgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 - >; - }; - pinctrl_reg_wl: regwlgrp { fsl,pins = < MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 @@ -411,6 +410,23 @@ >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */ + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */ + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */ + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */ + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */ + >; + }; + pinctrl_uart4: uart4grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi index 978dc1c2ff1b..41ebe4599e43 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi @@ -88,7 +88,7 @@ reg = <0x50>; }; - pmic@58 { + pmic: pmic@58 { compatible = "dlg,da9062"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; @@ -96,6 +96,8 @@ interrupt-parent = <&gpio1>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; + gpio-controller; + #gpio-cells = <2>; da9062_rtc: rtc { compatible = "dlg,da9062-rtc"; @@ -107,12 +109,13 @@ watchdog { compatible = "dlg,da9062-watchdog"; + dlg,use-sw-pm; }; regulators { vdd_arm: buck1 { regulator-name = "vdd_arm"; - regulator-min-microvolt = <730000>; + regulator-min-microvolt = <925000>; regulator-max-microvolt = <1380000>; regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; regulator-always-on; @@ -120,7 +123,7 @@ vdd_soc: buck2 { regulator-name = "vdd_soc"; - regulator-min-microvolt = <730000>; + regulator-min-microvolt = <1150000>; regulator-max-microvolt = <1380000>; regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>; regulator-always-on; @@ -192,7 +195,6 @@ pinctrl-0 = <&pinctrl_usdhc4>; bus-width = <8>; non-removable; - vmmc-supply = <&vdd_emmc_1p8>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6qdl-pico-dwarf.dtsi b/arch/arm/boot/dts/imx6qdl-pico-dwarf.dtsi new file mode 100644 index 000000000000..3a968782e854 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-pico-dwarf.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2017 NXP + +#include "imx6qdl-pico.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; + }; + }; + +}; + +&i2c1 { + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&i2c2 { + io-expander@25 { + compatible = "nxp,pca9554"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + +}; + +&iomuxc { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-pico-hobbit.dtsi b/arch/arm/boot/dts/imx6qdl-pico-hobbit.dtsi new file mode 100644 index 000000000000..144c4727fbc7 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-pico-hobbit.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2017 NXP + +#include "imx6qdl-pico.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; + }; + }; + +}; + +&i2c2 { + status = "okay"; + + adc081c: adc@50 { + compatible = "ti,adc081c"; + reg = <0x50>; + vref-supply = <®_3p3v>; + }; +}; + +&iomuxc { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-pico-nymph.dtsi b/arch/arm/boot/dts/imx6qdl-pico-nymph.dtsi new file mode 100644 index 000000000000..3d56a4216448 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-pico-nymph.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT + +#include "imx6qdl-pico.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; + }; + }; + +}; + +&i2c1 { + adc@52 { + compatible = "ti,adc081c"; + reg = <0x52>; + vref-supply = <®_2p5v>; + }; +}; + +&i2c2 { + io-expander@25 { + compatible = "nxp,pca9554"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; +}; + +&i2c3 { + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; +}; + +&pcie { + status = "okay"; +}; + +&iomuxc { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-pico-pi.dtsi b/arch/arm/boot/dts/imx6qdl-pico-pi.dtsi new file mode 100644 index 000000000000..b823dce62e63 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-pico-pi.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright 2017 NXP + +#include "imx6qdl-pico.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + }; + }; + +}; + +&hdmi { + status = "disabled"; +}; + +&iomuxc { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-pico.dtsi b/arch/arm/boot/dts/imx6qdl-pico.dtsi new file mode 100644 index 000000000000..39dfd90c2c6b --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-pico.dtsi @@ -0,0 +1,617 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright 2018 Technexion Ltd. +// +// Author: Wig Cheng <wig.cheng@technexion.com> +// Richard Hu <richard.hu@technexion.com> +// Tapani Utriainen <tapani@technexion.com> + +#include <dt-bindings/gpio/gpio.h> + +/ { + chosen { + stdout-path = &uart1; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_1p5v: regulator-1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + reg_2p8v: regulator-2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; + }; + + codec_osc: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6-pico-sgtl5000"; + ssi-controller = <&ssi1>; + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <3>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 50000 0>; + brightness-levels = <0 36 72 108 144 180 216 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + reg_lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcd>; + regulator-name = "lcd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel { + compatible = "vxt,vl050-8048nt-c01"; + backlight = <&backlight>; + power-supply = <®_lcd_3v3>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: audio-codec@a { + #sound-dai-cells = <0>; + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&codec_osc>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_1p8v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio5>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + wakeup-source; + }; + + camera@3c { + compatible = "ovti,ov5645"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5645>; + reg = <0x3c>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "xclk"; + clock-frequency = <24000000>; + vdddo-supply = <®_1p8v>; + vdda-supply = <®_2p8v>; + vddd-supply = <®_1p5v>; + enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + + port { + ov5645_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&mipi_csi { + status = "okay"; + + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5645_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reset>; + reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { /* Bluetooth module */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { /* Wifi/BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + no-1-8-v; + keep-power-in-suspend; + non-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x4001b0b5 /* PICO_P24 */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x4001b0b5 /* PICO_P26 */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b5 /* PICO_P28 */ + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b0b5 /* PICO_P30 */ + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b0b5 /* PICO_P32 */ + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x4001b0b5 /* PICO_P34 */ + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x4001b0b5 /* PICO_P42 */ + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x4001b0b5 /* PICO_P44 */ + MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x4001b0b5 /* PICO_P48 */ + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000f0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1b0b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x1b0b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x1b0b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000f0b0 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x000f0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1f0b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ov5645: ov5645grp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x0b0b0 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 + MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 + >; + }; + + pinctrl_pcie_reset: pciegrp { + fsl,pins = < + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x130b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_lcd: reglcdgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usbotg_vbus: usbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x17071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi index 44a97ba93a95..352ac585ca6b 100644 --- a/arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sr-som-ti.dtsi @@ -153,6 +153,7 @@ bus-width = <4>; keep-power-in-suspend; mmc-pwrseq = <&pwrseq_ti_wifi>; + cap-power-off-card; non-removable; vmmc-supply = <&vcc_3v3>; /* vqmmc-supply = <&nvcc_sd1>; - MMC layer doesn't like it! */ diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi index 6d7f6b9035bc..b06577808ff4 100644 --- a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi @@ -53,10 +53,21 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; + phy-handle = <&phy>; phy-mode = "rgmii-id"; phy-reset-duration = <2>; phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@0 { + reg = <0>; + qca,clk-out-frequency = <125000000>; + }; + }; }; &iomuxc { diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 0075637f9b0b..20350e803377 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -216,6 +216,13 @@ }; }; +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +}; + &cpu0 { fsl,soc-operating-points = < /* ARM kHz SOC-PU uV */ diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index e6b4b8525f98..39d4afd9e6f8 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -74,7 +74,8 @@ interrupt-parent = <&gpc>; interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; #thermal-sensor-cells = <0>; }; @@ -294,7 +295,7 @@ status = "disabled"; }; - aips-bus@2000000 { /* AIPS1 */ + bus@2000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -574,7 +575,7 @@ status = "disabled"; }; - gpt: gpt@2098000 { + gpt: timer@2098000 { compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; reg = <0x02098000 0x4000>; interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; @@ -661,7 +662,7 @@ #interrupt-cells = <2>; }; - kpp: kpp@20b8000 { + kpp: keypad@20b8000 { compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; @@ -669,14 +670,14 @@ status = "disabled"; }; - wdog1: wdog@20bc000 { + wdog1: watchdog@20bc000 { compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_IPG>; }; - wdog2: wdog@20c0000 { + wdog2: watchdog@20c0000 { compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; @@ -684,7 +685,7 @@ status = "disabled"; }; - clks: ccm@20c4000 { + clks: clock-controller@20c4000 { compatible = "fsl,imx6q-ccm"; reg = <0x020c4000 0x4000>; interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, @@ -857,7 +858,7 @@ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@20d8000 { + src: reset-controller@20d8000 { compatible = "fsl,imx6q-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, @@ -908,7 +909,7 @@ }; }; - iomuxc: iomuxc@20e0000 { + iomuxc: pinctrl@20e0000 { compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; reg = <0x20e0000 0x4000>; }; @@ -935,14 +936,14 @@ }; }; - aips-bus@2100000 { /* AIPS2 */ + bus@2100000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02100000 0x100000>; ranges; - crypto: caam@2100000 { + crypto: crypto@2100000 { compatible = "fsl,sec-v4.0"; #address-cells = <1>; #size-cells = <1>; @@ -954,13 +955,13 @@ <&clks IMX6QDL_CLK_EIM_SLOW>; clock-names = "mem", "aclk", "ipg", "emi_slow"; - sec_jr0: jr0@1000 { + sec_jr0: jr@1000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; }; - sec_jr1: jr1@2000 { + sec_jr1: jr@2000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x2000 0x1000>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; @@ -1039,13 +1040,13 @@ compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; interrupt-names = "int0", "pps"; - interrupts-extended = - <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, + <0 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET_REF>; clock-names = "ipg", "ahb", "ptp"; + gpr = <&gpr>; status = "disabled"; }; @@ -1161,10 +1162,24 @@ status = "disabled"; }; - ocotp: ocotp@21bc000 { + ocotp: ocotp-ctrl@21bc000 { compatible = "fsl,imx6q-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6QDL_CLK_IIM>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; tzasc@21d0000 { /* TZASC1 */ diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi index 5f51f8e5c1fa..b310f13a53f2 100644 --- a/arch/arm/boot/dts/imx6qp.dtsi +++ b/arch/arm/boot/dts/imx6qp.dtsi @@ -18,7 +18,7 @@ clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips-bus@2100000 { + bus@2100000 { pre1: pre@21c8000 { compatible = "fsl,imx6qp-pre"; reg = <0x021c8000 0x1000>; @@ -77,7 +77,6 @@ }; &fec { - /delete-property/interrupts-extended; interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, <0 119 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 59c54e6ad09a..911d8cf77f2c 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -74,6 +74,8 @@ arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; }; }; @@ -96,7 +98,8 @@ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gpc>; fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; }; @@ -143,7 +146,7 @@ arm,data-latency = <4 2 3>; }; - aips1: aips-bus@2000000 { + aips1: bus@2000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -380,7 +383,7 @@ clock-names = "ipg", "per"; }; - gpt: gpt@2098000 { + gpt: timer@2098000 { compatible = "fsl,imx6sl-gpt"; reg = <0x02098000 0x4000>; interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; @@ -491,7 +494,7 @@ <&iomuxc 21 161 1>; }; - kpp: kpp@20b8000 { + kpp: keypad@20b8000 { compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; @@ -499,14 +502,14 @@ status = "disabled"; }; - wdog1: wdog@20bc000 { + wdog1: watchdog@20bc000 { compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_IPG>; }; - wdog2: wdog@20c0000 { + wdog2: watchdog@20c0000 { compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; @@ -514,7 +517,7 @@ status = "disabled"; }; - clks: ccm@20c4000 { + clks: clock-controller@20c4000 { compatible = "fsl,imx6sl-ccm"; reg = <0x020c4000 0x4000>; interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, @@ -675,7 +678,7 @@ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@20d8000 { + src: reset-controller@20d8000 { compatible = "fsl,imx6sl-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, @@ -728,7 +731,7 @@ reg = <0x020e0000 0x38>; }; - iomuxc: iomuxc@20e0000 { + iomuxc: pinctrl@20e0000 { compatible = "fsl,imx6sl-iomuxc"; reg = <0x020e0000 0x4000>; }; @@ -777,7 +780,7 @@ power-domains = <&pd_disp>; }; - dcp: dcp@20fc000 { + dcp: crypto@20fc000 { compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp"; reg = <0x020fc000 0x4000>; interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, @@ -786,7 +789,7 @@ }; }; - aips2: aips-bus@2100000 { + aips2: bus@2100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -949,10 +952,24 @@ status = "disabled"; }; - ocotp: ocotp@21bc000 { + ocotp: ocotp-ctrl@21bc000 { compatible = "fsl,imx6sl-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6SL_CLK_OCOTP>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; audmux: audmux@21d8000 { diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index a1bc5bb31756..edd3abb9a9f1 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -72,6 +72,8 @@ <&clks IMX6SLL_CLK_PLL1_SYS>; clock-names = "arm", "pll2_pfd2_396m", "step", "pll1_sw", "pll1_sys"; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; }; }; @@ -144,7 +146,7 @@ arm,data-latency = <4 2 3>; }; - aips1: aips-bus@2000000 { + aips1: bus@2000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -652,7 +654,7 @@ status = "disabled"; }; - dcp: dcp@20fc000 { + dcp: crypto@20fc000 { compatible = "fsl,imx28-dcp"; reg = <0x020fc000 0x4000>; interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, @@ -663,7 +665,7 @@ }; }; - aips2: aips-bus@2100000 { + aips2: bus@2100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -791,6 +793,10 @@ reg = <0x021bc000 0x4000>; clocks = <&clks IMX6SLL_CLK_OCOTP>; + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; + tempmon_calib: calib@38 { reg = <0x38 4>; }; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index 832b5c5d7441..d84ea6999377 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -484,31 +484,31 @@ pinctrl_uart1: uart1grp { fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 >; }; pinctrl_uart3: uart3grp { fsl,pins = < - MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x1b0b1 - MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x1b0b1 + MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x1b0b1 + MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x1b0b1 >; }; pinctrl_uart5: uart5grp { fsl,pins = < - MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 - MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 - MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x1b0b1 - MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 + MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x1b0b1 + MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x1b0b1 >; }; diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-pinfunc.h index aa194a2fdd53..0b02c7e60c17 100644 --- a/arch/arm/boot/dts/imx6sx-pinfunc.h +++ b/arch/arm/boot/dts/imx6sx-pinfunc.h @@ -42,8 +42,8 @@ #define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020 0x0368 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP 0x0020 0x0368 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO03__PHY_TCK 0x0020 0x0368 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO04__UART1_RX 0x0024 0x036C 0x0830 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO04__UART1_TX 0x0024 0x036C 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x0024 0x036C 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO04__UART1_DTE_RX 0x0024 0x036C 0x0830 0x0 0x0 #define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B 0x0024 0x036C 0x0000 0x1 0x0 #define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0 #define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT 0x0024 0x036C 0x0000 0x3 0x0 @@ -51,8 +51,8 @@ #define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024 0x036C 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP 0x0024 0x036C 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO04__PHY_TMS 0x0024 0x036C 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO05__UART1_RX 0x0028 0x0370 0x0830 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO05__UART1_TX 0x0028 0x0370 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x0028 0x0370 0x0830 0x0 0x1 +#define MX6SX_PAD_GPIO1_IO05__UART1_DTE_TX 0x0028 0x0370 0x0000 0x0 0x0 #define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT 0x0028 0x0370 0x0000 0x1 0x0 #define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0 #define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK 0x0028 0x0370 0x0000 0x3 0x0 @@ -60,21 +60,23 @@ #define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028 0x0370 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK 0x0028 0x0370 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO05__PHY_TDO 0x0028 0x0370 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART2_RX 0x002C 0x0374 0x0838 0x0 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART2_TX 0x002C 0x0374 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x002C 0x0374 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO06__UART2_DTE_RX 0x002C 0x0374 0x0838 0x0 0x0 #define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B 0x002C 0x0374 0x086C 0x1 0x1 #define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0 #define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C 0x0374 0x082C 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO06__UART1_DCE_RTS 0x002C 0x0374 0x082C 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO06__UART1_DTE_CTS 0x002C 0x0374 0x0000 0x4 0x0 #define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0 -#define MX6SX_PAD_GPIO1_IO07__UART2_RX 0x0030 0x0378 0x0838 0x0 0x1 -#define MX6SX_PAD_GPIO1_IO07__UART2_TX 0x0030 0x0378 0x0000 0x0 0x0 +#define MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x0030 0x0378 0x0838 0x0 0x1 +#define MX6SX_PAD_GPIO1_IO07__UART2_DTE_TX 0x0030 0x0378 0x0000 0x0 0x0 #define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1 #define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0 #define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO07__UART1_DCE_CTS 0x0030 0x0378 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO07__UART1_DTE_RTS 0x0030 0x0378 0x082C 0x4 0x1 #define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0 @@ -83,7 +85,8 @@ #define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0034 0x037C 0x0000 0x1 0x0 #define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0 #define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1 -#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034 0x037C 0x0834 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO08__UART2_DCE_RTS 0x0034 0x037C 0x0834 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO08__UART2_DTE_CTS 0x0034 0x037C 0x0000 0x4 0x0 #define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0 @@ -92,7 +95,8 @@ #define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0 #define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0 #define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0 -#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO09__UART2_DCE_CTS 0x0038 0x0380 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO09__UART2_DTE_RTS 0x0038 0x0380 0x0834 0x4 0x1 #define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0 @@ -177,8 +181,8 @@ #define MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x005C 0x03A4 0x0794 0x1 0x1 #define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C 0x03A4 0x0000 0x2 0x0 #define MX6SX_PAD_CSI_DATA04__KPP_COL_6 0x005C 0x03A4 0x07CC 0x3 0x0 -#define MX6SX_PAD_CSI_DATA04__UART6_RX 0x005C 0x03A4 0x0858 0x4 0x0 -#define MX6SX_PAD_CSI_DATA04__UART6_TX 0x005C 0x03A4 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA04__UART6_DCE_RX 0x005C 0x03A4 0x0858 0x4 0x0 +#define MX6SX_PAD_CSI_DATA04__UART6_DTE_TX 0x005C 0x03A4 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x005C 0x03A4 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19 0x005C 0x03A4 0x0000 0x6 0x0 #define MX6SX_PAD_CSI_DATA04__PWM5_OUT 0x005C 0x03A4 0x0000 0x7 0x0 @@ -188,8 +192,8 @@ #define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x0060 0x03A8 0x07A0 0x1 0x1 #define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060 0x03A8 0x0824 0x2 0x1 #define MX6SX_PAD_CSI_DATA05__KPP_ROW_6 0x0060 0x03A8 0x07D8 0x3 0x0 -#define MX6SX_PAD_CSI_DATA05__UART6_RX 0x0060 0x03A8 0x0858 0x4 0x1 -#define MX6SX_PAD_CSI_DATA05__UART6_TX 0x0060 0x03A8 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA05__UART6_DCE_TX 0x0060 0x03A8 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA05__UART6_DTE_RX 0x0060 0x03A8 0x0858 0x4 0x1 #define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x0060 0x03A8 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18 0x0060 0x03A8 0x0000 0x6 0x0 #define MX6SX_PAD_CSI_DATA05__PWM6_OUT 0x0060 0x03A8 0x0000 0x7 0x0 @@ -199,7 +203,8 @@ #define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x0064 0x03AC 0x0798 0x1 0x1 #define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2 #define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0 -#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064 0x03AC 0x0854 0x4 0x0 +#define MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS 0x0064 0x03AC 0x0854 0x4 0x0 +#define MX6SX_PAD_CSI_DATA06__UART6_DTE_CTS 0x0064 0x03AC 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0 #define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0 @@ -209,7 +214,8 @@ #define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1 #define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2 #define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0 -#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS 0x0068 0x03B0 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA07__UART6_DTE_RTS 0x0068 0x03B0 0x0854 0x4 0x1 #define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0 #define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0 @@ -218,7 +224,8 @@ #define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x006C 0x03B4 0x0700 0x0 0x0 #define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1 #define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1 -#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2 +#define MX6SX_PAD_CSI_HSYNC__UART4_DCE_RTS 0x006C 0x03B4 0x0844 0x3 0x2 +#define MX6SX_PAD_CSI_HSYNC__UART4_DTE_CTS 0x006C 0x03B4 0x0000 0x3 0x0 #define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0 @@ -228,8 +235,8 @@ #define MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x0070 0x03B8 0x0000 0x0 0x0 #define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x0070 0x03B8 0x0784 0x1 0x1 #define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070 0x03B8 0x0000 0x2 0x0 -#define MX6SX_PAD_CSI_MCLK__UART4_RX 0x0070 0x03B8 0x0848 0x3 0x2 -#define MX6SX_PAD_CSI_MCLK__UART4_TX 0x0070 0x03B8 0x0000 0x3 0x0 +#define MX6SX_PAD_CSI_MCLK__UART4_DCE_RX 0x0070 0x03B8 0x0848 0x3 0x2 +#define MX6SX_PAD_CSI_MCLK__UART4_DTE_TX 0x0070 0x03B8 0x0000 0x3 0x0 #define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT 0x0070 0x03B8 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23 0x0070 0x03B8 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26 0x0070 0x03B8 0x0000 0x6 0x0 @@ -239,8 +246,8 @@ #define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x0074 0x03BC 0x0704 0x0 0x0 #define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK 0x0074 0x03BC 0x0780 0x1 0x1 #define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074 0x03BC 0x0000 0x2 0x0 -#define MX6SX_PAD_CSI_PIXCLK__UART4_RX 0x0074 0x03BC 0x0848 0x3 0x3 -#define MX6SX_PAD_CSI_PIXCLK__UART4_TX 0x0074 0x03BC 0x0000 0x3 0x0 +#define MX6SX_PAD_CSI_PIXCLK__UART4_DCE_TX 0x0074 0x03BC 0x0000 0x3 0x0 +#define MX6SX_PAD_CSI_PIXCLK__UART4_DTE_RX 0x0074 0x03BC 0x0848 0x3 0x3 #define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT 0x0074 0x03BC 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x0074 0x03BC 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27 0x0074 0x03BC 0x0000 0x6 0x0 @@ -250,7 +257,8 @@ #define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0 #define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1 #define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1 -#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0 +#define MX6SX_PAD_CSI_VSYNC__UART4_DCE_CTS 0x0078 0x03C0 0x0000 0x3 0x0 +#define MX6SX_PAD_CSI_VSYNC__UART4_DTE_RTS 0x0078 0x03C0 0x0844 0x3 0x3 #define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0 @@ -330,8 +338,8 @@ #define MX6SX_PAD_ENET2_COL__ENET2_COL 0x0094 0x03DC 0x0000 0x0 0x0 #define MX6SX_PAD_ENET2_COL__ENET1_MDC 0x0094 0x03DC 0x0000 0x1 0x0 #define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094 0x03DC 0x064C 0x2 0x1 -#define MX6SX_PAD_ENET2_COL__UART1_RX 0x0094 0x03DC 0x0830 0x3 0x2 -#define MX6SX_PAD_ENET2_COL__UART1_TX 0x0094 0x03DC 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET2_COL__UART1_DCE_RX 0x0094 0x03DC 0x0830 0x3 0x2 +#define MX6SX_PAD_ENET2_COL__UART1_DTE_TX 0x0094 0x03DC 0x0000 0x3 0x0 #define MX6SX_PAD_ENET2_COL__SPDIF_IN 0x0094 0x03DC 0x0824 0x4 0x3 #define MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x0094 0x03DC 0x0000 0x5 0x0 #define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x0094 0x03DC 0x0624 0x6 0x1 @@ -341,8 +349,8 @@ #define MX6SX_PAD_ENET2_CRS__ENET2_CRS 0x0098 0x03E0 0x0000 0x0 0x0 #define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098 0x03E0 0x0764 0x1 0x2 #define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098 0x03E0 0x0650 0x2 0x1 -#define MX6SX_PAD_ENET2_CRS__UART1_RX 0x0098 0x03E0 0x0830 0x3 0x3 -#define MX6SX_PAD_ENET2_CRS__UART1_TX 0x0098 0x03E0 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET2_CRS__UART1_DCE_TX 0x0098 0x03E0 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET2_CRS__UART1_DTE_RX 0x0098 0x03E0 0x0830 0x3 0x3 #define MX6SX_PAD_ENET2_CRS__MLB_SIG 0x0098 0x03E0 0x07F0 0x4 0x1 #define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x0098 0x03E0 0x0000 0x5 0x0 #define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x0098 0x03E0 0x0628 0x6 0x1 @@ -352,7 +360,8 @@ #define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK 0x009C 0x03E4 0x0774 0x0 0x0 #define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0 #define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1 -#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2 +#define MX6SX_PAD_ENET2_RX_CLK__UART1_DCE_RTS 0x009C 0x03E4 0x082C 0x3 0x2 +#define MX6SX_PAD_ENET2_RX_CLK__UART1_DTE_CTS 0x009C 0x03E4 0x0000 0x3 0x0 #define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1 #define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0 #define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1 @@ -362,7 +371,8 @@ #define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0 #define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1 #define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1 -#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__UART1_DCE_CTS 0x00A0 0x03E8 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__UART1_DTE_RTS 0x00A0 0x03E8 0x082C 0x3 0x3 #define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1 #define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0 #define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0 @@ -371,7 +381,8 @@ #define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 0x00A0 0x03E8 0x0000 0x9 0x0 #define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2 +#define MX6SX_PAD_KEY_COL0__UART6_DCE_RTS 0x00A4 0x03EC 0x0854 0x2 0x2 +#define MX6SX_PAD_KEY_COL0__UART6_DTE_CTS 0x00A4 0x03EC 0x0000 0x2 0x0 #define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0 #define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0 #define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0 @@ -380,8 +391,8 @@ #define MX6SX_PAD_KEY_COL0__VADC_DATA_0 0x00A4 0x03EC 0x0000 0x8 0x0 #define MX6SX_PAD_KEY_COL1__KPP_COL_1 0x00A8 0x03F0 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B 0x00A8 0x03F0 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL1__UART6_RX 0x00A8 0x03F0 0x0858 0x2 0x2 -#define MX6SX_PAD_KEY_COL1__UART6_TX 0x00A8 0x03F0 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_COL1__UART6_DCE_TX 0x00A8 0x03F0 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_COL1__UART6_DTE_RX 0x00A8 0x03F0 0x0858 0x2 0x2 #define MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x00A8 0x03F0 0x0714 0x3 0x0 #define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x00A8 0x03F0 0x0670 0x4 0x0 #define MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x00A8 0x03F0 0x0000 0x5 0x0 @@ -389,7 +400,8 @@ #define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x00A8 0x03F0 0x0818 0x7 0x0 #define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1 -#define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2 +#define MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x00AC 0x03F4 0x084C 0x2 0x2 +#define MX6SX_PAD_KEY_COL2__UART5_DTE_CTS 0x00AC 0x03F4 0x0000 0x2 0x0 #define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0 #define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0 #define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0 @@ -397,8 +409,8 @@ #define MX6SX_PAD_KEY_COL2__ECSPI1_RDY 0x00AC 0x03F4 0x0000 0x7 0x0 #define MX6SX_PAD_KEY_COL3__KPP_COL_3 0x00B0 0x03F8 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_COL3__USDHC4_LCTL 0x00B0 0x03F8 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_COL3__UART5_RX 0x00B0 0x03F8 0x0850 0x2 0x2 -#define MX6SX_PAD_KEY_COL3__UART5_TX 0x00B0 0x03F8 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x00B0 0x03F8 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_COL3__UART5_DTE_RX 0x00B0 0x03F8 0x0850 0x2 0x2 #define MX6SX_PAD_KEY_COL3__CAN2_TX 0x00B0 0x03F8 0x0000 0x3 0x0 #define MX6SX_PAD_KEY_COL3__CANFD_TX2 0x00B0 0x03F8 0x0000 0x4 0x0 #define MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x00B0 0x03F8 0x0000 0x5 0x0 @@ -414,7 +426,8 @@ #define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0 #define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW0__UART6_DCE_CTS 0x00B8 0x0400 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW0__UART6_DTE_RTS 0x00B8 0x0400 0x0854 0x2 0x3 #define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0 #define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0 #define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0 @@ -423,8 +436,8 @@ #define MX6SX_PAD_KEY_ROW0__GPU_IDLE 0x00B8 0x0400 0x0000 0x8 0x0 #define MX6SX_PAD_KEY_ROW1__KPP_ROW_1 0x00BC 0x0404 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT 0x00BC 0x0404 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_ROW1__UART6_RX 0x00BC 0x0404 0x0858 0x2 0x3 -#define MX6SX_PAD_KEY_ROW1__UART6_TX 0x00BC 0x0404 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW1__UART6_DCE_RX 0x00BC 0x0404 0x0858 0x2 0x3 +#define MX6SX_PAD_KEY_ROW1__UART6_DTE_TX 0x00BC 0x0404 0x0000 0x2 0x0 #define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0 0x00BC 0x0404 0x071C 0x3 0x0 #define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x00BC 0x0404 0x065C 0x4 0x0 #define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x00BC 0x0404 0x0000 0x5 0x0 @@ -433,7 +446,8 @@ #define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0 #define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1 -#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x00C0 0x0408 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW2__UART5_DTE_RTS 0x00C0 0x0408 0x084C 0x2 0x3 #define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1 #define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1 #define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0 @@ -441,8 +455,8 @@ #define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3 0x00C0 0x0408 0x0000 0x7 0x0 #define MX6SX_PAD_KEY_ROW3__KPP_ROW_3 0x00C4 0x040C 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL 0x00C4 0x040C 0x0000 0x1 0x0 -#define MX6SX_PAD_KEY_ROW3__UART5_RX 0x00C4 0x040C 0x0850 0x2 0x3 -#define MX6SX_PAD_KEY_ROW3__UART5_TX 0x00C4 0x040C 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x00C4 0x040C 0x0850 0x2 0x3 +#define MX6SX_PAD_KEY_ROW3__UART5_DTE_TX 0x00C4 0x040C 0x0000 0x2 0x0 #define MX6SX_PAD_KEY_ROW3__CAN2_RX 0x00C4 0x040C 0x0690 0x3 0x1 #define MX6SX_PAD_KEY_ROW3__CANFD_RX2 0x00C4 0x040C 0x0698 0x4 0x1 #define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x00C4 0x040C 0x0000 0x5 0x0 @@ -815,7 +829,8 @@ #define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0x0160 0x04A8 0x0000 0x0 0x0 #define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0 #define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160 0x04A8 0x083C 0x3 0x0 +#define MX6SX_PAD_NAND_DATA04__UART3_DCE_RTS 0x0160 0x04A8 0x083C 0x3 0x0 +#define MX6SX_PAD_NAND_DATA04__UART3_DTE_CTS 0x0160 0x04A8 0x0000 0x3 0x0 #define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0 #define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0 #define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0 @@ -825,7 +840,8 @@ #define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0 #define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0 #define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0 +#define MX6SX_PAD_NAND_DATA05__UART3_DCE_CTS 0x0164 0x04AC 0x0000 0x3 0x0 +#define MX6SX_PAD_NAND_DATA05__UART3_DTE_RTS 0x0164 0x04AC 0x083C 0x3 0x1 #define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0 #define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0 #define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0 @@ -835,8 +851,8 @@ #define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0x0168 0x04B0 0x0000 0x0 0x0 #define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6 0x0168 0x04B0 0x0000 0x1 0x0 #define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168 0x04B0 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA06__UART3_RX 0x0168 0x04B0 0x0840 0x3 0x0 -#define MX6SX_PAD_NAND_DATA06__UART3_TX 0x0168 0x04B0 0x0000 0x3 0x0 +#define MX6SX_PAD_NAND_DATA06__UART3_DCE_RX 0x0168 0x04B0 0x0840 0x3 0x0 +#define MX6SX_PAD_NAND_DATA06__UART3_DTE_TX 0x0168 0x04B0 0x0000 0x3 0x0 #define MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x0168 0x04B0 0x0000 0x4 0x0 #define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x0168 0x04B0 0x0000 0x5 0x0 #define MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0168 0x04B0 0x0000 0x6 0x0 @@ -846,8 +862,8 @@ #define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0x016C 0x04B4 0x0000 0x0 0x0 #define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7 0x016C 0x04B4 0x0000 0x1 0x0 #define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C 0x04B4 0x0000 0x2 0x0 -#define MX6SX_PAD_NAND_DATA07__UART3_RX 0x016C 0x04B4 0x0840 0x3 0x1 -#define MX6SX_PAD_NAND_DATA07__UART3_TX 0x016C 0x04B4 0x0000 0x3 0x0 +#define MX6SX_PAD_NAND_DATA07__UART3_DCE_TX 0x016C 0x04B4 0x0000 0x3 0x0 +#define MX6SX_PAD_NAND_DATA07__UART3_DTE_RX 0x016C 0x04B4 0x0840 0x3 0x1 #define MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x016C 0x04B4 0x0000 0x4 0x0 #define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x016C 0x04B4 0x0000 0x5 0x0 #define MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x016C 0x04B4 0x0000 0x6 0x0 @@ -967,7 +983,8 @@ #define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0 #define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0 #define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1B_DATA0__UART3_DCE_CTS 0x01A0 0x04E8 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1B_DATA0__UART3_DTE_RTS 0x01A0 0x04E8 0x083C 0x1 0x4 #define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1 #define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2 #define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1 @@ -975,7 +992,8 @@ #define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x01A0 0x04E8 0x0000 0x6 0x0 #define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0 #define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4 0x04EC 0x083C 0x1 0x5 +#define MX6SX_PAD_QSPI1B_DATA1__UART3_DCE_RTS 0x01A4 0x04EC 0x083C 0x1 0x5 +#define MX6SX_PAD_QSPI1B_DATA1__UART3_DTE_CTS 0x01A4 0x04EC 0x0000 0x1 0x0 #define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1 #define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2 #define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1 @@ -1007,8 +1025,8 @@ #define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x01B0 0x04F8 0x0000 0x6 0x0 #define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0 #define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x01B4 0x04FC 0x0840 0x1 0x4 -#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX 0x01B4 0x04FC 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x01B4 0x04FC 0x0840 0x1 0x4 +#define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x0 0x0 #define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1 #define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2 #define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1 @@ -1016,8 +1034,8 @@ #define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x01B4 0x04FC 0x0000 0x6 0x0 #define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 0x01B4 0x04FC 0x0000 0x7 0x0 #define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x01B8 0x0500 0x0000 0x0 0x0 -#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX 0x01B8 0x0500 0x0840 0x1 0x5 -#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x01B8 0x0500 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x01B8 0x0500 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1B_SS0_B__UART3_DTE_RX 0x01B8 0x0500 0x0840 0x1 0x5 #define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8 0x0500 0x073C 0x2 0x1 #define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK 0x01B8 0x0500 0x0784 0x3 0x3 #define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17 0x01B8 0x0500 0x06E0 0x4 0x1 @@ -1224,8 +1242,8 @@ #define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x0228 0x0570 0x065C 0x1 0x1 #define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228 0x0570 0x0000 0x2 0x0 #define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1 0x0228 0x0570 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA0__UART2_RX 0x0228 0x0570 0x0838 0x4 0x2 -#define MX6SX_PAD_SD1_DATA0__UART2_TX 0x0228 0x0570 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_DATA0__UART2_DCE_RX 0x0228 0x0570 0x0838 0x4 0x2 +#define MX6SX_PAD_SD1_DATA0__UART2_DTE_TX 0x0228 0x0570 0x0000 0x4 0x0 #define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x0228 0x0570 0x0000 0x5 0x0 #define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN 0x0228 0x0570 0x0000 0x6 0x0 #define MX6SX_PAD_SD1_DATA0__CCM_OUT2 0x0228 0x0570 0x0000 0x7 0x0 @@ -1235,8 +1253,8 @@ #define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x022C 0x0574 0x066C 0x1 0x1 #define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C 0x0574 0x0000 0x2 0x0 #define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2 0x022C 0x0574 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA1__UART2_RX 0x022C 0x0574 0x0838 0x4 0x3 -#define MX6SX_PAD_SD1_DATA1__UART2_TX 0x022C 0x0574 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_DATA1__UART2_DCE_TX 0x022C 0x0574 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_DATA1__UART2_DTE_RX 0x022C 0x0574 0x0838 0x4 0x3 #define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 0x022C 0x0574 0x0000 0x5 0x0 #define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT 0x022C 0x0574 0x0000 0x6 0x0 #define MX6SX_PAD_SD1_DATA1__CCM_CLKO2 0x022C 0x0574 0x0000 0x7 0x0 @@ -1246,7 +1264,8 @@ #define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1 #define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0 #define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_DATA2__UART2_DCE_CTS 0x0230 0x0578 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_DATA2__UART2_DTE_RTS 0x0230 0x0578 0x0834 0x4 0x2 #define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0 #define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0 #define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0 @@ -1255,7 +1274,8 @@ #define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x0234 0x057C 0x0660 0x1 0x1 #define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2 #define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0 -#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234 0x057C 0x0834 0x4 0x3 +#define MX6SX_PAD_SD1_DATA3__UART2_DCE_RTS 0x0234 0x057C 0x0834 0x4 0x3 +#define MX6SX_PAD_SD1_DATA3__UART2_DTE_CTS 0x0234 0x057C 0x0000 0x4 0x0 #define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0 #define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0 #define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2 @@ -1287,8 +1307,8 @@ #define MX6SX_PAD_SD2_DATA0__I2C4_SDA 0x0240 0x0588 0x07C4 0x4 0x3 #define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8 0x0240 0x0588 0x0000 0x5 0x0 #define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3 0x0240 0x0588 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_DATA0__UART4_RX 0x0240 0x0588 0x0848 0x7 0x4 -#define MX6SX_PAD_SD2_DATA0__UART4_TX 0x0240 0x0588 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_DATA0__UART4_DCE_RX 0x0240 0x0588 0x0848 0x7 0x4 +#define MX6SX_PAD_SD2_DATA0__UART4_DTE_TX 0x0240 0x0588 0x0000 0x7 0x0 #define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 0x0240 0x0588 0x0000 0x8 0x0 #define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50 0x0240 0x0588 0x0000 0x9 0x0 #define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x0244 0x058C 0x0000 0x0 0x0 @@ -1298,8 +1318,8 @@ #define MX6SX_PAD_SD2_DATA1__I2C4_SCL 0x0244 0x058C 0x07C0 0x4 0x3 #define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x0244 0x058C 0x0000 0x5 0x0 #define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2 0x0244 0x058C 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_DATA1__UART4_RX 0x0244 0x058C 0x0848 0x7 0x5 -#define MX6SX_PAD_SD2_DATA1__UART4_TX 0x0244 0x058C 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_DATA1__UART4_DCE_TX 0x0244 0x058C 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_DATA1__UART4_DTE_RX 0x0244 0x058C 0x0848 0x7 0x5 #define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 0x0244 0x058C 0x0000 0x8 0x0 #define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49 0x0244 0x058C 0x0000 0x9 0x0 #define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x0248 0x0590 0x0000 0x0 0x0 @@ -1309,8 +1329,8 @@ #define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248 0x0590 0x081C 0x4 0x2 #define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x0248 0x0590 0x0000 0x5 0x0 #define MX6SX_PAD_SD2_DATA2__SPDIF_OUT 0x0248 0x0590 0x0000 0x6 0x0 -#define MX6SX_PAD_SD2_DATA2__UART6_RX 0x0248 0x0590 0x0858 0x7 0x4 -#define MX6SX_PAD_SD2_DATA2__UART6_TX 0x0248 0x0590 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_DATA2__UART6_DCE_RX 0x0248 0x0590 0x0858 0x7 0x4 +#define MX6SX_PAD_SD2_DATA2__UART6_DTE_TX 0x0248 0x0590 0x0000 0x7 0x0 #define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 0x0248 0x0590 0x0000 0x8 0x0 #define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32 0x0248 0x0590 0x0000 0x9 0x0 #define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x024C 0x0594 0x0000 0x0 0x0 @@ -1320,12 +1340,13 @@ #define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C 0x0594 0x07EC 0x4 0x2 #define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x024C 0x0594 0x0000 0x5 0x0 #define MX6SX_PAD_SD2_DATA3__SPDIF_IN 0x024C 0x0594 0x0824 0x6 0x4 -#define MX6SX_PAD_SD2_DATA3__UART6_RX 0x024C 0x0594 0x0858 0x7 0x5 -#define MX6SX_PAD_SD2_DATA3__UART6_TX 0x024C 0x0594 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_DATA3__UART6_DCE_TX 0x024C 0x0594 0x0000 0x7 0x0 +#define MX6SX_PAD_SD2_DATA3__UART6_DTE_RX 0x024C 0x0594 0x0858 0x7 0x5 #define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0 #define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0 #define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_CLK__UART4_DCE_CTS 0x0250 0x0598 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_CLK__UART4_DTE_RTS 0x0250 0x0598 0x0844 0x1 0x0 #define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0 #define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0 #define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0 @@ -1334,8 +1355,8 @@ #define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29 0x0250 0x0598 0x0000 0x7 0x0 #define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 0x0250 0x0598 0x0000 0x9 0x0 #define MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x0254 0x059C 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_CMD__UART4_RX 0x0254 0x059C 0x0848 0x1 0x0 -#define MX6SX_PAD_SD3_CMD__UART4_TX 0x0254 0x059C 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_CMD__UART4_DCE_TX 0x0254 0x059C 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_CMD__UART4_DTE_RX 0x0254 0x059C 0x0848 0x1 0x0 #define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254 0x059C 0x0748 0x2 0x0 #define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC 0x0254 0x059C 0x067C 0x3 0x0 #define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC 0x0254 0x059C 0x07E4 0x4 0x1 @@ -1364,7 +1385,8 @@ #define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1 0x025C 0x05A4 0x0000 0x8 0x0 #define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0 #define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260 0x05A8 0x0844 0x1 0x1 +#define MX6SX_PAD_SD3_DATA2__UART4_DCE_RTS 0x0260 0x05A8 0x0844 0x1 0x1 +#define MX6SX_PAD_SD3_DATA2__UART4_DTE_CTS 0x0260 0x05A8 0x0000 0x1 0x0 #define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0 #define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0 #define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0 @@ -1374,8 +1396,8 @@ #define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2 0x0260 0x05A8 0x0000 0x8 0x0 #define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 0x0260 0x05A8 0x0000 0x9 0x0 #define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x0264 0x05AC 0x0000 0x0 0x0 -#define MX6SX_PAD_SD3_DATA3__UART4_RX 0x0264 0x05AC 0x0848 0x1 0x1 -#define MX6SX_PAD_SD3_DATA3__UART4_TX 0x0264 0x05AC 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_DATA3__UART4_DCE_RX 0x0264 0x05AC 0x0848 0x1 0x1 +#define MX6SX_PAD_SD3_DATA3__UART4_DTE_TX 0x0264 0x05AC 0x0000 0x1 0x0 #define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264 0x05AC 0x0744 0x2 0x0 #define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD 0x0264 0x05AC 0x0678 0x3 0x0 #define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE 0x0264 0x05AC 0x0000 0x4 0x0 @@ -1387,8 +1409,8 @@ #define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x0268 0x05B0 0x0000 0x0 0x0 #define MX6SX_PAD_SD3_DATA4__CAN2_RX 0x0268 0x05B0 0x0690 0x1 0x0 #define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268 0x05B0 0x0698 0x2 0x0 -#define MX6SX_PAD_SD3_DATA4__UART3_RX 0x0268 0x05B0 0x0840 0x3 0x2 -#define MX6SX_PAD_SD3_DATA4__UART3_TX 0x0268 0x05B0 0x0000 0x3 0x0 +#define MX6SX_PAD_SD3_DATA4__UART3_DCE_RX 0x0268 0x05B0 0x0840 0x3 0x2 +#define MX6SX_PAD_SD3_DATA4__UART3_DTE_TX 0x0268 0x05B0 0x0000 0x3 0x0 #define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3 0x0268 0x05B0 0x0000 0x4 0x0 #define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x0268 0x05B0 0x0000 0x5 0x0 #define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN 0x0268 0x05B0 0x0000 0x6 0x0 @@ -1398,8 +1420,8 @@ #define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x026C 0x05B4 0x0000 0x0 0x0 #define MX6SX_PAD_SD3_DATA5__CAN1_TX 0x026C 0x05B4 0x0000 0x1 0x0 #define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C 0x05B4 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA5__UART3_RX 0x026C 0x05B4 0x0840 0x3 0x3 -#define MX6SX_PAD_SD3_DATA5__UART3_TX 0x026C 0x05B4 0x0000 0x3 0x0 +#define MX6SX_PAD_SD3_DATA5__UART3_DCE_TX 0x026C 0x05B4 0x0000 0x3 0x0 +#define MX6SX_PAD_SD3_DATA5__UART3_DTE_RX 0x026C 0x05B4 0x0840 0x3 0x3 #define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2 0x026C 0x05B4 0x0000 0x4 0x0 #define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x026C 0x05B4 0x0000 0x5 0x0 #define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT 0x026C 0x05B4 0x0000 0x6 0x0 @@ -1409,7 +1431,8 @@ #define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x0270 0x05B8 0x0000 0x0 0x0 #define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0 #define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0 -#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2 +#define MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x0270 0x05B8 0x083C 0x3 0x2 +#define MX6SX_PAD_SD3_DATA6__UART3_DTE_CTS 0x0270 0x05B8 0x0000 0x3 0x0 #define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0 #define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0 #define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0 @@ -1419,7 +1442,8 @@ #define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0 #define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0 #define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0 -#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0 +#define MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x0274 0x05BC 0x0000 0x3 0x0 +#define MX6SX_PAD_SD3_DATA7__UART3_DTE_RTS 0x0274 0x05BC 0x083C 0x3 0x3 #define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0 #define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0 #define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0 @@ -1488,8 +1512,8 @@ #define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS 0x028C 0x05D4 0x0000 0x9 0x0 #define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x0290 0x05D8 0x0000 0x0 0x0 #define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09 0x0290 0x05D8 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA4__UART5_RX 0x0290 0x05D8 0x0850 0x2 0x0 -#define MX6SX_PAD_SD4_DATA4__UART5_TX 0x0290 0x05D8 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_DATA4__UART5_DCE_RX 0x0290 0x05D8 0x0850 0x2 0x0 +#define MX6SX_PAD_SD4_DATA4__UART5_DTE_TX 0x0290 0x05D8 0x0000 0x2 0x0 #define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x0290 0x05D8 0x0730 0x3 0x0 #define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8 0x0290 0x05D8 0x0000 0x4 0x0 #define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x0290 0x05D8 0x0000 0x5 0x0 @@ -1499,8 +1523,8 @@ #define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE 0x0290 0x05D8 0x0000 0x9 0x0 #define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x0294 0x05DC 0x0000 0x0 0x0 #define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B 0x0294 0x05DC 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA5__UART5_RX 0x0294 0x05DC 0x0850 0x2 0x1 -#define MX6SX_PAD_SD4_DATA5__UART5_TX 0x0294 0x05DC 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_DATA5__UART5_DCE_TX 0x0294 0x05DC 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_DATA5__UART5_DTE_RX 0x0294 0x05DC 0x0850 0x2 0x1 #define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x0294 0x05DC 0x0738 0x3 0x0 #define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7 0x0294 0x05DC 0x0000 0x4 0x0 #define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19 0x0294 0x05DC 0x0000 0x5 0x0 @@ -1510,7 +1534,8 @@ #define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 0x0294 0x05DC 0x0000 0x9 0x0 #define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0 #define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0 +#define MX6SX_PAD_SD4_DATA6__UART5_DCE_RTS 0x0298 0x05E0 0x084C 0x2 0x0 +#define MX6SX_PAD_SD4_DATA6__UART5_DTE_CTS 0x0298 0x05E0 0x0000 0x2 0x0 #define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0 #define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0 #define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0 @@ -1520,7 +1545,8 @@ #define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0 #define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0 #define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0 -#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_DATA7__UART5_DCE_CTS 0x029C 0x05E4 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_DATA7__UART5_DTE_RTS 0x029C 0x05E4 0x084C 0x2 0x1 #define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0 #define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0 #define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0 @@ -1551,4 +1577,92 @@ #define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB 0x02A8 0x05F0 0x0000 0x4 0x0 #define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x02A8 0x05F0 0x0000 0x5 0x0 +/* these are not supposed to be used any more and remove them after some time */ +#define MX6SX_PAD_GPIO1_IO04__UART1_RX MX6SX_PAD_GPIO1_IO04__UART1_DTE_RX +#define MX6SX_PAD_GPIO1_IO04__UART1_TX MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX +#define MX6SX_PAD_GPIO1_IO05__UART1_RX MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX +#define MX6SX_PAD_GPIO1_IO05__UART1_TX MX6SX_PAD_GPIO1_IO05__UART1_DTE_TX +#define MX6SX_PAD_GPIO1_IO06__UART2_RX MX6SX_PAD_GPIO1_IO06__UART2_DTE_RX +#define MX6SX_PAD_GPIO1_IO06__UART2_TX MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX +#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B MX6SX_PAD_GPIO1_IO06__UART1_DCE_RTS +#define MX6SX_PAD_GPIO1_IO07__UART2_RX MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX +#define MX6SX_PAD_GPIO1_IO07__UART2_TX MX6SX_PAD_GPIO1_IO07__UART2_DTE_TX +#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B MX6SX_PAD_GPIO1_IO07__UART1_DCE_CTS +#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B MX6SX_PAD_GPIO1_IO08__UART2_DCE_RTS +#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B MX6SX_PAD_GPIO1_IO09__UART2_DCE_CTS +#define MX6SX_PAD_CSI_DATA04__UART6_RX MX6SX_PAD_CSI_DATA04__UART6_DCE_RX +#define MX6SX_PAD_CSI_DATA04__UART6_TX MX6SX_PAD_CSI_DATA04__UART6_DTE_TX +#define MX6SX_PAD_CSI_DATA05__UART6_RX MX6SX_PAD_CSI_DATA05__UART6_DTE_RX +#define MX6SX_PAD_CSI_DATA05__UART6_TX MX6SX_PAD_CSI_DATA05__UART6_DCE_TX +#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS +#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS +#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B MX6SX_PAD_CSI_HSYNC__UART4_DCE_RTS +#define MX6SX_PAD_CSI_MCLK__UART4_RX MX6SX_PAD_CSI_MCLK__UART4_DCE_RX +#define MX6SX_PAD_CSI_MCLK__UART4_TX MX6SX_PAD_CSI_MCLK__UART4_DTE_TX +#define MX6SX_PAD_CSI_PIXCLK__UART4_RX MX6SX_PAD_CSI_PIXCLK__UART4_DTE_RX +#define MX6SX_PAD_CSI_PIXCLK__UART4_TX MX6SX_PAD_CSI_PIXCLK__UART4_DCE_TX +#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B MX6SX_PAD_CSI_VSYNC__UART4_DCE_CTS +#define MX6SX_PAD_ENET2_COL__UART1_RX MX6SX_PAD_ENET2_COL__UART1_DCE_RX +#define MX6SX_PAD_ENET2_COL__UART1_TX MX6SX_PAD_ENET2_COL__UART1_DTE_TX +#define MX6SX_PAD_ENET2_CRS__UART1_RX MX6SX_PAD_ENET2_CRS__UART1_DTE_RX +#define MX6SX_PAD_ENET2_CRS__UART1_TX MX6SX_PAD_ENET2_CRS__UART1_DCE_TX +#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B MX6SX_PAD_ENET2_RX_CLK__UART1_DCE_RTS +#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B MX6SX_PAD_ENET2_TX_CLK__UART1_DCE_CTS +#define MX6SX_PAD_KEY_COL0__UART6_RTS_B MX6SX_PAD_KEY_COL0__UART6_DCE_RTS +#define MX6SX_PAD_KEY_COL1__UART6_RX MX6SX_PAD_KEY_COL1__UART6_DTE_RX +#define MX6SX_PAD_KEY_COL1__UART6_TX MX6SX_PAD_KEY_COL1__UART6_DCE_TX +#define MX6SX_PAD_KEY_COL2__UART5_RTS_B MX6SX_PAD_KEY_COL2__UART5_DCE_RTS +#define MX6SX_PAD_KEY_COL3__UART5_RX MX6SX_PAD_KEY_COL3__UART5_DTE_RX +#define MX6SX_PAD_KEY_COL3__UART5_TX MX6SX_PAD_KEY_COL3__UART5_DCE_TX +#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B MX6SX_PAD_KEY_ROW0__UART6_DCE_CTS +#define MX6SX_PAD_KEY_ROW1__UART6_RX MX6SX_PAD_KEY_ROW1__UART6_DCE_RX +#define MX6SX_PAD_KEY_ROW1__UART6_TX MX6SX_PAD_KEY_ROW1__UART6_DTE_TX +#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS +#define MX6SX_PAD_KEY_ROW3__UART5_RX MX6SX_PAD_KEY_ROW3__UART5_DCE_RX +#define MX6SX_PAD_KEY_ROW3__UART5_TX MX6SX_PAD_KEY_ROW3__UART5_DTE_TX +#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B MX6SX_PAD_NAND_DATA04__UART3_DCE_RTS +#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B MX6SX_PAD_NAND_DATA05__UART3_DCE_CTS +#define MX6SX_PAD_NAND_DATA06__UART3_RX MX6SX_PAD_NAND_DATA06__UART3_DCE_RX +#define MX6SX_PAD_NAND_DATA06__UART3_TX MX6SX_PAD_NAND_DATA06__UART3_DTE_TX +#define MX6SX_PAD_NAND_DATA07__UART3_RX MX6SX_PAD_NAND_DATA07__UART3_DTE_RX +#define MX6SX_PAD_NAND_DATA07__UART3_TX MX6SX_PAD_NAND_DATA07__UART3_DCE_TX +#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B MX6SX_PAD_QSPI1B_DATA0__UART3_DCE_CTS +#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B MX6SX_PAD_QSPI1B_DATA1__UART3_DCE_RTS +#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX +#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX +#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX MX6SX_PAD_QSPI1B_SS0_B__UART3_DTE_RX +#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX +#define MX6SX_PAD_SD1_DATA0__UART2_RX MX6SX_PAD_SD1_DATA0__UART2_DCE_RX +#define MX6SX_PAD_SD1_DATA0__UART2_TX MX6SX_PAD_SD1_DATA0__UART2_DTE_TX +#define MX6SX_PAD_SD1_DATA1__UART2_RX MX6SX_PAD_SD1_DATA1__UART2_DTE_RX +#define MX6SX_PAD_SD1_DATA1__UART2_TX MX6SX_PAD_SD1_DATA1__UART2_DCE_TX +#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B MX6SX_PAD_SD1_DATA2__UART2_DCE_CTS +#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B MX6SX_PAD_SD1_DATA3__UART2_DCE_RTS +#define MX6SX_PAD_SD2_DATA0__UART4_RX MX6SX_PAD_SD2_DATA0__UART4_DCE_RX +#define MX6SX_PAD_SD2_DATA0__UART4_TX MX6SX_PAD_SD2_DATA0__UART4_DTE_TX +#define MX6SX_PAD_SD2_DATA1__UART4_RX MX6SX_PAD_SD2_DATA1__UART4_DTE_RX +#define MX6SX_PAD_SD2_DATA1__UART4_TX MX6SX_PAD_SD2_DATA1__UART4_DCE_TX +#define MX6SX_PAD_SD2_DATA2__UART6_RX MX6SX_PAD_SD2_DATA2__UART6_DCE_RX +#define MX6SX_PAD_SD2_DATA2__UART6_TX MX6SX_PAD_SD2_DATA2__UART6_DTE_TX +#define MX6SX_PAD_SD2_DATA3__UART6_RX MX6SX_PAD_SD2_DATA3__UART6_DTE_RX +#define MX6SX_PAD_SD2_DATA3__UART6_TX MX6SX_PAD_SD2_DATA3__UART6_DCE_TX +#define MX6SX_PAD_SD3_CLK__UART4_CTS_B MX6SX_PAD_SD3_CLK__UART4_DCE_CTS +#define MX6SX_PAD_SD3_CMD__UART4_RX MX6SX_PAD_SD3_CMD__UART4_DTE_RX +#define MX6SX_PAD_SD3_CMD__UART4_TX MX6SX_PAD_SD3_CMD__UART4_DCE_TX +#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B MX6SX_PAD_SD3_DATA2__UART4_DCE_RTS +#define MX6SX_PAD_SD3_DATA3__UART4_RX MX6SX_PAD_SD3_DATA3__UART4_DCE_RX +#define MX6SX_PAD_SD3_DATA3__UART4_TX MX6SX_PAD_SD3_DATA3__UART4_DTE_TX +#define MX6SX_PAD_SD3_DATA4__UART3_RX MX6SX_PAD_SD3_DATA4__UART3_DCE_RX +#define MX6SX_PAD_SD3_DATA4__UART3_TX MX6SX_PAD_SD3_DATA4__UART3_DTE_TX +#define MX6SX_PAD_SD3_DATA5__UART3_RX MX6SX_PAD_SD3_DATA5__UART3_DTE_RX +#define MX6SX_PAD_SD3_DATA5__UART3_TX MX6SX_PAD_SD3_DATA5__UART3_DCE_TX +#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS +#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS +#define MX6SX_PAD_SD4_DATA4__UART5_RX MX6SX_PAD_SD4_DATA4__UART5_DCE_RX +#define MX6SX_PAD_SD4_DATA4__UART5_TX MX6SX_PAD_SD4_DATA4__UART5_DTE_TX +#define MX6SX_PAD_SD4_DATA5__UART5_RX MX6SX_PAD_SD4_DATA5__UART5_DTE_RX +#define MX6SX_PAD_SD4_DATA5__UART5_TX MX6SX_PAD_SD4_DATA5__UART5_DCE_TX +#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B MX6SX_PAD_SD4_DATA6__UART5_DCE_RTS +#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B MX6SX_PAD_SD4_DATA7__UART5_DCE_CTS + #endif /* __DTS_IMX6SX_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts index 315044ccd65f..825924448ab4 100644 --- a/arch/arm/boot/dts/imx6sx-sabreauto.dts +++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts @@ -229,8 +229,8 @@ pinctrl_uart1: uart1grp { fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 >; }; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi index f6972deb5e39..3e5fb72f21fc 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi @@ -564,17 +564,17 @@ pinctrl_uart1: uart1grp { fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 >; }; pinctrl_uart5: uart5grp { fsl,pins = < - MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 - MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 - MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 - MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x1b0b1 >; }; diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts index 28563f21024e..6b728b03f1f2 100644 --- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts +++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts @@ -352,6 +352,12 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x10b0 + >; + }; + pinctrl_pwm1: pwm1grp-1 { fsl,pins = < /* blue LED */ @@ -384,15 +390,15 @@ pinctrl_uart1: uart1grp { fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 >; }; @@ -490,6 +496,14 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; + reset-gpio-active-high; + status = "okay"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi index 25d4aa985a69..ee645655090d 100644 --- a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi +++ b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi @@ -235,28 +235,28 @@ pinctrl_uart1: uart1grp { fsl,pins = - <MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1>, - <MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1>; + <MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1>, + <MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1>; }; pinctrl_uart2: uart2grp { fsl,pins = - <MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1>, - <MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1>; + <MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1>, + <MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1>; }; pinctrl_uart3: uart3grp { fsl,pins = - <MX6SX_PAD_SD3_DATA4__UART3_RX 0x13059>, - <MX6SX_PAD_SD3_DATA5__UART3_TX 0x13059>, - <MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x13059>, - <MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x13059>; + <MX6SX_PAD_SD3_DATA4__UART3_DCE_RX 0x13059>, + <MX6SX_PAD_SD3_DATA5__UART3_DCE_TX 0x13059>, + <MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x13059>, + <MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x13059>; }; pinctrl_uart5: uart5grp { fsl,pins = - <MX6SX_PAD_SD4_DATA4__UART5_RX 0x1b0b1>, - <MX6SX_PAD_SD4_DATA5__UART5_TX 0x1b0b1>; + <MX6SX_PAD_SD4_DATA4__UART5_DCE_RX 0x1b0b1>, + <MX6SX_PAD_SD4_DATA5__UART5_DCE_TX 0x1b0b1>; }; pinctrl_uart6: uart6grp { @@ -265,10 +265,10 @@ <MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x1b0b1>, <MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x1b0b1>, <MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x1b0b1>, - <MX6SX_PAD_CSI_DATA04__UART6_RX 0x1b0b1>, - <MX6SX_PAD_CSI_DATA05__UART6_TX 0x1b0b1>, - <MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x1b0b1>, - <MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x1b0b1>; + <MX6SX_PAD_CSI_DATA04__UART6_DCE_RX 0x1b0b1>, + <MX6SX_PAD_CSI_DATA05__UART6_DCE_TX 0x1b0b1>, + <MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS 0x1b0b1>, + <MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS 0x1b0b1>; }; pinctrl_otg1_reg: otg1grp { diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 59bad60a47dc..e03133740078 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -87,6 +87,8 @@ "pll1_sw", "pll1_sys"; arm-supply = <®_arm>; soc-supply = <®_soc>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; }; }; @@ -235,7 +237,7 @@ status = "disabled"; }; - aips1: aips-bus@2000000 { + aips1: bus@2000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -466,7 +468,7 @@ status = "disabled"; }; - gpt: gpt@2098000 { + gpt: timer@2098000 { compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt"; reg = <0x02098000 0x4000>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; @@ -559,7 +561,7 @@ gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; }; - kpp: kpp@20b8000 { + kpp: keypad@20b8000 { compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; @@ -567,14 +569,14 @@ status = "disabled"; }; - wdog1: wdog@20bc000 { + wdog1: watchdog@20bc000 { compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_IPG>; }; - wdog2: wdog@20c0000 { + wdog2: watchdog@20c0000 { compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; @@ -582,7 +584,7 @@ status = "disabled"; }; - clks: ccm@20c4000 { + clks: clock-controller@20c4000 { compatible = "fsl,imx6sx-ccm"; reg = <0x020c4000 0x4000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, @@ -752,7 +754,7 @@ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@20d8000 { + src: reset-controller@20d8000 { compatible = "fsl,imx6sx-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, @@ -806,7 +808,7 @@ }; }; - iomuxc: iomuxc@20e0000 { + iomuxc: pinctrl@20e0000 { compatible = "fsl,imx6sx-iomuxc"; reg = <0x020e0000 0x4000>; }; @@ -830,14 +832,14 @@ }; }; - aips2: aips-bus@2100000 { + aips2: bus@2100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02100000 0x100000>; ranges; - crypto: caam@2100000 { + crypto: crypto@2100000 { compatible = "fsl,sec-v4.0"; #address-cells = <1>; #size-cells = <1>; @@ -850,13 +852,13 @@ <&clks IMX6SX_CLK_EIM_SLOW>; clock-names = "mem", "aclk", "ipg", "emi_slow"; - sec_jr0: jr0@1000 { + sec_jr0: jr@1000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; }; - sec_jr1: jr1@2000 { + sec_jr1: jr@2000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x2000 0x1000>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; @@ -1051,13 +1053,17 @@ status = "disabled"; }; - ocotp: ocotp@21bc000 { + ocotp: ocotp-ctrl@21bc000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,imx6sx-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6SX_CLK_OCOTP>; + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; + tempmon_calib: calib@38 { reg = <0x38 4>; }; @@ -1188,7 +1194,7 @@ }; }; - aips3: aips-bus@2200000 { + aips3: bus@2200000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -1289,7 +1295,7 @@ status = "disabled"; }; - wdog3: wdog@2288000 { + wdog3: watchdog@2288000 { compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; reg = <0x02288000 0x4000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts index 3749fdda3611..5d3805b07032 100644 --- a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts @@ -25,7 +25,7 @@ }; panel { - compatible = "auo,g101evn010", "simple-panel"; + compatible = "auo,g101evn010"; power-supply = <&ldo4_ext>; backlight = <&lcd_backlight>; diff --git a/arch/arm/boot/dts/imx6ul-pico-dwarf.dts b/arch/arm/boot/dts/imx6ul-pico-dwarf.dts new file mode 100644 index 000000000000..162dc259edc8 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-pico-dwarf.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2015 Technexion Ltd. +// +// Author: Wig Cheng <wig.cheng@technexion.com> +// Richard Hu <richard.hu@technexion.com> +// Tapani Utriainen <tapani@technexion.com> +/dts-v1/; + +#include "imx6ul-pico.dtsi" +/ { + model = "TechNexion PICO-IMX6UL and DWARF baseboard"; + compatible = "technexion,imx6ul-pico-dwarf", "fsl,imx6ul"; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6ul-sgtl5000"; + audio-cpu = <&sai1>; + audio-codec = <&sgtl5000>; + audio-routing = + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + }; + + sys_mclk: clock-sys-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: audio-codec@a { + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&sys_mclk>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-pico.dtsi b/arch/arm/boot/dts/imx6ul-pico.dtsi index de9f83189ba8..df1da98ab10f 100644 --- a/arch/arm/boot/dts/imx6ul-pico.dtsi +++ b/arch/arm/boot/dts/imx6ul-pico.dtsi @@ -20,7 +20,7 @@ stdout-path = &uart6; }; - backlight { + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm3 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -72,6 +72,17 @@ regulator-max-microvolt = <3300000>; startup-delay-us = <200000>; }; + + panel { + compatible = "vxt,vl050-8048nt-c01"; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; }; &can1 { @@ -154,31 +165,11 @@ &lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; - display = <&display0>; status = "okay"; - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - - timing0: timing0 { - clock-frequency = <33200000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <210>; - hback-porch = <46>; - hsync-len = <1>; - vback-porch = <22>; - vfront-porch = <23>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; }; }; }; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index d9fdca12819b..35e730167960 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -204,7 +204,7 @@ status = "disabled"; }; - aips1: aips-bus@2000000 { + aips1: bus@2000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -430,7 +430,7 @@ status = "disabled"; }; - gpt1: gpt@2098000 { + gpt1: timer@2098000 { compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; reg = <0x02098000 0x4000>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; @@ -523,7 +523,7 @@ status = "disabled"; }; - kpp: kpp@20b8000 { + kpp: keypad@20b8000 { compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; @@ -531,14 +531,14 @@ status = "disabled"; }; - wdog1: wdog@20bc000 { + wdog1: watchdog@20bc000 { compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_WDOG1>; }; - wdog2: wdog@20c0000 { + wdog2: watchdog@20c0000 { compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; @@ -546,7 +546,7 @@ status = "disabled"; }; - clks: ccm@20c4000 { + clks: clock-controller@20c4000 { compatible = "fsl,imx6ul-ccm"; reg = <0x020c4000 0x4000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, @@ -676,7 +676,7 @@ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@20d8000 { + src: reset-controller@20d8000 { compatible = "fsl,imx6ul-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, @@ -693,7 +693,7 @@ interrupt-parent = <&intc>; }; - iomuxc: iomuxc@20e0000 { + iomuxc: pinctrl@20e0000 { compatible = "fsl,imx6ul-iomuxc"; reg = <0x020e0000 0x4000>; }; @@ -704,7 +704,7 @@ reg = <0x020e4000 0x4000>; }; - gpt2: gpt@20e8000 { + gpt2: timer@20e8000 { compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; reg = <0x020e8000 0x4000>; interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; @@ -771,14 +771,14 @@ }; }; - aips2: aips-bus@2100000 { + aips2: bus@2100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02100000 0x100000>; ranges; - crypto: caam@2140000 { + crypto: crypto@2140000 { compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0"; #address-cells = <1>; #size-cells = <1>; @@ -789,19 +789,19 @@ <&clks IMX6UL_CLK_CAAM_MEM>; clock-names = "ipg", "aclk", "mem"; - sec_jr0: jr0@1000 { + sec_jr0: jr@1000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; }; - sec_jr1: jr1@2000 { + sec_jr1: jr@2000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x2000 0x1000>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; }; - sec_jr2: jr2@3000 { + sec_jr2: jr@3000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x3000 0x1000>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; @@ -1007,7 +1007,7 @@ status = "disabled"; }; - wdog3: wdog@21e4000 { + wdog3: watchdog@21e4000 { compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; reg = <0x021e4000 0x4000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index b7e67d121322..fcde7f77ae42 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -51,7 +51,7 @@ / { soc { - aips3: aips-bus@2200000 { + aips3: bus@2200000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx7-colibri-aster.dtsi b/arch/arm/boot/dts/imx7-colibri-aster.dtsi new file mode 100644 index 000000000000..9fa701bec2ec --- /dev/null +++ b/arch/arm/boot/dts/imx7-colibri-aster.dtsi @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017-2020 Toradex AG + * + */ + + +#include <dt-bindings/input/input.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + power { + label = "Wake-Up"; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + panel: panel { + compatible = "edt,et057090dhu"; + backlight = <&bl>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; + +&adc1 { + status = "okay"; +}; + +/* + * ADC2 is not available on the Aster board and + * conflicts with AD7879 resistive touchscreen. + */ +&adc2 { + status = "disabled"; +}; + +&bl { + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <®_3v3>; + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + /* Microchip/Atmel maxtouch controller */ + touchscreen@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiotouch>; + reg = <0x4a>; + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + reset-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ + }; + + /* M41T0M6 real time clock on carrier board */ + rtc: m41t0m6@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl_gpiotouch: touchgpios { + fsl,pins = < + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 + >; + }; +}; + +&lcdif { + status = "okay"; + + port { + lcdif_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usdhc1 { + keep-power-in-suspend; + no-1-8-v; + wakeup-source; + vmmc-supply = <®_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi index 6aa123cbdadb..97601375f264 100644 --- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi @@ -1,46 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2016-2020 Toradex */ / { + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + chosen { stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index d05be3f0e2a7..e18e89dec879 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2016-2020 Toradex */ / { @@ -130,6 +93,184 @@ status = "disabled"; }; +&gpio1 { + gpio-line-names = "SODIMM_43", + "SODIMM_45", + "SODIMM_135", + "SODIMM_22", + "", + "", + "SODIMM_37", + "SODIMM_29", + "SODIMM_59", + "SODIMM_28", + "SODIMM_30", + "SODIMM_67", + "", + "", + "SODIMM_188", + "SODIMM_178"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_111", + "SODIMM_113", + "SODIMM_115", + "SODIMM_117", + "SODIMM_119", + "SODIMM_121", + "SODIMM_123", + "SODIMM_125", + "SODIMM_91", + "SODIMM_89", + "SODIMM_105", + "SODIMM_152", + "SODIMM_150", + "SODIMM_95", + "SODIMM_126", + "SODIMM_107", + "SODIMM_114", + "SODIMM_116", + "SODIMM_118", + "SODIMM_120", + "SODIMM_122", + "SODIMM_124", + "SODIMM_127", + "SODIMM_130", + "SODIMM_132", + "SODIMM_134", + "SODIMM_133", + "SODIMM_104", + "SODIMM_106", + "SODIMM_110", + "SODIMM_112", + "SODIMM_128"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_56", + "SODIMM_44", + "SODIMM_68", + "SODIMM_82", + "SODIMM_93", + "SODIMM_76", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_57", + "SODIMM_61", + "SODIMM_136", + "SODIMM_138", + "SODIMM_140", + "SODIMM_142", + "SODIMM_144", + "SODIMM_146"; +}; + +&gpio4 { + gpio-line-names = "SODIMM_35", + "SODIMM_33", + "SODIMM_38", + "SODIMM_36", + "SODIMM_21", + "SODIMM_19", + "SODIMM_131", + "SODIMM_129", + "SODIMM_90", + "SODIMM_92", + "SODIMM_88", + "SODIMM_86", + "SODIMM_81", + "SODIMM_94", + "SODIMM_96", + "SODIMM_75", + "SODIMM_101", + "SODIMM_103", + "SODIMM_79", + "SODIMM_97", + "SODIMM_67", + "SODIMM_59", + "SODIMM_85", + "SODIMM_65"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_69", + "SODIMM_71", + "SODIMM_73", + "SODIMM_47", + "SODIMM_190", + "SODIMM_192", + "SODIMM_49", + "SODIMM_51", + "SODIMM_53", + "", + "", + "SODIMM_98", + "SODIMM_184", + "SODIMM_186", + "SODIMM_23", + "SODIMM_31", + "SODIMM_100", + "SODIMM_102"; +}; + +&gpio6 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_169", + "", + "", + "", + "SODIMM_77", + "SODIMM_24", + "", + "SODIMM_25", + "SODIMM_27", + "SODIMM_32", + "SODIMM_34"; +}; + +&gpio7 { + gpio-line-names = "", + "", + "SODIMM_63", + "SODIMM_55", + "", + "", + "", + "", + "SODIMM_196", + "SODIMM_194", + "", + "SODIMM_99", + "", + "", + "SODIMM_137"; +}; + &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; @@ -336,7 +477,6 @@ assigned-clock-rates = <400000000>; bus-width = <8>; fsl,tuning-step = <2>; - max-frequency = <100000000>; vmmc-supply = <®_module_3v3>; vqmmc-supply = <®_DCDC3>; non-removable; @@ -346,7 +486,7 @@ &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4 - &pinctrl_gpio7>; + &pinctrl_gpio7 &pinctrl_usbc_det>; pinctrl_gpio1: gpio1-grp { fsl,pins = < @@ -357,7 +497,6 @@ MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */ MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */ MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */ - MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 */ MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */ MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */ MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */ @@ -374,7 +513,6 @@ MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */ MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */ MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */ - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x74 /* SODIMM 106 */ MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */ MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */ MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */ @@ -451,7 +589,6 @@ pinctrl_enet1: enet1grp { fsl,pins = < - MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73 @@ -649,6 +786,12 @@ >; }; + pinctrl_usbc_det: gpio-usbc-det { + fsl,pins = < + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 + >; + }; + pinctrl_usbh_reg: gpio-usbh-vbus { fsl,pins = < MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */ diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/imx7-tqma7.dtsi index 9aaed85138cb..8773344b54aa 100644 --- a/arch/arm/boot/dts/imx7-tqma7.dtsi +++ b/arch/arm/boot/dts/imx7-tqma7.dtsi @@ -16,7 +16,7 @@ }; &cpu0 { - arm-supply = <&sw1a_reg>; + cpu-supply = <&sw1a_reg>; }; &i2c1 { diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts index 7646284e13a7..713483c39c9d 100644 --- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts +++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts @@ -37,6 +37,10 @@ cpu-supply = <&sw1a_reg>; }; +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; @@ -85,12 +89,12 @@ pmic: pmic@8 { compatible = "fsl,pfuze3000"; - reg = <0x08>; + reg = <0x8>; regulators { sw1a_reg: sw1a { regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <6250>; diff --git a/arch/arm/boot/dts/imx7d-colibri-aster.dts b/arch/arm/boot/dts/imx7d-colibri-aster.dts new file mode 100644 index 000000000000..f3f0537d5a37 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-aster.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017-2020 Toradex AG + * + */ + +/dts-v1/; +#include "imx7d-colibri.dtsi" +#include "imx7-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX7D on Aster Carrier Board"; + compatible = "toradex,colibri-imx7d-aster", "toradex,colibri-imx7d", + "fsl,imx7d"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts new file mode 100644 index 000000000000..20480276cb0e --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017-2020 Toradex AG + * + */ + +/dts-v1/; +#include "imx7d-colibri-emmc.dtsi" +#include "imx7-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX7D 1GB (eMMC) on Aster Carrier Board"; + compatible = "toradex,colibri-imx7d-emmc-aster", + "toradex,colibri-imx7d-emmc", "fsl,imx7d"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi index 898f4b8d7421..af39e5370fa1 100644 --- a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi +++ b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi @@ -13,6 +13,32 @@ }; }; +&gpio6 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_169", + "SODIMM_157", + "", + "SODIMM_163", + "SODIMM_77", + "SODIMM_24", + "", + "SODIMM_25", + "SODIMM_27", + "SODIMM_32", + "SODIMM_34"; +}; + &usbotg2 { dr_mode = "host"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts index 136e11ab4893..87b132bcd272 100644 --- a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2016-2020 Toradex */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi index e2e327f437e3..219a0404a058 100644 --- a/arch/arm/boot/dts/imx7d-colibri.dtsi +++ b/arch/arm/boot/dts/imx7d-colibri.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2016-2020 Toradex */ #include "imx7d.dtsi" @@ -50,6 +13,10 @@ }; }; +&cpu1 { + cpu-supply = <®_DCDC2>; +}; + &gpmi { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index 6b4acea1ef79..e0751e6ba3c0 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -121,6 +121,10 @@ cpu-supply = <&sw1a_reg>; }; +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; diff --git a/arch/arm/boot/dts/imx7d-pico-dwarf.dts b/arch/arm/boot/dts/imx7d-pico-dwarf.dts new file mode 100644 index 000000000000..5162fe227d1e --- /dev/null +++ b/arch/arm/boot/dts/imx7d-pico-dwarf.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2015 Technexion Ltd. +// +// Author: Wig Cheng <wig.cheng@technexion.com> +// Richard Hu <richard.hu@technexion.com> +// Tapani Utriainen <tapani@technexion.com> +/dts-v1/; + +#include "imx7d-pico.dtsi" +/ { + model = "TechNexion PICO-IMX7D and DWARF baseboard"; + compatible = "technexion,imx7d-pico-dwarf", "fsl,imx7d"; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx7d-sgtl5000"; + audio-cpu = <&sai1>; + audio-codec = <&sgtl5000>; + audio-routing = + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + }; + + sys_mclk: clock-sys-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; +}; + +&i2c1 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: audio-codec@a { + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&sys_mclk>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + +&i2c4 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pca9554: io-expander@25 { + compatible = "nxp,pca9554"; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + reg = <0x25>; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupt-parent = <&gpio2>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pca9554 4 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; +}; + +&iomuxc { + pinctrl_touchscreen: touchscreengrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx7d-pico-nymph.dts b/arch/arm/boot/dts/imx7d-pico-nymph.dts new file mode 100644 index 000000000000..104a85254adb --- /dev/null +++ b/arch/arm/boot/dts/imx7d-pico-nymph.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2015 Technexion Ltd. +// +// Author: Wig Cheng <wig.cheng@technexion.com> +// Richard Hu <richard.hu@technexion.com> +// Tapani Utriainen <tapani@technexion.com> +/dts-v1/; + +#include "imx7d-pico.dtsi" +/ { + model = "TechNexion PICO-IMX7 and NYMPH baseboard"; + compatible = "technexion,imx7d-pico-nymph", "fsl,imx7d"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx7d-sgtl5000"; + audio-cpu = <&sai1>; + audio-codec = <&sgtl5000>; + audio-routing = + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + }; + + sys_mclk: clock-sys-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; +}; + +&i2c1 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: audio-codec@a { + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&sys_mclk>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + adc@52 { + compatible = "ti,adc081c"; + reg = <0x52>; + vref-supply = <®_2p5v>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h index 08ca1608fdb1..69f2c1ec8254 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ b/arch/arm/boot/dts/imx7d-pinfunc.h @@ -592,7 +592,7 @@ #define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0 #define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0 #define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 -#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0000 0x6 0x0 +#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0574 0x6 0x1 #define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0 #define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3 #define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0 diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 869efbc4af42..17cca8a9f77b 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -162,6 +162,10 @@ cpu-supply = <&sw1a_reg>; }; +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; + &ecspi3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; diff --git a/arch/arm/boot/dts/imx7d-tqma7.dtsi b/arch/arm/boot/dts/imx7d-tqma7.dtsi index 8ad3048dac0d..598aed1ffd99 100644 --- a/arch/arm/boot/dts/imx7d-tqma7.dtsi +++ b/arch/arm/boot/dts/imx7d-tqma7.dtsi @@ -9,3 +9,7 @@ #include "imx7d.dtsi" #include "imx7-tqma7.dtsi" + +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; diff --git a/arch/arm/boot/dts/imx7d-zii-rmu2.dts b/arch/arm/boot/dts/imx7d-zii-rmu2.dts index 2b8d6cc45a53..e5e20b07f184 100644 --- a/arch/arm/boot/dts/imx7d-zii-rmu2.dts +++ b/arch/arm/boot/dts/imx7d-zii-rmu2.dts @@ -33,7 +33,7 @@ }; &cpu0 { - arm-supply = <&sw1a_reg>; + cpu-supply = <&sw1a_reg>; }; &ecspi1 { diff --git a/arch/arm/boot/dts/imx7d-zii-rpu2.dts b/arch/arm/boot/dts/imx7d-zii-rpu2.dts index 39812c92bf0d..cbf0dbb4c198 100644 --- a/arch/arm/boot/dts/imx7d-zii-rpu2.dts +++ b/arch/arm/boot/dts/imx7d-zii-rpu2.dts @@ -182,7 +182,7 @@ }; &cpu0 { - arm-supply = <&sw1a_reg>; + cpu-supply = <&sw1a_reg>; }; &clks { diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 92f6d0c2a74f..4c22828df55f 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -44,7 +44,7 @@ opp-hz = /bits/ 64 <792000000>; opp-microvolt = <1000000>; clock-latency-ns = <150000>; - opp-supported-hw = <0xd>, <0xf>; + opp-supported-hw = <0xd>, <0x7>; opp-suspend; }; @@ -52,7 +52,7 @@ opp-hz = /bits/ 64 <996000000>; opp-microvolt = <1100000>; clock-latency-ns = <150000>; - opp-supported-hw = <0xc>, <0xf>; + opp-supported-hw = <0xc>, <0x7>; opp-suspend; }; @@ -60,7 +60,7 @@ opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1225000>; clock-latency-ns = <150000>; - opp-supported-hw = <0x8>, <0xf>; + opp-supported-hw = <0x8>, <0x3>; opp-suspend; }; }; diff --git a/arch/arm/boot/dts/imx7s-colibri-aster.dts b/arch/arm/boot/dts/imx7s-colibri-aster.dts new file mode 100644 index 000000000000..fca4e0a95c1b --- /dev/null +++ b/arch/arm/boot/dts/imx7s-colibri-aster.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017-2020 Toradex AG + * + */ + +/dts-v1/; +#include "imx7s-colibri.dtsi" +#include "imx7-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX7S on Aster Carrier Board"; + compatible = "toradex,colibri-imx7s-aster", "toradex,colibri-imx7s", + "fsl,imx7s"; +}; diff --git a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts index bd2a49c1ade6..aa70d3f2e2e2 100644 --- a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2016-2020 Toradex */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/imx7s-colibri.dtsi index 6d16e32aed89..94de220a5965 100644 --- a/arch/arm/boot/dts/imx7s-colibri.dtsi +++ b/arch/arm/boot/dts/imx7s-colibri.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2016 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2016-2020 Toradex */ #include "imx7s.dtsi" diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 568d7a984aa6..8bac49137692 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -315,7 +315,7 @@ <0x31006000 0x2000>; }; - aips1: aips-bus@30000000 { + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -406,14 +406,14 @@ gpio-ranges = <&iomuxc 0 139 16>; }; - wdog1: wdog@30280000 { + wdog1: watchdog@30280000 { compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; reg = <0x30280000 0x10000>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; }; - wdog2: wdog@30290000 { + wdog2: watchdog@30290000 { compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; reg = <0x30290000 0x10000>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; @@ -421,7 +421,7 @@ status = "disabled"; }; - wdog3: wdog@302a0000 { + wdog3: watchdog@302a0000 { compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; reg = <0x302a0000 0x10000>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; @@ -429,7 +429,7 @@ status = "disabled"; }; - wdog4: wdog@302b0000 { + wdog4: watchdog@302b0000 { compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; reg = <0x302b0000 0x10000>; interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; @@ -443,7 +443,7 @@ fsl,input-sel = <&iomuxc>; }; - gpt1: gpt@302d0000 { + gpt1: timer@302d0000 { compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; reg = <0x302d0000 0x10000>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; @@ -452,7 +452,7 @@ clock-names = "ipg", "per"; }; - gpt2: gpt@302e0000 { + gpt2: timer@302e0000 { compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; reg = <0x302e0000 0x10000>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; @@ -462,7 +462,7 @@ status = "disabled"; }; - gpt3: gpt@302f0000 { + gpt3: timer@302f0000 { compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; reg = <0x302f0000 0x10000>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; @@ -472,7 +472,7 @@ status = "disabled"; }; - gpt4: gpt@30300000 { + gpt4: timer@30300000 { compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; reg = <0x30300000 0x10000>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; @@ -482,7 +482,7 @@ status = "disabled"; }; - kpp: kpp@30320000 { + kpp: keypad@30320000 { compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; reg = <0x30320000 0x10000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; @@ -490,7 +490,7 @@ status = "disabled"; }; - iomuxc: iomuxc@30330000 { + iomuxc: pinctrl@30330000 { compatible = "fsl,imx7d-iomuxc"; reg = <0x30330000 0x10000>; }; @@ -606,13 +606,15 @@ compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs-pwrkey"; linux,keycode = <KEY_POWER>; wakeup-source; status = "disabled"; }; }; - clks: ccm@30380000 { + clks: clock-controller@30380000 { compatible = "fsl,imx7d-ccm"; reg = <0x30380000 0x10000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, @@ -622,7 +624,7 @@ clock-names = "ckil", "osc"; }; - src: src@30390000 { + src: reset-controller@30390000 { compatible = "fsl,imx7d-src", "syscon"; reg = <0x30390000 0x10000>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; @@ -663,7 +665,7 @@ }; }; - aips2: aips-bus@30400000 { + aips2: bus@30400000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -803,7 +805,7 @@ }; }; - aips3: aips-bus@30800000 { + aips3: bus@30800000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -932,7 +934,7 @@ }; }; - crypto: caam@30900000 { + crypto: crypto@30900000 { compatible = "fsl,sec-v4.0"; #address-cells = <1>; #size-cells = <1>; @@ -943,19 +945,19 @@ <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; clock-names = "ipg", "aclk"; - sec_jr0: jr0@1000 { + sec_jr0: jr@1000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; }; - sec_jr1: jr1@2000 { + sec_jr1: jr@2000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x2000 0x1000>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; }; - sec_jr2: jr1@3000 { + sec_jr2: jr@3000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x3000 0x1000>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts index a863a2b337d6..eff51e113db4 100644 --- a/arch/arm/boot/dts/imx7ulp-evk.dts +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -72,7 +72,7 @@ srp-disable; hnp-disable; adp-disable; - over-current-active-low; + disable-over-current; status = "okay"; }; @@ -110,7 +110,6 @@ pinctrl_usbotg1_id: otg1idgrp { fsl,pins = < IMX7ULP_PAD_PTC13__USB0_ID 0x10003 - IMX7ULP_PAD_PTC16__USB1_OC2 0x10003 >; }; diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index ab91c98f2124..f7c4878534c8 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -132,13 +132,13 @@ <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; clock-names = "aclk", "ipg"; - sec_jr0: jr0@1000 { + sec_jr0: jr@1000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; }; - sec_jr1: jr1@2000 { + sec_jr1: jr@2000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x2000 0x1000>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/integratorap-im-pd1.dts b/arch/arm/boot/dts/integratorap-im-pd1.dts new file mode 100644 index 000000000000..1412a1a968fc --- /dev/null +++ b/arch/arm/boot/dts/integratorap-im-pd1.dts @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for the ARM Integrator/AP platform + * with the IM-PD1 example logical module mounted. + */ + +#include "integratorap.dts" + +/ { + model = "ARM Integrator/AP with IM-PD1"; + compatible = "arm,integrator-ap"; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + impd1_ram: vram@c2000000 { + /* 1 MB of designated video RAM on the IM-PD1 */ + compatible = "shared-dma-pool"; + reg = <0xc2000000 0x00100000>; + no-map; + }; + }; +}; + +&lm0 { + syscon@0 { + compatible = "arm,im-pd1-syscon", "syscon"; + reg = <0x00000000 0x1000>; + + vco1: clock@00 { + compatible = "arm,impd1-vco1"; + #clock-cells = <0>; + lock-offset = <0x08>; + vco-offset = <0x00>; + clocks = <&sysclk>; + clock-output-names = "IM-PD1-VCO1"; + }; + + vco2: clock@04 { + compatible = "arm,impd1-vco2"; + #clock-cells = <0>; + lock-offset = <0x08>; + vco-offset = <0x04>; + clocks = <&sysclk>; + clock-output-names = "IM-PD1-VCO2"; + }; + }; + + /* Also used for the Smart Card Interface SCI */ + impd1_uartclk: clock@1_4 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clocks = <&vco2>; + clock-output-names = "VCO2_DIV4"; + }; + + /* For the SSP the clock is divided by 64 */ + impd1_sspclk: clock@1_64 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <64>; + clock-mult = <1>; + clocks = <&vco2>; + clock-output-names = "VCO2_DIV64"; + }; + + /* Fixed regulator for the MMC */ + impd1_3v3: regulator { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* Push buttons on the IM-PD1 */ + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@0 { + debounce-interval = <50>; + linux,code = <KEY_UP>; + label = "UP"; + gpios = <&impd1_gpio1 0 GPIO_ACTIVE_HIGH>; + }; + button@1 { + debounce-interval = <50>; + linux,code = <KEY_DOWN>; + label = "DOWN"; + gpios = <&impd1_gpio1 1 GPIO_ACTIVE_HIGH>; + }; + button@2 { + debounce-interval = <50>; + linux,code = <KEY_LEFT>; + label = "LEFT"; + gpios = <&impd1_gpio1 2 GPIO_ACTIVE_HIGH>; + }; + button@3 { + debounce-interval = <50>; + linux,code = <KEY_RIGHT>; + label = "UP"; + gpios = <&impd1_gpio1 3 GPIO_ACTIVE_HIGH>; + }; + button@4 { + debounce-interval = <50>; + linux,code = <KEY_ESC>; + label = "ESC"; + gpios = <&impd1_gpio1 4 GPIO_ACTIVE_HIGH>; + }; + button@5 { + debounce-interval = <50>; + linux,code = <KEY_ENTER>; + label = "ENTER"; + gpios = <&impd1_gpio1 5 GPIO_ACTIVE_HIGH>; + }; + }; + + + bridge { + compatible = "ti,ths8134b", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads_vga_dac>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + + uart@100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00100000 0x1000>; + interrupts-extended = <&impd1_vic 1>; + clocks = <&impd1_uartclk>, <&sysclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart@200000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00200000 0x1000>; + interrupts-extended = <&impd1_vic 2>; + clocks = <&impd1_uartclk>, <&sysclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + ssp@300000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00300000 0x1000>; + interrupts-extended = <&impd1_vic 3>; + clocks = <&impd1_sspclk>, <&sysclk>; + clock-names = "spiclk", "apb_pclk"; + }; + + impd1_gpio0: gpio@400000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x00400000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = <&impd1_vic 4>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + }; + + impd1_gpio1: gpio@500000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x00500000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = <&impd1_vic 5>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + }; + + rtc@600000 { + compatible = "arm,pl030", "arm,primecell"; + reg = <0x00600000 0x1000>; + interrupts-extended = <&impd1_vic 6>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + }; + + mmc@700000 { + compatible = "arm,pl181", "arm,primecell"; + reg = <0x00700000 0x1000>; + interrupts-extended = <&impd1_vic 7>, + <&impd1_vic 8>; + clocks = <&sysclk>, <&sysclk>; + clock-names = "mclk", "apb_pclk"; + bus-width = <1>; + max-frequency = <515633>; + vmmc-supply = <&impd1_3v3>; + wp-gpios = <&impd1_gpio0 3 GPIO_ACTIVE_HIGH>; + cd-gpios = <&impd1_gpio0 4 GPIO_ACTIVE_LOW>; + }; + + aaci@800000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x00800000 0x1000>; + interrupts-extended = <&impd1_vic 9>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + }; + + display@1000000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0x01000000 0x1000>; + interrupts-extended = <&impd1_vic 11>; + clocks = <&vco1>, <&sysclk>; + clock-names = "clcdclk", "apb_pclk"; + /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */ + max-memory-bandwidth = <40000000>; + memory-region = <&impd1_ram>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + clcd_pads_vga_dac: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_bridge_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; + + impd1_vic: interrupt-controller@3000000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x03000000 0x1000>; + /* Valid interrupts, 0-9 and 11 */ + valid-mask = <0x00000bff>; + /* LM site 0 has IRQ 9 on the PIC */ + interrupts-extended = <&pic 9>; + }; +}; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index 94d2ff9836d0..67d1f9b24a52 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -4,12 +4,13 @@ */ /dts-v1/; -/include/ "integrator.dtsi" +#include "integrator.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> / { model = "ARM Integrator/AP"; compatible = "arm,integrator-ap"; - dma-ranges = <0x80000000 0x0 0x80000000>; cpus { #address-cells = <1>; @@ -108,9 +109,6 @@ syscon { compatible = "arm,integrator-ap-syscon", "syscon"; reg = <0x11000000 0x100>; - interrupt-parent = <&pic>; - /* These are the logical module IRQs */ - interrupts = <9>, <10>, <11>, <12>; /* * SYSCLK clocks PCIv3 bridge, system controller and the @@ -240,4 +238,50 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; }; + + /* + * Logic module bus, we support up to 4 logical modules + * They appear at 0xc0000000, 0xd0000000, 0xe0000000 and 0xf0000000 + * and use interrupts 9, 10, 11 and 12 respectively. + */ + bus@c0000000 { + compatible = "arm,integrator-ap-lm"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc0000000 0xc0000000 0x40000000>; + dma-ranges; + + lm0: bus@c0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xc0000000 0x10000000>; + dma-ranges = <0x00000000 0x80000000 0x10000000>; + reg = <0xc0000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + lm1: bus@d0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xd0000000 0x10000000>; + dma-ranges = <0x00000000 0x80000000 0x10000000>; + reg = <0xd0000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + lm2: bus@e0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xe0000000 0x10000000>; + dma-ranges = <0x00000000 0x80000000 0x10000000>; + reg = <0xe0000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + lm3: bus@f0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xf0000000 0x10000000>; + dma-ranges = <0x00000000 0x80000000 0x10000000>; + reg = <0xf0000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; }; diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi index 085e7326ea8e..2d94faf31fab 100644 --- a/arch/arm/boot/dts/keystone-k2e.dtsi +++ b/arch/arm/boot/dts/keystone-k2e.dtsi @@ -86,14 +86,14 @@ }; }; - msm_ram: msmram@c000000 { + msm_ram: sram@c000000 { compatible = "mmio-sram"; reg = <0x0c000000 0x200000>; ranges = <0x0 0x0c000000 0x200000>; #address-cells = <1>; #size-cells = <1>; - sram-bm@1f0000 { + bm-sram@1f0000 { reg = <0x001f0000 0x8000>; }; }; diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index b7f10bf94576..db640bab8c1d 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -45,6 +45,19 @@ regulator-max-microvolt = <1800000>; regulator-always-on; }; + + hdmi: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; }; &k2g_pinctrl { @@ -89,6 +102,13 @@ >; }; + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + >; + }; + ecap0_pins: ecap0_pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */ @@ -160,6 +180,40 @@ K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ >; }; + + vout_pins: pinmux_vout_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */ + K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */ + K2G_CORE_IOPAD(0x1080) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata21.dssdata21 */ + K2G_CORE_IOPAD(0x1084) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata20.dssdata20 */ + K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata19.dssdata19 */ + K2G_CORE_IOPAD(0x108c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata18.dssdata18 */ + K2G_CORE_IOPAD(0x1090) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata17.dssdata17 */ + K2G_CORE_IOPAD(0x1094) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata16.dssdata16 */ + K2G_CORE_IOPAD(0x1098) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata15.dssdata15 */ + K2G_CORE_IOPAD(0x109c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata14.dssdata14 */ + K2G_CORE_IOPAD(0x10a0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata13.dssdata13 */ + K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata12.dssdata12 */ + K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata11.dssdata11 */ + K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata10.dssdata10 */ + K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata9.dssdata9 */ + K2G_CORE_IOPAD(0x10b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata8.dssdata8 */ + K2G_CORE_IOPAD(0x10b8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata7.dssdata7 */ + K2G_CORE_IOPAD(0x10bc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata6.dssdata6 */ + K2G_CORE_IOPAD(0x10c0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata5.dssdata5 */ + K2G_CORE_IOPAD(0x10c4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata4.dssdata4 */ + K2G_CORE_IOPAD(0x10c8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata3.dssdata3 */ + K2G_CORE_IOPAD(0x10cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata2.dssdata2 */ + K2G_CORE_IOPAD(0x10d0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata1.dssdata1 */ + K2G_CORE_IOPAD(0x10d4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata0.dssdata0 */ + K2G_CORE_IOPAD(0x10d8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssvsync.dssvsync */ + K2G_CORE_IOPAD(0x10dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsshsync.dsshsync */ + K2G_CORE_IOPAD(0x10e0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsspclk.dsspclk */ + K2G_CORE_IOPAD(0x10e4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssde.dssde */ + K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dssfid */ + >; + }; }; &uart0 { @@ -357,3 +411,50 @@ pinctrl-0 = <&emac_pins>; status = "okay"; }; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; + clock-frequency = <400000>; + + sii9022: sii9022@3b { + #sound-dai-cells = <0>; + compatible = "sil,sii9022"; + reg = <0x3b>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&vout_pins>; + status = "ok"; + + port { + dpi_out: endpoint { + remote-endpoint = <&sii9022_in>; + data-lines = <24>; + }; + }; +}; diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 1c833105d6c5..05a75019275e 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -95,14 +95,14 @@ ranges = <0x0 0x0 0x0 0xc0000000>; dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; - msm_ram: msmram@c000000 { + msm_ram: sram@c000000 { compatible = "mmio-sram"; reg = <0x0c000000 0x100000>; ranges = <0x0 0x0c000000 0x100000>; #address-cells = <1>; #size-cells = <1>; - sram-bm@f7000 { + bm-sram@f7000 { reg = <0x000f7000 0x8000>; }; }; @@ -324,6 +324,28 @@ clock-names = "gpio"; }; + dss: dss@02540000 { + compatible = "ti,k2g-dss"; + reg = <0x02540000 0x400>, + <0x02550000 0x1000>, + <0x02557000 0x1000>, + <0x0255a800 0x100>, + <0x0255ac00 0x100>; + reg-names = "cfg", "common", "vid1", "ovr1", "vp1"; + clocks = <&k2g_clks 0x2 0>, + <&k2g_clks 0x2 1>; + clock-names = "fck", "vp1"; + interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>; + + power-domains = <&k2g_pds 0x2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + max-memory-bandwidth = <230000000>; + }; + edma0: edma@2700000 { compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; reg = <0x02700000 0x8000>; diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi index ca0f198ba627..8a9447703310 100644 --- a/arch/arm/boot/dts/keystone-k2hk.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk.dtsi @@ -57,14 +57,14 @@ &soc0 { /include/ "keystone-k2hk-clocks.dtsi" - msm_ram: msmram@c000000 { + msm_ram: sram@c000000 { compatible = "mmio-sram"; reg = <0x0c000000 0x600000>; ranges = <0x0 0x0c000000 0x600000>; #address-cells = <1>; #size-cells = <1>; - sram-bm@5f0000 { + bm-sram@5f0000 { reg = <0x5f0000 0x8000>; }; }; diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi index 374c80124c4e..dff5fea72b2f 100644 --- a/arch/arm/boot/dts/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/keystone-k2l.dtsi @@ -255,14 +255,14 @@ }; }; - msm_ram: msmram@c000000 { + msm_ram: sram@c000000 { compatible = "mmio-sram"; reg = <0x0c000000 0x200000>; ranges = <0x0 0x0c000000 0x200000>; #address-cells = <1>; #size-cells = <1>; - sram-bm@1f8000 { + bm-sram@1f8000 { reg = <0x001f8000 0x8000>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-l-50.dts b/arch/arm/boot/dts/kirkwood-l-50.dts new file mode 100644 index 000000000000..0d81c43a6a73 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-l-50.dts @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Check Point L-50 Board Description + * Copyright 2020 Pawel Dembicki <paweldembicki@gmail.com> + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Check Point L-50"; + compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>; + pinctrl-names = "default"; + + pmx_sysrst: pmx-sysrst { + marvell,pins = "mpp6"; + marvell,function = "sysrst"; + }; + + pmx_button29: pmx_button29 { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led38: pmx_led38 { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + mvsdio@90000 { + status = "okay"; + cd-gpios = <&gpio1 14 9>; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <400000>; + + gpio2: gpio-expander@20{ + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1505q"; + reg = <0x20>; + + gpio-controller; + }; + + /* Three GPIOs from 0x21 exp. are undescribed in dts: + * 1: DSL module reset (active low) + * 5: mPCIE reset (active low) + * 6: Express card reset (active low) + */ + gpio3: gpio-expander@21{ + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1505q"; + reg = <0x21>; + + gpio-controller; + }; + + rtc@30 { + compatible = "s35390a"; + reg = <0x30>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + status_green { + label = "l-50:green:status"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + status_red { + label = "l-50:red:status"; + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + }; + + wifi { + label = "l-50:green:wifi"; + gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + internet_green { + label = "l-50:green:internet"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + }; + + internet_red { + label = "l-50:red:internet"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + usb1_green { + label = "l-50:green:usb1"; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port3>; + }; + + usb1_red { + label = "l-50:red:usb1"; + gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + }; + + usb2_green { + label = "l-50:green:usb2"; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port1>; + }; + + usb2_red { + label = "l-50:red:usb2"; + gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + }; + }; + + usb2_pwr { + compatible = "regulator-fixed"; + regulator-name = "usb2_pwr"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + usb1_pwr { + compatible = "regulator-fixed"; + regulator-name = "usb1_pwr"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + mpcie_pwr { + compatible = "regulator-fixed"; + regulator-name = "mpcie_pwr"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + express_card_pwr { + compatible = "regulator-fixed"; + regulator-name = "express_card_pwr"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + keys { + compatible = "gpio-keys"; + + factory_defaults { + label = "factory_defaults"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RESTART>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy8: ethernet-phy@8 { + reg = <0x08>; + }; + + switch0: switch@10 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + dsa,member = <0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan5"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan6"; + }; + + port@3 { + reg = <3>; + label = "lan2"; + }; + + port@4 { + reg = <4>; + label = "lan7"; + }; + + switch0port5: port@5 { + reg = <5>; + phy-mode = "rgmii-txid"; + link = <&switch1port5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + label = "cpu"; + phy-mode = "rgmii-id"; + ethernet = <ð1port>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + switch@11 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11>; + dsa,member = <0 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan3"; + }; + + port@1 { + reg = <1>; + label = "lan8"; + }; + + port@2 { + reg = <2>; + label = "lan4"; + }; + + port@3 { + reg = <3>; + label = "dmz"; + }; + + switch1port5: port@5 { + reg = <5>; + phy-mode = "rgmii-txid"; + link = <&switch0port5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + label = "dsl"; + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy8>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + speed = <1000>; + duplex = <1>; + }; +}; + +&nand { + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x000c0000>; + }; + + partition@a0000 { + label = "bootldr-env"; + reg = <0x000c0000 0x00040000>; + }; + + partition@100000 { + label = "kernel-1"; + reg = <0x00100000 0x00800000>; + }; + + partition@900000 { + label = "rootfs-1"; + reg = <0x00900000 0x07100000>; + }; + + partition@7a00000 { + label = "kernel-2"; + reg = <0x07a00000 0x00800000>; + }; + + partition@8200000 { + label = "rootfs-2"; + reg = <0x08200000 0x07100000>; + }; + + partition@f300000 { + label = "default_sw"; + reg = <0x0f300000 0x07900000>; + }; + + partition@16c00000 { + label = "logs"; + reg = <0x16c00000 0x01800000>; + }; + + partition@18400000 { + label = "preset_cfg"; + reg = <0x18400000 0x00100000>; + }; + + partition@18500000 { + label = "adsl"; + reg = <0x18500000 0x00100000>; + }; + + partition@18600000 { + label = "storage"; + reg = <0x18600000 0x07a00000>; + }; +}; + +&rtc { + status = "disabled"; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&sata_phy0 { + status = "disabled"; +}; + +&sata_phy1 { + status = "disabled"; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + #trigger-source-cells = <0>; + + hub_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + hub_port3: port@3 { + reg = <3>; + #trigger-source-cells = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts index 8cc8550242ef..b13aee570804 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts @@ -113,6 +113,20 @@ }; }; + auxdisplay { + compatible = "hit,hd44780"; + data-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>, + <&gpio1 1 GPIO_ACTIVE_HIGH>, + <&gpio1 3 GPIO_ACTIVE_HIGH>, + <&gpio1 17 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + rs-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + rw-gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + backlight-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + display-height-chars = <2>; + display-width-chars = <16>; + }; + gpio-leds { compatible = "gpio-leds"; pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_backup diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 2161e23bd98e..6c8d94beae78 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -228,7 +228,7 @@ reg = <0x20128 0x4>; }; - intc: main-interrupt-ctrl@20200 { + intc: interrupt-controller@20200 { compatible = "marvell,orion-intc"; interrupt-controller; #interrupt-cells = <1>; diff --git a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi index f7b82ced4080..381f0e82bb70 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi +++ b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi @@ -65,6 +65,7 @@ pinctrl-0 = <&pwm_pins>; ti,timers = <&timer10>; #pwm-cells = <3>; + ti,clock-source = <0x01>; }; }; diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts index 9b1fe99d55b1..5edf001f6138 100644 --- a/arch/arm/boot/dts/ls1021a-twr.dts +++ b/arch/arm/boot/dts/ls1021a-twr.dts @@ -242,6 +242,20 @@ status = "okay"; }; +&qspi { + status = "okay"; + + n25q128a130: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + &sai1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 0855b1fe98e0..760a68c163c8 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -747,7 +747,7 @@ }; mdio0: mdio@2d24000 { - compatible = "fsl,etsec2-mdio"; + compatible = "gianfar"; device_type = "mdio"; #address-cells = <1>; #size-cells = <0>; @@ -756,7 +756,7 @@ }; mdio1: mdio@2d64000 { - compatible = "fsl,etsec2-mdio"; + compatible = "gianfar"; device_type = "mdio"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 5d198309058a..ae89deaa8c9c 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -229,6 +229,9 @@ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb0_phy>; phy-names = "usb2-phy"; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <500>; + g-tx-fifo-size = <256 192 128 128 128>; dr_mode = "host"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index a2a47804fc4a..cb21ac9f517c 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -202,9 +202,8 @@ pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; - phy-mode = "rgmii"; phy-handle = <ð_phy>; - amlogic,tx-delay-ns = <4>; + phy-mode = "rgmii-id"; nvmem-cells = <ðernet_mac_address>; nvmem-cell-names = "mac-address"; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index e34b039b9357..ba36168b9c1b 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -425,8 +425,9 @@ clocks = <&clkc CLKID_ETH>, <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; rx-fifo-depth = <4096>; tx-fifo-depth = <2048>; diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts index d54477b1001c..cc498191ddd1 100644 --- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts +++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts @@ -69,9 +69,7 @@ pinctrl-names = "default"; phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <4>; + phy-mode = "rgmii-id"; mdio { compatible = "snps,dwmac-mdio"; diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index 5bde7f502007..2397ba06d608 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -30,8 +30,9 @@ 0xc1108140 0x8>; clocks = <&clkc CLKID_ETH>, <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; resets = <&reset RESET_ETHERNET>; reset-names = "stmmaceth"; }; @@ -64,6 +65,14 @@ compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; }; +&usb0_phy { + compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; +}; + +&usb1_phy { + compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; +}; + &wdt { compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt"; }; diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts index aaedc4c742ea..04f1ae1382e7 100644 --- a/arch/arm/boot/dts/mmp2-brownstone.dts +++ b/arch/arm/boot/dts/mmp2-brownstone.dts @@ -19,176 +19,174 @@ device_type = "memory"; reg = <0x00000000 0x08000000>; }; +}; + +&uart3 { + status = "okay"; +}; - soc { - apb@d4000000 { - uart3: uart@d4018000 { - status = "okay"; - }; - twsi1: i2c@d4011000 { - status = "okay"; - pmic: max8925@3c { - compatible = "maxium,max8925"; - reg = <0x3c>; - interrupts = <1>; - interrupt-parent = <&intcmux4>; - interrupt-controller; - #interrupt-cells = <1>; - maxim,tsc-irq = <0>; +&twsi1 { + status = "okay"; + pmic: max8925@3c { + compatible = "maxium,max8925"; + reg = <0x3c>; + interrupts = <1>; + interrupt-parent = <&intcmux4>; + interrupt-controller; + #interrupt-cells = <1>; + maxim,tsc-irq = <0>; - regulators { - SDV1 { - regulator-min-microvolt = <637500>; - regulator-max-microvolt = <1425000>; - regulator-boot-on; - regulator-always-on; - }; - SDV2 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2225000>; - regulator-boot-on; - regulator-always-on; - }; - SDV3 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO1 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO2 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO3 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO4 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO5 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO6 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO7 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO8 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO9 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO10 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - }; - LDO11 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO12 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO13 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO14 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO15 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO16 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO17 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO18 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO19 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO20 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - }; - backlight { - maxim,max8925-dual-string = <0>; - }; - charger { - batt-detect = <0>; - topoff-threshold = <1>; - fast-charge = <7>; - no-temp-support = <0>; - no-insert-detect = <0>; - }; - }; - }; - rtc: rtc@d4010000 { - status = "okay"; + regulators { + SDV1 { + regulator-min-microvolt = <637500>; + regulator-max-microvolt = <1425000>; + regulator-boot-on; + regulator-always-on; + }; + SDV2 { + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2225000>; + regulator-boot-on; + regulator-always-on; + }; + SDV3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO1 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO2 { + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2250000>; + regulator-boot-on; + regulator-always-on; + }; + LDO3 { + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2250000>; + regulator-boot-on; + regulator-always-on; + }; + LDO4 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO5 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO6 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO7 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO8 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO9 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO10 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; }; + LDO11 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO12 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO13 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO14 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO15 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO16 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO17 { + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2250000>; + regulator-boot-on; + regulator-always-on; + }; + LDO18 { + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2250000>; + regulator-boot-on; + regulator-always-on; + }; + LDO19 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO20 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3900000>; + regulator-boot-on; + regulator-always-on; + }; + }; + backlight { + maxim,max8925-dual-string = <0>; + }; + charger { + batt-detect = <0>; + topoff-threshold = <1>; + fast-charge = <7>; + no-temp-support = <0>; + no-insert-detect = <0>; }; }; }; + +&rtc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index 6a2f072c1d0a..4306f3a6742b 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -208,8 +208,8 @@ clocks = <&soc_clocks MMP2_CLK_TIMER>; }; - uart1: uart@d4030000 { - compatible = "mrvl,mmp-uart"; + uart1: serial@d4030000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4030000 0x1000>; interrupts = <27>; clocks = <&soc_clocks MMP2_CLK_UART0>; @@ -218,8 +218,8 @@ status = "disabled"; }; - uart2: uart@d4017000 { - compatible = "mrvl,mmp-uart"; + uart2: serial@d4017000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4017000 0x1000>; interrupts = <28>; clocks = <&soc_clocks MMP2_CLK_UART1>; @@ -228,8 +228,8 @@ status = "disabled"; }; - uart3: uart@d4018000 { - compatible = "mrvl,mmp-uart"; + uart3: serial@d4018000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4018000 0x1000>; interrupts = <24>; clocks = <&soc_clocks MMP2_CLK_UART2>; @@ -238,8 +238,8 @@ status = "disabled"; }; - uart4: uart@d4016000 { - compatible = "mrvl,mmp-uart"; + uart4: serial@d4016000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4016000 0x1000>; interrupts = <46>; clocks = <&soc_clocks MMP2_CLK_UART3>; @@ -364,7 +364,7 @@ rtc: rtc@d4010000 { compatible = "mrvl,mmp-rtc"; reg = <0xd4010000 0x1000>; - interrupts = <1 0>; + interrupts = <1>, <0>; interrupt-names = "rtc 1Hz", "rtc alarm"; interrupt-parent = <&intcmux5>; clocks = <&soc_clocks MMP2_CLK_RTC>; diff --git a/arch/arm/boot/dts/mmp3-dell-ariel.dts b/arch/arm/boot/dts/mmp3-dell-ariel.dts index 15449c72c042..b0ec14c42164 100644 --- a/arch/arm/boot/dts/mmp3-dell-ariel.dts +++ b/arch/arm/boot/dts/mmp3-dell-ariel.dts @@ -98,19 +98,19 @@ status = "okay"; }; -&ssp3 { +&ssp1 { status = "okay"; - cs-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; firmware-flash@0 { - compatible = "st,m25p80", "jedec,spi-nor"; + compatible = "winbond,w25q32", "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <40000000>; + spi-max-frequency = <104000000>; m25p,fast-read; }; }; -&ssp4 { - cs-gpios = <&gpio 56 GPIO_ACTIVE_HIGH>; +&ssp2 { + cs-gpios = <&gpio 56 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/mmp3.dtsi index 59a108e49b41..57231d49d938 100644 --- a/arch/arm/boot/dts/mmp3.dtsi +++ b/arch/arm/boot/dts/mmp3.dtsi @@ -183,14 +183,14 @@ mrvl,intc-nr-irqs = <5>; }; - usb_otg_phy0: usb-otg-phy@d4207000 { + usb_otg_phy0: usb-phy@d4207000 { compatible = "marvell,mmp3-usb-phy"; reg = <0xd4207000 0x40>; #phy-cells = <0>; status = "disabled"; }; - usb_otg0: usb-otg@d4208000 { + usb_otg0: usb@d4208000 { compatible = "marvell,pxau2o-ehci"; reg = <0xd4208000 0x200>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; @@ -201,15 +201,14 @@ status = "disabled"; }; - hsic_phy0: hsic-phy@f0001800 { - compatible = "marvell,mmp3-hsic-phy", - "usb-nop-xceiv"; + hsic_phy0: usb-phy@f0001800 { + compatible = "marvell,mmp3-hsic-phy"; reg = <0xf0001800 0x40>; #phy-cells = <0>; status = "disabled"; }; - hsic0: hsic@f0001000 { + hsic0: usb@f0001000 { compatible = "marvell,pxau2o-ehci"; reg = <0xf0001000 0x200>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; @@ -223,15 +222,14 @@ status = "disabled"; }; - hsic_phy1: hsic-phy@f0002800 { - compatible = "marvell,mmp3-hsic-phy", - "usb-nop-xceiv"; + hsic_phy1: usb-phy@f0002800 { + compatible = "marvell,mmp3-hsic-phy"; reg = <0xf0002800 0x40>; #phy-cells = <0>; status = "disabled"; }; - hsic1: hsic@f0002000 { + hsic1: usb@f0002000 { compatible = "marvell,pxau2o-ehci"; reg = <0xf0002000 0x200>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; @@ -281,6 +279,16 @@ status = "disabled"; }; + mmc5: mmc@d4217000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4217000 0x120>; + clocks = <&soc_clocks MMP3_CLK_SDH4>; + clock-names = "io"; + interrupt-parent = <&hsi1_mux>; + interrupts = <0>; + status = "disabled"; + }; + camera0: camera@d420a000 { compatible = "marvell,mmp2-ccic"; reg = <0xd420a000 0x800>; @@ -318,8 +326,8 @@ clocks = <&soc_clocks MMP2_CLK_TIMER>; }; - uart1: uart@d4030000 { - compatible = "mrvl,mmp-uart"; + uart1: serial@d4030000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4030000 0x1000>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&soc_clocks MMP2_CLK_UART0>; @@ -328,8 +336,8 @@ status = "disabled"; }; - uart2: uart@d4017000 { - compatible = "mrvl,mmp-uart"; + uart2: serial@d4017000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4017000 0x1000>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&soc_clocks MMP2_CLK_UART1>; @@ -338,8 +346,8 @@ status = "disabled"; }; - uart3: uart@d4018000 { - compatible = "mrvl,mmp-uart"; + uart3: serial@d4018000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4018000 0x1000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&soc_clocks MMP2_CLK_UART2>; @@ -348,8 +356,8 @@ status = "disabled"; }; - uart4: uart@d4016000 { - compatible = "mrvl,mmp-uart"; + uart4: serial@d4016000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4016000 0x1000>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; clocks = <&soc_clocks MMP2_CLK_UART3>; @@ -474,7 +482,7 @@ rtc: rtc@d4010000 { compatible = "mrvl,mmp-rtc"; reg = <0xd4010000 0x1000>; - interrupts = <1 0>; + interrupts = <1>, <0>; interrupt-names = "rtc 1Hz", "rtc alarm"; interrupt-parent = <&rtc_mux>; clocks = <&soc_clocks MMP2_CLK_RTC>; @@ -523,7 +531,7 @@ }; }; - l2: l2-cache-controller@d0020000 { + l2: cache-controller@d0020000 { compatible = "marvell,tauros3-cache", "arm,pl310-cache"; reg = <0xd0020000 0x1000>; cache-unified; @@ -531,7 +539,7 @@ }; soc_clocks: clocks@d4050000 { - compatible = "marvell,mmp2-clock"; + compatible = "marvell,mmp3-clock"; reg = <0xd4050000 0x1000>, <0xd4282800 0x400>, <0xd4015000 0x1000>; diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi index 85665506f4f8..9067e0ef4240 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi @@ -182,6 +182,14 @@ pwm-names = "enable", "direction"; direction-duty-cycle-ns = <10000000>; }; + + backlight: backlight { + compatible = "led-backlight"; + + leds = <&backlight_led>; + brightness-levels = <31 63 95 127 159 191 223 255>; + default-brightness-level = <6>; + }; }; &dss { @@ -205,6 +213,8 @@ vddi-supply = <&lcd_regulator>; reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ + backlight = <&backlight>; + width-mm = <50>; height-mm = <89>; @@ -393,12 +403,11 @@ ramp-up-us = <1024>; ramp-down-us = <8193>; - led@0 { + backlight_led: led@0 { reg = <0>; led-sources = <2>; ti,led-mode = <0>; label = ":backlight"; - linux,default-trigger = "backlight"; }; led@1 { @@ -420,7 +429,7 @@ reset-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio173 */ /* gpio_183 with sys_nirq2 pad as wakeup */ - interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_FALLING>, + interrupts-extended = <&gpio6 23 IRQ_TYPE_LEVEL_LOW>, <&omap4_pmx_core 0x160>; interrupt-names = "irq", "wakeup"; wakeup-source; diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts index 88f8fd22302a..d1535f385f36 100644 --- a/arch/arm/boot/dts/mt2701-evb.dts +++ b/arch/arm/boot/dts/mt2701-evb.dts @@ -6,6 +6,7 @@ */ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include "mt2701.dtsi" / { @@ -61,6 +62,15 @@ >; default-brightness-level = <9>; }; + + usb_vbus: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 45 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &auxadc { @@ -230,3 +240,14 @@ &uart0 { status = "okay"; }; + +&usb2 { + status = "okay"; + usb-role-switch; + connector{ + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb_vbus>; + }; +}; diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 51e1305c6471..39b3a2f4bef4 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -148,7 +148,7 @@ reg = <0 0x10005000 0 0x1000>; }; - scpsys: scpsys@10006000 { + scpsys: power-controller@10006000 { compatible = "mediatek,mt2701-scpsys", "syscon"; #power-domain-cells = <1>; reg = <0 0x10006000 0 0x1000>; @@ -671,6 +671,39 @@ }; }; + usb2: usb@11200000 { + compatible = "mediatek,mt2701-musb", + "mediatek,mtk-musb"; + reg = <0 0x11200000 0 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "mc"; + phys = <&u2port2 PHY_TYPE_USB2>; + dr_mode = "otg"; + clocks = <&pericfg CLK_PERI_USB0>, + <&pericfg CLK_PERI_USB0_MCU>, + <&pericfg CLK_PERI_USB_SLV>; + clock-names = "main","mcu","univpll"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; + status = "disabled"; + }; + + u2phy0: usb-phy@11210000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0 0x11210000 0 0x0800>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "okay"; + + u2port2: usb-phy@1a1c4800 { + reg = <0 0x11210800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt2701-ethsys", "syscon"; reg = <0 0x1b000000 0 0x1000>; diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index a79f0b6c3429..3a6b856e5b74 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2017-2018 MediaTek Inc. * Author: John Crispin <john@phrozen.org> * Sean Wang <sean.wang@mediatek.com> + * Ryder Lee <ryder.lee@mediatek.com> * */ @@ -268,7 +269,7 @@ reg = <0 0x10005000 0 0x1000>; }; - scpsys: scpsys@10006000 { + scpsys: power-controller@10006000 { compatible = "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys", "syscon"; @@ -733,6 +734,30 @@ #reset-cells = <1>; }; + mali: gpu@13040000 { + compatible = "mediatek,mt7623-mali", "arm,mali-450"; + reg = <0 0x13040000 0 0x30000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", + "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3", + "pp"; + clocks = <&topckgen CLK_TOP_MMPLL>, + <&g3dsys CLK_G3DSYS_CORE>; + clock-names = "bus", "core"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>; + resets = <&g3dsys MT2701_G3DSYS_CORE_RST>; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts index b7606130ade9..0447748f9fa0 100644 --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts @@ -138,6 +138,7 @@ mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; + phy-mode = "rgmii"; phy-handle = <&phy5>; }; diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi index 867b88103b9d..5cbb3d244c75 100644 --- a/arch/arm/boot/dts/mt7629.dtsi +++ b/arch/arm/boot/dts/mt7629.dtsi @@ -90,7 +90,7 @@ #clock-cells = <1>; }; - scpsys: scpsys@10006000 { + scpsys: power-controller@10006000 { compatible = "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys"; #power-domain-cells = <1>; @@ -241,6 +241,20 @@ status = "disabled"; }; + pwm: pwm@11006000 { + compatible = "mediatek,mt7629-pwm"; + reg = <0x11006000 0x1000>; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&pericfg CLK_PERI_PWM_PD>, + <&pericfg CLK_PERI_PWM1_PD>; + clock-names = "top", "main", "pwm1"; + assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>; + assigned-clock-parents = + <&topckgen CLK_TOP_UNIVPLL2_D4>; + status = "disabled"; + }; + i2c: i2c@11007000 { compatible = "mediatek,mt7629-i2c", "mediatek,mt2712-i2c"; diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 409a758c99f1..ecc45862b4f3 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -150,6 +150,7 @@ compatible = "ti,omap-dmtimer-pwm"; ti,timers = <&timer11>; #pwm-cells = <3>; + ti,clock-source = <0x01>; }; hsusb2_phy: hsusb2_phy { diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index c3c6d7d04a76..4089d97405c9 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -854,34 +854,46 @@ compatible = "ti,omap2-onenand"; reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ + /* + * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported + * bootloader set values when booted with v5.1 + * (OneNAND Manufacturer: Samsung): + * + * cs0 GPMC_CS_CONFIG1: 0xfb001202 + * cs0 GPMC_CS_CONFIG2: 0x00111100 + * cs0 GPMC_CS_CONFIG3: 0x00020200 + * cs0 GPMC_CS_CONFIG4: 0x11001102 + * cs0 GPMC_CS_CONFIG5: 0x03101616 + * cs0 GPMC_CS_CONFIG6: 0x90060000 + */ gpmc,sync-read; gpmc,sync-write; gpmc,burst-length = <16>; gpmc,burst-read; gpmc,burst-wrap; gpmc,burst-write; - gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ - gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */ + gpmc,device-width = <2>; + gpmc,mux-add-data = <2>; gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <87>; - gpmc,cs-wr-off-ns = <87>; + gpmc,cs-rd-off-ns = <102>; + gpmc,cs-wr-off-ns = <102>; gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <10>; - gpmc,adv-wr-off-ns = <10>; - gpmc,oe-on-ns = <15>; - gpmc,oe-off-ns = <87>; + gpmc,adv-rd-off-ns = <12>; + gpmc,adv-wr-off-ns = <12>; + gpmc,oe-on-ns = <12>; + gpmc,oe-off-ns = <102>; gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <87>; - gpmc,rd-cycle-ns = <112>; - gpmc,wr-cycle-ns = <112>; - gpmc,access-ns = <81>; - gpmc,page-burst-access-ns = <15>; + gpmc,we-off-ns = <102>; + gpmc,rd-cycle-ns = <132>; + gpmc,wr-cycle-ns = <132>; + gpmc,access-ns = <96>; + gpmc,page-burst-access-ns = <18>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,wait-monitoring-ns = <0>; - gpmc,clk-activation-ns = <5>; - gpmc,wr-data-mux-bus-ns = <30>; - gpmc,wr-access-ns = <81>; + gpmc,clk-activation-ns = <6>; + gpmc,wr-data-mux-bus-ns = <36>; + gpmc,wr-access-ns = <96>; gpmc,sync-clk-ps = <15000>; /* diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index a075b63f3087..11d41e86f814 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -341,6 +341,11 @@ status = "disabled"; }; +/* RNG not directly accessible on N950/N9. */ +&rng_target { + status = "disabled"; +}; + &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index 459fd7027591..ef59e4e97d7c 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -1529,6 +1529,7 @@ }; }; + /* Unused DSS L4 access, see L3 instead */ target-module@40000 { /* 0x48040000, ap 13 0a.0 */ compatible = "ti,sysc"; status = "disabled"; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 9a87440d0b9d..763bdea8c829 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -108,7 +108,6 @@ dsp { compatible = "ti,omap3-c64"; - ti,hwmods = "dsp"; }; iva { @@ -415,87 +414,213 @@ */ }; - dss: dss@58000000 { - compatible = "ti,omap4-dss"; - reg = <0x58000000 0x80>; - status = "disabled"; - ti,hwmods = "dss_core"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; + /* + * DSS is only using l3 mapping without l4 as noted in the TRM + * "10.1.3 DSS Register Manual" for omap4460. + */ + target-module@58000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x58000000 4>, + <0x58000014 4>; + reg-names = "rev", "syss"; + ti,syss-mask = <1>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>; + clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; #address-cells = <1>; #size-cells = <1>; - ranges; - - dispc@58001000 { - compatible = "ti,omap4-dispc"; - reg = <0x58001000 0x1000>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "dss_dispc"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; - }; - - rfbi: encoder@58002000 { - compatible = "ti,omap4-rfbi"; - reg = <0x58002000 0x1000>; - status = "disabled"; - ti,hwmods = "dss_rfbi"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>; - clock-names = "fck", "ick"; - }; + ranges = <0 0x58000000 0x1000000>; - venc: encoder@58003000 { - compatible = "ti,omap4-venc"; - reg = <0x58003000 0x1000>; + dss: dss@0 { + compatible = "ti,omap4-dss"; + reg = <0 0x80>; status = "disabled"; - ti,hwmods = "dss_venc"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; - }; - - dsi1: encoder@58004000 { - compatible = "ti,omap4-dsi"; - reg = <0x58004000 0x200>, - <0x58004200 0x40>, - <0x58004300 0x20>; - reg-names = "proto", "phy", "pll"; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - ti,hwmods = "dss_dsi1"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, - <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - }; - - dsi2: encoder@58005000 { - compatible = "ti,omap4-dsi"; - reg = <0x58005000 0x200>, - <0x58005200 0x40>, - <0x58005300 0x20>; - reg-names = "proto", "phy", "pll"; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - ti,hwmods = "dss_dsi2"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, - <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - }; - - hdmi: encoder@58006000 { - compatible = "ti,omap4-hdmi"; - reg = <0x58006000 0x200>, - <0x58006200 0x100>, - <0x58006300 0x100>, - <0x58006400 0x1000>; - reg-names = "wp", "pll", "phy", "core"; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - ti,hwmods = "dss_hdmi"; - clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, - <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - dmas = <&sdma 76>; - dma-names = "audio_tx"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000000>; + + target-module@1000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x1000 0x4>, + <0x1010 0x4>, + <0x1014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; + clock-names = "fck", "sys_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000 0x1000>; + + dispc@0 { + compatible = "ti,omap4-dispc"; + reg = <0 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; + clock-names = "fck"; + }; + }; + + target-module@2000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x2000 0x4>, + <0x2010 0x4>, + <0x2014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; + clock-names = "fck", "sys_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x1000>; + + rfbi: encoder@0 { + reg = <0 0x1000>; + status = "disabled"; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>; + clock-names = "fck", "ick"; + }; + }; + + target-module@3000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x3000 0x4>; + reg-names = "rev"; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; + clock-names = "sys_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x3000 0x1000>; + + venc: encoder@0 { + compatible = "ti,omap4-venc"; + reg = <0 0x1000>; + status = "disabled"; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>; + clock-names = "fck"; + }; + }; + + target-module@4000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4000 0x4>, + <0x4010 0x4>, + <0x4014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4000 0x1000>; + + dsi1: encoder@0 { + compatible = "ti,omap4-dsi"; + reg = <0 0x200>, + <0x200 0x40>, + <0x300 0x20>; + reg-names = "proto", "phy", "pll"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; + clock-names = "fck", "sys_clk"; + }; + }; + + target-module@5000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x5000 0x4>, + <0x5010 0x4>, + <0x5014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5000 0x1000>; + + dsi2: encoder@0 { + compatible = "ti,omap4-dsi"; + reg = <0 0x200>, + <0x200 0x40>, + <0x300 0x20>; + reg-names = "proto", "phy", "pll"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; + clock-names = "fck", "sys_clk"; + }; + }; + + target-module@6000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x6000 0x4>, + <0x6010 0x4>; + reg-names = "rev", "sysc"; + /* + * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP + * but HDMI audio will fail with them. + */ + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>; + ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>; + clock-names = "fck", "dss_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x6000 0x2000>; + + hdmi: encoder@0 { + compatible = "ti,omap4-hdmi"; + reg = <0 0x200>, + <0x200 0x100>, + <0x300 0x100>, + <0x400 0x1000>; + reg-names = "wp", "pll", "phy", "core"; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, + <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; + clock-names = "fck", "sys_clk"; + dmas = <&sdma 76>; + dma-names = "audio_tx"; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/omap5-l4-abe.dtsi b/arch/arm/boot/dts/omap5-l4-abe.dtsi index 4ec7909df78b..bafd6adf9f45 100644 --- a/arch/arm/boot/dts/omap5-l4-abe.dtsi +++ b/arch/arm/boot/dts/omap5-l4-abe.dtsi @@ -426,8 +426,20 @@ }; target-module@f1000 { /* 0x401f1000, ap 32 20.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xf1000 0x4>, + <0xf1010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */ + clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xf1000 0x1000>, diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index f68740abb8aa..55999655a3bc 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -1003,6 +1003,7 @@ <0x00090000 0x00090000 0x002000>, /* ap 55 */ <0x00092000 0x00092000 0x001000>, /* ap 56 */ <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ + <0x000a5000 0x000a5000 0x001000>, <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ @@ -1908,6 +1909,36 @@ <0x00001000 0x000a5000 0x00001000>; }; + des_target: target-module@a5000 { /* 0x480a5000 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xa5030 0x4>, + <0xa5034 0x4>, + <0xa5038 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_DES3DES_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa5000 0x00001000>; + status = "disabled"; + + des: des@0 { + compatible = "ti,omap4-des"; + reg = <0 0xa0>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 117>, <&sdma 116>; + dma-names = "tx", "rx"; + }; + }; + target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */ compatible = "ti,sysc"; status = "disabled"; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index d0ecf54d5a23..5e74f441c7e5 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -143,6 +143,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xc0000000>; + dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; reg = <0 0x44000000 0 0x2000>, <0 0x44800000 0 0x3000>, @@ -246,6 +247,92 @@ hw-caps-temp-alert; }; + aes1_target: target-module@4b501000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4b501080 0x4>, + <0x4b501084 0x4>, + <0x4b501088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b501000 0x1000>; + + aes1: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 111>, <&sdma 110>; + dma-names = "tx", "rx"; + }; + }; + + aes2_target: target-module@4b701000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4b701080 0x4>, + <0x4b701084 0x4>, + <0x4b701088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b701000 0x1000>; + + aes2: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 114>, <&sdma 113>; + dma-names = "tx", "rx"; + }; + }; + + sham_target: target-module@4b100000 { + compatible = "ti,sysc-omap3-sham", "ti,sysc"; + reg = <0x4b100100 0x4>, + <0x4b100110 0x4>, + <0x4b100114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b100000 0x1000>; + + sham: sham@0 { + compatible = "ti,omap4-sham"; + reg = <0 0x300>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 119>; + dma-names = "rx"; + }; + }; + bandgap: bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc @@ -292,78 +379,185 @@ */ }; - dss: dss@58000000 { - compatible = "ti,omap5-dss"; - reg = <0x58000000 0x80>; - status = "disabled"; - ti,hwmods = "dss_core"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; - clock-names = "fck"; + target-module@58000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x58000000 4>, + <0x58000014 4>; + reg-names = "rev", "syss"; + ti,syss-mask = <1>; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>, + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>, + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>; + clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0 0x58000000 0x1000000>; - dispc@58001000 { - compatible = "ti,omap5-dispc"; - reg = <0x58001000 0x1000>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "dss_dispc"; + dss: dss@0 { + compatible = "ti,omap5-dss"; + reg = <0 0x80>; + status = "disabled"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; - }; - - rfbi: encoder@58002000 { - compatible = "ti,omap5-rfbi"; - reg = <0x58002000 0x100>; - status = "disabled"; - ti,hwmods = "dss_rfbi"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>; - clock-names = "fck", "ick"; - }; - - dsi1: encoder@58004000 { - compatible = "ti,omap5-dsi"; - reg = <0x58004000 0x200>, - <0x58004200 0x40>, - <0x58004300 0x40>; - reg-names = "proto", "phy", "pll"; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - ti,hwmods = "dss_dsi1"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - }; - - dsi2: encoder@58005000 { - compatible = "ti,omap5-dsi"; - reg = <0x58009000 0x200>, - <0x58009200 0x40>, - <0x58009300 0x40>; - reg-names = "proto", "phy", "pll"; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - ti,hwmods = "dss_dsi2"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - }; - - hdmi: encoder@58060000 { - compatible = "ti,omap5-hdmi"; - reg = <0x58040000 0x200>, - <0x58040200 0x80>, - <0x58040300 0x80>, - <0x58060000 0x19000>; - reg-names = "wp", "pll", "phy", "core"; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - ti,hwmods = "dss_hdmi"; - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; - clock-names = "fck", "sys_clk"; - dmas = <&sdma 76>; - dma-names = "audio_tx"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000000>; + + target-module@1000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x1000 0x4>, + <0x1010 0x4>, + <0x1014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000 0x1000>; + + dispc@0 { + compatible = "ti,omap5-dispc"; + reg = <0 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; + clock-names = "fck"; + }; + }; + + target-module@2000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x2000 0x4>, + <0x2010 0x4>, + <0x2014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x1000>; + + rfbi: encoder@0 { + compatible = "ti,omap5-rfbi"; + reg = <0 0x100>; + status = "disabled"; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>; + clock-names = "fck", "ick"; + }; + }; + + target-module@5000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x5000 0x4>, + <0x5010 0x4>, + <0x5014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5000 0x1000>; + + dsi1: encoder@0 { + compatible = "ti,omap5-dsi"; + reg = <0 0x200>, + <0x200 0x40>, + <0x300 0x40>; + reg-names = "proto", "phy", "pll"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; + clock-names = "fck"; + }; + }; + + target-module@9000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x9000 0x4>, + <0x9010 0x4>, + <0x9014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x9000 0x1000>; + + dsi2: encoder@0 { + compatible = "ti,omap5-dsi"; + reg = <0 0x200>, + <0x200 0x40>, + <0x300 0x40>; + reg-names = "proto", "phy", "pll"; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; + clock-names = "fck"; + }; + }; + + target-module@40000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x40000 0x4>, + <0x40010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; + clock-names = "fck", "dss_clk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000 0x40000>; + + hdmi: encoder@0 { + compatible = "ti,omap5-hdmi"; + reg = <0 0x200>, + <0x200 0x80>, + <0x300 0x80>, + <0x20000 0x19000>; + reg-names = "wp", "pll", "phy", "core"; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; + clock-names = "fck", "sys_clk"; + dmas = <&sdma 76>; + dma-names = "audio_tx"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/ox810se.dtsi b/arch/arm/boot/dts/ox810se.dtsi index 9f6c2b660ed3..0755e5864c4a 100644 --- a/arch/arm/boot/dts/ox810se.dtsi +++ b/arch/arm/boot/dts/ox810se.dtsi @@ -323,8 +323,8 @@ interrupt-controller; reg = <0 0x200>; #interrupt-cells = <1>; - valid-mask = <0xFFFFFFFF>; - clear-mask = <0>; + valid-mask = <0xffffffff>; + clear-mask = <0xffffffff>; }; timer0: timer@200 { diff --git a/arch/arm/boot/dts/ox820.dtsi b/arch/arm/boot/dts/ox820.dtsi index c9b327732063..90846a7655b4 100644 --- a/arch/arm/boot/dts/ox820.dtsi +++ b/arch/arm/boot/dts/ox820.dtsi @@ -240,8 +240,8 @@ reg = <0 0x200>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; - valid-mask = <0xFFFFFFFF>; - clear-mask = <0>; + valid-mask = <0xffffffff>; + clear-mask = <0xffffffff>; }; timer0: timer@200 { diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/pxa168-aspenite.dts index 2ad40e373194..8bade6bf395b 100644 --- a/arch/arm/boot/dts/pxa168-aspenite.dts +++ b/arch/arm/boot/dts/pxa168-aspenite.dts @@ -18,18 +18,16 @@ memory { reg = <0x00000000 0x04000000>; }; +}; - soc { - apb@d4000000 { - uart1: uart@d4017000 { - status = "okay"; - }; - twsi1: i2c@d4011000 { - status = "okay"; - }; - rtc: rtc@d4010000 { - status = "okay"; - }; - }; - }; +&uart1 { + status = "okay"; +}; + +&twsi1 { + status = "okay"; +}; + +&rtc { + status = "okay"; }; diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi index 72f8cb60cb53..4fe7735c7c58 100644 --- a/arch/arm/boot/dts/pxa168.dtsi +++ b/arch/arm/boot/dts/pxa168.dtsi @@ -55,27 +55,30 @@ interrupts = <13>; }; - uart1: uart@d4017000 { - compatible = "mrvl,mmp-uart"; + uart1: serial@d4017000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4017000 0x1000>; + reg-shift = <2>; interrupts = <27>; clocks = <&soc_clocks PXA168_CLK_UART0>; resets = <&soc_clocks PXA168_CLK_UART0>; status = "disabled"; }; - uart2: uart@d4018000 { - compatible = "mrvl,mmp-uart"; + uart2: serial@d4018000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4018000 0x1000>; + reg-shift = <2>; interrupts = <28>; clocks = <&soc_clocks PXA168_CLK_UART1>; resets = <&soc_clocks PXA168_CLK_UART1>; status = "disabled"; }; - uart3: uart@d4026000 { - compatible = "mrvl,mmp-uart"; + uart3: serial@d4026000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4026000 0x1000>; + reg-shift = <2>; interrupts = <29>; clocks = <&soc_clocks PXA168_CLK_UART2>; resets = <&soc_clocks PXA168_CLK_UART2>; @@ -94,7 +97,7 @@ resets = <&soc_clocks PXA168_CLK_GPIO>; interrupt-names = "gpio_mux"; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; ranges; gcb0: gpio@d4019000 { @@ -116,6 +119,8 @@ twsi1: i2c@d4011000 { compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xd4011000 0x1000>; interrupts = <7>; clocks = <&soc_clocks PXA168_CLK_TWSI0>; @@ -126,6 +131,8 @@ twsi2: i2c@d4025000 { compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xd4025000 0x1000>; interrupts = <58>; clocks = <&soc_clocks PXA168_CLK_TWSI1>; @@ -136,7 +143,7 @@ rtc: rtc@d4010000 { compatible = "mrvl,mmp-rtc"; reg = <0xd4010000 0x1000>; - interrupts = <5 6>; + interrupts = <5>, <6>; interrupt-names = "rtc 1Hz", "rtc alarm"; clocks = <&soc_clocks PXA168_CLK_RTC>; resets = <&soc_clocks PXA168_CLK_RTC>; diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index c237a0e4b12a..d19674812cd2 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -170,7 +170,7 @@ clocks = <&clks CLK_GPIO>; gpio-ranges = <&pinctrl 0 0 128>; interrupt-names = "gpio0", "gpio1", "gpio_mux"; - interrupts = <8 9 10>; + interrupts = <8>, <9>, <10>; gpio-controller; #gpio-cells = <0x2>; interrupt-controller; diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts index 0f899e672e82..ce76158867c7 100644 --- a/arch/arm/boot/dts/pxa910-dkb.dts +++ b/arch/arm/boot/dts/pxa910-dkb.dts @@ -18,155 +18,153 @@ memory { reg = <0x00000000 0x10000000>; }; +}; - soc { - apb@d4000000 { - uart1: uart@d4017000 { - status = "okay"; - }; - twsi1: i2c@d4011000 { - status = "okay"; +&uart1 { + status = "okay"; +}; + +&twsi1 { + status = "okay"; - pmic: 88pm860x@34 { - compatible = "marvell,88pm860x"; - reg = <0x34>; - interrupts = <4>; - interrupt-parent = <&intc>; - interrupt-controller; - #interrupt-cells = <1>; + pmic: 88pm860x@34 { + compatible = "marvell,88pm860x"; + reg = <0x34>; + interrupts = <4>; + interrupt-parent = <&intc>; + interrupt-controller; + #interrupt-cells = <1>; - marvell,88pm860x-irq-read-clr; - marvell,88pm860x-slave-addr = <0x11>; + marvell,88pm860x-irq-read-clr; + marvell,88pm860x-slave-addr = <0x11>; - regulators { - BUCK1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - BUCK2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - BUCK3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - LDO1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - regulator-always-on; - }; - LDO2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - LDO5 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO10 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - LDO13 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - LDO14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - rtc { - marvell,88pm860x-vrtc = <1>; - }; - touch { - marvell,88pm860x-gpadc-prebias = <1>; - marvell,88pm860x-gpadc-slot-cycle = <1>; - marvell,88pm860x-tsi-prebias = <6>; - marvell,88pm860x-pen-prebias = <16>; - marvell,88pm860x-pen-prechg = <2>; - marvell,88pm860x-resistor-X = <300>; - }; - backlights { - backlight-0 { - marvell,88pm860x-iset = <4>; - marvell,88pm860x-pwm = <3>; - }; - backlight-2 { - }; - }; - leds { - led0-red { - marvell,88pm860x-iset = <12>; - }; - led0-green { - marvell,88pm860x-iset = <12>; - }; - led0-blue { - marvell,88pm860x-iset = <12>; - }; - }; - }; - }; - rtc: rtc@d4010000 { - status = "okay"; + regulators { + BUCK1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + BUCK2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + BUCK3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + LDO1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + regulator-always-on; + }; + LDO2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + LDO5 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + regulator-always-on; + }; + LDO9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO10 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + LDO12 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + LDO13 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + LDO14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + rtc { + marvell,88pm860x-vrtc = <1>; + }; + touch { + marvell,88pm860x-gpadc-prebias = <1>; + marvell,88pm860x-gpadc-slot-cycle = <1>; + marvell,88pm860x-tsi-prebias = <6>; + marvell,88pm860x-pen-prebias = <16>; + marvell,88pm860x-pen-prechg = <2>; + marvell,88pm860x-resistor-X = <300>; + }; + backlights { + backlight-0 { + marvell,88pm860x-iset = <4>; + marvell,88pm860x-pwm = <3>; + }; + backlight-2 { + }; + }; + leds { + led0-red { + marvell,88pm860x-iset = <12>; + }; + led0-green { + marvell,88pm860x-iset = <12>; + }; + led0-blue { + marvell,88pm860x-iset = <12>; }; }; }; }; + +&rtc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi index b3d6182d4de4..352a39357810 100644 --- a/arch/arm/boot/dts/pxa910.dtsi +++ b/arch/arm/boot/dts/pxa910.dtsi @@ -67,27 +67,30 @@ status = "disabled"; }; - uart1: uart@d4017000 { - compatible = "mrvl,mmp-uart"; + uart1: serial@d4017000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4017000 0x1000>; + reg-shift = <2>; interrupts = <27>; clocks = <&soc_clocks PXA910_CLK_UART0>; resets = <&soc_clocks PXA910_CLK_UART0>; status = "disabled"; }; - uart2: uart@d4018000 { - compatible = "mrvl,mmp-uart"; + uart2: serial@d4018000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4018000 0x1000>; + reg-shift = <2>; interrupts = <28>; clocks = <&soc_clocks PXA910_CLK_UART1>; resets = <&soc_clocks PXA910_CLK_UART1>; status = "disabled"; }; - uart3: uart@d4036000 { - compatible = "mrvl,mmp-uart"; + uart3: serial@d4036000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4036000 0x1000>; + reg-shift = <2>; interrupts = <59>; clocks = <&soc_clocks PXA910_CLK_UART2>; resets = <&soc_clocks PXA910_CLK_UART2>; @@ -106,7 +109,7 @@ clocks = <&soc_clocks PXA910_CLK_GPIO>; resets = <&soc_clocks PXA910_CLK_GPIO>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; ranges; gcb0: gpio@d4019000 { @@ -152,7 +155,7 @@ rtc: rtc@d4010000 { compatible = "mrvl,mmp-rtc"; reg = <0xd4010000 0x1000>; - interrupts = <5 6>; + interrupts = <5>, <6>; interrupt-names = "rtc 1Hz", "rtc alarm"; clocks = <&soc_clocks PXA910_CLK_RTC>; resets = <&soc_clocks PXA910_CLK_RTC>; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 8b79b4112ee1..2687c4e890ba 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -350,6 +350,7 @@ reg = <0x800000 0x4000>; gpio-controller; + gpio-ranges = <&tlmm_pinmux 0 0 90>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index fa1852eed37b..bf6a03506b45 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -403,6 +403,7 @@ compatible = "qcom,apq8084-pinctrl"; reg = <0xfd510000 0x4000>; gpio-controller; + gpio-ranges = <&tlmm 0 0 147>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 71bb25a8afc0..c6956015dedc 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -166,6 +166,7 @@ <1 4 0xf08>, <1 1 0xf08>; clock-frequency = <48000000>; + always-on; }; soc { @@ -201,6 +202,7 @@ compatible = "qcom,ipq4019-pinctrl"; reg = <0x01000000 0x300000>; gpio-controller; + gpio-ranges = <&tlmm 0 0 100>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 16c0da97932c..b912da9a3ff3 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -93,6 +93,12 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-ipq806x", "qcom,scm"; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -119,6 +125,7 @@ reg = <0x800000 0x4000>; gpio-controller; + gpio-ranges = <&qcom_pinmux 0 0 69>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index 356e9535f7a6..347b4f7d7889 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -128,6 +128,7 @@ msmgpio: pinctrl@800000 { compatible = "qcom,mdm9615-pinctrl"; gpio-controller; + gpio-ranges = <&msmgpio 0 0 88>; #gpio-cells = <2>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index ec5cbc468bd3..480fc08cbe8e 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -115,6 +115,7 @@ reg = <0x800000 0x4000>; gpio-controller; + gpio-ranges = <&tlmm 0 0 173>; #gpio-cells = <2>; interrupts = <0 16 0x4>; interrupt-controller; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index f2aeaccdc1ad..172ea3c70eac 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -107,6 +107,7 @@ msmgpio: pinctrl@800000 { compatible = "qcom,msm8960-pinctrl"; gpio-controller; + gpio-ranges = <&msmgpio 0 0 152>; #gpio-cells = <2>; interrupts = <0 16 0x4>; interrupt-controller; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 3487daf98e81..32b474bfeec3 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -12,6 +12,7 @@ aliases { serial0 = &blsp1_uart1; + serial1 = &blsp2_uart10; }; chosen { @@ -355,6 +356,57 @@ bias-disable; }; }; + + bt_pin: bt { + hostwake { + pins = "gpio42"; + function = "gpio"; + }; + + devwake { + pins = "gpio62"; + function = "gpio"; + }; + + shutdown { + pins = "gpio41"; + function = "gpio"; + }; + }; + + blsp2_uart10_pin_a: blsp2-uart10-pin-active { + tx { + pins = "gpio53"; + function = "blsp_uart10"; + + drive-strength = <2>; + bias-disable; + }; + + rx { + pins = "gpio54"; + function = "blsp_uart10"; + + drive-strength = <2>; + bias-pull-up; + }; + + cts { + pins = "gpio55"; + function = "blsp_uart10"; + + drive-strength = <2>; + bias-pull-up; + }; + + rts { + pins = "gpio56"; + function = "blsp_uart10"; + + drive-strength = <2>; + bias-disable; + }; + }; }; sdhci@f9824900 { @@ -418,6 +470,25 @@ }; }; + serial@f9960000 { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_uart10_pin_a>; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&bt_pin>; + + host-wakeup-gpios = <&msmgpio 42 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&msmgpio 62 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&msmgpio 41 GPIO_ACTIVE_HIGH>; + }; + }; + i2c@f9967000 { status = "ok"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index eaa1001d0a46..d4dc98214225 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -1,7 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-msm8974pro.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" +#include "qcom-pma8084.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> / { model = "Samsung Galaxy S5"; @@ -14,6 +16,194 @@ chosen { stdout-path = "serial0:115200n8"; }; + + smd { + rpm { + rpm_requests { + pma8084-regulators { + compatible = "qcom,rpm-pma8084-regulators"; + status = "okay"; + + pma8084_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_s3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pma8084_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_s5: s5 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + + pma8084_s6: s6 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pma8084_l3: l3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1200000>; + }; + + pma8084_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pma8084_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pma8084_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pma8084_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pma8084_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pma8084_l19: l19 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + }; + + pma8084_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + pma8084_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pma8084_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pma8084_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pma8084_l25: l25 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + }; + + pma8084_l26: l26 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2050000>; + }; + + pma8084_l27: l27 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_lvs1: lvs1 {}; + pma8084_lvs2: lvs2 {}; + pma8084_lvs3: lvs3 {}; + pma8084_lvs4: lvs4 {}; + + pma8084_5vs1: 5vs1 {}; + }; + }; + }; + }; + + /delete-node/ vreg-boost; }; &soc { @@ -21,4 +211,215 @@ status = "ok"; }; + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + volume-down { + label = "volume_down"; + gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <15>; + }; + + home-key { + label = "home_key"; + gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_HOMEPAGE>; + wakeup-source; + debounce-interval = <15>; + }; + + volume-up { + label = "volume_up"; + gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <15>; + }; + }; + + pinctrl@fd510000 { + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <4>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <4>; + bias-pull-up; + }; + }; + }; + + sdhci@f9824900 { + status = "ok"; + + vmmc-supply = <&pma8084_l20>; + vqmmc-supply = <&pma8084_s4>; + + bus-width = <8>; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; + }; + + usb@f9a55000 { + status = "ok"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + /*extcon = <&smbb>, <&usb_id>;*/ + /*vbus-supply = <&chg_otg>;*/ + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "ok"; + + v1p8-supply = <&pma8084_l6>; + v3p3-supply = <&pma8084_l24>; + + /*extcon = <&smbb>;*/ + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; + }; + + pinctrl@fd510000 { + i2c6_pins: i2c6 { + mux { + pins = "gpio29", "gpio30"; + function = "blsp_i2c6"; + + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c@f9928000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + + pmic@60 { + reg = <0x60>; + compatible = "maxim,max77826"; + + regulators { + max77826_ldo1: LDO1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + max77826_ldo2: LDO2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + max77826_ldo3: LDO3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + max77826_ldo4: LDO4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo5: LDO5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo6: LDO6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo7: LDO7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo8: LDO8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo9: LDO9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo10: LDO10 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2950000>; + }; + + max77826_ldo11: LDO11 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2950000>; + }; + + max77826_ldo12: LDO12 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo13: LDO13 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo14: LDO14 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo15: LDO15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_buck: BUCK { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + max77826_buckboost: BUCKBOOST { + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; + }; +}; + +&spmi_bus { + pma8084@0 { + gpios@c000 { + gpio_keys_pin_a: gpio-keys-active { + pins = "gpio2", "gpio3", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = <PMA8084_GPIO_S4>; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts index 450b8321e0a6..611bae9fe66b 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts @@ -260,6 +260,31 @@ }; &soc { + usb@f9a55000 { + status = "ok"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "ok"; + + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; + }; + sdhci@f9824900 { status = "ok"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 4b161b809dd5..51f5f904f9eb 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -715,6 +715,15 @@ status = "disabled"; }; + blsp2_uart10: serial@f9960000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf9960000 0x1000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + sdhci@f9824900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; @@ -925,6 +934,7 @@ compatible = "qcom,msm8974-pinctrl"; reg = <0xfd510000 0x4000>; gpio-controller; + gpio-ranges = <&msmgpio 0 0 146>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -964,6 +974,17 @@ #size-cells = <0>; }; + blsp_i2c6: i2c@f9928000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9928000 0x1000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + blsp_i2c8: i2c@f9964000 { status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts index fe1a4aa4d7cb..2562cc9b5356 100644 --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts @@ -41,6 +41,9 @@ bank-width = <4>; device-width = <1>; + clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>; + power-domains = <&cpg_clocks>; + #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 75b2796ebfca..0a567d8ebc66 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -467,11 +467,12 @@ #clock-cells = <1>; compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0xfcfe0438 4>; - clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>; + clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>; clock-indices = < R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 + R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1 >; - clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3"; + clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1"; }; mstp10_clks: mstp10_clks@fcfe043c { diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index a5351ddbf506..b088e8e351d5 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -157,11 +157,8 @@ &cpu0 { cpu0-supply = <&vdd_dvfs>; - operating-points = < - /* kHz uV */ - 1950000 1115000 - 1462500 995000 - >; + operating-points = <1950000 1115000>, /* kHz uV */ + <1462500 995000>; voltage-tolerance = <1>; /* 1% */ }; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index ebc1ff64f530..014805894ea7 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -83,7 +83,7 @@ }; cmt1: timer@e6138000 { - compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; + compatible = "renesas,r8a7740-cmt1"; reg = <0xe6138000 0x170>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7740_CLK_CMT1>; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts new file mode 100644 index 000000000000..1f5c35c66d91 --- /dev/null +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZ/G1H Qseven board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a7742-iwg21m.dtsi" + +/ { + model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H"; + compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"; + + aliases { + serial2 = &scifa2; + }; + + chosen { + bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait"; + stdout-path = "serial2:115200n8"; + }; +}; + +&pfc { + scifa2_pins: scifa2 { + groups = "scifa2_data_c"; + function = "scifa2"; + }; +}; + +&scifa2 { + pinctrl-0 = <&scifa2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi new file mode 100644 index 000000000000..85aff429d408 --- /dev/null +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave RZ/G1H Qseven SOM + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include "r8a7742.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "iwave,g21m", "renesas,r8a7742"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + mmc1_pins: mmc1 { + groups = "mmc1_data4", "mmc1_ctrl"; + function = "mmc1"; + }; +}; + +&mmcif1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <4>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi new file mode 100644 index 000000000000..305d8086a3dd --- /dev/null +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -0,0 +1,648 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a7742 SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include <dt-bindings/clock/r8a7742-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/power/r8a7742-sysc.h> + +/ { + compatible = "renesas,r8a7742"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU1>; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <2>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU2>; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <3>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU3>; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU0>; + next-level-cache = <&L2_CA7>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU1>; + next-level-cache = <&L2_CA7>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU2>; + next-level-cache = <&L2_CA7>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU3>; + next-level-cache = <&L2_CA7>; + }; + + L2_CA15: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7742_PD_CA15_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA7: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A7742_PD_CA7_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + pmu-0 { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + pmu-1 { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7742"; + reg = <0 0xe6060000 0 0x250>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7742-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7742-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7742-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7742", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63a0000 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe6300000 0x40000>; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7742", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7742", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; + + scif2: serial@e6e56000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e56000 0 0x40>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7742", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7742", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + mmcif1: mmc@ee220000 { + compatible = "renesas,mmcif-r8a7742", + "renesas,sh-mmcif"; + reg = <0 0xee220000 0 0x80>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 305>; + dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, + <&dmac1 0xe1>, <&dmac1 0xe2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 305>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 1cd19a569bd0..fff123753b85 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -338,7 +338,7 @@ #thermal-sensor-cells = <0>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -348,7 +348,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -357,7 +357,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -367,7 +367,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -376,7 +376,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -386,7 +386,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; @@ -1669,9 +1669,10 @@ reg = <0 0xfeb00000 0 0x40000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; status = "disabled"; ports { diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 1c82dd0abd76..5050ac19041d 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -338,7 +338,7 @@ #thermal-sensor-cells = <0>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -348,7 +348,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -357,7 +357,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -367,7 +367,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -376,7 +376,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -386,7 +386,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; @@ -1655,9 +1655,10 @@ reg = <0 0xfeb00000 0 0x40000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; status = "disabled"; ports { diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts index 2aeebfc9e4f1..92aa26ba423c 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts @@ -108,6 +108,12 @@ }; }; +&lcd_panel { + status = "disabled"; + + /delete-node/ port; +}; + &pfc { can1_pins: can1 { groups = "can1_data_b"; diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts index 58d369ad8279..b15b1b088a32 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts @@ -30,6 +30,7 @@ /dts-v1/; #include "r8a7745-iwg22m.dtsi" +#include <dt-bindings/pwm/pwm.h> / { model = "iWave Systems RainboW-G22D-SODIMM board based on RZ/G1E"; @@ -78,6 +79,49 @@ gpios-states = <1>; states = <3300000 1>, <1800000 0>; }; + + vccq_panel: regulator-vccq-panel { + compatible = "regulator-fixed"; + regulator-name = "Panel VccQ"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; + enable-active-high; + }; + + backlight_lcd: backlight { + compatible = "pwm-backlight"; + pwms = <&tpu 3 5000000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + lcd_panel: lcd { + compatible = "edt,etm043080dh6gp"; + power-supply = <&vccq_panel>; + backlight = <&backlight_lcd>; + + port { + lcd_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&lcd_in>; + }; + }; + }; }; &avb { @@ -127,6 +171,39 @@ status = "okay"; clock-frequency = <400000>; + stmpe811@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + interrupt-parent = <&gpio4>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + }; + sgtl5000: codec@a { compatible = "fsl,sgtl5000"; #sound-dai-cells = <0>; @@ -149,11 +226,21 @@ function = "avb"; }; + backlight_pins: backlight { + groups = "tpu_to3_c"; + function = "tpu"; + }; + can0_pins: can0 { groups = "can0_data"; function = "can0"; }; + du0_pins: du0 { + groups = "du0_rgb666", "du0_sync", "du0_disp", "du0_clk0_out"; + function = "du0"; + }; + hscif1_pins: hscif1 { groups = "hscif1_data", "hscif1_ctrl"; function = "hscif1"; @@ -229,6 +316,12 @@ shared-pin; }; +&tpu { + pinctrl-0 = <&backlight_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &usbphy { status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 3f88a7e34af2..b0d1fc24e97e 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -302,7 +302,7 @@ resets = <&cpg 407>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -312,7 +312,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -321,7 +321,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -331,7 +331,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -340,7 +340,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -350,7 +350,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; @@ -1506,11 +1506,12 @@ du: display@feb00000 { compatible = "renesas,du-r8a7745"; reg = <0 0xfeb00000 0 0x40000>; - reg-names = "du"; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; status = "disabled"; ports { diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 6efcef1670e1..f55153192276 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -942,9 +942,10 @@ reg = <0 0xfeb00000 0 0x40000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; status = "disabled"; ports { diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index beb9885e6ffc..c0999e27e9b1 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -377,7 +377,7 @@ }; sata: sata@fc600000 { - compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; + compatible = "renesas,sata-r8a7779"; reg = <0xfc600000 0x200000>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7779_CLK_SATA>; diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 097fd9317c6e..69745def44d4 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -674,6 +674,7 @@ interrupt-parent = <&irqc0>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; + reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts index a315ba749aa4..4138efb2766d 100644 --- a/arch/arm/boot/dts/r8a7790-stout.dts +++ b/arch/arm/boot/dts/r8a7790-stout.dts @@ -203,6 +203,7 @@ interrupt-parent = <&irqc0>; interrupts = <1 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; + reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 334ba19769b9..166d5566229d 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -427,7 +427,7 @@ #thermal-sensor-cells = <0>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -437,7 +437,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -446,7 +446,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -456,7 +456,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -465,7 +465,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -475,7 +475,7 @@ status = "disabled"; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xffc80000 0 0x1000>; @@ -1719,6 +1719,8 @@ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>; clock-names = "du.0", "du.1", "du.2"; + resets = <&cpg 724>; + reset-names = "du.0"; status = "disabled"; ports { diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 2b096d5e06fb..687167b70cb6 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -633,6 +633,7 @@ interrupt-parent = <&irqc0>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; + reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index f9ece7ab2010..a8e0335148a5 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -307,6 +307,7 @@ interrupt-parent = <&irqc0>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; + reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 59a55e87fcc6..225676fbe312 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -291,6 +291,17 @@ reg = <0 0xe6060000 0 0x250>; }; + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7791", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7791-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -350,7 +361,7 @@ #thermal-sensor-cells = <0>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -360,7 +371,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -369,7 +380,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -379,7 +390,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -388,7 +399,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -398,7 +409,7 @@ status = "disabled"; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xffc80000 0 0x1000>; @@ -407,7 +418,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; @@ -1067,6 +1078,76 @@ status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + adc: adc@e6e54000 { compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc"; @@ -1681,9 +1762,10 @@ reg = <0 0xfeb00000 0 0x40000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; status = "disabled"; ports { diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 39af16caa2ae..4627eefa502b 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -852,9 +852,10 @@ reg = <0 0xfeb00000 0 0x40000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; status = "disabled"; ports { diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 22ca7cd1e7d2..cfe06a74ce89 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -591,6 +591,7 @@ interrupt-parent = <&irqc0>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; + reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index eef035c4d983..1b62a7e06b42 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -336,7 +336,7 @@ #thermal-sensor-cells = <0>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -346,7 +346,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -355,7 +355,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -365,7 +365,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -374,7 +374,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -384,7 +384,7 @@ status = "disabled"; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xffc80000 0 0x1000>; @@ -393,7 +393,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; @@ -1341,9 +1341,10 @@ reg = <0 0xfeb00000 0 0x40000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; status = "disabled"; ports { diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index f79fce74cd9c..935935c1dbac 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -343,6 +343,7 @@ interrupt-parent = <&irqc0>; interrupts = <8 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; + reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index 2c16ad854300..9aaa96ea9943 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -394,6 +394,7 @@ interrupt-parent = <&irqc0>; interrupts = <8 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; + reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 05ef79c6ed7f..8d7f8798628a 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -290,7 +290,7 @@ resets = <&cpg 407>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -300,7 +300,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -309,7 +309,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -319,7 +319,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -328,7 +328,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -338,7 +338,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; @@ -1356,6 +1356,8 @@ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; status = "disabled"; ports { diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index fb3cf005cc90..7154b827ea2f 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -16,7 +16,7 @@ leds: gpio-leds { compatible = "gpio-leds"; - work { + work_led: led-0 { gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; label = "kylin:red:led"; pinctrl-names = "default"; @@ -319,7 +319,7 @@ bus-width = <4>; cap-sd-highspeed; cap-sdio-irq; - default-sample-phase = <90>; + rockchip,default-sample-phase = <90>; keep-power-in-suspend; mmc-pwrseq = <&sdio_pwrseq>; non-removable; diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index cf36e25195b4..781ac7583522 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -54,7 +54,7 @@ }; }; - amba { + amba: bus { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -101,7 +101,7 @@ #clock-cells = <0>; }; - bus_intmem@10080000 { + bus_intmem: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x2000>; #address-cells = <1>; @@ -263,7 +263,7 @@ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - default-sample-phase = <158>; + rockchip,default-sample-phase = <158>; disable-wp; dmas = <&pdma 12>; dma-names = "rx-tx"; @@ -281,8 +281,6 @@ compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s"; reg = <0x10220000 0x4000>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; dmas = <&pdma 0>, <&pdma 1>; diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts index 365eff621113..eed9e60cffa2 100644 --- a/arch/arm/boot/dts/rk3066a-mk808.dts +++ b/arch/arm/boot/dts/rk3066a-mk808.dts @@ -22,7 +22,7 @@ gpio-leds { compatible = "gpio-leds"; - blue { + blue_led: led-0 { label = "mk808:blue:power"; gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 3d1b02f45ffd..b599394d149d 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -156,14 +156,12 @@ compatible = "rockchip,rk3066-i2s"; reg = <0x10118000 0x2000>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; + clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac1_s 4>, <&dmac1_s 5>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; rockchip,playback-channels = <8>; rockchip,capture-channels = <2>; #sound-dai-cells = <0>; @@ -174,14 +172,12 @@ compatible = "rockchip,rk3066-i2s"; reg = <0x1011a000 0x2000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2s1_bus>; + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; + clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac1_s 6>, <&dmac1_s 7>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; #sound-dai-cells = <0>; @@ -192,14 +188,12 @@ compatible = "rockchip,rk3066-i2s"; reg = <0x1011c000 0x2000>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2s2_bus>; + clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; + clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac1_s 9>, <&dmac1_s 10>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; #sound-dai-cells = <0>; diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts index ad1afd403052..66a0ff196eb1 100644 --- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -58,20 +58,25 @@ lvds-encoder { compatible = "ti,sn75lvds83", "lvds-encoder"; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - lvds_in_vop0: endpoint { - remote-endpoint = <&vop0_out_lvds>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_in_vop0: endpoint { + remote-endpoint = <&vop0_out_lvds>; + }; }; - }; - port@1 { - reg = <1>; - lvds_out_panel: endpoint { - remote-endpoint = <&panel_in_lvds>; + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; }; }; }; @@ -465,7 +470,7 @@ non-removable; pinctrl-names = "default"; pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>; - vmmcq-supply = <&vccio_wl>; + vqmmc-supply = <&vccio_wl>; #address-cells = <1>; #size-cells = <0>; status = "okay"; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index c9a7f5409960..b0fef82c0a71 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -33,19 +33,19 @@ gpio-leds { compatible = "gpio-leds"; - green { + green_led: led-0 { label = "rock:green:user1"; gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>; default-state = "off"; }; - blue { + blue_led: led-1 { label = "rock:blue:user2"; gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; default-state = "off"; }; - sleep { + sleep_led: led-2 { label = "rock:red:power"; gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 10ede65d90f3..2298a8d840ba 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -166,14 +166,12 @@ compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; reg = <0x1011a000 0x2000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; + clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac1_s 6>, <&dmac1_s 7>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; #sound-dai-cells = <0>; @@ -184,8 +182,8 @@ compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; reg = <0x1011e000 0x2000>; #sound-dai-cells = <0>; - clock-names = "hclk", "mclk"; - clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>; + clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; + clock-names = "mclk", "hclk"; dmas = <&dmac1_s 8>; dma-names = "tx"; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/rk3229-xms6.dts b/arch/arm/boot/dts/rk3229-xms6.dts index 679fc2b00e5a..96c9372a89ee 100644 --- a/arch/arm/boot/dts/rk3229-xms6.dts +++ b/arch/arm/boot/dts/rk3229-xms6.dts @@ -33,12 +33,18 @@ power-led { compatible = "gpio-leds"; - blue { + blue_led: led-0 { gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, + <&gpio2 29 GPIO_ACTIVE_LOW>; + }; + vcc_host: vcc-host-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -131,7 +137,6 @@ &emmc { cap-mmc-highspeed; - disable-wp; non-removable; status = "okay"; }; @@ -202,6 +207,16 @@ status = "okay"; }; +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + vqmmc-supply = <&vccio_1v8>; + status = "okay"; +}; + &sdmmc { cap-mmc-highspeed; disable-wp; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 4e90efdc9630..b37ba72d32ca 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -95,7 +95,7 @@ }; }; - amba { + amba: bus { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -152,8 +152,6 @@ compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100b0000 0x4000>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; dmas = <&pdma 14>, <&pdma 15>; @@ -167,8 +165,6 @@ compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100c0000 0x4000>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; dmas = <&pdma 11>, <&pdma 12>; @@ -193,8 +189,6 @@ compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100e0000 0x4000>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; dmas = <&pdma 0>, <&pdma 1>; @@ -621,6 +615,16 @@ status = "disabled"; }; + rga: rga@20060000 { + compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga"; + reg = <0x20060000 0x1000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; + reset-names = "core", "axi", "ahb"; + }; + iep_mmu: iommu@20070800 { compatible = "rockchip,iommu"; reg = <0x20070800 0x100>; @@ -698,7 +702,7 @@ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; bus-width = <8>; - default-sample-phase = <158>; + rockchip,default-sample-phase = <158>; fifo-depth = <0x100>; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; @@ -718,7 +722,6 @@ g-np-tx-fifo-size = <16>; g-rx-fifo-size = <280>; g-tx-fifo-size = <256 128 128 64 32 16>; - g-use-dma; phys = <&u2phy0_otg>; phy-names = "usb2-phy"; status = "disabled"; @@ -729,7 +732,6 @@ reg = <0x30080000 0x20000>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_HOST0>, <&u2phy0>; - clock-names = "usbhost", "utmi"; phys = <&u2phy0_host>; phy-names = "usb"; status = "disabled"; @@ -740,7 +742,6 @@ reg = <0x300a0000 0x20000>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_HOST0>, <&u2phy0>; - clock-names = "usbhost", "utmi"; phys = <&u2phy0_host>; phy-names = "usb"; status = "disabled"; @@ -751,7 +752,6 @@ reg = <0x300c0000 0x20000>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_HOST1>, <&u2phy1>; - clock-names = "usbhost", "utmi"; phys = <&u2phy1_otg>; phy-names = "usb"; status = "disabled"; @@ -762,7 +762,6 @@ reg = <0x300e0000 0x20000>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_HOST1>, <&u2phy1>; - clock-names = "usbhost", "utmi"; phys = <&u2phy1_otg>; phy-names = "usb"; status = "disabled"; @@ -775,7 +774,6 @@ clocks = <&cru HCLK_HOST2>, <&u2phy1>; phys = <&u2phy1_host>; phy-names = "usb"; - clock-names = "usbhost", "utmi"; status = "disabled"; }; @@ -784,7 +782,6 @@ reg = <0x30120000 0x20000>; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_HOST2>, <&u2phy1>; - clock-names = "usbhost", "utmi"; phys = <&u2phy1_host>; phy-names = "usb"; status = "disabled"; diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts index 80080767c365..be695b8c1f67 100644 --- a/arch/arm/boot/dts/rk3288-evb-act8846.dts +++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts @@ -4,6 +4,7 @@ #include "rk3288-evb.dtsi" / { + model = "Rockchip RK3288 EVB ACT8846"; compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288"; vcc_lcd: vcc-lcd { diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts index 16788209625b..42384ea4ca21 100644 --- a/arch/arm/boot/dts/rk3288-evb-rk808.dts +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts @@ -4,6 +4,7 @@ #include "rk3288-evb.dtsi" / { + model = "Rockchip RK3288 EVB RK808"; compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; }; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index 1574383fd2dc..9a4a9749c405 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -45,20 +45,20 @@ leds { compatible = "gpio-leds"; - power { + power_led: led-0 { gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>; label = "firefly:blue:power"; pinctrl-names = "default"; - pinctrl-0 = <&power_led>; + pinctrl-0 = <&power_led_pin>; panic-indicator; }; - work { + work_led: led-1 { gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; label = "firefly:blue:user"; linux,default-trigger = "rc-feedback"; pinctrl-names = "default"; - pinctrl-0 = <&work_led>; + pinctrl-0 = <&work_led_pin>; }; }; @@ -234,6 +234,7 @@ }; &saradc { + vref-supply = <&vcc_18>; status = "okay"; }; @@ -333,11 +334,11 @@ }; leds { - power_led: power-led { + power_led_pin: power-led-pin { rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; - work_led: work-led { + work_led_pin: work-led-pin { rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 5e0a19004e46..e5c4fd4ea67e 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -62,20 +62,20 @@ leds { compatible = "gpio-leds"; - work { + work_led: led-0 { gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; label = "firefly:blue:user"; linux,default-trigger = "rc-feedback"; pinctrl-names = "default"; - pinctrl-0 = <&work_led>; + pinctrl-0 = <&work_led_pin>; }; - power { + power_led: led-1 { gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>; label = "firefly:green:power"; linux,default-trigger = "default-on"; pinctrl-names = "default"; - pinctrl-0 = <&power_led>; + pinctrl-0 = <&power_led_pin>; }; }; @@ -429,11 +429,11 @@ }; leds { - power_led: power-led { + power_led_pin: power-led-pin { rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; - work_led: work-led { + work_led_pin: work-led-pin { rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts index c41d012c8850..213c9eb84f76 100644 --- a/arch/arm/boot/dts/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rk3288-miqi.dts @@ -30,7 +30,7 @@ leds { compatible = "gpio-leds"; - work { + work_led: led-0 { gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; label = "miqi:green:user"; linux,default-trigger = "timer"; diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi index 77a47b9b756d..e43887c9635f 100644 --- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi @@ -36,9 +36,9 @@ leds: user-leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&user_led>; + pinctrl-0 = <&user_led_pin>; - user { + user_led: led-0 { label = "green_led"; gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -372,7 +372,7 @@ }; leds { - user_led: user-led { + user_led_pin: user-led-pin { rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>; }; }; diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts index a6ffc381abaa..a258c7ae5329 100644 --- a/arch/arm/boot/dts/rk3288-r89.dts +++ b/arch/arm/boot/dts/rk3288-r89.dts @@ -9,6 +9,7 @@ #include "rk3288.dtsi" / { + model = "Netxeon R89"; compatible = "netxeon,r89", "rockchip,rk3288"; memory@0 { diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index cdcdc921ee09..3cca4d0f9b09 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -41,13 +41,13 @@ gpio-leds { compatible = "gpio-leds"; - heartbeat { + heartbeat_led: led-0 { gpios = <&gpio7 RK_PB7 GPIO_ACTIVE_LOW>; label = "rock2:green:state1"; linux,default-trigger = "heartbeat"; }; - mmc { + mmc_led: led-1 { gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; label = "rock2:blue:state2"; linux,default-trigger = "mmc0"; diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi index 312582c1bd37..90e9be443fe6 100644 --- a/arch/arm/boot/dts/rk3288-tinker.dtsi +++ b/arch/arm/boot/dts/rk3288-tinker.dtsi @@ -46,17 +46,17 @@ gpio-leds { compatible = "gpio-leds"; - act-led { + act_led: led-0 { gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; }; - heartbeat-led { + heartbeat_led: led-1 { gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - pwr-led { + pwr_led: led-2 { gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; @@ -276,6 +276,7 @@ }; vccio_sd: LDO_REG5 { + regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts index ba06e9f97ddc..385dd59393e1 100644 --- a/arch/arm/boot/dts/rk3288-vyasa.dts +++ b/arch/arm/boot/dts/rk3288-vyasa.dts @@ -78,6 +78,18 @@ vin-supply = <&vcc_io>; }; + vcc50_hdmi: vcc50-hdmi { + compatible = "regulator-fixed"; + regulator-name = "vcc50_hdmi"; + enable-active-high; + gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>; /* HDMI_EN */ + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vsus_5v>; + }; + vusb1_5v: vusb1-5v { compatible = "regulator-fixed"; regulator-name = "vusb1_5v"; @@ -150,7 +162,7 @@ }; &hdmi { - ddc-i2c-bus = <&i2c2>; + ddc-i2c-bus = <&i2c5>; status = "okay"; }; @@ -286,15 +298,15 @@ }; }; - vcc10_lcd: LDO_REG6 { - regulator-name = "vcc10_lcd"; + vdd10_lcd: LDO_REG6 { + regulator-name = "vdd10_lcd"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; + regulator-suspend-microvolt = <1000000>; }; }; @@ -347,7 +359,7 @@ }; }; -&i2c2 { +&i2c5 { status = "okay"; }; @@ -446,6 +458,12 @@ }; }; + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int: pmic-int { rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 9beb662166aa..2e1edd85f04a 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -7,7 +7,6 @@ #include <dt-bindings/clock/rk3288-cru.h> #include <dt-bindings/power/rk3288-power.h> #include <dt-bindings/thermal/thermal.h> -#include <dt-bindings/power/rk3288-power.h> #include <dt-bindings/soc/rockchip,boot-mode.h> / { @@ -155,7 +154,7 @@ }; }; - amba { + amba: bus { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -420,6 +419,8 @@ reg-io-width = <4>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac_peri 1>, <&dmac_peri 2>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; status = "disabled"; @@ -433,6 +434,8 @@ reg-io-width = <4>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac_peri 3>, <&dmac_peri 4>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart1_xfer>; status = "disabled"; @@ -459,6 +462,8 @@ reg-io-width = <4>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac_peri 7>, <&dmac_peri 8>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart3_xfer>; status = "disabled"; @@ -472,6 +477,8 @@ reg-io-width = <4>; clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac_peri 9>, <&dmac_peri 10>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart4_xfer>; status = "disabled"; @@ -601,7 +608,6 @@ reg = <0x0 0xff500000 0x0 0x100>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_USBHOST0>; - clock-names = "usbhost"; phys = <&usbphy1>; phy-names = "usb"; status = "disabled"; @@ -644,7 +650,6 @@ reg = <0x0 0xff5c0000 0x0 0x100>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_HSIC>; - clock-names = "usbhost"; status = "disabled"; }; @@ -718,7 +723,7 @@ status = "disabled"; }; - bus_intmem@ff700000 { + bus_intmem: sram@ff700000 { compatible = "mmio-sram"; reg = <0x0 0xff700000 0x0 0x18000>; #address-cells = <1>; @@ -730,7 +735,7 @@ }; }; - sram@ff720000 { + pmu_sram: sram@ff720000 { compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; reg = <0x0 0xff720000 0x0 0x1000>; }; @@ -946,8 +951,8 @@ compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; reg = <0x0 0xff8b0000 0x0 0x10000>; #sound-dai-cells = <0>; - clock-names = "hclk", "mclk"; - clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; + clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>; + clock-names = "mclk", "hclk"; dmas = <&dmac_bus_s 3>; dma-names = "tx"; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; @@ -962,12 +967,10 @@ reg = <0x0 0xff890000 0x0 0x10000>; #sound-dai-cells = <0>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; + clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; rockchip,playback-channels = <8>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 241f43e29c77..f9fcb7e9657b 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -32,7 +32,7 @@ spi1 = &spi1; }; - amba { + amba: bus { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -91,7 +91,7 @@ status = "disabled"; }; - L2: l2-cache-controller@10138000 { + L2: cache-controller@10138000 { compatible = "arm,pl310-cache"; reg = <0x10138000 0x1000>; cache-unified; diff --git a/arch/arm/boot/dts/rtd1195-horseradish.dts b/arch/arm/boot/dts/rtd1195-horseradish.dts new file mode 100644 index 000000000000..9d06d3d34c74 --- /dev/null +++ b/arch/arm/boot/dts/rtd1195-horseradish.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1195.dtsi" + +/ { + compatible = "realtek,horseradish", "realtek,rtd1195"; + model = "Realtek Horseradish EVB"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@a800 { + device_type = "memory"; + reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */ + <0x18070000 0x00090000>, /* r-bus to NOR flash */ + <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */ + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rtd1195-mele-x1000.dts b/arch/arm/boot/dts/rtd1195-mele-x1000.dts new file mode 100644 index 000000000000..c7951b9a2c97 --- /dev/null +++ b/arch/arm/boot/dts/rtd1195-mele-x1000.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2017-2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1195.dtsi" + +/ { + compatible = "mele,x1000", "realtek,rtd1195"; + model = "MeLE X1000"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@a800 { + device_type = "memory"; + reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */ + <0x18070000 0x00090000>, /* r-bus to NOR flash */ + <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */ + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi new file mode 100644 index 000000000000..21897210d9d0 --- /dev/null +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2017-2019 Andreas Färber + */ + +/memreserve/ 0x00000000 0x0000a800; /* boot code */ +/memreserve/ 0x0000a800 0x000f5800; +/memreserve/ 0x17fff000 0x00001000; + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/realtek,rtd1195.h> + +/ { + compatible = "realtek,rtd1195"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clock-frequency = <1000000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + clock-frequency = <1000000000>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rpc_comm: rpc@b000 { + reg = <0x0000b000 0x1000>; + }; + + audio@1b00000 { + reg = <0x01b00000 0x400000>; + }; + + rpc_ringbuf: rpc@1ffe000 { + reg = <0x01ffe000 0x4000>; + }; + + secure@10000000 { + reg = <0x10000000 0x100000>; + no-map; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <27000000>; + }; + + osc27M: osc { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + #clock-cells = <0>; + clock-output-names = "osc27M"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x0000a800>, + <0x18000000 0x18000000 0x00070000>, + <0x18100000 0x18100000 0x01000000>, + <0x80000000 0x80000000 0x80000000>; + + rbus: bus@18000000 { + compatible = "simple-bus"; + reg = <0x18000000 0x70000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000000 0x70000>; + + crt: syscon@0 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + iso: syscon@7000 { + compatible = "syscon", "simple-mfd"; + reg = <0x7000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; + }; + + sb2: syscon@1a000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1a000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1a000 0x1000>; + }; + + misc: syscon@1b000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1b000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b000 0x1000>; + }; + + scpu_wrapper: syscon@1d000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1d000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1d000 0x1000>; + }; + }; + + gic: interrupt-controller@ff011000 { + compatible = "arm,cortex-a7-gic"; + reg = <0xff011000 0x1000>, + <0xff012000 0x2000>, + <0xff014000 0x2000>, + <0xff016000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; + +&crt { + reset1: reset-controller@0 { + compatible = "snps,dw-low-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + }; + + reset2: reset-controller@4 { + compatible = "snps,dw-low-reset"; + reg = <0x4 0x4>; + #reset-cells = <1>; + }; + + reset3: reset-controller@8 { + compatible = "snps,dw-low-reset"; + reg = <0x8 0x4>; + #reset-cells = <1>; + }; +}; + +&iso { + iso_reset: reset-controller@88 { + compatible = "snps,dw-low-reset"; + reg = <0x88 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@800 { + compatible = "snps,dw-apb-uart"; + reg = <0x800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&iso_reset RTD1195_ISO_RSTN_UR0>; + clock-frequency = <27000000>; + status = "disabled"; + }; +}; + +&misc { + uart1: serial@200 { + compatible = "snps,dw-apb-uart"; + reg = <0x200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&reset2 RTD1195_RSTN_UR1>; + clock-frequency = <27000000>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 1fd06e7cb983..f9cfe2c80791 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -85,7 +85,7 @@ #clock-cells = <0>; }; - amba { + amba: bus { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -102,7 +102,7 @@ }; }; - bus_intmem@10080000 { + bus_intmem: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x2000>; #address-cells = <1>; @@ -120,7 +120,6 @@ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; dmas = <&pdma 6>, <&pdma 7>; - #dma-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&uart2m0_xfer>; status = "disabled"; @@ -136,7 +135,6 @@ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; dmas = <&pdma 4>, <&pdma 5>; - #dma-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&uart1_xfer>; status = "disabled"; @@ -152,7 +150,6 @@ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; dmas = <&pdma 2>, <&pdma 3>; - #dma-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; status = "disabled"; @@ -208,7 +205,6 @@ clock-names = "spiclk", "apb_pclk"; dmas = <&pdma 8>, <&pdma 9>; dma-names = "tx", "rx"; - #dma-cells = <2>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -370,7 +366,6 @@ reg = <0x1038c000 0x100>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; #io-channel-cells = <1>; - clock-frequency = <1000000>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; status = "disabled"; @@ -499,7 +494,6 @@ reg = <0x30140000 0x20000>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_HOST0>, <&u2phy>; - clock-names = "usbhost", "utmi"; phys = <&u2phy_host>; phy-names = "usb"; status = "disabled"; @@ -510,7 +504,6 @@ reg = <0x30160000 0x20000>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_HOST0>, <&u2phy>; - clock-names = "usbhost", "utmi"; phys = <&u2phy_host>; phy-names = "usb"; status = "disabled"; @@ -527,7 +520,6 @@ g-np-tx-fifo-size = <16>; g-rx-fifo-size = <280>; g-tx-fifo-size = <256 128 128 64 32 16>; - g-use-dma; phys = <&u2phy_otg>; phy-names = "usb2-phy"; status = "disabled"; diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 8ff70b856334..cf858029292e 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -11,9 +11,15 @@ / { compatible = "samsung,aries", "samsung,s5pv210"; - aliases { + aliases: aliases { + i2c4 = &i2c_sound; + i2c5 = &i2c_accel; i2c6 = &i2c_pmic; + i2c7 = &i2c_musb; i2c9 = &i2c_fuel; + i2c10 = &i2c_touchkey; + i2c11 = &i2c_prox; + i2c12 = &i2c_magnetometer; }; memory@30000000 { @@ -46,6 +52,21 @@ regulator-name = "vibrator-en"; enable-active-high; gpio = <&gpj1 1 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctr-0 = <&vibrator_ena>; + }; + + touchkey_vdd: regulator-fixed-1 { + compatible = "regulator-fixed"; + regulator-name = "VTOUCH_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpj3 2 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_vdd_ena>; }; wifi_pwrseq: wifi-pwrseq { @@ -57,7 +78,71 @@ power-off-delay-us = <500>; }; - i2c_pmic: i2c-gpio-0 { + i2c_sound: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&mp05 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&mp05 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&sound_i2c_pins>; + + wm8994: wm8994@1a { + compatible = "wlf,wm8994"; + reg = <0x1a>; + + #sound-dai-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + clocks = <&clocks MOUT_CLKOUT>; + clock-names = "MCLK1"; + + AVDD2-supply = <&buck3_reg>; + DBVDD-supply = <&buck3_reg>; + CPVDD-supply = <&buck3_reg>; + SPKVDD1-supply = <&buck3_reg>; + SPKVDD2-supply = <&buck3_reg>; + + wlf,gpio-cfg = <0xa101 0x8100 0x0100 0x0100 0x8100 + 0xa101 0x0100 0x8100 0x0100 0x0100 + 0x0100>; + + wlf,ldo1ena = <&gpf3 4 GPIO_ACTIVE_HIGH>; + wlf,ldo2ena = <&gpf3 4 GPIO_ACTIVE_HIGH>; + + wlf,lineout1-se; + wlf,lineout2-se; + + assigned-clocks = <&clocks MOUT_CLKOUT>; + assigned-clock-rates = <0>; + assigned-clock-parents = <&xusbxti>; + + pinctrl-names = "default"; + pinctrl-0 = <&codec_ldo>; + }; + }; + + i2c_accel: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&accel_i2c_pins>; + + status = "disabled"; + + /* bma023 accelerometer, no mainline binding */ + }; + + i2c_pmic: i2c-gpio-2 { compatible = "i2c-gpio"; sda-gpios = <&gpj4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&gpj4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -65,6 +150,9 @@ #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_i2c_pins>; + pmic@66 { compatible = "maxim,max8998"; reg = <0x66>; @@ -81,6 +169,9 @@ max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; max8998,pmic-buck2-dvs-voltage = <1100000>, <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_dvs_pins &pmic_irq>; + regulators { ldo2_reg: LDO2 { regulator-name = "VALIVE_1.2V"; @@ -107,7 +198,6 @@ regulator-name = "VADC_3.3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; regulator-state-mem { regulator-off-in-suspend; @@ -134,8 +224,6 @@ regulator-name = "VLCD_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - /* Till we get panel driver */ - regulator-always-on; regulator-state-mem { regulator-off-in-suspend; @@ -234,8 +322,6 @@ regulator-name = "VCC_3.0V_LCD"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; - /* Till we get panel driver */ - regulator-always-on; regulator-state-mem { regulator-off-in-suspend; @@ -306,7 +392,29 @@ }; }; - i2c_fuel: i2c-gpio-1 { + i2c_musb: i2c-gpio-3 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj3 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&musb_i2c_pins>; + + fsa9480: musb@25 { + compatible = "fcs,fsa9480"; + reg = <0x25>; + interrupt-parent = <&gph2>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&musb_irq>; + }; + }; + + i2c_fuel: i2c-gpio-4 { compatible = "i2c-gpio"; sda-gpios = <&mp05 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&mp05 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -314,6 +422,9 @@ #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fg_i2c_pins>; + fuelgauge@36 { compatible = "maxim,max17040"; interrupt-parent = <&vic0>; @@ -322,6 +433,64 @@ }; }; + i2c_touchkey: i2c-gpio-5 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj3 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj3 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_i2c_pins>; + + touchkey@20 { + compatible = "cypress,aries-touchkey"; + reg = <0x20>; + vdd-supply = <&touchkey_vdd>; + vcc-supply = <&buck3_reg>; + linux,keycodes = <KEY_MENU KEY_BACK + KEY_HOMEPAGE KEY_SEARCH>; + interrupt-parent = <&gpj4>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_irq>; + }; + }; + + i2c_prox: i2c-gpio-6 { + compatible = "i2c-gpio"; + sda-gpios = <&gpg2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpg0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&prox_i2c_pins>; + + status = "disabled"; + + /* Sharp gp2a prox/light sensor, incomplete mainline binding */ + }; + + i2c_magnetometer: i2c-gpio-7 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&magnetometer_i2c_pins>; + + status = "disabled"; + + /* Yamaha yas529 magnetometer, no mainline binding */ + }; + vibrator: pwm-vibrator { compatible = "pwm-vibrator"; pwms = <&pwm 1 44642 0>; @@ -337,6 +506,45 @@ offset = <0x681c>; /* PS_HOLD_CONTROL */ value = <0x5200>; }; + + spi_lcd: spi-gpio-0 { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&mp04 1 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&mp04 3 GPIO_ACTIVE_HIGH>; + cs-gpios = <&mp01 1 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_spi_pins>; + + panel@0 { + compatible = "samsung,s6e63m0"; + reg = <0>; + reset-gpios = <&mp05 5 GPIO_ACTIVE_LOW>; + vdd3-supply = <&ldo7_reg>; + vci-supply = <&ldo17_reg>; + spi-cs-high; + spi-max-frequency = <1200000>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_rst>; + + port { + lcd_ep: endpoint { + remote-endpoint = <&fimd_ep>; + }; + }; + }; + }; +}; + +&adc { + vdd-supply = <&ldo4_reg>; + + status = "okay"; }; &fimd { @@ -347,18 +555,13 @@ samsung,invert-vden; samsung,invert-vclk; - display-timings { - timing-0 { - /* 480x800@60Hz */ - clock-frequency = <25628040>; - hactive = <480>; - vactive = <800>; - hfront-porch = <16>; - hback-porch = <16>; - hsync-len = <2>; - vfront-porch = <28>; - vback-porch = <1>; - vsync-len = <2>; + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + fimd_ep: endpoint { + remote-endpoint = <&lcd_ep>; }; }; }; @@ -399,12 +602,39 @@ samsung,pin-val = <1>; }; + codec_ldo: codec-ldo { + samsung,pins = "gpf3-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + }; + + prox_i2c_pins: gp2a-i2c-pins { + samsung,pins = "gpg0-2", "gpg2-2"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + wlan_gpio_rst: wlan-gpio-rst { samsung,pins = "gpg1-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; + pmic_dvs_pins: pmic-dvs-pins { + samsung,pins = "gph0-3", "gph0-4", "gph0-5"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-val = <0>; + }; + + pmic_irq: pmic-irq { + samsung,pins = "gph0-7"; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + wifi_host_wake: wifi-host-wake { samsung,pins = "gph2-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; @@ -419,6 +649,13 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; + musb_irq: musq-irq { + samsung,pins = "gph2-7"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + tf_detect: tf-detect { samsung,pins = "gph3-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; @@ -432,12 +669,85 @@ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; }; + magnetometer_i2c_pins: yas529-i2c-pins { + samsung,pins = "gpj0-0", "gpj0-1"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + ts_irq: ts-irq { samsung,pins = "gpj0-5"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; + + vibrator_ena: vibrator-ena { + samsung,pins = "gpj1-1"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + touchkey_i2c_pins: touchkey-i2c-pins { + samsung,pins = "gpj3-0", "gpj3-1"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + touchkey_vdd_ena: touchkey-vdd-ena { + samsung,pins = "gpj3-2"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + musb_i2c_pins: musb-i2c-pins { + samsung,pins = "gpj3-4", "gpj3-5"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + accel_i2c_pins: accel-i2c-pins { + samsung,pins = "gpj3-6", "gpj3-7"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + pmic_i2c_pins: pmic-i2c-pins { + samsung,pins = "gpj4-0", "gpj4-3"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + touchkey_irq: touchkey-irq { + samsung,pins = "gpj4-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + lcd_spi_pins: spi-lcd-pins { + samsung,pins = "mp01-1", "mp04-1", "mp04-3"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + fg_i2c_pins: fg-i2c-pins { + samsung,pins = "mp05-0", "mp05-1"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + sound_i2c_pins: sound-i2c-pins { + samsung,pins = "mp05-2", "mp05-3"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + panel_rst: panel-rst { + samsung,pins = "mp05-5"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; }; &pwm { @@ -454,11 +764,16 @@ pinctrl-names = "default"; cap-sd-highspeed; cap-mmc-highspeed; + keep-power-in-suspend; mmc-pwrseq = <&wifi_pwrseq>; non-removable; status = "okay"; + assigned-clocks = <&clocks MOUT_MMC1>, <&clocks SCLK_MMC1>; + assigned-clock-rates = <0>, <50000000>; + assigned-clock-parents = <&clocks MOUT_MPLL>; + wlan@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; @@ -475,6 +790,10 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &tf_detect>; pinctrl-names = "default"; status = "okay"; + + assigned-clocks = <&clocks MOUT_MMC2>, <&clocks SCLK_MMC2>; + assigned-clock-rates = <0>, <50000000>; + assigned-clock-parents = <&clocks MOUT_MPLL>; }; &uart0 { diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts index 07a8d9bbe5b8..5e1b81823a8d 100644 --- a/arch/arm/boot/dts/s5pv210-fascinate4g.dts +++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts @@ -36,3 +36,252 @@ }; }; }; + +&pinctrl0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep_cfg>; + + /* Based on vendor kernel v2.6.35.7 */ + sleep_cfg: sleep-cfg { + PIN_SLP(gpa0-0, PREV, NONE); + PIN_SLP(gpa0-1, PREV, NONE); + PIN_SLP(gpa0-2, PREV, NONE); + PIN_SLP(gpa0-3, OUT1, NONE); + PIN_SLP(gpa0-4, PREV, NONE); + PIN_SLP(gpa0-5, PREV, NONE); + PIN_SLP(gpa0-6, PREV, NONE); + PIN_SLP(gpa0-7, PREV, NONE); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, OUT0, NONE); + PIN_SLP(gpa1-2, INPUT, DOWN); + PIN_SLP(gpa1-3, OUT0, NONE); + + PIN_SLP(gpb-0, OUT0, NONE); + PIN_SLP(gpb-1, OUT1, NONE); + PIN_SLP(gpb-2, OUT0, NONE); + PIN_SLP(gpb-3, PREV, NONE); + PIN_SLP(gpb-4, INPUT, NONE); + PIN_SLP(gpb-5, PREV, NONE); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, OUT0, NONE); + + PIN_SLP(gpc0-0, OUT0, NONE); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, OUT0, NONE); + PIN_SLP(gpc0-3, INPUT, DOWN); + PIN_SLP(gpc0-4, OUT0, NONE); + + PIN_SLP(gpc1-0, INPUT, DOWN); + PIN_SLP(gpc1-1, INPUT, DOWN); + PIN_SLP(gpc1-2, INPUT, DOWN); + PIN_SLP(gpc1-3, INPUT, DOWN); + PIN_SLP(gpc1-4, INPUT, DOWN); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, OUT0, NONE); + PIN_SLP(gpd0-2, INPUT, DOWN); + PIN_SLP(gpd0-3, INPUT, DOWN); + + PIN_SLP(gpd1-0, INPUT, NONE); + PIN_SLP(gpd1-1, INPUT, NONE); + PIN_SLP(gpd1-2, INPUT, DOWN); + PIN_SLP(gpd1-3, INPUT, DOWN); + PIN_SLP(gpd1-4, INPUT, DOWN); + PIN_SLP(gpd1-5, INPUT, DOWN); + + PIN_SLP(gpe0-0, INPUT, DOWN); + PIN_SLP(gpe0-1, INPUT, DOWN); + PIN_SLP(gpe0-2, INPUT, DOWN); + PIN_SLP(gpe0-3, INPUT, DOWN); + PIN_SLP(gpe0-4, INPUT, DOWN); + PIN_SLP(gpe0-5, INPUT, DOWN); + PIN_SLP(gpe0-6, INPUT, DOWN); + PIN_SLP(gpe0-7, INPUT, DOWN); + + PIN_SLP(gpe1-0, INPUT, DOWN); + PIN_SLP(gpe1-1, INPUT, DOWN); + PIN_SLP(gpe1-2, INPUT, DOWN); + PIN_SLP(gpe1-3, OUT0, NONE); + PIN_SLP(gpe1-4, INPUT, DOWN); + + PIN_SLP(gpf0-0, OUT0, NONE); + PIN_SLP(gpf0-1, OUT0, NONE); + PIN_SLP(gpf0-2, OUT0, NONE); + PIN_SLP(gpf0-3, OUT0, NONE); + PIN_SLP(gpf0-4, OUT0, NONE); + PIN_SLP(gpf0-5, OUT0, NONE); + PIN_SLP(gpf0-6, OUT0, NONE); + PIN_SLP(gpf0-7, OUT0, NONE); + + PIN_SLP(gpf1-0, OUT0, NONE); + PIN_SLP(gpf1-1, OUT0, NONE); + PIN_SLP(gpf1-2, OUT0, NONE); + PIN_SLP(gpf1-3, OUT0, NONE); + PIN_SLP(gpf1-4, OUT0, NONE); + PIN_SLP(gpf1-5, OUT0, NONE); + PIN_SLP(gpf1-6, OUT0, NONE); + PIN_SLP(gpf1-7, OUT0, NONE); + + PIN_SLP(gpf2-0, OUT0, NONE); + PIN_SLP(gpf2-1, OUT0, NONE); + PIN_SLP(gpf2-2, OUT0, NONE); + PIN_SLP(gpf2-3, OUT0, NONE); + PIN_SLP(gpf2-4, OUT0, NONE); + PIN_SLP(gpf2-5, OUT0, NONE); + PIN_SLP(gpf2-6, OUT0, NONE); + PIN_SLP(gpf2-7, OUT0, NONE); + + PIN_SLP(gpf3-0, OUT0, NONE); + PIN_SLP(gpf3-1, OUT0, NONE); + PIN_SLP(gpf3-2, OUT0, NONE); + PIN_SLP(gpf3-3, OUT0, NONE); + PIN_SLP(gpf3-4, PREV, NONE); + PIN_SLP(gpf3-5, INPUT, DOWN); + + PIN_SLP(gpg0-0, INPUT, DOWN); + PIN_SLP(gpg0-1, INPUT, DOWN); + PIN_SLP(gpg0-2, INPUT, NONE); + PIN_SLP(gpg0-3, INPUT, DOWN); + PIN_SLP(gpg0-4, INPUT, DOWN); + PIN_SLP(gpg0-5, INPUT, DOWN); + PIN_SLP(gpg0-6, INPUT, DOWN); + + PIN_SLP(gpg1-0, OUT0, NONE); + PIN_SLP(gpg1-1, OUT1, NONE); + PIN_SLP(gpg1-2, PREV, NONE); + PIN_SLP(gpg1-3, OUT1, NONE); + PIN_SLP(gpg1-4, OUT1, NONE); + PIN_SLP(gpg1-5, OUT1, NONE); + PIN_SLP(gpg1-6, OUT1, NONE); + + PIN_SLP(gpg2-0, OUT0, NONE); + PIN_SLP(gpg2-1, OUT0, NONE); + PIN_SLP(gpg2-2, INPUT, NONE); + PIN_SLP(gpg2-3, OUT0, NONE); + PIN_SLP(gpg2-4, OUT0, NONE); + PIN_SLP(gpg2-5, OUT0, NONE); + PIN_SLP(gpg2-6, OUT0, NONE); + + PIN_SLP(gpg3-0, PREV, UP); + PIN_SLP(gpg3-1, PREV, UP); + PIN_SLP(gpg3-2, INPUT, NONE); + PIN_SLP(gpg3-3, INPUT, DOWN); + PIN_SLP(gpg3-4, OUT0, NONE); + PIN_SLP(gpg3-5, OUT0, NONE); + PIN_SLP(gpg3-6, INPUT, DOWN); + + PIN_SLP(gpi-0, PREV, NONE); + PIN_SLP(gpi-1, INPUT, DOWN); + PIN_SLP(gpi-2, PREV, NONE); + PIN_SLP(gpi-3, PREV, NONE); + PIN_SLP(gpi-4, PREV, NONE); + PIN_SLP(gpi-5, INPUT, DOWN); + PIN_SLP(gpi-6, INPUT, DOWN); + + PIN_SLP(gpj0-0, INPUT, NONE); + PIN_SLP(gpj0-1, INPUT, NONE); + PIN_SLP(gpj0-2, INPUT, NONE); + PIN_SLP(gpj0-3, INPUT, NONE); + PIN_SLP(gpj0-4, INPUT, NONE); + PIN_SLP(gpj0-5, INPUT, DOWN); + PIN_SLP(gpj0-6, OUT0, NONE); + PIN_SLP(gpj0-7, INPUT, NONE); + + PIN_SLP(gpj1-0, OUT1, NONE); + PIN_SLP(gpj1-1, OUT0, NONE); + PIN_SLP(gpj1-2, INPUT, DOWN); + PIN_SLP(gpj1-3, PREV, NONE); + PIN_SLP(gpj1-4, PREV, NONE); + PIN_SLP(gpj1-5, OUT0, NONE); + + PIN_SLP(gpj2-0, INPUT, DOWN); + PIN_SLP(gpj2-1, INPUT, DOWN); + PIN_SLP(gpj2-2, OUT0, NONE); + PIN_SLP(gpj2-3, INPUT, DOWN); + PIN_SLP(gpj2-4, INPUT, DOWN); + PIN_SLP(gpj2-5, PREV, NONE); + PIN_SLP(gpj2-6, PREV, NONE); + PIN_SLP(gpj2-7, INPUT, DOWN); + + PIN_SLP(gpj3-0, INPUT, NONE); + PIN_SLP(gpj3-1, INPUT, NONE); + PIN_SLP(gpj3-2, OUT0, NONE); + PIN_SLP(gpj3-3, INPUT, DOWN); + PIN_SLP(gpj3-4, INPUT, NONE); + PIN_SLP(gpj3-5, INPUT, NONE); + PIN_SLP(gpj3-6, INPUT, NONE); + PIN_SLP(gpj3-7, INPUT, NONE); + + PIN_SLP(gpj4-0, INPUT, NONE); + PIN_SLP(gpj4-1, INPUT, DOWN); + PIN_SLP(gpj4-2, PREV, NONE); + PIN_SLP(gpj4-3, INPUT, NONE); + PIN_SLP(gpj4-4, INPUT, DOWN); + + PIN_SLP(mp01-0, OUT1, NONE); + PIN_SLP(mp01-1, OUT0, NONE); + PIN_SLP(mp01-2, INPUT, DOWN); + PIN_SLP(mp01-3, INPUT, DOWN); + PIN_SLP(mp01-4, OUT1, NONE); + PIN_SLP(mp01-5, INPUT, DOWN); + PIN_SLP(mp01-6, INPUT, DOWN); + PIN_SLP(mp01-7, INPUT, DOWN); + + PIN_SLP(mp02-0, INPUT, DOWN); + PIN_SLP(mp02-1, INPUT, DOWN); + PIN_SLP(mp02-2, INPUT, NONE); + PIN_SLP(mp02-3, INPUT, DOWN); + + PIN_SLP(mp03-0, INPUT, DOWN); + PIN_SLP(mp03-1, INPUT, DOWN); + PIN_SLP(mp03-2, OUT1, NONE); + PIN_SLP(mp03-3, OUT0, NONE); + PIN_SLP(mp03-4, INPUT, NONE); + PIN_SLP(mp03-5, OUT0, NONE); + PIN_SLP(mp03-6, INPUT, DOWN); + PIN_SLP(mp03-7, INPUT, DOWN); + + PIN_SLP(mp04-0, INPUT, DOWN); + PIN_SLP(mp04-1, OUT0, NONE); + PIN_SLP(mp04-2, INPUT, DOWN); + PIN_SLP(mp04-3, OUT0, NONE); + PIN_SLP(mp04-4, INPUT, DOWN); + PIN_SLP(mp04-5, INPUT, DOWN); + PIN_SLP(mp04-6, OUT0, NONE); + PIN_SLP(mp04-7, INPUT, DOWN); + + PIN_SLP(mp05-0, INPUT, NONE); + PIN_SLP(mp05-1, INPUT, NONE); + PIN_SLP(mp05-2, INPUT, NONE); + PIN_SLP(mp05-3, INPUT, NONE); + PIN_SLP(mp05-4, INPUT, DOWN); + PIN_SLP(mp05-5, OUT0, NONE); + PIN_SLP(mp05-6, INPUT, DOWN); + PIN_SLP(mp05-7, PREV, NONE); + + PIN_SLP(mp06-0, INPUT, DOWN); + PIN_SLP(mp06-1, INPUT, DOWN); + PIN_SLP(mp06-2, INPUT, DOWN); + PIN_SLP(mp06-3, INPUT, DOWN); + PIN_SLP(mp06-4, INPUT, DOWN); + PIN_SLP(mp06-5, INPUT, DOWN); + PIN_SLP(mp06-6, INPUT, DOWN); + PIN_SLP(mp06-7, INPUT, DOWN); + + PIN_SLP(mp07-0, INPUT, DOWN); + PIN_SLP(mp07-1, INPUT, DOWN); + PIN_SLP(mp07-2, INPUT, DOWN); + PIN_SLP(mp07-3, INPUT, DOWN); + PIN_SLP(mp07-4, INPUT, DOWN); + PIN_SLP(mp07-5, INPUT, DOWN); + PIN_SLP(mp07-6, INPUT, DOWN); + PIN_SLP(mp07-7, INPUT, DOWN); + }; +}; + +&wm8994 { + /* GPIO3 (BCLK2) and GPIO4 (LRCLK2) as outputs */ + wlf,gpio-cfg = <0xa101 0x8100 0x8100 0x8100 0x8100 0xa101 + 0x0100 0x8100 0x0100 0x0100 0x0100>; +}; diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts index cf161bbfbacf..5d10dd67eacc 100644 --- a/arch/arm/boot/dts/s5pv210-galaxys.dts +++ b/arch/arm/boot/dts/s5pv210-galaxys.dts @@ -49,15 +49,303 @@ wakeup-source; }; }; + + i2c_fmradio: i2c-gpio-8 { + compatible = "i2c-gpio"; + sda-gpios = <&gpd1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpd1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&fm_i2c_pins>; + + fmradio@10 { + compatible = "silabs,si470x"; + reg = <0x10>; + interrupt-parent = <&gpj2>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpj2 5 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&fm_irq &fm_rst>; + }; + }; +}; + +&aliases { + i2c8 = &i2c_fmradio; }; &pinctrl0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep_cfg>; + + fm_i2c_pins: fm-i2c-pins { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + fm_irq: fm-irq { + samsung,pins = "gpj2-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_UP>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + fm_rst: fm-rst { + samsung,pins = "gpj2-5"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + massmemory_en: massmemory-en { samsung,pins = "gpj2-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; + + /* Based on CyanogenMod 3.0.101 kernel */ + sleep_cfg: sleep-cfg { + PIN_SLP(gpa0-0, PREV, NONE); + PIN_SLP(gpa0-1, PREV, NONE); + PIN_SLP(gpa0-2, PREV, NONE); + PIN_SLP(gpa0-3, OUT1, NONE); + PIN_SLP(gpa0-4, INPUT, DOWN); + PIN_SLP(gpa0-5, OUT0, NONE); + PIN_SLP(gpa0-6, INPUT, DOWN); + PIN_SLP(gpa0-7, OUT1, NONE); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, OUT0, NONE); + PIN_SLP(gpa1-2, INPUT, NONE); + PIN_SLP(gpa1-3, OUT0, NONE); + + PIN_SLP(gpb-0, OUT0, NONE); + PIN_SLP(gpb-1, OUT1, NONE); + PIN_SLP(gpb-2, OUT0, NONE); + PIN_SLP(gpb-3, PREV, NONE); + PIN_SLP(gpb-4, INPUT, NONE); + PIN_SLP(gpb-5, PREV, NONE); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, OUT0, NONE); + + PIN_SLP(gpc0-0, OUT0, NONE); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, OUT0, NONE); + PIN_SLP(gpc0-3, INPUT, NONE); + PIN_SLP(gpc0-4, OUT0, NONE); + + PIN_SLP(gpc1-0, INPUT, DOWN); + PIN_SLP(gpc1-1, INPUT, DOWN); + PIN_SLP(gpc1-2, INPUT, DOWN); + PIN_SLP(gpc1-3, INPUT, DOWN); + PIN_SLP(gpc1-4, INPUT, DOWN); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, OUT0, NONE); + PIN_SLP(gpd0-2, INPUT, DOWN); + PIN_SLP(gpd0-3, INPUT, DOWN); + + PIN_SLP(gpd1-0, INPUT, NONE); + PIN_SLP(gpd1-1, INPUT, NONE); + PIN_SLP(gpd1-2, INPUT, NONE); + PIN_SLP(gpd1-3, INPUT, NONE); + PIN_SLP(gpd1-4, INPUT, DOWN); + PIN_SLP(gpd1-5, INPUT, DOWN); + + PIN_SLP(gpe0-0, INPUT, DOWN); + PIN_SLP(gpe0-1, INPUT, DOWN); + PIN_SLP(gpe0-2, INPUT, DOWN); + PIN_SLP(gpe0-3, INPUT, DOWN); + PIN_SLP(gpe0-4, INPUT, DOWN); + PIN_SLP(gpe0-5, INPUT, DOWN); + PIN_SLP(gpe0-6, INPUT, DOWN); + PIN_SLP(gpe0-7, INPUT, DOWN); + + PIN_SLP(gpe1-0, INPUT, DOWN); + PIN_SLP(gpe1-1, INPUT, DOWN); + PIN_SLP(gpe1-2, INPUT, DOWN); + PIN_SLP(gpe1-3, OUT0, NONE); + PIN_SLP(gpe1-4, INPUT, DOWN); + + PIN_SLP(gpf0-0, OUT0, NONE); + PIN_SLP(gpf0-1, OUT0, NONE); + PIN_SLP(gpf0-2, OUT0, NONE); + PIN_SLP(gpf0-3, OUT0, NONE); + PIN_SLP(gpf0-4, OUT0, NONE); + PIN_SLP(gpf0-5, OUT0, NONE); + PIN_SLP(gpf0-6, OUT0, NONE); + PIN_SLP(gpf0-7, OUT0, NONE); + + PIN_SLP(gpf1-0, OUT0, NONE); + PIN_SLP(gpf1-1, OUT0, NONE); + PIN_SLP(gpf1-2, OUT0, NONE); + PIN_SLP(gpf1-3, OUT0, NONE); + PIN_SLP(gpf1-4, OUT0, NONE); + PIN_SLP(gpf1-5, OUT0, NONE); + PIN_SLP(gpf1-6, OUT0, NONE); + PIN_SLP(gpf1-7, OUT0, NONE); + + PIN_SLP(gpf2-0, OUT0, NONE); + PIN_SLP(gpf2-1, OUT0, NONE); + PIN_SLP(gpf2-2, OUT0, NONE); + PIN_SLP(gpf2-3, OUT0, NONE); + PIN_SLP(gpf2-4, OUT0, NONE); + PIN_SLP(gpf2-5, OUT0, NONE); + PIN_SLP(gpf2-6, OUT0, NONE); + PIN_SLP(gpf2-7, OUT0, NONE); + + PIN_SLP(gpf3-0, OUT0, NONE); + PIN_SLP(gpf3-1, OUT0, NONE); + PIN_SLP(gpf3-2, OUT0, NONE); + PIN_SLP(gpf3-3, OUT0, NONE); + PIN_SLP(gpf3-4, PREV, NONE); + PIN_SLP(gpf3-5, INPUT, DOWN); + + PIN_SLP(gpg0-0, OUT0, NONE); + PIN_SLP(gpg0-1, INPUT, NONE); + PIN_SLP(gpg0-2, INPUT, NONE); + PIN_SLP(gpg0-3, INPUT, NONE); + PIN_SLP(gpg0-4, INPUT, NONE); + PIN_SLP(gpg0-5, INPUT, NONE); + PIN_SLP(gpg0-6, INPUT, NONE); + + PIN_SLP(gpg1-0, OUT0, NONE); + PIN_SLP(gpg1-1, OUT1, NONE); + PIN_SLP(gpg1-2, PREV, NONE); + PIN_SLP(gpg1-3, OUT1, NONE); + PIN_SLP(gpg1-4, OUT1, NONE); + PIN_SLP(gpg1-5, OUT1, NONE); + PIN_SLP(gpg1-6, OUT1, NONE); + + PIN_SLP(gpg2-0, OUT0, NONE); + PIN_SLP(gpg2-1, OUT0, NONE); + PIN_SLP(gpg2-2, INPUT, NONE); + PIN_SLP(gpg2-3, OUT0, NONE); + PIN_SLP(gpg2-4, OUT0, NONE); + PIN_SLP(gpg2-5, OUT0, NONE); + PIN_SLP(gpg2-6, OUT0, NONE); + + PIN_SLP(gpg3-0, OUT1, NONE); + PIN_SLP(gpg3-1, OUT0, NONE); + PIN_SLP(gpg3-2, INPUT, NONE); + PIN_SLP(gpg3-3, INPUT, DOWN); + PIN_SLP(gpg3-4, OUT0, NONE); + PIN_SLP(gpg3-5, OUT0, NONE); + PIN_SLP(gpg3-6, INPUT, DOWN); + + PIN_SLP(gpi-0, PREV, NONE); + PIN_SLP(gpi-1, INPUT, DOWN); + PIN_SLP(gpi-2, PREV, NONE); + PIN_SLP(gpi-3, PREV, NONE); + PIN_SLP(gpi-4, PREV, NONE); + PIN_SLP(gpi-5, INPUT, DOWN); + PIN_SLP(gpi-6, INPUT, DOWN); + + PIN_SLP(gpj0-0, INPUT, NONE); + PIN_SLP(gpj0-1, INPUT, NONE); + PIN_SLP(gpj0-2, INPUT, NONE); + PIN_SLP(gpj0-3, INPUT, NONE); + PIN_SLP(gpj0-4, INPUT, NONE); + PIN_SLP(gpj0-5, INPUT, DOWN); + PIN_SLP(gpj0-6, OUT0, NONE); + PIN_SLP(gpj0-7, INPUT, NONE); + + PIN_SLP(gpj1-0, INPUT, DOWN); + PIN_SLP(gpj1-1, OUT0, NONE); + PIN_SLP(gpj1-2, INPUT, DOWN); + PIN_SLP(gpj1-3, PREV, NONE); + PIN_SLP(gpj1-4, PREV, NONE); + PIN_SLP(gpj1-5, OUT0, NONE); + + PIN_SLP(gpj2-0, INPUT, DOWN); + PIN_SLP(gpj2-1, INPUT, DOWN); + PIN_SLP(gpj2-2, OUT0, NONE); + PIN_SLP(gpj2-3, INPUT, DOWN); + PIN_SLP(gpj2-4, INPUT, UP); + PIN_SLP(gpj2-5, PREV, NONE); + PIN_SLP(gpj2-6, PREV, NONE); + PIN_SLP(gpj2-7, OUT1, NONE); + + PIN_SLP(gpj3-0, INPUT, NONE); + PIN_SLP(gpj3-1, INPUT, NONE); + PIN_SLP(gpj3-2, OUT0, NONE); + PIN_SLP(gpj3-3, INPUT, DOWN); + PIN_SLP(gpj3-4, INPUT, NONE); + PIN_SLP(gpj3-5, INPUT, NONE); + PIN_SLP(gpj3-6, INPUT, NONE); + PIN_SLP(gpj3-7, INPUT, NONE); + + PIN_SLP(gpj4-0, INPUT, NONE); + PIN_SLP(gpj4-1, INPUT, DOWN); + PIN_SLP(gpj4-2, PREV, NONE); + PIN_SLP(gpj4-3, INPUT, NONE); + PIN_SLP(gpj4-4, INPUT, DOWN); + + PIN_SLP(mp01-0, INPUT, DOWN); + PIN_SLP(mp01-1, OUT0, NONE); + PIN_SLP(mp01-2, INPUT, DOWN); + PIN_SLP(mp01-3, INPUT, DOWN); + PIN_SLP(mp01-4, OUT1, NONE); + PIN_SLP(mp01-5, INPUT, DOWN); + PIN_SLP(mp01-6, INPUT, DOWN); + PIN_SLP(mp01-7, INPUT, DOWN); + + PIN_SLP(mp02-0, INPUT, DOWN); + PIN_SLP(mp02-1, INPUT, DOWN); + PIN_SLP(mp02-2, INPUT, NONE); + PIN_SLP(mp02-3, INPUT, DOWN); + + PIN_SLP(mp03-0, INPUT, DOWN); + PIN_SLP(mp03-1, INPUT, DOWN); + PIN_SLP(mp03-2, OUT1, NONE); + PIN_SLP(mp03-3, OUT0, NONE); + PIN_SLP(mp03-4, INPUT, NONE); + PIN_SLP(mp03-5, OUT1, NONE); + PIN_SLP(mp03-6, INPUT, DOWN); + PIN_SLP(mp03-7, INPUT, DOWN); + + PIN_SLP(mp04-0, INPUT, DOWN); + PIN_SLP(mp04-1, OUT0, NONE); + PIN_SLP(mp04-2, INPUT, DOWN); + PIN_SLP(mp04-3, OUT0, NONE); + PIN_SLP(mp04-4, INPUT, DOWN); + PIN_SLP(mp04-5, INPUT, DOWN); + PIN_SLP(mp04-6, OUT0, NONE); + PIN_SLP(mp04-7, INPUT, DOWN); + + PIN_SLP(mp05-0, INPUT, NONE); + PIN_SLP(mp05-1, INPUT, NONE); + PIN_SLP(mp05-2, INPUT, NONE); + PIN_SLP(mp05-3, INPUT, NONE); + PIN_SLP(mp05-4, INPUT, DOWN); + PIN_SLP(mp05-5, OUT0, NONE); + PIN_SLP(mp05-6, INPUT, DOWN); + PIN_SLP(mp05-7, PREV, NONE); + + PIN_SLP(mp06-0, INPUT, DOWN); + PIN_SLP(mp06-1, INPUT, DOWN); + PIN_SLP(mp06-2, INPUT, DOWN); + PIN_SLP(mp06-3, INPUT, DOWN); + PIN_SLP(mp06-4, INPUT, DOWN); + PIN_SLP(mp06-5, INPUT, DOWN); + PIN_SLP(mp06-6, INPUT, DOWN); + PIN_SLP(mp06-7, INPUT, DOWN); + + PIN_SLP(mp07-0, INPUT, DOWN); + PIN_SLP(mp07-1, INPUT, DOWN); + PIN_SLP(mp07-2, INPUT, DOWN); + PIN_SLP(mp07-3, INPUT, DOWN); + PIN_SLP(mp07-4, INPUT, DOWN); + PIN_SLP(mp07-5, INPUT, DOWN); + PIN_SLP(mp07-6, INPUT, DOWN); + PIN_SLP(mp07-7, INPUT, DOWN); + }; }; &sdhci0 { @@ -67,4 +355,8 @@ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; pinctrl-names = "default"; status = "okay"; + + assigned-clocks = <&clocks MOUT_MMC0>, <&clocks SCLK_MMC0>; + assigned-clock-rates = <0>, <52000000>; + assigned-clock-parents = <&clocks MOUT_MPLL>; }; diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi index 7f0c9d447871..5e8b66281f01 100644 --- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi @@ -18,6 +18,13 @@ #include <dt-bindings/pinctrl/samsung.h> +#define PIN_SLP(_pin, _mode, _pull) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \ + samsung,pin-pud-pdn = <S3C64XX_PIN_PULL_ ##_pull>; \ + } + &pinctrl0 { gpa0: gpa0 { gpio-controller; @@ -195,7 +202,7 @@ #interrupt-cells = <2>; }; - gpgi: gpgi { + gpi: gpi { gpio-controller; #gpio-cells = <2>; }; diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 2ad642f51fd9..1b0ee884e91d 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -159,6 +159,18 @@ }; }; + adc: adc@e1700000 { + compatible = "samsung,s5pv210-adc"; + reg = <0xe1700000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <23>, <24>; + clocks = <&clocks CLK_TSADC>; + clock-names = "adc"; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; + }; + spi0: spi@e1300000 { compatible = "samsung,s5pv210-spi"; reg = <0xe1300000 0x1000>; @@ -614,7 +626,7 @@ clock-names = "fimc", "sclk_fimc"; samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; + samsung,min-pix-alignment = <16 8>; samsung,cam-if; }; @@ -628,8 +640,10 @@ clock-names = "fimc", "sclk_fimc"; samsung,pix-limits = <4224 8192 1920 4224>; + samsung,min-pix-alignment = <1 1>; samsung,mainscaler-ext; samsung,cam-if; + samsung,lcd-wb; }; fimc2: fimc@fb400000 { @@ -641,9 +655,10 @@ <&clocks SCLK_FIMC2>; clock-names = "fimc", "sclk_fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,lcd-wb; + samsung,pix-limits = <1920 8192 1280 1920>; + samsung,min-pix-alignment = <16 8>; + samsung,rotators = <0>; + samsung,cam-if; }; }; diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index 326b39328b58..6763423d64b8 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -686,6 +686,14 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&clk32k 0>; }; + + watchdog: watchdog@ffffff80 { + compatible = "microchip,sam9x60-wdt"; + reg = <0xffffff80 0x24>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k 0>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 2012b7407c60..c0a3ca8f9bf7 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -21,10 +21,6 @@ aliases { serial0 = &uart1; serial1 = &uart3; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2s0 = &i2s0; - i2s1 = &i2s1; }; cpus { @@ -635,6 +631,64 @@ #size-cells = <1>; ranges = <0x0 0xf8034000 0x800>; status = "disabled"; + + uart5: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi2: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c2: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx1: flexcom@f8038000 { @@ -645,6 +699,64 @@ #size-cells = <1>; ranges = <0x0 0xf8038000 0x800>; status = "disabled"; + + uart6: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi3: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c3: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; securam: sram@f8044000 { @@ -695,7 +807,7 @@ }; rtc: rtc@f80480b0 { - compatible = "atmel,at91rm9200-rtc"; + compatible = "atmel,sama5d2-rtc"; reg = <0xf80480b0 0x30>; interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&clk32k>; @@ -794,6 +906,64 @@ #size-cells = <1>; ranges = <0x0 0xfc010000 0x800>; status = "disabled"; + + uart7: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi4: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c4: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx3: flexcom@fc014000 { @@ -804,6 +974,65 @@ #size-cells = <1>; ranges = <0x0 0xfc014000 0x800>; status = "disabled"; + + uart8: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi5: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c5: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; flx4: flexcom@fc018000 { @@ -814,6 +1043,64 @@ #size-cells = <1>; ranges = <0x0 0xfc018000 0x800>; status = "disabled"; + + uart9: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi6: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c6: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; trng@fc01c000 { diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 203d40be70a5..c53e48445e4d 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -108,7 +108,7 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; clock-names = "mci_clk"; }; @@ -123,7 +123,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; clock-names = "spi_clk"; status = "disabled"; }; @@ -137,7 +137,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; clock-names = "pclk"; status = "disabled"; }; @@ -148,7 +148,7 @@ #size-cells = <0>; reg = <0xf0010000 0x100>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; @@ -159,11 +159,14 @@ dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; dma-names = "tx", "rx"; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; status = "disabled"; }; @@ -174,11 +177,14 @@ dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; dma-names = "tx", "rx"; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&pioC 26 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioC 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; status = "disabled"; }; @@ -191,7 +197,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "usart"; status = "disabled"; }; @@ -205,7 +211,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names = "usart"; status = "disabled"; }; @@ -216,7 +222,7 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; clock-names = "usart"; status = "disabled"; }; @@ -226,7 +232,7 @@ reg = <0xf002c000 0x300>; interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; #pwm-cells = <3>; - clocks = <&pwm_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; status = "disabled"; }; @@ -236,7 +242,7 @@ interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_isi_data_0_7>; - clocks = <&isi_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; clock-names = "isi_clk"; status = "disabled"; port { @@ -261,7 +267,7 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; clock-names = "mci_clk"; }; @@ -276,7 +282,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; clock-names = "spi_clk"; status = "disabled"; }; @@ -290,7 +296,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; clock-names = "pclk"; status = "disabled"; }; @@ -317,7 +323,7 @@ &pinctrl_adc0_ad10 &pinctrl_adc0_ad11 >; - clocks = <&adc_clk>, + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&adc_op_clk>; clock-names = "adc_clk", "adc_op_clk"; atmel,adc-channels-used = <0xfff>; @@ -357,11 +363,14 @@ dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; dma-names = "tx", "rx"; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&pioA 18 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; status = "disabled"; }; @@ -374,7 +383,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "usart"; status = "disabled"; }; @@ -388,7 +397,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; clock-names = "usart"; status = "disabled"; }; @@ -399,7 +408,7 @@ interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; dma-names = "tx"; - clocks = <&sha_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; clock-names = "sha_clk"; }; @@ -410,7 +419,7 @@ dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; dma-names = "tx", "rx"; - clocks = <&aes_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; clock-names = "aes_clk"; }; @@ -421,7 +430,7 @@ dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; dma-names = "tx", "rx"; - clocks = <&tdes_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; clock-names = "tdes_clk"; }; @@ -429,14 +438,14 @@ compatible = "atmel,at91sam9g45-trng"; reg = <0xf8040000 0x100>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&trng_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; }; hsmc: hsmc@ffffc000 { compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; reg = <0xffffc000 0x1000>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; - clocks = <&hsmc_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -453,7 +462,7 @@ reg = <0xffffe600 0x200>; interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; - clocks = <&dma0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; clock-names = "dma_clk"; }; @@ -462,14 +471,14 @@ reg = <0xffffe800 0x200>; interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; - clocks = <&dma1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 31>; clock-names = "dma_clk"; }; ramc0: ramc@ffffea00 { compatible = "atmel,sama5d3-ddramc"; reg = <0xffffea00 0x200>; - clocks = <&ddrck>, <&mpddr_clk>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>; clock-names = "ddrck", "mpddr"; }; @@ -482,7 +491,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&dbgu_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; clock-names = "usart"; status = "disabled"; }; @@ -639,6 +648,12 @@ <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ }; + + pinctrl_i2c0_gpio: i2c0-gpio { + atmel,pins = + <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; }; i2c1 { @@ -647,6 +662,12 @@ <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ }; + + pinctrl_i2c1_gpio: i2c1-gpio { + atmel,pins = + <AT91_PIOC 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + AT91_PIOC 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; }; i2c2 { @@ -655,6 +676,12 @@ <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */ AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ }; + + pinctrl_i2c2_gpio: i2c2-gpio { + atmel,pins = + <AT91_PIOA 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + AT91_PIOA 19 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; }; isi { @@ -940,7 +967,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioA_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; }; pioB: gpio@fffff400 { @@ -951,7 +978,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; }; pioC: gpio@fffff600 { @@ -962,7 +989,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioC_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; }; pioD: gpio@fffff800 { @@ -973,7 +1000,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioD_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; }; pioE: gpio@fffffa00 { @@ -984,7 +1011,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioE_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; }; }; @@ -992,353 +1019,9 @@ compatible = "atmel,sama5d3-pmc", "syscon"; reg = <0xfffffc00 0x120>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = <AT91_PMC_MOSCRCS>; - clock-frequency = <12000000>; - clock-accuracy = <50000000>; - }; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = <AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = <AT91_PMC_MOSCSELS>; - clocks = <&main_rc_osc &main_osc>; - }; - - plla: pllack { - compatible = "atmel,sama5d3-clk-pll"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = <AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <8000000 50000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = <AT91_PMC_LOCKU>; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91sam9x5-clk-master"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = <AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; - atmel,clk-output-range = <0 166000000>; - atmel,clk-divisors = <1 2 4 3>; - }; - - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - prog: progck { - compatible = "atmel,at91sam9x5-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = <AT91_PMC_PCKRDY(0)>; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = <AT91_PMC_PCKRDY(1)>; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = <AT91_PMC_PCKRDY(2)>; - }; - }; - - smd: smdclk { - compatible = "atmel,at91sam9x5-clk-smd"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - smdck: smdck { - #clock-cells = <0>; - reg = <4>; - clocks = <&smd>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - }; - - periphck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - dbgu_clk: dbgu_clk { - #clock-cells = <0>; - reg = <2>; - }; - - hsmc_clk: hsmc_clk { - #clock-cells = <0>; - reg = <5>; - }; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <6>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <7>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <8>; - }; - - pioD_clk: pioD_clk { - #clock-cells = <0>; - reg = <9>; - }; - - pioE_clk: pioE_clk { - #clock-cells = <0>; - reg = <10>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <12>; - atmel,clk-output-range = <0 83000000>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <13>; - atmel,clk-output-range = <0 83000000>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <14>; - atmel,clk-output-range = <0 83000000>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <15>; - atmel,clk-output-range = <0 83000000>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <16>; - atmel,clk-output-range = <0 83000000>; - }; - - twi0_clk: twi0_clk { - reg = <18>; - #clock-cells = <0>; - atmel,clk-output-range = <0 41500000>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <19>; - atmel,clk-output-range = <0 41500000>; - }; - - twi2_clk: twi2_clk { - #clock-cells = <0>; - reg = <20>; - atmel,clk-output-range = <0 41500000>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <21>; - }; - - mci1_clk: mci1_clk { - #clock-cells = <0>; - reg = <22>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <24>; - atmel,clk-output-range = <0 166000000>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <25>; - atmel,clk-output-range = <0 166000000>; - }; - - tcb0_clk: tcb0_clk { - #clock-cells = <0>; - reg = <26>; - atmel,clk-output-range = <0 166000000>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <28>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <29>; - atmel,clk-output-range = <0 83000000>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <30>; - }; - - dma1_clk: dma1_clk { - #clock-cells = <0>; - reg = <31>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <32>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <33>; - }; - - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <37>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <38>; - atmel,clk-output-range = <0 83000000>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <39>; - atmel,clk-output-range = <0 83000000>; - }; - - sha_clk: sha_clk { - #clock-cells = <0>; - reg = <42>; - }; - - aes_clk: aes_clk { - #clock-cells = <0>; - reg = <43>; - }; - - tdes_clk: tdes_clk { - #clock-cells = <0>; - reg = <44>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <45>; - }; - - fuse_clk: fuse_clk { - #clock-cells = <0>; - reg = <48>; - }; - - mpddr_clk: mpddr_clk { - #clock-cells = <0>; - reg = <49>; - }; - }; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; }; reset_controller: rstc@fffffe00 { @@ -1357,7 +1040,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; watchdog: watchdog@fffffe40 { @@ -1399,7 +1082,7 @@ reg = <0x00500000 0x100000 0xf8030000 0x4000>; interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udphs_clk>, <&utmi>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>, <&pmc PMC_TYPE_CORE PMC_UTMI>; clock-names = "pclk", "hclk"; status = "disabled"; @@ -1513,7 +1196,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_SYSTEM 6>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -1522,7 +1205,7 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 32>; clock-names = "usb_clk", "ehci_clk"; status = "disabled"; }; @@ -1538,7 +1221,7 @@ 0x1 0x0 0x40000000 0x10000000 0x2 0x0 0x50000000 0x10000000 0x3 0x0 0x60000000 0x10000000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; status = "disabled"; nand_controller: nand-controller { diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi index 2470dd3fff25..9ac29bf3f933 100644 --- a/arch/arm/boot/dts/sama5d3_can.dtsi +++ b/arch/arm/boot/dts/sama5d3_can.dtsi @@ -31,29 +31,13 @@ }; - pmc: pmc@fffffc00 { - periphck { - can0_clk: can0_clk { - #clock-cells = <0>; - reg = <40>; - atmel,clk-output-range = <0 83000000>; - }; - - can1_clk: can1_clk { - #clock-cells = <0>; - reg = <41>; - atmel,clk-output-range = <0 83000000>; - }; - }; - }; - can0: can@f000c000 { compatible = "atmel,at91sam9x5-can"; reg = <0xf000c000 0x300>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_rx_tx>; - clocks = <&can0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; clock-names = "can_clk"; status = "disabled"; }; @@ -64,7 +48,7 @@ interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_rx_tx>; - clocks = <&can1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; clock-names = "can_clk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi index 9aef414bcd2e..45226108850d 100644 --- a/arch/arm/boot/dts/sama5d3_emac.dtsi +++ b/arch/arm/boot/dts/sama5d3_emac.dtsi @@ -31,12 +31,6 @@ }; pmc: pmc@fffffc00 { - periphck { - macb1_clk: macb1_clk { - #clock-cells = <0>; - reg = <35>; - }; - }; }; macb1: ethernet@f802c000 { @@ -45,7 +39,7 @@ interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb1_rmii>; - clocks = <&macb1_clk>, <&macb1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_PERIPHERAL 35>; clock-names = "hclk", "pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi index 3667765a138b..884df7a54dbb 100644 --- a/arch/arm/boot/dts/sama5d3_gmac.dtsi +++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi @@ -63,22 +63,13 @@ }; }; - pmc: pmc@fffffc00 { - periphck { - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <34>; - }; - }; - }; - macb0: ethernet@f0028000 { compatible = "atmel,sama5d3-gem"; reg = <0xf0028000 0x100>; interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; - clocks = <&macb0_clk>, <&macb0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_PERIPHERAL 34>; clock-names = "hclk", "pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi index 2cf046cd4e99..308d2fc276d6 100644 --- a/arch/arm/boot/dts/sama5d3_lcd.dtsi +++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi @@ -16,7 +16,7 @@ compatible = "atmel,sama5d3-hlcdc"; reg = <0xf0030000 0x2000>; interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; clock-names = "periph_clk","sys_clk", "slow_clk"; status = "disabled"; @@ -192,23 +192,6 @@ }; }; }; - - pmc: pmc@fffffc00 { - periphck { - lcdc_clk: lcdc_clk { - #clock-cells = <0>; - reg = <36>; - }; - }; - - systemck { - lcdck: lcdck { - #clock-cells = <0>; - reg = <3>; - clocks = <&mck>; - }; - }; - }; }; }; }; diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi index 3c83c1c36ac8..7141ee97ec3e 100644 --- a/arch/arm/boot/dts/sama5d3_mci2.dtsi +++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi @@ -30,15 +30,6 @@ }; }; - pmc: pmc@fffffc00 { - periphck { - mci2_clk: mci2_clk { - #clock-cells = <0>; - reg = <23>; - }; - }; - }; - mmc2: mmc@f8004000 { compatible = "atmel,hsmci"; reg = <0xf8004000 0x600>; @@ -47,7 +38,7 @@ dma-names = "rxtx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; - clocks = <&mci2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "mci_clk"; status = "disabled"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi index 215802b8db30..2b18c5c2cc03 100644 --- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi +++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi @@ -17,23 +17,13 @@ ahb { apb { - pmc: pmc@fffffc00 { - periphck { - tcb1_clk: tcb1_clk { - #clock-cells = <0>; - reg = <27>; - atmel,clk-output-range = <0 166000000>; - }; - }; - }; - tcb1: timer@f8014000 { compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; #address-cells = <1>; #size-cells = <0>; reg = <0xf8014000 0x100>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb1_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; }; diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi index cb62adbd28ed..a3eaba995cf4 100644 --- a/arch/arm/boot/dts/sama5d3_uart.dtsi +++ b/arch/arm/boot/dts/sama5d3_uart.dtsi @@ -36,29 +36,13 @@ }; }; - pmc: pmc@fffffc00 { - periphck { - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <16>; - atmel,clk-output-range = <0 83000000>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <17>; - atmel,clk-output-range = <0 83000000>; - }; - }; - }; - uart0: serial@f0024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf0024000 0x100>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; clock-names = "usart"; status = "disabled"; }; @@ -69,7 +53,7 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; clock-names = "usart"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index 35031bbc7e70..a499de8a7a64 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -46,7 +46,7 @@ wm8904: wm8904@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - clocks = <&pck0>; + clocks = <&pmc PMC_TYPE_SYSTEM 8>; clock-names = "mclk"; }; }; @@ -60,9 +60,9 @@ resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; /* use pck1 for the master clock of ov2640 */ - clocks = <&pck1>; + clocks = <&pmc PMC_TYPE_SYSTEM 9>; clock-names = "xvclk"; - assigned-clocks = <&pck1>; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; assigned-clock-rates = <25000000>; port { diff --git a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi index 8a6916a69da4..fa9e5e2a745d 100644 --- a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi @@ -45,7 +45,7 @@ wm8904: wm8904@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - clocks = <&pck0>; + clocks = <&pmc PMC_TYPE_SYSTEM 8>; clock-names = "mclk"; }; }; @@ -59,9 +59,9 @@ resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; /* use pck1 for the master clock of ov2640 */ - clocks = <&pck1>; + clocks = <&pmc PMC_TYPE_SYSTEM 9>; clock-names = "xvclk"; - assigned-clocks = <&pck1>; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; assigned-clock-rates = <25000000>; port { diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 6ab27a7b388d..fff679734c9c 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -458,8 +458,11 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(3))>; dma-names = "tx", "rx"; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; @@ -477,8 +480,11 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(5))>; dma-names = "tx", "rx"; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioE 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; @@ -519,8 +525,11 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(7))>; dma-names = "tx", "rx"; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&pioB 29 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioB 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; @@ -884,7 +893,7 @@ }; rtc@fc0686b0 { - compatible = "atmel,at91rm9200-rtc"; + compatible = "atmel,sama5d4-rtc"; reg = <0xfc0686b0 0x30>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&clk32k>; @@ -1122,6 +1131,12 @@ <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; }; + + pinctrl_i2c0_gpio: i2c0-gpio { + atmel,pins = + <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; }; i2c1 { @@ -1130,6 +1145,12 @@ <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */ AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */ }; + + pinctrl_i2c1_gpio: i2c1-gpio { + atmel,pins = + <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + AT91_PIOE 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; }; i2c2 { @@ -1138,6 +1159,12 @@ <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */ AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */ }; + + pinctrl_i2c2_gpio: i2c2-gpio { + atmel,pins = + <AT91_PIOB 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + AT91_PIOB 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; }; isi { diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts index 1916f31a30ff..5a8d92a061df 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts @@ -25,12 +25,9 @@ cpus { cpu@0 { cpu0-supply = <&vdd_dvfs>; - operating-points = < - /* kHz uV */ - 1196000 1315000 - 598000 1175000 - 398667 1065000 - >; + operating-points = <1196000 1315000>, /* kHz uV */ + < 598000 1175000>, + < 398667 1065000>; voltage-tolerance = <1>; /* 1% */ }; }; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index c134154bcce8..01fd06328420 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -99,7 +99,7 @@ }; cmt1: timer@e6138000 { - compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; + compatible = "renesas,sh73a0-cmt1"; reg = <0xe6138000 0x200>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_CMT1>; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 4f3993cc0227..c2b54af417a2 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -531,6 +531,7 @@ reg = <0xff400000 0x100000>; resets = <&rst LWHPS2FPGA_RESET>; clocks = <&l4_main_clk>; + status = "disabled"; }; fpga_bridge1: fpga_bridge@ff500000 { @@ -538,6 +539,21 @@ reg = <0xff500000 0x10000>; resets = <&rst HPS2FPGA_RESET>; clocks = <&l4_main_clk>; + status = "disabled"; + }; + + fpga_bridge2: fpga-bridge@ff600000 { + compatible = "altr,socfpga-fpga2hps-bridge"; + reg = <0xff600000 0x100000>; + resets = <&rst FPGA2HPS_RESET>; + clocks = <&l4_main_clk>; + status = "disabled"; + }; + + fpga_bridge3: fpga-bridge@ffc25080 { + compatible = "altr,socfpga-fpga2sdram-bridge"; + reg = <0xffc25080 0x4>; + status = "disabled"; }; fpgamgr0: fpgamgr@ff706000 { diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 2a86e72d9791..3b8571b8b412 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -431,8 +431,8 @@ snps,perfect-filter-entries = <128>; tx-fifo-depth = <4096>; rx-fifo-depth = <16384>; - clocks = <&l4_mp_clk>; - clock-names = "stmmaceth"; + clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; + clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; @@ -451,8 +451,8 @@ snps,perfect-filter-entries = <128>; tx-fifo-depth = <4096>; rx-fifo-depth = <16384>; - clocks = <&l4_mp_clk>; - clock-names = "stmmaceth"; + clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; + clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; @@ -471,8 +471,8 @@ snps,perfect-filter-entries = <128>; tx-fifo-depth = <4096>; rx-fifo-depth = <16384>; - clocks = <&l4_mp_clk>; - clock-names = "stmmaceth"; + clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; + clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts index 9bd9e04c7361..9aa897b79544 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts @@ -16,11 +16,11 @@ partition@0 { label = "Boot and fpga data"; - reg = <0x0 0x1C00000>; + reg = <0x0 0x02000000>; }; partition@1c00000 { label = "Root Filesystem - JFFS2"; - reg = <0x1C00000 0x6400000>; + reg = <0x02000000 0x06000000>; }; }; }; diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/ste-ab8500.dtsi index 14d4d8617d75..3cd6ee6d50e0 100644 --- a/arch/arm/boot/dts/ste-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-ab8500.dtsi @@ -314,13 +314,13 @@ mcde@a0350000 { vana-supply = <&ab8500_ldo_ana_reg>; - dsi@a0351000 { + dsi-controller@a0351000 { vana-supply = <&ab8500_ldo_ana_reg>; }; - dsi@a0352000 { + dsi-controller@a0352000 { vana-supply = <&ab8500_ldo_ana_reg>; }; - dsi@a0353000 { + dsi-controller@a0353000 { vana-supply = <&ab8500_ldo_ana_reg>; }; }; diff --git a/arch/arm/boot/dts/ste-ab8505.dtsi b/arch/arm/boot/dts/ste-ab8505.dtsi index c72aa250bf6f..67bc69e67b33 100644 --- a/arch/arm/boot/dts/ste-ab8505.dtsi +++ b/arch/arm/boot/dts/ste-ab8505.dtsi @@ -261,13 +261,13 @@ mcde@a0350000 { vana-supply = <&ab8500_ldo_ana_reg>; - dsi@a0351000 { + dsi-controller@a0351000 { vana-supply = <&ab8500_ldo_ana_reg>; }; - dsi@a0352000 { + dsi-controller@a0352000 { vana-supply = <&ab8500_ldo_ana_reg>; }; - dsi@a0353000 { + dsi-controller@a0353000 { vana-supply = <&ab8500_ldo_ana_reg>; }; }; diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 6671f74c9f03..3e10da3f8fd3 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -1097,7 +1097,7 @@ ranges; status = "disabled"; - dsi0: dsi@a0351000 { + dsi0: dsi-controller@a0351000 { compatible = "ste,mcde-dsi"; reg = <0xa0351000 0x1000>; clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>; @@ -1105,7 +1105,7 @@ #address-cells = <1>; #size-cells = <0>; }; - dsi1: dsi@a0352000 { + dsi1: dsi-controller@a0352000 { compatible = "ste,mcde-dsi"; reg = <0xa0352000 0x1000>; clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>; @@ -1113,7 +1113,7 @@ #address-cells = <1>; #size-cells = <0>; }; - dsi2: dsi@a0353000 { + dsi2: dsi-controller@a0353000 { compatible = "ste,mcde-dsi"; reg = <0xa0353000 0x1000>; /* This DSI port only has the Low Power / Energy Save clock */ diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi index e32d0c36feb8..b8fd8f18ba16 100644 --- a/arch/arm/boot/dts/ste-href-stuib.dtsi +++ b/arch/arm/boot/dts/ste-href-stuib.dtsi @@ -199,7 +199,7 @@ mcde@a0350000 { status = "okay"; - dsi@a0351000 { + dsi-controller@a0351000 { panel { compatible = "samsung,s6d16d0"; reg = <0>; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi index e024520f4d47..de82b9db956f 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi @@ -66,7 +66,7 @@ mcde@a0350000 { status = "okay"; - dsi@a0351000 { + dsi-controller@a0351000 { panel { compatible = "samsung,s6d16d0"; reg = <0>; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi index cb3677f0a1cb..9f285c7cf914 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi @@ -45,7 +45,7 @@ mcde@a0350000 { status = "okay"; - dsi@a0351000 { + dsi-controller@a0351000 { panel { compatible = "sony,acx424akp"; reg = <0>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index 313f0ab16866..5b499c0b2745 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -24,6 +24,26 @@ stdout-path = &serial2; }; + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_1_default>; + + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@c { + compatible = "alps,hscdtd008a"; + reg = <0x0c>; + + avdd-supply = <&ab8500_ldo_aux1_reg>; + dvdd-supply = <&ab8500_ldo_aux8_reg>; + }; + }; + soc { /* External Micro SD card slot */ sdi0_per1@80126000 { @@ -146,6 +166,32 @@ pinctrl-1 = <&u2rxtx_c_1_sleep>; }; + i2c@80004000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + + proximity@44 { + compatible = "sharp,gp2ap002s00f"; + reg = <0x44>; + + /* GPIO146 (PS_INT) */ + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&ab8500_ldo_aux1_reg>; + vio-supply = <&ab8500_ldo_aux8_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&proximity_default>; + + sharp,proximity-far-hysteresis = <0x40>; + sharp,proximity-close-hysteresis = <0x0f>; + }; + }; + i2c@80128000 { status = "okay"; @@ -357,6 +403,16 @@ }; }; + i2c-gpio-1 { + i2c_gpio_1_default: i2c_gpio_1 { + golden_cfg1 { + pins = "GPIO151", /* COMP_SCL */ + "GPIO152"; /* COMP_SDA */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + sdi0 { sd_level_translator_default: sd_level_translator_default { golden_cfg1 { @@ -375,6 +431,15 @@ }; }; + proximity { + proximity_default: proximity_default { + golden_cfg1 { + pins = "GPIO146_D13"; /* PS_INT */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + imu { imu_default: imu_default { golden_cfg1 { diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts new file mode 100644 index 000000000000..8edef161613a --- /dev/null +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -0,0 +1,616 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Devicetree for the Samsung XCover 2 GT-S7710 also known as Skomer. + */ + +/dts-v1/; +#include "ste-db8500.dtsi" +#include "ste-ab8505.dtsi" +#include "ste-dbx5x0-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "Samsung XCover 2 (GT-S7710)"; + compatible = "samsung,skomer", "st-ericsson,u8500"; + + chosen { + stdout-path = &serial2; + }; + + /* TI TXS0206 level translator for 2.9 V */ + sd_level_translator: regulator-gpio { + compatible = "regulator-fixed"; + + /* GPIO87 EN */ + gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-name = "sd-level-translator"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + + startup-delay-us = <200>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_level_translator_default>; + }; + + /* External LDO MIC5366-3.3YMT for eMMC */ + ldo_3v3_reg: regulator-gpio-ldo-3v3 { + compatible = "regulator-fixed"; + regulator-name = "en-3v3-fixed-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_ldo_en_default_mode>; + }; + + wlan_en: regulator-gpio-wlan-en { + compatible = "regulator-fixed"; + regulator-name = "wl-reg-on"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + startup-delay-us = <200000>; + /* GPIO215 WLAN_EN */ + gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_default_mode>; + }; + + vibrator { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_default>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default_mode>; + + button-home { + linux,code = <KEY_HOME>; + label = "HOME"; + /* GPIO91 */ + gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + }; + button-volup { + linux,code = <KEY_VOLUMEUP>; + label = "VOL+"; + /* GPIO67 */ + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + }; + button-voldown { + linux,code = <KEY_VOLUMEDOWN>; + label = "VOL-"; + /* GPIO92 */ + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; + button-menu { + linux,code = <KEY_MENU>; + label = "MENU"; + /* GPIO204 */ + gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; + }; + button-back { + linux,code = <KEY_BACK>; + label = "BACK"; + /* GPIO205 */ + gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; + }; + }; + + /* + * FIXME: this is not quite GPIO backlight. This is a + * KTD253 one-wire GPIO-controlled backlight. It can + * work as a GPIO backlight. + */ + gpio_bl: backlight { + compatible = "gpio-backlight"; + /* GPIO 69 */ + gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_backlight_default_mode>; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_0_default>; + #address-cells = <1>; + #size-cells = <0>; + /* TODO: this should be used by the NCP6914 Camera power management unit */ + }; + + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_1_default>; + #address-cells = <1>; + #size-cells = <0>; + magnetometer@c { + compatible = "alps,hscdtd008a"; + reg = <0x0c>; + avdd-supply = <&ab8500_ldo_aux1_reg>; + dvdd-supply = <&ab8500_ldo_aux8_reg>; + }; + }; + + soc { + // External Micro SD slot + sdi0_per1@80126000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + /* All direction control is used */ + st,sig-dir-cmd; + st,sig-dir-dat0; + st,sig-dir-dat2; + st,sig-dir-dat31; + st,sig-pin-fbclk; + full-pwr-cycle; + vmmc-supply = <&ab8500_ldo_aux3_reg>; + vqmmc-supply = <&sd_level_translator>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc0_a_1_default>; + pinctrl-1 = <&mc0_a_1_sleep>; + status = "okay"; + }; + + // WLAN SDIO channel + sdi1_per2@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <4>; + non-removable; + cap-sd-highspeed; + vmmc-supply = <&wlan_en>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc1_a_2_default>; + pinctrl-1 = <&mc1_a_2_sleep>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + /* GPIO216 WL_HOST_WAKE */ + interrupt-parent = <&gpio6>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_mode>; + }; + }; + + // eMMC + sdi2_per3@80005000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + non-removable; + cap-mmc-highspeed; + mmc-ddr-1_8v; + vmmc-supply = <&ldo_3v3_reg>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mc2_a_1_default>; + pinctrl-1 = <&mc2_a_1_sleep>; + + status = "okay"; + }; + + /* GBF (Bluetooth) UART */ + uart@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u0_a_1_default>; + pinctrl-1 = <&u0_a_1_sleep>; + status = "okay"; + + /* FIXME: not quite working yet, probably needs regulators */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_mode>; + }; + }; + + /* GPF UART */ + uart@80121000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; + pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; + }; + + /* Debugging console UART connected to AB8505 USB */ + uart@80007000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&u2rxtx_c_1_default>; + pinctrl-1 = <&u2rxtx_c_1_sleep>; + }; + + prcmu@80157000 { + ab8505 { + ab8500_usb { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usb_a_1_default>; + pinctrl-1 = <&usb_a_1_sleep>; + }; + + ab8505-regulators { + ab8500_ldo_aux1 { + /* Used for VDD for sensors */ + regulator-name = "AUX1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux2 { + /* Supplies the Cypress TMA140 touchscreen only with 3.3V */ + regulator-name = "AUX2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux3 { + /* Used for voltage for external MMC/SD card */ + regulator-name = "AUX3"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <3300000>; + }; + + ab8500_ldo_aux4 { + regulator-name = "AUX4"; + /* Hammer to 3.0V for the display */ + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ab8500_ldo_aux5 { + regulator-name = "AUX5"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <2790000>; + regulator-always-on; + }; + + ab8500_ldo_aux6 { + regulator-name = "AUX6"; + /* Hammer to 1.8V for the display */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ab8500_ldo_aux8 { + /* Mostly VIO for sensors */ + regulator-name = "AUX8"; + }; + }; + }; + }; + + /* I2C0 */ + i2c@80004000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + + proximity@44 { + compatible = "sharp,gp2ap002s00f"; + clock-frequency = <400000>; + reg = <0x44>; + + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vio-supply = <&ab8500_ldo_aux8_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&gp2ap002_skomer_default>; + sharp,proximity-far-hysteresis = /bits/ 8 <0x2f>; + sharp,proximity-close-hysteresis = /bits/ 8 <0x0f>; + }; + }; + + + /* I2C2 */ + i2c@80128000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_b_2_default>; + pinctrl-1 = <&i2c2_b_2_sleep>; + + accel@18 { + compatible = "bosch,bma254"; + clock-frequency = <400000>; + reg = <0x18>; + + /* GPIO224 used as "smart alert" interrupt */ + interrupt-parent = <&gpio7>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + vdd-supply = <&ab8500_ldo_aux1_reg>; + vddio-supply = <&ab8500_ldo_aux8_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&bma254_skomer_default>; + }; + }; + + /* I2C3 */ + i2c@80110000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_c_2_default>; + pinctrl-1 = <&i2c3_c_2_sleep>; + + /* Cypress CY8CTMA140 touchscreen */ + touchscreen@20 { + compatible = "cypress,cy8ctma140"; + clock-frequency = <400000>; + reg = <0x20>; + + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + touchscreen-max-pressure = <255>; + + /* GPIO218 for IRQ */ + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + + /* VDD is "digital supply" nominally 1.71-3.6V */ + vdd-supply = <&ab8500_ldo_aux2_reg>; + /* VCPIN is "analog supply", 2.7-3.6 V */ + vcpin-supply = <&ab8500_ldo_aux2_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&tma140_skomer_default>; + }; + }; + + mcde@a0350000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dsi_default_mode>; + + dsi-controller@a0351000 { + panel { + /* NT35510-based Hydis HVA40WV1 */ + compatible = "hydis,hva40wv1", "novatek,nt35510"; + reg = <0>; + /* v_lcd_3v0 2.3-4.8V */ + vdd-supply = <&ab8500_ldo_aux4_reg>; + /* v_lcd_1v8 1.65-3.3V */ + vddi-supply = <&ab8500_ldo_aux6_reg>; + /* GPIO 139 */ + reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&display_default_mode>; + backlight = <&gpio_bl>; + }; + }; + }; + }; +}; + +&pinctrl { + /* + * This extends the MC0 default config to include DAT32DIR + * which is used by this machine. If we don't do this the + * SD card does not work. + */ + sdi0 { + mc0_a_1_default { + default_mux { + function = "mc0"; + /* This machine uses the DAT31 pin */ + groups = "mc0_a_1", "mc0dat31dir_a_1"; + }; + default_cfg5 { + pins = "GPIO21_AB3"; /* DAT31DIR */ + ste,config = <&out_hi>; + }; + }; + }; + + mcde { + dsi_default_mode: dsi_default { + default_mux1 { + /* Mux in VSI0 used for DSI TE */ + function = "lcd"; + groups = "lcdvsi0_a_1"; /* VSI0 for LCD */ + }; + default_cfg1 { + pins = "GPIO68_E1"; /* VSI0 */ + ste,config = <&in_nopull>; + }; + }; + }; + + /* Two GPIO lines used by the display */ + display { + display_default_mode: display_default { + skomer_cfg1 { + /* + * OLED DETECT or check_pba, this appears to be high + * on "PBA" which I guess is "prototype board A". + */ + pins = "GPIO93_B7"; + ste,config = <&gpio_in_nopull>; + }; + skomer_cfg2 { + pins = "GPIO139_C9"; + /* + * MIPI_DSI0_RESET_N resets the display, leave high + * (de-asserted) so we only assert reset explicitly + * from the display driver. + */ + ste,config = <&gpio_out_hi>; + }; + }; + }; + backlight { + gpio_backlight_default_mode: backlight_default { + skomer_cfg1 { + pins = "GPIO69_E2"; /* LCD_BL_CTRL */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* GPIO that enables the 2.9V SD card level translator */ + sd-level-translator { + sd_level_translator_default: sd_level_translator_default { + /* level shifter on GPIO87 */ + skomer_cfg1 { + pins = "GPIO87_B3"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO that enables the LDO regulator for the eMMC */ + emmc-ldo { + emmc_ldo_en_default_mode: emmc_ldo_default { + /* LDO enable on GPIO223 */ + skomer_cfg1 { + pins = "GPIO223_AH9"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + /* GPIO keys */ + gpio-keys { + gpio_keys_default_mode: gpio_keys_default { + skomer_cfg1 { + pins = "GPIO67_G2", /* VOL UP */ + "GPIO91_B6", /* HOME */ + "GPIO92_D6", /* VOL DOWN */ + "GPIO204_AF23", /* MENU */ + "GPIO205_AG23"; /* BACK */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + /* Interrupt line for BMA254 */ + bma254 { + bma254_skomer_default: bma254_skomer { + skomer_cfg1 { + pins = "GPIO224_AG9"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + /* Interrupt line for light/proximity sensor GP2AP002 */ + gp2ap002 { + gp2ap002_skomer_default: gp2ap002_skomer { + skomer_cfg1 { + pins = "GPIO146_D13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for NCP6914 */ + i2c-gpio-0 { + i2c_gpio_0_default: i2c_gpio_0 { + skomer_cfg1 { + pins = "GPIO143_D12", "GPIO144_B13"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + /* GPIO-based I2C bus for ALPS HSCD compass */ + i2c-gpio-1 { + i2c_gpio_1_default: i2c_gpio_1 { + skomer_cfg1 { + pins = "GPIO151_B17", "GPIO152_D16"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + wlan { + wlan_default_mode: wlan_default { + skomer_cfg1 { + pins = "GPIO216_AG12"; + ste,config = <&gpio_in_pd>; + }; + }; + wlan_en_default_mode: wlan_en_default { + skomer_cfg2 { + pins = "GPIO215_AH13"; + ste,config = <&gpio_out_lo>; + }; + }; + }; + bluetooth { + bluetooth_default_mode: bluetooth_default { + skomer_cfg1 { + pins = "GPIO199_AH23", "GPIO222_AJ9"; + ste,config = <&gpio_out_lo>; + }; + skomer_cfg2 { + pins = "GPIO97_D9"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; + vibrator { + vibrator_default: vibrator_default { + skomer_cfg1 { + pins = "GPIO195_AG28"; /* MOT_EN */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + /* Interrupt line for the Cypress TMA140 touchscreen */ + touchscreen { + tma140_skomer_default: tma140_skomer { + skomer_cfg1 { + pins = "GPIO218_AH11"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; +}; + +&ab8505_gpio { + /* Hog a few default settings */ + pinctrl-names = "default"; + pinctrl-0 = <&gpio_default>; + + gpio { + gpio_default: gpio_default { + skomer_mux { + /* Change unused pins to GPIO mode */ + function = "gpio"; + groups = "gpio3_a_1", /* default: SysClkReq4 */ + "gpio14_a_1"; /* default: PWMOut1 */ + }; + skomer_cfg1 { + pins = "GPIO11_B17", "GPIO13_D17", "GPIO50_L4"; + bias-disable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 7c36c37260a4..23a1746f3baa 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -767,20 +767,6 @@ <&clk_s_c0_flexgen CLK_ETH_PHY>; }; - rng10: rng@8a89000 { - compatible = "st,rng"; - reg = <0x08a89000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - rng11: rng@8a8a000 { - compatible = "st,rng"; - reg = <0x08a8a000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - mailbox0: mailbox@8f00000 { compatible = "st,stih407-mailbox"; reg = <0x8f00000 0x1000>; diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts index 4fbd8e9eb5b7..e2bb59783146 100644 --- a/arch/arm/boot/dts/stih410-b2260.dts +++ b/arch/arm/boot/dts/stih410-b2260.dts @@ -178,9 +178,6 @@ phy-mode = "rgmii"; pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>; - snps,phy-bus-name = "stmmac"; - snps,phy-bus-id = <0>; - snps,phy-addr = <0>; snps,reset-gpio = <&pio0 7 0>; snps,reset-active-low; snps,reset-delays-us = <0 10000 1000000>; diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi index 83411322bd92..a05e2278b448 100644 --- a/arch/arm/boot/dts/stih418.dtsi +++ b/arch/arm/boot/dts/stih418.dtsi @@ -50,7 +50,7 @@ ohci0: usb@9a03c00 { compatible = "st,st-ohci-300x"; reg = <0x9a03c00 0x100>; - interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, <&softreset STIH407_USB2_PORT0_SOFTRESET>; @@ -62,7 +62,7 @@ ehci0: usb@9a03e00 { compatible = "st,st-ehci-300x"; reg = <0x9a03e00 0x100>; - interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; @@ -76,7 +76,7 @@ ohci1: usb@9a83c00 { compatible = "st,st-ohci-300x"; reg = <0x9a83c00 0x100>; - interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, <&softreset STIH407_USB2_PORT1_SOFTRESET>; @@ -88,7 +88,7 @@ ehci1: usb@9a83e00 { compatible = "st,st-ehci-300x"; reg = <0x9a83e00 0x100>; - interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index 60e11045ad76..d051f080e52e 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -46,7 +46,7 @@ /* DAC */ format = "i2s"; mclk-fs = <256>; - frame-inversion = <1>; + frame-inversion; cpu { sound-dai = <&sti_uni_player2>; }; diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts index fcc804e3c158..4ea3f98dd275 100644 --- a/arch/arm/boot/dts/stm32746g-eval.dts +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -165,7 +165,7 @@ interrupts = <8 IRQ_TYPE_EDGE_RISING>; interrupt-parent = <&gpioi>; - stmfx_pinctrl: stmfx-pin-controller { + stmfx_pinctrl: pinctrl { compatible = "st,stmfx-0300-pinctrl"; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index d7770699feb5..393f43c85a3c 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -414,14 +414,14 @@ dac1: dac@1 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <1>; status = "disabled"; }; dac2: dac@2 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 05eb02e6d083..9b7fc68380e9 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -180,14 +180,14 @@ dac1: dac@1 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <1>; status = "disabled"; }; dac2: dac@2 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 0237d4ddaa92..7eb858732d6d 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -6,7 +6,7 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { - adc1_in6_pins_a: adc1-in6 { + adc1_in6_pins_a: adc1-in6-0 { pins { pinmux = <STM32_PINMUX('F', 12, ANALOG)>; }; @@ -21,6 +21,13 @@ }; }; + adc12_ain_pins_b: adc12-ain-1 { + pins { + pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ + <STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */ + }; + }; + adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { pins { pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */ @@ -37,7 +44,7 @@ }; }; - cec_pins_sleep_a: cec-sleep-0 { + cec_sleep_pins_a: cec-sleep-0 { pins { pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */ }; @@ -52,19 +59,19 @@ }; }; - cec_pins_sleep_b: cec-sleep-1 { + cec_sleep_pins_b: cec-sleep-1 { pins { pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */ }; }; - dac_ch1_pins_a: dac-ch1 { + dac_ch1_pins_a: dac-ch1-0 { pins { pinmux = <STM32_PINMUX('A', 4, ANALOG)>; }; }; - dac_ch2_pins_a: dac-ch2 { + dac_ch2_pins_a: dac-ch2-0 { pins { pinmux = <STM32_PINMUX('A', 5, ANALOG)>; }; @@ -142,7 +149,7 @@ }; }; - ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 { + ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 { pins1 { pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ @@ -162,6 +169,142 @@ }; }; + ethernet0_rgmii_pins_b: rgmii-1 { + pins1 { + pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 { + pins1 { + pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ + }; + }; + + ethernet0_rgmii_pins_c: rgmii-2 { + pins1 { + pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 { + pins1 { + pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ + }; + }; + + ethernet0_rmii_pins_a: rmii-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_sleep_pins_a: rmii-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ @@ -216,14 +359,14 @@ }; }; - i2c1_pins_sleep_a: i2c1-1 { + i2c1_sleep_pins_a: i2c1-sleep-0 { pins { pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ }; }; - i2c1_pins_b: i2c1-2 { + i2c1_pins_b: i2c1-1 { pins { pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ @@ -233,7 +376,7 @@ }; }; - i2c1_pins_sleep_b: i2c1-3 { + i2c1_sleep_pins_b: i2c1-sleep-1 { pins { pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ @@ -250,14 +393,14 @@ }; }; - i2c2_pins_sleep_a: i2c2-1 { + i2c2_sleep_pins_a: i2c2-sleep-0 { pins { pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */ <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ }; }; - i2c2_pins_b1: i2c2-2 { + i2c2_pins_b1: i2c2-1 { pins { pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ bias-disable; @@ -266,12 +409,29 @@ }; }; - i2c2_pins_sleep_b1: i2c2-3 { + i2c2_sleep_pins_b1: i2c2-sleep-1 { pins { pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ }; }; + i2c2_pins_c: i2c2-2 { + pins { + pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */ + <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_pins_sleep_c: i2c2-sleep-2 { + pins { + pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */ + <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ + }; + }; + i2c5_pins_a: i2c5-0 { pins { pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */ @@ -282,7 +442,7 @@ }; }; - i2c5_pins_sleep_a: i2c5-1 { + i2c5_sleep_pins_a: i2c5-sleep-0 { pins { pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */ <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */ @@ -290,6 +450,23 @@ }; }; + i2c5_pins_b: i2c5-1 { + pins { + pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */ + <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_b: i2c5-sleep-1 { + pins { + pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */ + <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */ + }; + }; + i2s2_pins_a: i2s2-0 { pins { pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ @@ -301,7 +478,7 @@ }; }; - i2s2_pins_sleep_a: i2s2-1 { + i2s2_sleep_pins_a: i2s2-sleep-0 { pins { pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */ <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */ @@ -309,7 +486,7 @@ }; }; - ltdc_pins_a: ltdc-a-0 { + ltdc_pins_a: ltdc-0 { pins { pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ @@ -345,7 +522,7 @@ }; }; - ltdc_pins_sleep_a: ltdc-a-1 { + ltdc_sleep_pins_a: ltdc-sleep-0 { pins { pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ @@ -378,7 +555,7 @@ }; }; - ltdc_pins_b: ltdc-b-0 { + ltdc_pins_b: ltdc-1 { pins { pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ @@ -414,7 +591,7 @@ }; }; - ltdc_pins_sleep_b: ltdc-b-1 { + ltdc_sleep_pins_b: ltdc-sleep-1 { pins { pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */ <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */ @@ -447,6 +624,142 @@ }; }; + ltdc_pins_c: ltdc-2 { + pins1 { + pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */ + <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */ + <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */ + <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */ + <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */ + <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */ + <STM32_PINMUX('E', 11, AF14)>, /* LTDC_G3 */ + <STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */ + <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */ + <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */ + <STM32_PINMUX('H', 4, AF9)>, /* LTDC_G5 */ + <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */ + <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */ + <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */ + <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */ + <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */ + <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */ + <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */ + <STM32_PINMUX('I', 6, AF14)>, /* LTDC_B6 */ + <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */ + <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 14, AF14)>; /* LTDC_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_sleep_pins_c: ltdc-sleep-2 { + pins1 { + pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */ + <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */ + <STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */ + <STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */ + <STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */ + <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */ + <STM32_PINMUX('E', 11, ANALOG)>, /* LTDC_G3 */ + <STM32_PINMUX('E', 12, ANALOG)>, /* LTDC_B4 */ + <STM32_PINMUX('E', 13, ANALOG)>, /* LTDC_DE */ + <STM32_PINMUX('E', 15, ANALOG)>, /* LTDC_R7 */ + <STM32_PINMUX('H', 4, ANALOG)>, /* LTDC_G5 */ + <STM32_PINMUX('H', 8, ANALOG)>, /* LTDC_R2 */ + <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */ + <STM32_PINMUX('H', 10, ANALOG)>, /* LTDC_R4 */ + <STM32_PINMUX('H', 13, ANALOG)>, /* LTDC_G2 */ + <STM32_PINMUX('H', 15, ANALOG)>, /* LTDC_G4 */ + <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */ + <STM32_PINMUX('I', 5, ANALOG)>, /* LTDC_B5 */ + <STM32_PINMUX('I', 6, ANALOG)>, /* LTDC_B6 */ + <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */ + <STM32_PINMUX('I', 10, ANALOG)>, /* LTDC_HSYNC */ + <STM32_PINMUX('E', 14, ANALOG)>; /* LTDC_CLK */ + }; + }; + + ltdc_pins_d: ltdc-3 { + pins1 { + pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LCD_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ + <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ + <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */ + <STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */ + <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ + <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ + <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ + <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */ + <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */ + <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ + <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ + <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ + <STM32_PINMUX('B', 0, AF14)>, /* LCD_G1 */ + <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ + <STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */ + <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ + <STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */ + <STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */ + <STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */ + <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ + <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ + <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ + <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ + <STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */ + <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ + <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ + <STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + ltdc_sleep_pins_d: ltdc-sleep-3 { + pins { + pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ + <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ + <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ + <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */ + <STM32_PINMUX('G', 13, ANALOG)>, /* LCD_R0 */ + <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ + <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ + <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ + <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */ + <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */ + <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ + <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ + <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ + <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_G1 */ + <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ + <STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */ + <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ + <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */ + <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */ + <STM32_PINMUX('G', 8, ANALOG)>, /* LCD_G7 */ + <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ + <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ + <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ + <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ + <STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */ + <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ + <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ + <STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ @@ -467,6 +780,46 @@ }; }; + m_can1_pins_b: m-can1-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can1_sleep_pins_b: m_can1-sleep-1 { + pins { + pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */ + <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */ + }; + }; + + m_can2_pins_a: m-can2-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */ + bias-disable; + }; + }; + + m_can2_sleep_pins_a: m_can2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */ + <STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */ + }; + }; + pwm1_pins_a: pwm1-0 { pins { pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */ @@ -516,6 +869,21 @@ }; }; + pwm3_pins_b: pwm3-1 { + pins { + pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm3_sleep_pins_b: pwm3-sleep-1 { + pins { + pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* TIM3_CH2 */ + }; + }; + pwm4_pins_a: pwm4-0 { pins { pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */ @@ -563,6 +931,25 @@ }; }; + pwm5_pins_b: pwm5-1 { + pins { + pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */ + <STM32_PINMUX('H', 12, AF2)>, /* TIM5_CH3 */ + <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm5_sleep_pins_b: pwm5-sleep-1 { + pins { + pinmux = <STM32_PINMUX('H', 11, ANALOG)>, /* TIM5_CH2 */ + <STM32_PINMUX('H', 12, ANALOG)>, /* TIM5_CH3 */ + <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */ + }; + }; + pwm8_pins_a: pwm8-0 { pins { pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */ @@ -676,7 +1063,7 @@ }; }; - sai2a_sleep_pins_a: sai2a-1 { + sai2a_sleep_pins_a: sai2a-sleep-0 { pins { pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ @@ -685,6 +1072,45 @@ }; }; + + sai2a_pins_b: sai2a-1 { + pins1 { + pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ + <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ + <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai2a_sleep_pins_b: sai2a-sleep-1 { + pins { + pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ + <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ + <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */ + }; + }; + + sai2a_pins_c: sai2a-4 { + pins { + pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */ + <STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */ + <STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai2a_sleep_pins_c: sai2a-5 { + pins { + pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */ + <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */ + <STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */ + }; + }; + sai2b_pins_a: sai2b-0 { pins1 { pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */ @@ -700,7 +1126,7 @@ }; }; - sai2b_sleep_pins_a: sai2b-1 { + sai2b_sleep_pins_a: sai2b-sleep-0 { pins { pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */ <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */ @@ -709,14 +1135,27 @@ }; }; - sai2b_pins_b: sai2b-2 { + sai2b_pins_b: sai2b-1 { pins { pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ bias-disable; }; }; - sai2b_sleep_pins_b: sai2b-3 { + sai2b_sleep_pins_b: sai2b-sleep-1 { + pins { + pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ + }; + }; + + sai2b_pins_c: sai2a-4 { + pins1 { + pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ + bias-disable; + }; + }; + + sai2b_sleep_pins_c: sai2a-sleep-5 { pins { pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ }; @@ -731,7 +1170,7 @@ }; }; - sai4a_sleep_pins_a: sai4a-1 { + sai4a_sleep_pins_a: sai4a-sleep-0 { pins { pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */ }; @@ -815,6 +1254,30 @@ }; }; + sdmmc1_dir_pins_b: sdmmc1-dir-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ + <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { + pins { + pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ + <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ + <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ + }; + }; + sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins1 { pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ @@ -933,6 +1396,48 @@ }; }; + sdmmc2_d47_pins_b: sdmmc2-d47-1 { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { + pins { + pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ + }; + }; + + sdmmc2_d47_pins_c: sdmmc2-d47-2 { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 { + pins { + pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ + }; + }; + sdmmc3_b4_pins_a: sdmmc3-b4-0 { pins1 { pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ @@ -987,6 +1492,60 @@ }; }; + sdmmc3_b4_pins_b: sdmmc3-b4-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ + <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ + <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ + <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + pins3 { + pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { + pins { + pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ + <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ + <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ + <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */ + }; + }; + spdifrx_pins_a: spdifrx-0 { pins { pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ @@ -994,12 +1553,88 @@ }; }; - spdifrx_sleep_pins_a: spdifrx-1 { + spdifrx_sleep_pins_a: spdifrx-sleep-0 { pins { pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */ }; }; + spi2_pins_a: spi2-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI1_SCK */ + <STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */ + bias-disable; + }; + }; + + usart2_pins_a: usart2-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ + <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ + <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ + <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ + }; + }; + + usart2_pins_b: usart2-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ + <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */ + <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_sleep_pins_b: usart2-sleep-1 { + pins { + pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ + <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */ + <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ + }; + }; + + usart3_pins_a: usart3-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ + bias-disable; + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ @@ -1026,6 +1661,19 @@ }; }; + uart4_pins_c: uart4-2 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + uart7_pins_a: uart7-0 { pins1 { pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */ @@ -1040,6 +1688,45 @@ bias-disable; }; }; + + uart7_pins_b: uart7-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */ + bias-disable; + }; + }; + + uart8_pins_a: uart8-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */ + bias-disable; + }; + }; + + usbotg_hs_pins_a: usbotg-hs-0 { + pins { + pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ + }; + }; + + usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { + pins { + pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */ + <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */ + }; + }; }; &pinctrl_z { @@ -1052,7 +1739,7 @@ }; }; - i2c2_pins_sleep_b2: i2c2-1 { + i2c2_sleep_pins_b2: i2c2-sleep-0 { pins { pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */ }; @@ -1068,7 +1755,7 @@ }; }; - i2c4_pins_sleep_a: i2c4-1 { + i2c4_sleep_pins_a: i2c4-sleep-0 { pins { pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */ <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */ @@ -1089,4 +1776,18 @@ bias-disable; }; }; + + spi4_pins_a: spi4-0 { + pins { + pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */ + <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */ + bias-disable; + }; + }; }; diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index fb41d0778b00..36f38a95b4de 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -17,16 +17,15 @@ cpu0: cpu@0 { compatible = "arm,cortex-a7"; + clock-frequency = <650000000>; device_type = "cpu"; reg = <0>; }; }; psci { - compatible = "arm,psci"; + compatible = "arm,psci-1.0"; method = "smc"; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; }; intc: interrupt-controller@a0021000 { @@ -474,7 +473,7 @@ }; i2c1: i2c@40012000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x40012000 0x400>; interrupt-names = "event", "error"; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, @@ -483,11 +482,13 @@ resets = <&rcc I2C1_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x1>; + wakeup-source; status = "disabled"; }; i2c2: i2c@40013000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x40013000 0x400>; interrupt-names = "event", "error"; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, @@ -496,11 +497,13 @@ resets = <&rcc I2C2_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x2>; + wakeup-source; status = "disabled"; }; i2c3: i2c@40014000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x40014000 0x400>; interrupt-names = "event", "error"; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, @@ -509,11 +512,13 @@ resets = <&rcc I2C3_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + wakeup-source; status = "disabled"; }; i2c5: i2c@40015000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x40015000 0x400>; interrupt-names = "event", "error"; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, @@ -522,6 +527,8 @@ resets = <&rcc I2C5_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + wakeup-source; status = "disabled"; }; @@ -545,14 +552,14 @@ dac1: dac@1 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <1>; status = "disabled"; }; dac2: dac@2 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <2>; status = "disabled"; }; @@ -959,6 +966,7 @@ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc DMA1>; + resets = <&rcc DMA1_R>; #dma-cells = <4>; st,mem2mem; dma-requests = <8>; @@ -976,6 +984,7 @@ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc DMA2>; + resets = <&rcc DMA2_R>; #dma-cells = <4>; st,mem2mem; dma-requests = <8>; @@ -989,6 +998,7 @@ dma-masters = <&dma1 &dma2>; dma-channels = <16>; clocks = <&rcc DMAMUX>; + resets = <&rcc DMAMUX_R>; }; adc: adc@48003000 { @@ -1044,7 +1054,7 @@ }; usbotg_hs: usb-otg@49000000 { - compatible = "snps,dwc2"; + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; reg = <0x49000000 0x10000>; clocks = <&rcc USBO_K>; clock-names = "otg"; @@ -1055,6 +1065,7 @@ g-np-tx-fifo-size = <32>; g-tx-fifo-size = <128 128 64 64 64 64 32 32>; dr_mode = "otg"; + usb33d-supply = <&usb33>; status = "disabled"; }; @@ -1115,6 +1126,11 @@ }; }; + pwr_mcu: pwr_mcu@50001014 { + compatible = "syscon"; + reg = <0x50001014 0x4>; + }; + exti: interrupt-controller@5000d000 { compatible = "st,stm32mp1-exti", "syscon"; interrupt-controller; @@ -1280,6 +1296,7 @@ reg = <0x58000000 0x1000>; interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc MDMA>; + resets = <&rcc MDMA_R>; #dma-cells = <5>; dma-channels = <32>; dma-requests = <48>; @@ -1369,10 +1386,12 @@ clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx", + "eth-ck", "ethstp"; clocks = <&rcc ETHMAC>, <&rcc ETHTX>, <&rcc ETHRX>, + <&rcc ETHCK_K>, <&rcc ETHSTP>; st,syscon = <&syscfg 0x4>; snps,mixed-burst; @@ -1411,6 +1430,11 @@ clock-names = "lcd"; resets = <&rcc LTDC_R>; status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + }; }; iwdg2: watchdog@5a002000 { @@ -1464,7 +1488,7 @@ }; i2c4: i2c@5c002000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x5c002000 0x400>; interrupt-names = "event", "error"; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, @@ -1473,6 +1497,8 @@ resets = <&rcc I2C4_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + wakeup-source; status = "disabled"; }; @@ -1499,7 +1525,7 @@ }; i2c6: i2c@5c009000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x5c009000 0x400>; interrupt-names = "event", "error"; interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, @@ -1508,6 +1534,8 @@ resets = <&rcc I2C6_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x20>; + wakeup-source; status = "disabled"; }; @@ -1686,6 +1714,7 @@ resets = <&rcc MCU_R>; st,syscfg-holdboot = <&rcc 0x10C 0x1>; st,syscfg-tz = <&rcc 0x000 0x1>; + st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi index 2d759fc6015c..6d9ab08667fc 100644 --- a/arch/arm/boot/dts/stm32mp153.dtsi +++ b/arch/arm/boot/dts/stm32mp153.dtsi @@ -10,6 +10,7 @@ cpus { cpu1: cpu@1 { compatible = "arm,cortex-a7"; + clock-frequency = <650000000>; device_type = "cpu"; reg = <1>; }; diff --git a/arch/arm/boot/dts/stm32mp157.dtsi b/arch/arm/boot/dts/stm32mp157.dtsi index 3f0a4a91cce6..54e73ccea446 100644 --- a/arch/arm/boot/dts/stm32mp157.dtsi +++ b/arch/arm/boot/dts/stm32mp157.dtsi @@ -15,7 +15,6 @@ clocks = <&rcc GPU>, <&rcc GPU_K>; clock-names = "bus" ,"core"; resets = <&rcc GPU_R>; - status = "disabled"; }; dsi: dsi@5a000000 { @@ -25,7 +24,14 @@ clock-names = "pclk", "ref", "px_clk"; resets = <&rcc DSI_R>; reset-names = "apb"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; }; }; }; diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index cbfa4075907e..8a6eaca994d1 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -2,325 +2,10 @@ /* * Copyright (C) Linaro Ltd 2019 - All Rights Reserved * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + * Copyright (C) 2020 Marek Vasut <marex@denx.de> */ /dts-v1/; -#include "stm32mp157.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/mfd/st,stpmic1.h> - -/ { - model = "Arrow Electronics STM32MP157A Avenger96 board"; - compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - mmc0 = &sdmmc1; - serial0 = &uart4; - serial1 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x40000000>; - }; - - led { - compatible = "gpio-leds"; - led1 { - label = "green:user1"; - gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led2 { - label = "green:user2"; - gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led3 { - label = "green:user3"; - gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led4 { - label = "green:user3"; - gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - panic-indicator; - }; - - led5 { - label = "yellow:wifi"; - gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - led6 { - label = "blue:bt"; - gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - default-state = "off"; - }; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@7 { - reg = <7>; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - st,main-control-register = <0x04>; - st,vin-control-register = <0xc0>; - st,usb-control-register = <0x30>; - - regulators { - compatible = "st,stpmic1-regulators"; - - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask_reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - vdda: ldo1 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = <IT_CURLIM_LDO1 0>; - interrupt-parent = <&pmic>; - }; - - v2v8: ldo2 { - regulator-name = "v2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - interrupts = <IT_CURLIM_LDO2 0>; - interrupt-parent = <&pmic>; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - interrupts = <IT_CURLIM_LDO4 0>; - interrupt-parent = <&pmic>; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = <IT_CURLIM_LDO5 0>; - interrupt-parent = <&pmic>; - regulator-boot-on; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - interrupts = <IT_CURLIM_LDO6 0>; - interrupt-parent = <&pmic>; - regulator-enable-ramp-delay = <300000>; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - regulator-over-current-protection; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = <IT_OCP_BOOST 0>; - interrupt-parent = <&pmic>; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = <IT_OCP_OTG 0>; - interrupt-parent = <&pmic>; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = <IT_OCP_SWOUT 0>; - interrupt-parent = <&pmic>; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>; - interrupt-names = "onkey-falling", "onkey-rising"; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - broken-cd; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - status = "okay"; -}; - -&uart4 { - /* On Low speed expansion header */ - label = "LS-UART1"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_b>; - status = "okay"; -}; - -&uart7 { - /* On Low speed expansion header */ - label = "LS-UART0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - status = "okay"; -}; +/* This DT is here only for backward compatibility */ +#include "stm32mp157a-dhcor-avenger96.dts" diff --git a/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts new file mode 100644 index 000000000000..2e3c9fbb4eb3 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + * Copyright (C) 2020 Marek Vasut <marex@denx.de> + * + * DHCOR STM32MP1 variant: + * DHCR-STM32MP157A-C065-R102-V18-SPI-C-01LG + * DHCOR PCB number: 586-100 or newer + * Avenger96 PCB number: 588-200 or newer + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" +#include "stm32mp15xx-dhcor-avenger96.dtsi" + +/ { + model = "Arrow Electronics STM32MP157A Avenger96 board"; + compatible = "arrow,stm32mp157a-avenger96", "dh,stm32mp157a-dhcor-som", + "st,stm32mp157"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_b>; + pinctrl-1 = <&m_can1_sleep_pins_b>; + status = "disabled"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/stm32mp157a-iot-box.dts b/arch/arm/boot/dts/stm32mp157a-iot-box.dts new file mode 100644 index 000000000000..70f394b4d3c0 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-iot-box.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Manivannan Sadhasivam + */ + +/dts-v1/; +#include "stm32mp157a-stinger96.dtsi" + +/ { + model = "Shiratech STM32MP157A IoT Box"; + compatible = "shiratech,stm32mp157a-iot-box", "st,stm32mp157"; + + wlan_pwr: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&i2c2 { + ccs811@5b { + compatible = "ams,ccs811"; + reg = <0x5b>; + wakeup-gpios = <&gpioa 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; + }; +}; + +/* WiFi */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + broken-cd; + non-removable; + st,neg-edge; + bus-width = <1>; + vmmc-supply = <&wlan_pwr>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* Bluetooth */ +&uart4 { + /* Note: HW flow control is broken, hence using custom CTS/RTS gpios */ + /delete-property/st,hw-flow-ctrl; + cts-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpiob 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + bluetooth { + shutdown-gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; + compatible = "brcm,bcm43438-bt"; + max-speed = <115200>; + }; +}; diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dts b/arch/arm/boot/dts/stm32mp157a-stinger96.dts new file mode 100644 index 000000000000..249a53877512 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Manivannan Sadhasivam + */ + +/dts-v1/; +#include "stm32mp157a-stinger96.dtsi" + +/ { + model = "Shiratech STM32MP157A Stinger96 board"; + compatible = "shiratech,stm32mp157a-stinger96", "st,stm32mp157"; +}; diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi new file mode 100644 index 000000000000..58275bcf9e26 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Manivannan Sadhasivam + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/mfd/st,stpmic1.h> + +/ { + aliases { + mmc0 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + serial2 = &usart2; + spi0 = &spi4; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x10000000>; + }; + + led { + compatible = "gpio-leds"; + + led1 { + label = "green:user1"; + gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:user2"; + gpios = <&gpioh 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "green:user3"; + gpios = <&gpioh 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "green:user4"; + gpios = <&gpiof 12 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; +}; + +/* Only headless mode is supported */ +&gpu { + status = "disabled"; +}; + +/* LS-I2C0 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <1000>; + i2c-scl-falling-time-ns = <300>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO1 0>; + }; + + v2v9: ldo2 { + regulator-name = "v2v9"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO2 0>; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = <IT_CURLIM_LDO4 0>; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = <IT_CURLIM_LDO5 0>; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO6 0>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = <IT_OCP_BOOST 0>; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = <IT_OCP_OTG 0>; + regulator-active-discharge; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = <IT_OCP_SWOUT 0>; + regulator-active-discharge; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + broken-cd; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +/* LS-SPI0 */ +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins_a>; + cs-gpios = <&gpioe 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* BG96 */ +&usart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_b>; + pinctrl-1 = <&usart2_sleep_pins_b>; + st,hw-flow-ctrl; + status = "okay"; +}; + +/* LS-UART0 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_c>; + st,hw-flow-ctrl; + status = "okay"; +}; + +/* Debug console */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_b>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts new file mode 100644 index 000000000000..197aa98d49e2 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de> + * + * DHCOM STM32MP1 variant: + * DHCM-STM32MP157C-C065-R102-F0819-SPI-E2-CAN2-SDR104-RTC-WBT-T-DSI-I-01D2 + * DHCOR PCB number: 587-200 or newer + * PDK2 PCB number: 516-400 or newer + */ +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcom-som.dtsi" +#include "stm32mp15xx-dhcom-pdk2.dtsi" + +/ { + model = "DH Electronics STM32MP157C DHCOM Premium Developer Kit (2)"; + compatible = "dh,stm32mp157c-dhcom-pdk2", "dh,stm32mp157c-dhcom-som", + "st,stm32mp157"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts index 7985b80967ca..9a8a26710ac1 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts @@ -27,15 +27,10 @@ }; &dsi { - #address-cells = <1>; - #size-cells = <0>; status = "okay"; phy-dsi-supply = <®18>; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; dsi_in: endpoint { @@ -83,9 +78,6 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - ltdc_ep1_out: endpoint@1 { reg = <1>; remote-endpoint = <&dsi_in>; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 1fc43251d697..32ccd50b4144 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -126,14 +126,15 @@ &gpu { contiguous-area = <&gpu_reserved>; - status = "okay"; }; &i2c4 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; status = "okay"; /* spare dmas for other usage */ /delete-property/dmas; @@ -218,8 +219,6 @@ vdd_usb: ldo4 { regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; interrupts = <IT_CURLIM_LDO4 0>; }; @@ -241,7 +240,6 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -313,13 +311,18 @@ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; - broken-cd; + cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; st,sig-dir; st,neg-edge; st,use-ckin; bus-width = <4>; vmmc-supply = <&vdd_sd>; vqmmc-supply = <&sd_switch>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; status = "okay"; }; @@ -334,7 +337,7 @@ st,neg-edge; bus-width = <8>; vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd>; mmc-ddr-3_3v; status = "okay"; }; @@ -355,6 +358,10 @@ status = "okay"; }; +&usbotg_hs { + vbus-supply = <&vbus_otg>; +}; + &usbphyc_port0 { phy-supply = <&vdd_usb>; vdda1v1-supply = <®11>; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 228e35e16884..b19056557ef0 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -98,15 +98,10 @@ }; &dsi { - #address-cells = <1>; - #size-cells = <0>; phy-dsi-supply = <®18>; status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; dsi_in: endpoint { @@ -141,7 +136,7 @@ ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rgmii-id"; max-speed = <1000>; @@ -174,8 +169,9 @@ }; &i2c2 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c2_pins_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; @@ -210,7 +206,7 @@ interrupt-parent = <&gpioi>; vdd-supply = <&v3v3>; - stmfx_pinctrl: stmfx-pin-controller { + stmfx_pinctrl: pinctrl { compatible = "st,stmfx-0300-pinctrl"; gpio-controller; #gpio-cells = <2>; @@ -218,7 +214,7 @@ #interrupt-cells = <2>; gpio-ranges = <&stmfx_pinctrl 0 0 24>; - joystick_pins: joystick { + joystick_pins: joystick-pins { pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; bias-pull-down; }; @@ -227,8 +223,9 @@ }; &i2c5 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c5_pins_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; @@ -238,9 +235,6 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - ltdc_ep0_out: endpoint@0 { reg = <0>; remote-endpoint = <&dsi_in>; @@ -353,7 +347,8 @@ }; &usbotg_hs { - dr_mode = "peripheral"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; status = "okay"; diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts new file mode 100644 index 000000000000..5700e6b700d3 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2020 Ahmad Fatoum, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xx-osd32.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "Linux Automation MC-1 board"; + compatible = "lxa,stm32mp157c-mc1", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + serial0 = &uart4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&backlight_pwm 1 100000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 31 63 95 127 159 191 223 255>; + default-brightness-level = <7>; + power-supply = <®_5v2>; /* 3V3_BACKLIGHT */ + }; + + chosen { + stdout-path = &uart4; + }; + + led-act { + compatible = "gpio-leds"; + + led-green { + label = "mc1:green:act"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + led-rgb { + compatible = "pwm-leds"; + + led-red { + label = "mc1:red:rgb"; + pwms = <&leds_pwm 1 1000000 0>; + max-brightness = <255>; + active-low; + }; + + led-green { + label = "mc1:green:rgb"; + pwms = <&leds_pwm 2 1000000 0>; + max-brightness = <255>; + active-low; + }; + + led-blue { + label = "mc1:blue:rgb"; + pwms = <&leds_pwm 3 1000000 0>; + max-brightness = <255>; + active-low; + }; + }; + + panel: panel { + compatible = "edt,etm0700g0edh6", "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + + port { + panel_input: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + }; + + reg_3v3: regulator_3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&v3v3>; + }; + + /* supplied by either debug board or PoE */ + reg_5v2: regulator_5v2 { + compatible = "regulator-fixed"; + regulator-name = "5V2"; + regulator-min-microvolt = <5200000>; + regulator-max-microvolt = <5200000>; + regulator-always-on; + }; +}; + +ðernet0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ðernet0_rgmii_pins_b>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_b>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy>; + status = "okay"; + + mdio0 { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { /* KSZ9031RN */ + reg = <3>; + reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ + interrupt-parent = <&gpioa>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* ETH_MDINT# */ + rxc-skew-ps = <1860>; + txc-skew-ps = <1860>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + micrel,force-master; + }; + }; +}; + +&gpioz { + gpio-line-names = "HWID0", "HWID1", "HWID2", "HWID3", "", "", + "HWID4", "HWID5"; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_b>; + pinctrl-1 = <&i2c5_sleep_pins_b>; + clock-frequency = <400000>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + interrupt-parent = <&gpiod>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; /* TOUCH_INT# */ + vcc-supply = <®_3v3>; + reg = <0x38>; + reset-gpios = <&gpiof 8 GPIO_ACTIVE_LOW>; /* TOUCH_RESET# */ + touchscreen-size-x = <1792>; + touchscreen-size-y = <1024>; + wakeup-source; + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_c>; + pinctrl-1 = <<dc_sleep_pins_c>; + status = "okay"; + + port { + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; +}; + +&pmic { + regulators { + buck4-supply = <®_5v2>; /* VIN */ + ldo2-supply = <®_5v2>; /* PMIC_LDO25IN */ + ldo5-supply = <®_5v2>; /* PMIC_LDO25IN */ + boost-supply = <®_5v2>; /* PMIC_BSTIN */ + pwr_sw2-supply = <&bst_out>; /* PMIC_SWIN */ + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + bus-width = <4>; + cd-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + disable-wp; + no-1-8-v; + st,neg-edge; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +&sdmmc1_b4_pins_a { + /* + * board lacks external pull-ups on SDMMC lines. Class 10 SD refuses to + * work, thus enable internal pull-ups. + */ + pins1 { + /delete-property/ bias-disable; + bias-pull-up; + }; + pins2 { + /delete-property/ bias-disable; + bias-pull-up; + }; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + bus-width = <8>; + no-1-8-v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +&timers3 { + status = "okay"; + + backlight_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm3_pins_b>; + pinctrl-1 = <&pwm3_sleep_pins_b>; + status = "okay"; + }; +}; + +&timers5 { + status = "okay"; + + leds_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm5_pins_b>; + pinctrl-1 = <&pwm5_sleep_pins_b>; + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi new file mode 100644 index 000000000000..7c4bd615b311 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de> + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart8; + ethernet0 = ðernet0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clk_ext_audio_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + display_bl: display-bl { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; + default-brightness-level = <8>; + enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + ethernet_vio: vioregulator { + compatible = "regulator-fixed"; + regulator-name = "vio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #size-cells = <0>; + poll-interval = <20>; + + /* + * The EXTi IRQ line 3 is shared with touchscreen and ethernet, + * so mark this as polled GPIO key. + */ + button-0 { + label = "TA1-GPIO-A"; + linux,code = <KEY_A>; + gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #size-cells = <0>; + + button-1 { + label = "TA2-GPIO-B"; + linux,code = <KEY_B>; + gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-2 { + label = "TA3-GPIO-C"; + linux,code = <KEY_C>; + gpios = <&gpioi 11 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-3 { + label = "TA4-GPIO-D"; + linux,code = <KEY_D>; + gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + label = "green:led5"; + gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + label = "green:led6"; + gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-2 { + label = "green:led7"; + gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-3 { + label = "green:led8"; + gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + panel { + compatible = "edt,etm0700g0edh6"; + backlight = <&display_bl>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + sound { + compatible = "audio-graph-card"; + routing = + "MIC_IN", "Capture", + "Capture", "Mic Bias", + "Playback", "HP_OUT"; + dais = <&sai2a_port &sai2b_port>; + status = "okay"; + }; +}; + +&cec { + pinctrl-names = "default"; + pinctrl-0 = <&cec_pins_a>; + status = "okay"; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rmii_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0>; + st,eth-ref-clk-sel; + phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&i2c2 { /* Header X22 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&i2c5 { /* Header X21 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_ext_audio_codec>; + VDDA-supply = <&v3v3>; + VDDIO-supply = <&vdd>; + + sgtl5000_port: port { + #address-cells = <1>; + #size-cells = <0>; + + sgtl5000_tx_endpoint: endpoint@0 { + reg = <0>; + remote-endpoint = <&sai2a_endpoint>; + frame-master; + bitclock-master; + }; + + sgtl5000_rx_endpoint: endpoint@1 { + reg = <1>; + remote-endpoint = <&sai2b_endpoint>; + frame-master; + bitclock-master; + }; + }; + + }; + + polytouch@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpiog>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ + linux,wakeup; + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_b>; + pinctrl-1 = <<dc_sleep_pins_b>; + status = "okay"; + + port { + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_b &sai2b_pins_b>; + pinctrl-1 = <&sai2a_sleep_pins_b &sai2b_sleep_pins_b>; + status = "okay"; + + sai2a: audio-controller@4400b004 { + #clock-cells = <0>; + dma-names = "tx"; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + status = "okay"; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&sgtl5000_tx_endpoint>; + format = "i2s"; + mclk-fs = <512>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; + }; + + sai2b: audio-controller@4400b024 { + dma-names = "rx"; + st,sync = <&sai2a 2>; + clocks = <&rcc SAI2_K>, <&sai2a>; + clock-names = "sai_ck", "MCLK"; + status = "okay"; + + sai2b_port: port { + sai2b_endpoint: endpoint { + remote-endpoint = <&sgtl5000_rx_endpoint>; + format = "i2s"; + mclk-fs = <512>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; + }; +}; + +&timers2 { + /* spare dmas for other usage (un-delete to enable pwm capture) */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + pwm2: pwm { + pinctrl-0 = <&pwm2_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + timer@1 { + status = "okay"; + }; +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi new file mode 100644 index 000000000000..ba905196fb54 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de> + */ + +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/mfd/st,stpmic1.h> + +/ { + memory@c0000000 { + device_type = "memory"; + reg = <0xC0000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; +}; + +&adc { + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,min-sample-time-nsecs = <5000>; + st,adc-channels = <0>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <1>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +&dac { + pinctrl-names = "default"; + pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; + vref-supply = <&vdda>; + status = "okay"; + + dac1: dac@1 { + status = "okay"; + }; + dac2: dac@2 { + status = "okay"; + }; +}; + +&dts { + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + rtc@32 { + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = <IT_CURLIM_LDO1 0>; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = <IT_CURLIM_LDO2 0>; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = <IT_CURLIM_LDO4 0>; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = <IT_CURLIM_LDO5 0>; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = <IT_CURLIM_LDO6 0>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = <IT_OCP_BOOST 0>; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = <IT_OCP_OTG 0>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = <IT_OCP_SWOUT 0>; + regulator-active-discharge; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + + touchscreen@49 { + compatible = "ti,tsc2004"; + reg = <0x49>; + vio-supply = <&v3v3>; + interrupts-extended = <&gpioh 3 IRQ_TYPE_EDGE_FALLING>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: mx66l51235l@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; + broken-cd; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi new file mode 100644 index 000000000000..930202742a3f --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -0,0 +1,401 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + * Copyright (C) 2020 Marek Vasut <marex@denx.de> + */ + +/* Avenger96 uses DHCOR SoM configured for 1V8 IO operation */ +#include "stm32mp15xx-dhcor-io1v8.dtsi" + +/ { + aliases { + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + serial2 = &usart2; + spi0 = &qspi; + }; + + /* XTal Q1 */ + cec_clock: clk-cec-fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7513_out>; + }; + }; + }; + + led { + compatible = "gpio-leds"; + led1 { + label = "green:user0"; + gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:user1"; + gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "green:user2"; + gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "green:user3"; + gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP1-AV96-HDMI"; + dais = <&sai2a_port>; + status = "okay"; + }; + + wlan_pwr: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 6>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <0 1 2>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + + phy0: ethernet-phy@7 { + reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; + }; + }; +}; + +&i2c1 { /* X6 I2C1 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c2 { /* X6 I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_c>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + hdmi-transmitter@3d { + compatible = "adi,adv7513"; + reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>; + reg-names = "main", "cec", "edid", "packet"; + clocks = <&cec_clock>; + clock-names = "cec"; + + avdd-supply = <&v3v3>; + dvdd-supply = <&v3v3>; + pvdd-supply = <&v3v3>; + dvdd-3v-supply = <&v3v3>; + bgvdd-supply = <&v3v3>; + + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpiog>; + + status = "okay"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7513_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7513_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + + port@2 { + reg = <2>; + adv7513_i2s0: endpoint { + remote-endpoint = <&sai2a_endpoint>; + }; + }; + }; + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_d>; + pinctrl-1 = <<dc_sleep_pins_d>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&adv7513_in>; + }; + }; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_c>; + pinctrl-1 = <&sai2a_sleep_pins_c>; + clock-names = "pclk", "x8k", "x11k"; + status = "okay"; + + sai2a: audio-controller@4400b004 { + #clock-cells = <0>; + dma-names = "tx"; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + status = "okay"; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&adv7513_i2s0>; + format = "i2s"; + mclk-fs = <256>; + }; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + bus-width = <8>; + mmc-ddr-1_8v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd_io>; + status = "okay"; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_b>; + pinctrl-1 = <&sdmmc3_b4_od_pins_b>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; + broken-cd; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&wlan_pwr>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + cs-gpios = <&gpioi 0 0>; + status = "disabled"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&uart4 { + /* On Low speed expansion header */ + label = "LS-UART1"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_b>; + status = "okay"; +}; + +&uart7 { + /* On Low speed expansion header */ + label = "LS-UART0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; +}; + +/* Bluetooth */ +&usart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_sleep_pins_a>; + st,hw-flow-ctrl; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + status = "okay"; + vbus-supply = <&vbus_otg>; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi new file mode 100644 index 000000000000..75172314d7af --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + * Copyright (C) 2020 Marek Vasut <marex@denx.de> + */ + +/ { + /* Enpirion EP3A8LQI U2 on the DHCOR */ + vdd_io: regulator-buck-io { + compatible = "regulator-fixed"; + regulator-name = "buck-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; +}; + +&pwr_regulators { + vdd-supply = <&vdd_io>; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi new file mode 100644 index 000000000000..04fbb324a541 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + * Copyright (C) 2020 Marek Vasut <marex@denx.de> + */ + +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/mfd/st,stpmic1.h> + +/ { + aliases { + spi0 = &qspi; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x40000000>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = <IT_CURLIM_LDO1 0>; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = <IT_CURLIM_LDO2 0>; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = <IT_CURLIM_LDO4 0>; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = <IT_CURLIM_LDO5 0>; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = <IT_CURLIM_LDO6 0>; + regulator-enable-ramp-delay = <300000>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = <IT_OCP_BOOST 0>; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = <IT_OCP_OTG 0>; + regulator-active-discharge = <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = <IT_OCP_SWOUT 0>; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x200000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index f6672e87aef3..70db923a45f7 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -112,14 +112,18 @@ &cec { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cec_pins_b>; - pinctrl-1 = <&cec_pins_sleep_b>; + pinctrl-1 = <&cec_sleep_pins_b>; + status = "okay"; +}; + +&dts { status = "okay"; }; ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rgmii-id"; max-speed = <1000>; @@ -137,13 +141,12 @@ &gpu { contiguous-area = <&gpu_reserved>; - status = "okay"; }; &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; - pinctrl-1 = <&i2c1_pins_sleep_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; i2c-scl-rising-time-ns = <100>; i2c-scl-falling-time-ns = <7>; status = "okay"; @@ -216,10 +219,12 @@ }; &i2c4 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; status = "okay"; /* spare dmas for other usage */ /delete-property/dmas; @@ -304,8 +309,6 @@ vdd_usb: ldo4 { regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; interrupts = <IT_CURLIM_LDO4 0>; }; @@ -328,7 +331,6 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -368,7 +370,7 @@ clock-names = "pclk", "i2sclk", "x8k", "x11k"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2s2_pins_a>; - pinctrl-1 = <&i2s2_pins_sleep_a>; + pinctrl-1 = <&i2s2_sleep_pins_a>; status = "okay"; i2s2_port: port { @@ -392,13 +394,10 @@ <dc { pinctrl-names = "default", "sleep"; pinctrl-0 = <<dc_pins_a>; - pinctrl-1 = <<dc_pins_sleep_a>; + pinctrl-1 = <<dc_sleep_pins_a>; status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - ltdc_ep0_out: endpoint@0 { reg = <0>; remote-endpoint = <&sii9022_in>; @@ -479,7 +478,8 @@ pinctrl-0 = <&sdmmc1_b4_pins_a>; pinctrl-1 = <&sdmmc1_b4_od_pins_a>; pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - broken-cd; + cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; st,neg-edge; bus-width = <4>; vmmc-supply = <&v3v3>; diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi new file mode 100644 index 000000000000..713485a95795 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2020 Ahmad Fatoum, Pengutronix + */ + +#include "stm32mp15-pinctrl.dtsi" + +#include <dt-bindings/mfd/st,stpmic1.h> + +/ { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + + reg_sip_eeprom: regulator_eeprom { + compatible = "regulator-fixed"; + regulator-name = "sip_eeprom"; + regulator-always-on; + }; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO1 0>; + + }; + + v3v3_hdmi: ldo2 { + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO2 0>; + + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = <IT_CURLIM_LDO4 0>; + }; + + vdda: ldo5 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = <IT_CURLIM_LDO5 0>; + regulator-boot-on; + }; + + v1v2_hdmi: ldo6 { + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO6 0>; + + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = <IT_OCP_BOOST 0>; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = <IT_OCP_OTG 0>; + regulator-active-discharge; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = <IT_OCP_SWOUT 0>; + regulator-active-discharge; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>; + interrupt-names = "onkey-falling", "onkey-rising"; + }; + + pmic_watchdog: watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + + sip_eeprom: eeprom@50 { + compatible = "atmel,24c32"; + vcc-supply = <®_sip_eeprom>; + reg = <0x50>; + }; +}; + +&ipcc { + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&rng1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun5i-a13-pocketbook-touch-lux-3.dts b/arch/arm/boot/dts/sun5i-a13-pocketbook-touch-lux-3.dts new file mode 100644 index 000000000000..e9ef97c9c893 --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a13-pocketbook-touch-lux-3.dts @@ -0,0 +1,257 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2019 Ondrej Jirman <megous@megous.com> + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sunxi-common-regulators.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "PocketBook Touch Lux 3"; + compatible = "pocketbook,touch-lux-3", "allwinner,sun5i-a13"; + + aliases { + serial0 = &uart1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + enable-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + power { + gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */ + default-state = "on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + label = "GPIO Keys"; + + key-right { + label = "Right"; + linux,code = <KEY_RIGHT>; + gpios = <&pio 6 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG9 */ + }; + + key-left { + label = "Left"; + linux,code = <KEY_LEFT>; + gpios = <&pio 6 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG10 */ + }; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd-1v8-nor-ctp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 2 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_1v8_nor: regulator-nor { + compatible = "regulator-fixed"; + regulator-name = "vdd-nor"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 2 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_1v8>; + regulator-always-on; + }; + + reg_1v8_ctp: regulator-ctp { + compatible = "regulator-fixed"; + regulator-name = "vdd-ctp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 2 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_1v8>; + }; + + reg_3v3_mmc0: regulator-mmc0 { + compatible = "regulator-fixed"; + regulator-name = "vdd-mmc0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 4 4 GPIO_ACTIVE_LOW>; /* PE4 */ + vin-supply = <®_vcc3v3>; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + status = "okay"; + + /* Touchpanel is connected here. */ +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-200 { + label = "Home"; + linux,code = <KEY_HOME>; + channel = <0>; + voltage = <200000>; + }; + + button-400 { + label = "Menu"; + linux,code = <KEY_MENU>; + channel = <0>; + voltage = <400000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_3v3_mmc0>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_4bit_pc_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd-int-pll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; + /* We need this otherwise the LDO3 would overload */ + regulator-soft-start; + regulator-ramp-delay = <1600>; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pe_pins>, <&spi2_cs0_pe_pin>; + status = "okay"; + + epd_flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "macronix,mx25u4033", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_ldo3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 0b526e6e5a95..e6b036734a64 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -186,6 +186,8 @@ compatible = "allwinner,sun5i-a13-mbus"; reg = <0x01c01000 0x1000>; clocks = <&ccu CLK_MBUS>; + #address-cells = <1>; + #size-cells = <1>; dma-ranges = <0x00000000 0x40000000 0x20000000>; #interconnect-cells = <1>; }; @@ -771,9 +773,6 @@ interconnect-names = "dma-mem"; status = "disabled"; - assigned-clocks = <&ccu CLK_DE_BE>; - assigned-clock-rates = <300000000>; - ports { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 7762fbd9a133..f3425a66fc0a 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -1139,9 +1139,6 @@ "ram"; resets = <&ccu RST_AHB1_BE1>; - assigned-clocks = <&ccu CLK_BE1>; - assigned-clock-rates = <300000000>; - ports { #address-cells = <1>; #size-cells = <0>; @@ -1185,9 +1182,6 @@ "ram"; resets = <&ccu RST_AHB1_DRC1>; - assigned-clocks = <&ccu CLK_IEP_DRC1>; - assigned-clock-rates = <300000000>; - ports { #address-cells = <1>; #size-cells = <0>; @@ -1231,9 +1225,6 @@ "ram"; resets = <&ccu RST_AHB1_BE0>; - assigned-clocks = <&ccu CLK_BE0>; - assigned-clock-rates = <300000000>; - ports { #address-cells = <1>; #size-cells = <0>; @@ -1274,9 +1265,6 @@ "ram"; resets = <&ccu RST_AHB1_DRC0>; - assigned-clocks = <&ccu CLK_IEP_DRC0>; - assigned-clock-rates = <300000000>; - ports { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sun7i-a20-linutronix-testbox-v2.dts b/arch/arm/boot/dts/sun7i-a20-linutronix-testbox-v2.dts new file mode 100644 index 000000000000..da5a2eea4ce3 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-linutronix-testbox-v2.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2020 Linutronix GmbH + * Author: Benedikt Spranger <b.spranger@linutronix.de> + */ + +/dts-v1/; +#include "sun7i-a20-lamobo-r1.dts" + +/ { + model = "Lamobo R1"; + compatible = "linutronix,testbox-v2", "lamobo,lamobo-r1", "allwinner,sun7i-a20"; + + leds { + led-opto1 { + label = "lamobo_r1:opto:powerswitch"; + gpios = <&pio 7 3 GPIO_ACTIVE_HIGH>; + }; + + led-opto2 { + label = "lamobo_r1:opto:relay"; + gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + status = "okay"; + }; + + atecc508a@60 { + compatible = "atmel,atecc508a"; + reg = <0x60>; + }; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can_ph_pins>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts new file mode 100644 index 000000000000..033cab3443f8 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Olimex Ltd. + * Author: Stefan Mavrodiev <stefan@olimex.com> + */ + +#include "sun7i-a20-olinuxino-lime.dts" + +/ { + model = "Olimex A20-OLinuXino-LIME-eMMC"; + compatible = "olimex,a20-olinuxino-lime-emmc", "allwinner,sun7i-a20"; + + mmc2_pwrseq: pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc2 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + mmc-pwrseq = <&mmc2_pwrseq>; + status = "okay"; + + emmc: emmc@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 92b5be97085d..ffe1d10a1a84 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -47,6 +47,7 @@ #include <dt-bindings/dma/sun4i-a10.h> #include <dt-bindings/clock/sun7i-a20-ccu.h> #include <dt-bindings/reset/sun4i-a10-ccu.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> / { interrupt-parent = <&gic>; @@ -404,11 +405,12 @@ }; tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun7i-a20-tcon"; + compatible = "allwinner,sun7i-a20-tcon0", + "allwinner,sun7i-a20-tcon"; reg = <0x01c0c000 0x1000>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - resets = <&ccu RST_TCON0>; - reset-names = "lcd"; + resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>; + reset-names = "lcd", "lvds"; clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_TCON0_CH0>, <&ccu CLK_TCON0_CH1>; @@ -454,7 +456,8 @@ }; tcon1: lcd-controller@1c0d000 { - compatible = "allwinner,sun7i-a20-tcon"; + compatible = "allwinner,sun7i-a20-tcon1", + "allwinner,sun7i-a20-tcon"; reg = <0x01c0d000 0x1000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; resets = <&ccu RST_TCON1>; @@ -932,6 +935,20 @@ }; /omit-if-no-ref/ + lcd_lvds0_pins: lcd-lvds0-pins { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", + "PD5", "PD6", "PD7", "PD8", "PD9"; + function = "lvds0"; + }; + + /omit-if-no-ref/ + lcd_lvds1_pins: lcd-lvds1-pins { + pins = "PD10", "PD11", "PD12", "PD13", "PD14", + "PD15", "PD16", "PD17", "PD18", "PD19"; + function = "lvds1"; + }; + + /omit-if-no-ref/ mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 48487f6d4ab9..c1362d0f0ff8 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -684,9 +684,6 @@ clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_BUS_DRC>; - assigned-clocks = <&ccu CLK_DRC>; - assigned-clock-rates = <300000000>; - ports { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 1532a0e59af4..cfd3858afb3e 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -215,7 +215,7 @@ }; crypto: crypto-engine@1c15000 { - compatible = "allwinner,sun4i-a10-crypto"; + compatible = "allwinner,sun8i-a33-crypto"; reg = <0x01c15000 0x1000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; @@ -372,8 +372,6 @@ "ram", "sat"; resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; reset-names = "be", "sat"; - assigned-clocks = <&ccu CLK_DE_BE>; - assigned-clock-rates = <300000000>; }; &ccu { diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts index 2fd31a0a0b34..bfc9bb277a49 100644 --- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts +++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts @@ -374,8 +374,8 @@ }; ®_dldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-name = "vdd-csi"; }; @@ -493,12 +493,12 @@ }; &usb_otg { - dr_mode = "otg"; status = "okay"; }; &usbphy { - usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ + usb0_id_det-gpios = <&pio 7 11 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH11 */ + usb0_vbus_power-supply = <&usb_power_supply>; usb0_vbus-supply = <®_drivevbus>; usb1_vbus-supply = <®_vmain>; usb2_vbus-supply = <®_vmain>; diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 74ac7ee9383c..c010b27fdb6a 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -72,7 +72,7 @@ #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; clocks = <&ccu CLK_C0CPUX>; @@ -83,7 +83,7 @@ #cooling-cells = <2>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; clocks = <&ccu CLK_C0CPUX>; @@ -94,7 +94,7 @@ #cooling-cells = <2>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; clocks = <&ccu CLK_C0CPUX>; @@ -116,7 +116,7 @@ #cooling-cells = <2>; }; - cpu@101 { + cpu101: cpu@101 { compatible = "arm,cortex-a7"; device_type = "cpu"; clocks = <&ccu CLK_C1CPUX>; @@ -127,7 +127,7 @@ #cooling-cells = <2>; }; - cpu@102 { + cpu102: cpu@102 { compatible = "arm,cortex-a7"; device_type = "cpu"; clocks = <&ccu CLK_C1CPUX>; @@ -138,7 +138,7 @@ #cooling-cells = <2>; }; - cpu@103 { + cpu103: cpu@103 { compatible = "arm,cortex-a7"; device_type = "cpu"; clocks = <&ccu CLK_C1CPUX>; @@ -314,7 +314,7 @@ display_clocks: clock@1000000 { compatible = "allwinner,sun8i-a83t-de2-clk"; - reg = <0x01000000 0x100000>; + reg = <0x01000000 0x10000>; clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_PLL_DE>; clock-names = "bus", @@ -324,6 +324,17 @@ #reset-cells = <1>; }; + rotate: rotate@1020000 { + compatible = "allwinner,sun8i-a83t-de2-rotate"; + reg = <0x1020000 0x10000>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&display_clocks CLK_BUS_ROT>, + <&display_clocks CLK_ROT>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_ROT>; + }; + mixer0: mixer@1100000 { compatible = "allwinner,sun8i-a83t-de2-mixer-0"; reg = <0x01100000 0x100000>; @@ -599,6 +610,16 @@ clock-names = "bus", "mod"; }; + msgbox: mailbox@1c17000 { + compatible = "allwinner,sun8i-a83t-msgbox", + "allwinner,sun6i-a31-msgbox"; + reg = <0x01c17000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX>; + resets = <&ccu RST_BUS_MSGBOX>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + }; + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-a83t-musb", "allwinner,sun8i-a33-musb"; @@ -1006,10 +1027,10 @@ reg = <0x01c30000 0x104>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; - resets = <&ccu CLK_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu RST_BUS_EMAC>; + clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; status = "disabled"; mdio: mdio { @@ -1188,12 +1209,60 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 0>; + + trips { + cpu0_hot: cpu-hot { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_very_hot: cpu-very-hot { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + cpu-hot-limit { + trip = <&cpu0_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu1_thermal: cpu1-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 1>; + + trips { + cpu1_hot: cpu-hot { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_very_hot: cpu-very-hot { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + cpu-hot-limit { + trip = <&cpu1_hot>; + cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpu_thermal: gpu-thermal { diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts index d277d043031b..4c6704e4c57e 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -31,7 +31,7 @@ pwr_led { label = "bananapi-m2-zero:red:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */ default-state = "on"; }; }; diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 20217e2ca4d3..4e89701df91f 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -41,6 +41,7 @@ */ #include "sunxi-h3-h5.dtsi" +#include <dt-bindings/thermal/thermal.h> / { cpu0_opp_table: opp_table0 { @@ -111,6 +112,26 @@ }; }; + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + }; + + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + }; + }; + pmu { compatible = "arm,cortex-a7-pmu"; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, @@ -204,9 +225,7 @@ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; clock-names = "bus", "core"; resets = <&ccu RST_BUS_GPU>; - - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <384000000>; + operating-points-v2 = <&gpu_opp_table>; }; ths: thermal-sensor@1c25000 { @@ -227,6 +246,30 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 0>; + + trips { + cpu_hot_trip: cpu-hot { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_very_hot_trip: cpu-very-hot { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + cpu-hot-limit { + trip = <&cpu_hot_trip>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 8f09a24b36ec..b782041e0e04 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -47,6 +47,7 @@ #include <dt-bindings/clock/sun8i-tcon-top.h> #include <dt-bindings/reset/sun8i-r40-ccu.h> #include <dt-bindings/reset/sun8i-de2.h> +#include <dt-bindings/thermal/thermal.h> / { #address-cells = <1>; @@ -110,6 +111,22 @@ status = "disabled"; }; + thermal-zones { + cpu_thermal: cpu0-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; + + gpu_thermal: gpu-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -119,7 +136,7 @@ display_clocks: clock@1000000 { compatible = "allwinner,sun8i-r40-de2-clk", "allwinner,sun8i-h3-de2-clk"; - reg = <0x01000000 0x100000>; + reg = <0x01000000 0x10000>; clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; clock-names = "bus", @@ -181,6 +198,32 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; }; + spi0: spi@1c05000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c06000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + csi0: csi@1c09000 { compatible = "allwinner,sun8i-r40-csi0", "allwinner,sun7i-a20-csi0"; @@ -290,6 +333,29 @@ resets = <&ccu RST_BUS_CE>; }; + spi2: spi@1c17000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ahci: sata@1c18000 { + compatible = "allwinner,sun8i-r40-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; + resets = <&ccu RST_BUS_SATA>; + reset-names = "ahci"; + status = "disabled"; + }; + ehci1: usb@1c19000 { compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; reg = <0x01c19000 0x100>; @@ -336,6 +402,19 @@ status = "disabled"; }; + spi3: spi@1c1f000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c1f000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-r40-ccu"; reg = <0x01c20000 0x400>; @@ -500,6 +579,17 @@ clocks = <&osc24M>; }; + ths: thermal-sensor@1c24c00 { + compatible = "allwinner,sun8i-r40-ths"; + reg = <0x01c24c00 0x100>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "bus", "mod"; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_BUS_THS>; + /* TODO: add nvmem-cells for calibration */ + #thermal-sensor-cells = <1>; + }; + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; @@ -653,69 +743,6 @@ #size-cells = <0>; }; - spi0: spi@1c05000 { - compatible = "allwinner,sun8i-r40-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c05000 0x1000>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c06000 { - compatible = "allwinner,sun8i-r40-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c06000 0x1000>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi2: spi@1c07000 { - compatible = "allwinner,sun8i-r40-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c07000 0x1000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi3: spi@1c0f000 { - compatible = "allwinner,sun8i-r40-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x01c0f000 0x1000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; - clock-names = "ahb", "mod"; - resets = <&ccu RST_BUS_SPI3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ahci: sata@1c18000 { - compatible = "allwinner,sun8i-r40-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; - resets = <&ccu RST_BUS_SATA>; - reset-names = "ahci"; - status = "disabled"; - - }; - gmac: ethernet@1c50000 { compatible = "allwinner,sun8i-r40-gmac"; syscon = <&ccu>; @@ -739,6 +766,8 @@ compatible = "allwinner,sun8i-r40-mbus"; reg = <0x01c62000 0x1000>; clocks = <&ccu 155>; + #address-cells = <1>; + #size-cells = <1>; dma-ranges = <0x00000000 0x40000000 0x80000000>; #interconnect-cells = <1>; }; diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 81ea50838cd5..e5312869c0d2 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -105,7 +105,7 @@ display_clocks: clock@1000000 { compatible = "allwinner,sun8i-v3s-de2-clk"; - reg = <0x01000000 0x100000>; + reg = <0x01000000 0x10000>; clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; clock-names = "bus", diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 5e9c3060aa08..22d533d18992 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -114,7 +114,7 @@ display_clocks: clock@1000000 { /* compatible is in per SoC .dtsi file */ - reg = <0x01000000 0x100000>; + reg = <0x01000000 0x10000>; clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; clock-names = "bus", @@ -239,6 +239,16 @@ }; }; + msgbox: mailbox@1c17000 { + compatible = "allwinner,sun8i-h3-msgbox", + "allwinner,sun6i-a31-msgbox"; + reg = <0x01c17000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX>; + resets = <&ccu RST_BUS_MSGBOX>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + }; + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-h3-musb"; reg = <0x01c19000 0x400>; @@ -560,6 +570,8 @@ compatible = "allwinner,sun8i-h3-mbus"; reg = <0x01c62000 0x1000>; clocks = <&ccu CLK_MBUS>; + #address-cells = <1>; + #size-cells = <1>; dma-ranges = <0x00000000 0x40000000 0xc0000000>; #interconnect-cells = <1>; }; @@ -892,6 +904,21 @@ pins = "PL0", "PL1"; function = "s_i2c"; }; + + r_pwm_pin: r-pwm-pin { + pins = "PL10"; + function = "s_pwm"; + }; + }; + + r_pwm: pwm@1f03800 { + compatible = "allwinner,sun8i-h3-pwm"; + reg = <0x01f03800 0x8>; + pinctrl-names = "default"; + pinctrl-0 = <&r_pwm_pin>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; }; }; }; diff --git a/arch/arm/boot/dts/tango4-common.dtsi b/arch/arm/boot/dts/tango4-common.dtsi index ff72a8efb73d..54fd522badfc 100644 --- a/arch/arm/boot/dts/tango4-common.dtsi +++ b/arch/arm/boot/dts/tango4-common.dtsi @@ -85,7 +85,7 @@ }; uart: serial@10700 { - compatible = "ralink,rt2880-uart"; + compatible = "ralink,rt2880-uart", "ns16550a"; reg = <0x10700 0x30>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <7372800>; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 97a5c3504bbe..08be733ee2cd 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -46,8 +46,7 @@ avdd-dsi-csi-supply = <&avdd_1v2_reg>; panel@0 { - compatible = "panasonic,vvx10f004b00", - "simple-panel"; + compatible = "panasonic,vvx10f004b00"; reg = <0>; power-supply = <&avdd_lcd_reg>; @@ -1296,7 +1295,13 @@ clocks = <&tegra_car TEGRA114_CLK_PLL_A>, <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA114_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA114_CLK_EXTERN1>; }; }; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 0d7a6327e404..450a1f1b12a0 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -4,6 +4,7 @@ #include <dt-bindings/memory/tegra114-mc.h> #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/tegra-pmc.h> / { compatible = "nvidia,tegra114"; @@ -514,11 +515,12 @@ status = "disabled"; }; - pmc@7000e400 { + tegra_pmc: pmc@7000e400 { compatible = "nvidia,tegra114-pmc"; reg = <0x7000e400 0x400>; clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; }; fuse@7000f800 { diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 0462ed2dd8b8..de499f736bda 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -2009,8 +2009,14 @@ nvidia,audio-codec = <&sgtl5000>; clocks = <&tegra_car TEGRA124_CLK_PLL_A>, <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; }; thermal-zones { diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index d1e8593ef0d9..d70a86da4ee4 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -2001,8 +2001,14 @@ nvidia,audio-codec = <&sgtl5000>; clocks = <&tegra_car TEGRA124_CLK_PLL_A>, <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; }; thermal-zones { diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index d5fd642f8b77..1b567e2d5ce0 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1782,12 +1782,6 @@ }; ports { - /* Micro A/B */ - usb2-0 { - status = "okay"; - mode = "otg"; - }; - /* Mini PCIe */ usb2-1 { status = "okay"; @@ -2058,8 +2052,14 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_A>, <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; }; thermal-zones { diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 3b10f475037f..9b1af50cd4b8 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -788,9 +788,15 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_A>, <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 7309393bfced..73361dbe2e43 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -1087,7 +1087,7 @@ }; panel: panel { - compatible = "lg,lp129qe", "simple-panel"; + compatible = "lg,lp129qe"; backlight = <&backlight>; ddc-i2c-bus = <&dpaux>; @@ -1266,8 +1266,14 @@ clocks = <&tegra_car TEGRA124_CLK_PLL_A>, <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; }; }; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 7f330b1f150f..94cac13d3e50 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/tegra124-car.h> #include <dt-bindings/thermal/tegra124-soctherm.h> +#include <dt-bindings/soc/tegra-pmc.h> / { compatible = "nvidia,tegra124"; @@ -595,11 +596,12 @@ clocks = <&tegra_car TEGRA124_CLK_RTC>; }; - pmc@7000e400 { + tegra_pmc: pmc@7000e400 { compatible = "nvidia,tegra124-pmc"; reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; }; fuse@7000f800 { diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts index 3c0f2681fcde..37ad508b61d9 100644 --- a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts @@ -223,7 +223,7 @@ * edt,et057090dhu: EDT 5.7" LCD TFT * edt,et070080dh6: EDT 7.0" LCD TFT */ - compatible = "edt,et057090dhu", "simple-panel"; + compatible = "edt,et057090dhu"; backlight = <&backlight>; power-supply = <®_3v3>; }; diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index d8004d68efa0..af4740847769 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -205,7 +205,7 @@ * edt,et057090dhu: EDT 5.7" LCD TFT * edt,et070080dh6: EDT 7.0" LCD TFT */ - compatible = "edt,et057090dhu", "simple-panel"; + compatible = "edt,et057090dhu"; backlight = <&backlight>; power-supply = <®_3v3>; }; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 1d96d92b72a7..02cd67ea2503 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -665,7 +665,7 @@ }; panel: panel { - compatible = "auo,b101aw03", "simple-panel"; + compatible = "auo,b101aw03"; power-supply = <&vdd_pnl_reg>; enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index cda5448c2ace..c73510cd501c 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -57,7 +57,7 @@ }; panel: panel { - compatible = "innolux,n156bge-l21", "simple-panel"; + compatible = "innolux,n156bge-l21"; power-supply = <&vdd_1v8_reg>, <&vdd_3v3_reg>; enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index be0ab9b84b9a..cce3a3fb82ed 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -604,7 +604,7 @@ }; panel: panel { - compatible = "samsung,ltn101nt05", "simple-panel"; + compatible = "samsung,ltn101nt05"; ddc-i2c-bus = <&lvds_ddc>; power-supply = <&vdd_pnl_reg>; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index f91441683aad..376ecb6435f4 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -826,7 +826,7 @@ }; panel: panel { - compatible = "chunghwa,claa101wa01a", "simple-panel"; + compatible = "chunghwa,claa101wa01a"; power-supply = <&vdd_pnl_reg>; enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index f44551e2d9d0..022649119821 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -611,7 +611,7 @@ }; panel: panel { - compatible = "chunghwa,claa101wa01a", "simple-panel"; + compatible = "chunghwa,claa101wa01a"; power-supply = <&vdd_pnl_reg>; enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 9c58e7fcf5c0..c3b8ad53b967 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -4,6 +4,7 @@ #include <dt-bindings/memory/tegra20-mc.h> #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/tegra-pmc.h> / { compatible = "nvidia,tegra20"; @@ -608,11 +609,12 @@ status = "disabled"; }; - pmc@7000e400 { + tegra_pmc: pmc@7000e400 { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; }; mc: memory-controller@7000f000 { diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 749fc6d1ff70..b39c26806bf2 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -195,7 +195,7 @@ * edt,et057090dhu: EDT 5.7" LCD TFT * edt,et070080dh6: EDT 7.0" LCD TFT */ - compatible = "edt,et057090dhu", "simple-panel"; + compatible = "edt,et057090dhu"; backlight = <&backlight>; power-supply = <®_3v3>; }; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts index 0be50e881684..e29dca92ba0a 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts @@ -196,7 +196,7 @@ * edt,et057090dhu: EDT 5.7" LCD TFT * edt,et070080dh6: EDT 7.0" LCD TFT */ - compatible = "edt,et057090dhu", "simple-panel"; + compatible = "edt,et057090dhu"; backlight = <&backlight>; power-supply = <®_3v3>; }; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index 8b7a827d604d..387b17458e22 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -1189,7 +1189,13 @@ nvidia,audio-codec = <&sgtl5000>; clocks = <&tegra_car TEGRA30_CLK_PLL_A>, <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; }; }; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index c18f6f61d764..6648506f3aa4 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -1171,7 +1171,13 @@ nvidia,audio-codec = <&sgtl5000>; clocks = <&tegra_car TEGRA30_CLK_PLL_A>, <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; }; }; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index a3b0f3555cd2..6b6fd8a8058f 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" / { model = "NVIDIA Tegra30 Beaver evaluation board"; @@ -1806,9 +1808,14 @@ vddctrl_reg: vddctrl { regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; + + nvidia,tegra-cpu-regulator; }; vio_reg: vio { @@ -1868,17 +1875,22 @@ }; }; - tps62361@60 { + core_vdd_reg: tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; regulator-name = "tps62361-vout"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1500000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; ti,vsel0-state-high; ti,vsel1-state-high; + + nvidia,tegra-core-regulator; }; }; @@ -2111,7 +2123,35 @@ clocks = <&tegra_car TEGRA30_CLK_PLL_A>, <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 7ce61edd52f5..5ee5d141bd81 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -432,7 +432,7 @@ }; panel: panel { - compatible = "chunghwa,claa101wb01", "simple-panel"; + compatible = "chunghwa,claa101wb01"; ddc-i2c-bus = <&panelddc>; power-supply = <&vdd_pnl1_reg>; @@ -619,8 +619,14 @@ clocks = <&tegra_car TEGRA30_CLK_PLL_A>, <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; }; gpio-keys { diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 5965150ecdd2..8e106e784dce 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -159,7 +159,7 @@ * edt,et057090dhu: EDT 5.7" LCD TFT * edt,et070080dh6: EDT 7.0" LCD TFT */ - compatible = "edt,et057090dhu", "simple-panel"; + compatible = "edt,et057090dhu"; backlight = <&backlight>; power-supply = <®_3v3>; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 1f9198bb24ff..adba554381c7 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -1030,8 +1030,14 @@ nvidia,audio-codec = <&sgtl5000>; clocks = <&tegra_car TEGRA30_CLK_PLL_A>, <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA30_CLK_EXTERN1>; + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 55ae050042ce..d2d05f1da274 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -4,6 +4,7 @@ #include <dt-bindings/memory/tegra30-mc.h> #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/tegra-pmc.h> / { compatible = "nvidia,tegra30"; @@ -714,11 +715,12 @@ status = "disabled"; }; - pmc@7000e400 { + tegra_pmc: pmc@7000e400 { compatible = "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>; clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; }; mc: memory-controller@7000f000 { diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index 64ec46c72a4c..b52957ccda0d 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -51,7 +51,7 @@ ranges; interrupt-parent = <&intc>; - l2: l2-cache@500c0000 { + l2: cache-controller@500c0000 { compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; @@ -67,6 +67,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -245,7 +247,7 @@ #dma-cells = <1>; }; - sd: sdhc@5a400000 { + sd: mmc@5a400000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a400000 0x200>; @@ -265,7 +267,7 @@ sd-uhs-sdr50; }; - emmc: sdhc@5a500000 { + emmc: mmc@5a500000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a500000 0x200>; @@ -375,7 +377,7 @@ interrupt-controller; }; - aidet: aidet@61830000 { + aidet: interrupt-controller@61830000 { compatible = "socionext,uniphier-ld4-aidet"; reg = <0x61830000 0x200>; interrupt-controller; @@ -398,7 +400,7 @@ }; }; - nand: nand@68000000 { + nand: nand-controller@68000000 { compatible = "socionext,uniphier-denali-nand-v5a"; status = "disabled"; reg-names = "nand_data", "denali_reg"; diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts index 60994b6e8b99..079cadc11e6c 100644 --- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts +++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts @@ -29,6 +29,7 @@ i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/uniphier-pro4-ace.dts index 92cc48dd86d0..64246fad325c 100644 --- a/arch/arm/boot/dts/uniphier-pro4-ace.dts +++ b/arch/arm/boot/dts/uniphier-pro4-ace.dts @@ -26,6 +26,7 @@ i2c3 = &i2c3; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts index 854f2eba3e72..181442c48532 100644 --- a/arch/arm/boot/dts/uniphier-pro4-ref.dts +++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts @@ -29,6 +29,7 @@ i2c3 = &i2c3; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/uniphier-pro4-sanji.dts index dda1a2f214a8..5396556dee58 100644 --- a/arch/arm/boot/dts/uniphier-pro4-sanji.dts +++ b/arch/arm/boot/dts/uniphier-pro4-sanji.dts @@ -25,6 +25,7 @@ i2c3 = &i2c3; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index 2ec04d7972ef..a53b73ee93e9 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -59,7 +59,7 @@ ranges; interrupt-parent = <&intc>; - l2: l2-cache@500c0000 { + l2: cache-controller@500c0000 { compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; @@ -75,6 +75,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -279,7 +281,7 @@ #dma-cells = <1>; }; - sd: sdhc@5a400000 { + sd: mmc@5a400000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a400000 0x200>; @@ -299,7 +301,7 @@ sd-uhs-sdr50; }; - emmc: sdhc@5a500000 { + emmc: mmc@5a500000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a500000 0x200>; @@ -317,7 +319,7 @@ non-removable; }; - sd1: sdhc@5a600000 { + sd1: mmc@5a600000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a600000 0x200>; @@ -426,7 +428,15 @@ }; }; - aidet: aidet@5fc20000 { + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-pro4-aidet"; reg = <0x5fc20000 0x200>; interrupt-controller; @@ -588,7 +598,7 @@ }; }; - nand: nand@68000000 { + nand: nand-controller@68000000 { compatible = "socionext,uniphier-denali-nand-v5a"; status = "disabled"; reg-names = "nand_data", "denali_reg"; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index ea3961f920a0..feadb4a378eb 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -131,7 +131,7 @@ ranges; interrupt-parent = <&intc>; - l2: l2-cache@500c0000 { + l2: cache-controller@500c0000 { compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; @@ -144,7 +144,7 @@ next-level-cache = <&l3>; }; - l3: l3-cache@500c8000 { + l3: cache-controller@500c8000 { compatible = "socionext,uniphier-system-cache"; reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; @@ -160,6 +160,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -171,11 +173,13 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006100 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 216 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; + clocks = <&peri_clk 11>; /* common with spi0 */ + resets = <&peri_rst 12>; }; serial0: serial@54006800 { @@ -408,7 +412,15 @@ }; }; - aidet: aidet@5fc20000 { + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-pro5-aidet"; reg = <0x5fc20000 0x200>; interrupt-controller; @@ -453,7 +465,155 @@ }; }; - nand: nand@68000000 { + usb0: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host"; + interrupts = <0 134 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; + resets = <&usb0_rst 15>; + phys = <&usb0_hsphy0>, <&usb0_ssphy0>; + dr_mode = "host"; + }; + + usb-glue@65b00000 { + compatible = "socionext,uniphier-pro5-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb0_rst: reset@0 { + compatible = "socionext,uniphier-pro5-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + }; + + usb0_vbus0: regulator@100 { + compatible = "socionext,uniphier-pro5-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + }; + + usb0_hsphy0: hs-phy@280 { + compatible = "socionext,uniphier-pro5-usb3-hsphy"; + reg = <0x280 0x10>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + vbus-supply = <&usb0_vbus0>; + }; + + usb0_ssphy0: ss-phy@380 { + compatible = "socionext,uniphier-pro5-usb3-ssphy"; + reg = <0x380 0x10>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 14>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 14>; + vbus-supply = <&usb0_vbus0>; + }; + }; + + usb1: usb@65c00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65c00000 0xcd00>; + interrupt-names = "host"; + interrupts = <0 137 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; + resets = <&usb1_rst 15>; + phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>; + dr_mode = "host"; + }; + + usb-glue@65d00000 { + compatible = "socionext,uniphier-pro5-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65d00000 0x400>; + + usb1_rst: reset@0 { + compatible = "socionext,uniphier-pro5-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + }; + + usb1_vbus0: regulator@100 { + compatible = "socionext,uniphier-pro5-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + }; + + usb1_vbus1: regulator@110 { + compatible = "socionext,uniphier-pro5-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + }; + + usb1_hsphy0: hs-phy@280 { + compatible = "socionext,uniphier-pro5-usb3-hsphy"; + reg = <0x280 0x10>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + vbus-supply = <&usb1_vbus0>; + }; + + usb1_hsphy1: hs-phy@290 { + compatible = "socionext,uniphier-pro5-usb3-hsphy"; + reg = <0x290 0x10>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + vbus-supply = <&usb1_vbus1>; + }; + + usb1_ssphy0: ss-phy@380 { + compatible = "socionext,uniphier-pro5-usb3-ssphy"; + reg = <0x380 0x10>; + #phy-cells = <0>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 15>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 15>; + vbus-supply = <&usb1_vbus0>; + }; + }; + + nand: nand-controller@68000000 { compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled"; reg-names = "nand_data", "denali_reg"; @@ -469,7 +629,7 @@ resets = <&sys_rst 2>, <&sys_rst 2>; }; - emmc: sdhc@68400000 { + emmc: mmc@68400000 { compatible = "socionext,uniphier-sd-v3.1"; status = "disabled"; reg = <0x68400000 0x800>; @@ -485,7 +645,7 @@ non-removable; }; - sd: sdhc@68800000 { + sd: mmc@68800000 { compatible = "socionext,uniphier-sd-v3.1"; status = "disabled"; reg = <0x68800000 0x800>; diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts index e27fd4f2a569..8e9ac579aa9a 100644 --- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts +++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts @@ -26,6 +26,7 @@ i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts index 23fe42b7408b..8eacc7bdecb7 100644 --- a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts +++ b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts @@ -24,6 +24,7 @@ i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 13b0d4a7741f..b0b15c97306b 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -157,7 +157,7 @@ ranges; interrupt-parent = <&intc>; - l2: l2-cache@500c0000 { + l2: cache-controller@500c0000 { compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; @@ -173,6 +173,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -184,11 +186,13 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006100 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 216 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; + clocks = <&peri_clk 12>; + resets = <&peri_rst 12>; }; serial0: serial@54006800 { @@ -446,7 +450,7 @@ }; }; - emmc: sdhc@5a000000 { + emmc: mmc@5a000000 { compatible = "socionext,uniphier-sd-v3.1.1"; status = "disabled"; reg = <0x5a000000 0x800>; @@ -462,7 +466,7 @@ non-removable; }; - sd: sdhc@5a400000 { + sd: mmc@5a400000 { compatible = "socionext,uniphier-sd-v3.1.1"; status = "disabled"; reg = <0x5a400000 0x800>; @@ -508,7 +512,15 @@ }; }; - aidet: aidet@5fc20000 { + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-pxs2-aidet"; reg = <0x5fc20000 0x200>; interrupt-controller; @@ -761,7 +773,7 @@ }; }; - nand: nand@68000000 { + nand: nand-controller@68000000 { compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled"; reg-names = "nand_data", "denali_reg"; diff --git a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi b/arch/arm/boot/dts/uniphier-ref-daughter.dtsi index 04e60c295319..a11897669c26 100644 --- a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi +++ b/arch/arm/boot/dts/uniphier-ref-daughter.dtsi @@ -7,7 +7,7 @@ &i2c0 { eeprom@50 { - compatible = "microchip,24lc128"; + compatible = "microchip,24lc128", "atmel,24c128"; reg = <0x50>; pagesize = <64>; }; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index 4fc6676f5486..96a766deb8d1 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -51,7 +51,7 @@ ranges; interrupt-parent = <&intc>; - l2: l2-cache@500c0000 { + l2: cache-controller@500c0000 { compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; @@ -67,6 +67,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -249,7 +251,7 @@ #dma-cells = <1>; }; - sd: sdhc@5a400000 { + sd: mmc@5a400000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a400000 0x200>; @@ -269,7 +271,7 @@ sd-uhs-sdr50; }; - emmc: sdhc@5a500000 { + emmc: mmc@5a500000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; reg = <0x5a500000 0x200>; @@ -379,7 +381,7 @@ interrupt-controller; }; - aidet: aidet@61830000 { + aidet: interrupt-controller@61830000 { compatible = "socionext,uniphier-sld8-aidet"; reg = <0x61830000 0x200>; interrupt-controller; @@ -402,7 +404,7 @@ }; }; - nand: nand@68000000 { + nand: nand-controller@68000000 { compatible = "socionext,uniphier-denali-nand-v5a"; status = "disabled"; reg-names = "nand_data", "denali_reg"; diff --git a/arch/arm/boot/dts/versatile-ab-ib2.dts b/arch/arm/boot/dts/versatile-ab-ib2.dts index 5890cb974f78..c577ff4bb4be 100644 --- a/arch/arm/boot/dts/versatile-ab-ib2.dts +++ b/arch/arm/boot/dts/versatile-ab-ib2.dts @@ -10,7 +10,7 @@ model = "ARM Versatile AB + IB2 board"; /* Special IB2 control register */ - ib2_syscon@27000000 { + syscon@27000000 { compatible = "arm,versatile-ib2-syscon", "syscon", "simple-mfd"; reg = <0x27000000 0x4>; diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index dfae90adbb7c..e6308fb76183 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -19,8 +19,162 @@ */ / { - smb@8000000 { - motherboard { + v2m_fixed_3v3: fixed-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + leds { + compatible = "gpio-leds"; + + led-1 { + label = "v2m:green:user1"; + gpios = <&v2m_led_gpios 0 0>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + label = "v2m:green:user2"; + gpios = <&v2m_led_gpios 1 0>; + linux,default-trigger = "disk-activity"; + }; + + led-3 { + label = "v2m:green:user3"; + gpios = <&v2m_led_gpios 2 0>; + linux,default-trigger = "cpu0"; + }; + + led-4 { + label = "v2m:green:user4"; + gpios = <&v2m_led_gpios 3 0>; + linux,default-trigger = "cpu1"; + }; + + led-5 { + label = "v2m:green:user5"; + gpios = <&v2m_led_gpios 4 0>; + linux,default-trigger = "cpu2"; + }; + + led-6 { + label = "v2m:green:user6"; + gpios = <&v2m_led_gpios 5 0>; + linux,default-trigger = "cpu3"; + }; + + led-7 { + label = "v2m:green:user7"; + gpios = <&v2m_led_gpios 6 0>; + linux,default-trigger = "cpu4"; + }; + + led-8 { + label = "v2m:green:user8"; + gpios = <&v2m_led_gpios 7 0>; + linux,default-trigger = "cpu5"; + }; + }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + oscclk0 { + /* MCC static memory clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <25000000 60000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk0"; + }; + + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 65000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + v2m_oscclk2: oscclk2 { + /* IO FPGA peripheral clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <24000000 24000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk2"; + }; + + volt-vio { + /* Logic level voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VIO"; + regulator-always-on; + label = "VIO"; + }; + + temp-mcc { + /* MCC internal operating temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "MCC"; + }; + + reset { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + + bus@8000000 { + motherboard-bus { model = "V2M-P1"; arm,hbi = <0x190>; arm,vexpress,site = <0>; @@ -31,7 +185,7 @@ #interrupt-cells = <1>; ranges; - nor_flash: flash@0,00000000 { + nor_flash: flash@0 { compatible = "arm,vexpress-flash", "cfi-flash"; reg = <0 0x00000000 0x04000000>, <4 0x00000000 0x04000000>; @@ -41,13 +195,13 @@ }; }; - psram@1,00000000 { + psram@100000000 { compatible = "arm,vexpress-psram", "mtd-ram"; reg = <1 0x00000000 0x02000000>; bank-width = <4>; }; - ethernet@2,02000000 { + ethernet@202000000 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <2 0x02000000 0x10000>; interrupts = <15>; @@ -59,14 +213,14 @@ vddvario-supply = <&v2m_fixed_3v3>; }; - usb@2,03000000 { + usb@203000000 { compatible = "nxp,usb-isp1761"; reg = <2 0x03000000 0x20000>; interrupts = <16>; port1-otg; }; - iofpga@3,00000000 { + iofpga-bus@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -162,7 +316,7 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; - v2m_serial0: uart@90000 { + v2m_serial0: serial@90000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; @@ -170,7 +324,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial1: uart@a0000 { + v2m_serial1: serial@a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; @@ -178,7 +332,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial2: uart@b0000 { + v2m_serial2: serial@b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; @@ -186,7 +340,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial3: uart@c0000 { + v2m_serial3: serial@c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; @@ -282,160 +436,6 @@ }; }; }; - - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - leds { - compatible = "gpio-leds"; - - user1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "mmc0"; - }; - - user3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; - - user4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; - - user5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; - - user6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - user7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - user8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; }; }; }; diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index 2e29d7790497..5e48b641068a 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi @@ -19,7 +19,7 @@ */ / { - smb@4000000 { + bus@4000000 { motherboard { model = "V2M-P1"; arm,hbi = <0x190>; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts index 0dc4277d5f8b..f82fa34c90be 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts @@ -236,7 +236,7 @@ }; }; - smb@8000000 { + bus@8000000 { compatible = "simple-bus"; #address-cells = <2>; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 1de0a658adf1..3ac95a179452 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -608,7 +608,7 @@ }; }; - smb: smb@8000000 { + smb: bus@8000000 { compatible = "simple-bus"; #address-cells = <2>; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts index d5b47d526f9e..7aa64ae25779 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts @@ -206,7 +206,7 @@ }; }; - smb: smb@8000000 { + smb: bus@8000000 { compatible = "simple-bus"; #address-cells = <2>; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts index d796efaadbe3..623246f37448 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts @@ -295,7 +295,7 @@ }; }; - smb: smb@4000000 { + smb: bus@4000000 { compatible = "simple-bus"; #address-cells = <2>; diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi index e2da122a63f4..c12a1b8bc086 100644 --- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2014-2020 Toradex */ / { diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi index fba37b8756f7..cc1e069c44e6 100644 --- a/arch/arm/boot/dts/vf-colibri.dtsi +++ b/arch/arm/boot/dts/vf-colibri.dtsi @@ -1,42 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2014 Toradex AG + * Copyright 2014-2020 Toradex * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ / { diff --git a/arch/arm/boot/dts/vf500-colibri-eval-v3.dts b/arch/arm/boot/dts/vf500-colibri-eval-v3.dts index 076998968fb5..088964f8dc4b 100644 --- a/arch/arm/boot/dts/vf500-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/vf500-colibri-eval-v3.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2014-2020 Toradex */ /dts-v1/; diff --git a/arch/arm/boot/dts/vf500-colibri.dtsi b/arch/arm/boot/dts/vf500-colibri.dtsi index 92255f8893ce..8af7ed56e653 100644 --- a/arch/arm/boot/dts/vf500-colibri.dtsi +++ b/arch/arm/boot/dts/vf500-colibri.dtsi @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2014-2020 Toradex */ #include "vf500.dtsi" diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi index b0ec475017ad..0c0dd442300a 100644 --- a/arch/arm/boot/dts/vf500.dtsi +++ b/arch/arm/boot/dts/vf500.dtsi @@ -23,7 +23,7 @@ }; soc { - aips-bus@40000000 { + bus@40000000 { intc: interrupt-controller@40003000 { compatible = "arm,cortex-a9-gic"; @@ -43,7 +43,7 @@ }; }; - aips-bus@40080000 { + bus@40080000 { pmu@40089000 { compatible = "arm,cortex-a5-pmu"; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts index ef9b4d6209f6..fb661e8a2dc6 100644 --- a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2014-2020 Toradex */ /dts-v1/; diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi index 05c9a39509b8..607cec2df861 100644 --- a/arch/arm/boot/dts/vf610-colibri.dtsi +++ b/arch/arm/boot/dts/vf610-colibri.dtsi @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2014 Toradex AG - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2014-2020 Toradex */ #include "vf610.dtsi" diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index 28732249cfc0..ce1920c052fc 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -71,6 +71,14 @@ los-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; tx-disable-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; }; + + supply-voltage-monitor { + compatible = "iio-hwmon"; + io-channels = <&adc0 8>, /* 28VDC_IN */ + <&adc0 9>, /* +3.3V */ + <&adc1 8>, /* VCC_1V5 */ + <&adc1 9>; /* VCC_1V2 */ + }; }; &adc0 { diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi index a1b4ccee2a10..95d0060fb56c 100644 --- a/arch/arm/boot/dts/vf610-zii-dev.dtsi +++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi @@ -84,6 +84,14 @@ regulator-boot-on; gpio = <&gpio0 6 0>; }; + + supply-voltage-monitor { + compatible = "iio-hwmon"; + io-channels = <&adc0 8>, /* VCC_1V5 */ + <&adc0 9>, /* VCC_1V8 */ + <&adc1 8>, /* VCC_1V0 */ + <&adc1 9>; /* VCC_1V2 */ + }; }; &adc0 { diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/vf610-zii-spb4.dts index 77e1484211e4..55b4201e27f6 100644 --- a/arch/arm/boot/dts/vf610-zii-spb4.dts +++ b/arch/arm/boot/dts/vf610-zii-spb4.dts @@ -42,6 +42,14 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + supply-voltage-monitor { + compatible = "iio-hwmon"; + io-channels = <&adc0 8>, /* 28V_SW */ + <&adc0 9>, /* +3.3V */ + <&adc1 8>, /* VCC_1V5 */ + <&adc1 9>; /* VCC_1V2 */ + }; }; &adc0 { diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts index 847c5858fea1..a6c22a79779e 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts @@ -46,6 +46,14 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + supply-voltage-monitor { + compatible = "iio-hwmon"; + io-channels = <&adc0 8>, /* 12V_MAIN */ + <&adc0 9>, /* +3.3V */ + <&adc1 8>, /* VCC_1V5 */ + <&adc1 9>; /* VCC_1V2 */ + }; }; &adc0 { diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index 453fce80f858..3d05c894bdc0 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -46,6 +46,14 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + supply-voltage-monitor { + compatible = "iio-hwmon"; + io-channels = <&adc0 8>, /* 12V_MAIN */ + <&adc0 9>, /* +3.3V */ + <&adc1 8>, /* VCC_1V5 */ + <&adc1 9>; /* VCC_1V2 */ + }; }; &adc0 { diff --git a/arch/arm/boot/dts/vf610m4-colibri.dts b/arch/arm/boot/dts/vf610m4-colibri.dts index d4bc0e3f2f11..2c2db47af441 100644 --- a/arch/arm/boot/dts/vf610m4-colibri.dts +++ b/arch/arm/boot/dts/vf610m4-colibri.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* * Device tree for Colibri VF61 Cortex-M4 support * * Copyright (C) 2015 Stefan Agner - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 028e0ec30e0c..2d547e7b21ad 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -59,7 +59,7 @@ interrupt-parent = <&mscm_ir>; ranges; - aips0: aips-bus@40000000 { + aips0: bus@40000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -471,7 +471,7 @@ }; }; - aips1: aips-bus@40080000 { + aips1: bus@40080000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; |