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Diffstat (limited to 'arch/arm64/boot/dts/qcom/msm8998.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/msm8998.dtsi417
1 files changed, 351 insertions, 66 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index f0e943ff0046..f180047cacb0 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -316,73 +316,98 @@
};
};
+ dsi_opp_table: opp-table-dsi {
+ compatible = "operating-points-v2";
+
+ opp-131250000 {
+ opp-hz = /bits/ 64 <131250000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-210000000 {
+ opp-hz = /bits/ 64 <210000000>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+
+ opp-312500000 {
+ opp-hz = /bits/ 64 <312500000>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
- rpm-glink {
- compatible = "qcom,glink-rpm";
+ rpm: remoteproc {
+ compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,rpm-msg-ram = <&rpm_msg_ram>;
- mboxes = <&apcs_glb 0>;
+ glink-edge {
+ compatible = "qcom,glink-rpm";
- rpm_requests: rpm-requests {
- compatible = "qcom,rpm-msm8998";
- qcom,glink-channels = "rpm_requests";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
- rpmcc: clock-controller {
- compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
- #clock-cells = <1>;
- };
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-msm8998";
+ qcom,glink-channels = "rpm_requests";
- rpmpd: power-controller {
- compatible = "qcom,msm8998-rpmpd";
- #power-domain-cells = <1>;
- operating-points-v2 = <&rpmpd_opp_table>;
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
+ clocks = <&xo>;
+ clock-names = "xo";
+ #clock-cells = <1>;
+ };
- rpmpd_opp_table: opp-table {
- compatible = "operating-points-v2";
+ rpmpd: power-controller {
+ compatible = "qcom,msm8998-rpmpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmpd_opp_table>;
- rpmpd_opp_ret: opp1 {
- opp-level = <RPM_SMD_LEVEL_RETENTION>;
- };
+ rpmpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
- rpmpd_opp_ret_plus: opp2 {
- opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
- };
+ rpmpd_opp_ret: opp1 {
+ opp-level = <RPM_SMD_LEVEL_RETENTION>;
+ };
- rpmpd_opp_min_svs: opp3 {
- opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
- };
+ rpmpd_opp_ret_plus: opp2 {
+ opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
+ };
- rpmpd_opp_low_svs: opp4 {
- opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
- };
+ rpmpd_opp_min_svs: opp3 {
+ opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
+ };
- rpmpd_opp_svs: opp5 {
- opp-level = <RPM_SMD_LEVEL_SVS>;
- };
+ rpmpd_opp_low_svs: opp4 {
+ opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
+ };
- rpmpd_opp_svs_plus: opp6 {
- opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
- };
+ rpmpd_opp_svs: opp5 {
+ opp-level = <RPM_SMD_LEVEL_SVS>;
+ };
- rpmpd_opp_nom: opp7 {
- opp-level = <RPM_SMD_LEVEL_NOM>;
- };
+ rpmpd_opp_svs_plus: opp6 {
+ opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+ };
- rpmpd_opp_nom_plus: opp8 {
- opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
- };
+ rpmpd_opp_nom: opp7 {
+ opp-level = <RPM_SMD_LEVEL_NOM>;
+ };
- rpmpd_opp_turbo: opp9 {
- opp-level = <RPM_SMD_LEVEL_TURBO>;
- };
+ rpmpd_opp_nom_plus: opp8 {
+ opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+ };
- rpmpd_opp_turbo_plus: opp10 {
- opp-level = <RPM_SMD_LEVEL_BINNING>;
+ rpmpd_opp_turbo: opp9 {
+ opp-level = <RPM_SMD_LEVEL_TURBO>;
+ };
+
+ rpmpd_opp_turbo_plus: opp10 {
+ opp-level = <RPM_SMD_LEVEL_BINNING>;
+ };
};
};
};
@@ -909,10 +934,10 @@
pcie0: pci@1c00000 {
compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
- reg = <0x01c00000 0x2000>,
- <0x1b000000 0xf1d>,
- <0x1b000f20 0xa8>,
- <0x1b100000 0x100000>;
+ reg = <0x01c00000 0x2000>,
+ <0x1b000000 0xf1d>,
+ <0x1b000f20 0xa8>,
+ <0x1b100000 0x100000>;
reg-names = "parf", "dbi", "elbi", "config";
device_type = "pci";
linux,pci-domain = <0>;
@@ -1488,7 +1513,7 @@
"rbcpr",
"core";
- interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&adreno_smmu 0>;
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&rpmpd MSM8998_VDDMX>;
@@ -1574,7 +1599,7 @@
reg = <0x05065000 0x9000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
- <&gcc GPLL0_OUT_MAIN>;
+ <&gcc GCC_GPU_GPLL0_CLK>;
clock-names = "xo",
"gpll0";
};
@@ -2074,11 +2099,11 @@
spmi_bus: spmi@800f000 {
compatible = "qcom,spmi-pmic-arb";
- reg = <0x0800f000 0x1000>,
- <0x08400000 0x1000000>,
- <0x09400000 0x1000000>,
- <0x0a400000 0x220000>,
- <0x0800a000 0x3000>;
+ reg = <0x0800f000 0x1000>,
+ <0x08400000 0x1000000>,
+ <0x09400000 0x1000000>,
+ <0x0a400000 0x220000>,
+ <0x0800a000 0x3000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
@@ -2718,16 +2743,274 @@
"dsi1byte",
"hdmipll",
"dplink",
- "dpvco";
+ "dpvco",
+ "gpll0_div";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_MMSS_GPLL0_CLK>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi1_phy 1>,
+ <&mdss_dsi1_phy 0>,
<0>,
<0>,
<0>,
- <0>,
- <0>,
- <0>,
- <0>;
+ <&gcc GCC_MMSS_GPLL0_DIV_CLK>;
+ };
+
+ mdss: display-subsystem@c900000 {
+ compatible = "qcom,msm8998-mdss";
+ reg = <0x0c900000 0x1000>;
+ reg-names = "mdss";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ clocks = <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MDSS_MDP_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core";
+
+ power-domains = <&mmcc MDSS_GDSC>;
+ iommus = <&mmss_smmu 0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@c901000 {
+ compatible = "qcom,msm8998-dpu";
+ reg = <0x0c901000 0x8f000>,
+ <0x0c9a8e00 0xf0>,
+ <0x0c9b0000 0x2008>,
+ <0x0c9b8000 0x1040>;
+ reg-names = "mdp",
+ "regdma",
+ "vbif",
+ "vbif_nrt";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ clocks = <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MNOC_AHB_CLK>,
+ <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_VSYNC_CLK>;
+ clock-names = "iface",
+ "bus",
+ "mnoc",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd MSM8998_VDDMX>;
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-171430000 {
+ opp-hz = /bits/ 64 <171430000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-275000000 {
+ opp-hz = /bits/ 64 <275000000>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+
+ opp-330000000 {
+ opp-hz = /bits/ 64 <330000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
+
+ opp-412500000 {
+ opp-hz = /bits/ 64 <412500000>;
+ required-opps = <&rpmpd_opp_turbo>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&mdss_dsi1_in>;
+ };
+ };
+ };
+ };
+
+ mdss_dsi0: dsi@c994000 {
+ compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0c994000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&mmcc MDSS_BYTE0_CLK>,
+ <&mmcc MDSS_BYTE0_INTF_CLK>,
+ <&mmcc MDSS_PCLK0_CLK>,
+ <&mmcc MDSS_ESC0_CLK>,
+ <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+ assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
+ <&mmcc PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmpd MSM8998_VDDCX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@c994400 {
+ compatible = "qcom,dsi-phy-10nm-8998";
+ reg = <0x0c994400 0x200>,
+ <0x0c994600 0x280>,
+ <0x0c994a00 0x1e0>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ clocks = <&mmcc MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss_dsi1: dsi@c996000 {
+ compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0c996000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5>;
+
+ clocks = <&mmcc MDSS_BYTE1_CLK>,
+ <&mmcc MDSS_BYTE1_INTF_CLK>,
+ <&mmcc MDSS_PCLK1_CLK>,
+ <&mmcc MDSS_ESC1_CLK>,
+ <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+ assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
+ <&mmcc PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmpd MSM8998_VDDCX>;
+
+ phys = <&mdss_dsi1_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dsi1_in: endpoint {
+ remote-endpoint = <&dpu_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi1_phy: phy@c996400 {
+ compatible = "qcom,dsi-phy-10nm-8998";
+ reg = <0x0c996400 0x200>,
+ <0x0c996600 0x280>,
+ <0x0c996a00 0x10e>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ clocks = <&mmcc MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
};
mmss_smmu: iommu@cd00000 {
@@ -2737,10 +3020,10 @@
clocks = <&mmcc MNOC_AHB_CLK>,
<&mmcc BIMC_SMMU_AHB_CLK>,
- <&rpmcc RPM_SMD_MMAXI_CLK>,
<&mmcc BIMC_SMMU_AXI_CLK>;
- clock-names = "iface-mm", "iface-smmu",
- "bus-mm", "bus-smmu";
+ clock-names = "iface-mm",
+ "iface-smmu",
+ "bus-smmu";
#global-interrupts = <0>;
interrupts =
@@ -2764,6 +3047,8 @@
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&mmcc BIMC_SMMU_GDSC>;
};
remoteproc_adsp: remoteproc@17300000 {
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-05 03:55:18 +0300