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Diffstat (limited to 'arch/arm64/boot/dts/qcom/sc8180x.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/sc8180x.dtsi177
1 files changed, 65 insertions, 112 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 486f7ffef43b..a34f438ef2d9 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -1749,23 +1749,28 @@
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
- phys = <&pcie0_lane>;
+ phys = <&pcie0_phy>;
phy-names = "pciephy";
status = "disabled";
};
- pcie0_phy: phy-wrapper@1c06000 {
+ pcie0_phy: phy@1c06000 {
compatible = "qcom,sc8180x-qmp-pcie-phy";
- reg = <0 0x1c06000 0 0x1c0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01c06000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
- <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "refgen";
+ <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+ #clock-cells = <0>;
+ clock-output-names = "pcie_0_pipe_clk";
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
@@ -1774,21 +1779,6 @@
assigned-clock-rates = <100000000>;
status = "disabled";
-
- pcie0_lane: phy@1c06200 {
- reg = <0 0x1c06200 0 0x170>, /* tx0 */
- <0 0x1c06400 0 0x200>, /* rx0 */
- <0 0x1c06a00 0 0x1f0>, /* pcs */
- <0 0x1c06600 0 0x170>, /* tx1 */
- <0 0x1c06800 0 0x200>, /* rx1 */
- <0 0x1c06e00 0 0xf4>; /* pcs_com */
- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
- clock-names = "pipe0";
-
- #clock-cells = <0>;
- clock-output-names = "pcie_0_pipe_clk";
- #phy-cells = <0>;
- };
};
pcie3: pci@1c08000 {
@@ -1856,23 +1846,29 @@
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
- phys = <&pcie3_lane>;
+ phys = <&pcie3_phy>;
phy-names = "pciephy";
status = "disabled";
};
- pcie3_phy: phy-wrapper@1c0c000 {
+ pcie3_phy: phy@1c0c000 {
compatible = "qcom,sc8180x-qmp-pcie-phy";
- reg = <0 0x1c0c000 0 0x1c0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01c0c000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
<&gcc GCC_PCIE_3_CLKREF_CLK>,
- <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "refgen";
+ <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
+ <&gcc GCC_PCIE_3_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+ #clock-cells = <0>;
+ clock-output-names = "pcie_3_pipe_clk";
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_3_PHY_BCR>;
reset-names = "phy";
@@ -1881,21 +1877,6 @@
assigned-clock-rates = <100000000>;
status = "disabled";
-
- pcie3_lane: phy@1c0c200 {
- reg = <0 0x1c0c200 0 0x170>, /* tx0 */
- <0 0x1c0c400 0 0x200>, /* rx0 */
- <0 0x1c0ca00 0 0x1f0>, /* pcs */
- <0 0x1c0c600 0 0x170>, /* tx1 */
- <0 0x1c0c800 0 0x200>, /* rx1 */
- <0 0x1c0ce00 0 0xf4>; /* pcs_com */
- clocks = <&gcc GCC_PCIE_3_PIPE_CLK>;
- clock-names = "pipe0";
-
- #clock-cells = <0>;
- clock-output-names = "pcie_3_pipe_clk";
- #phy-cells = <0>;
- };
};
pcie1: pci@1c10000 {
@@ -1963,23 +1944,29 @@
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
- phys = <&pcie1_lane>;
+ phys = <&pcie1_phy>;
phy-names = "pciephy";
status = "disabled";
};
- pcie1_phy: phy-wrapper@1c16000 {
+ pcie1_phy: phy@1c16000 {
compatible = "qcom,sc8180x-qmp-pcie-phy";
- reg = <0 0x1c16000 0 0x1c0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01c16000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_CLKREF_CLK>,
- <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "refgen";
+ <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
+ <&gcc GCC_PCIE_1_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+ #clock-cells = <0>;
+ clock-output-names = "pcie_1_pipe_clk";
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
@@ -1988,21 +1975,6 @@
assigned-clock-rates = <100000000>;
status = "disabled";
-
- pcie1_lane: phy@1c0e200 {
- reg = <0 0x1c16200 0 0x170>, /* tx0 */
- <0 0x1c16400 0 0x200>, /* rx0 */
- <0 0x1c16a00 0 0x1f0>, /* pcs */
- <0 0x1c16600 0 0x170>, /* tx1 */
- <0 0x1c16800 0 0x200>, /* rx1 */
- <0 0x1c16e00 0 0xf4>; /* pcs_com */
- clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
- clock-names = "pipe0";
- #clock-cells = <0>;
- clock-output-names = "pcie_1_pipe_clk";
-
- #phy-cells = <0>;
- };
};
pcie2: pci@1c18000 {
@@ -2070,23 +2042,29 @@
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
- phys = <&pcie2_lane>;
+ phys = <&pcie2_phy>;
phy-names = "pciephy";
status = "disabled";
};
- pcie2_phy: phy-wrapper@1c1c000 {
+ pcie2_phy: phy@1c1c000 {
compatible = "qcom,sc8180x-qmp-pcie-phy";
- reg = <0 0x1c1c000 0 0x1c0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01c1c000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
<&gcc GCC_PCIE_2_CLKREF_CLK>,
- <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "refgen";
+ <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
+ <&gcc GCC_PCIE_2_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+ #clock-cells = <0>;
+ clock-output-names = "pcie_3_pipe_clk";
+
+ #phy-cells = <0>;
resets = <&gcc GCC_PCIE_2_PHY_BCR>;
reset-names = "phy";
@@ -2095,22 +2073,6 @@
assigned-clock-rates = <100000000>;
status = "disabled";
-
- pcie2_lane: phy@1c0e200 {
- reg = <0 0x1c1c200 0 0x170>, /* tx0 */
- <0 0x1c1c400 0 0x200>, /* rx0 */
- <0 0x1c1ca00 0 0x1f0>, /* pcs */
- <0 0x1c1c600 0 0x170>, /* tx1 */
- <0 0x1c1c800 0 0x200>, /* rx1 */
- <0 0x1c1ce00 0 0xf4>; /* pcs_com */
- clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
- clock-names = "pipe0";
-
- #clock-cells = <0>;
- clock-output-names = "pcie_2_pipe_clk";
-
- #phy-cells = <0>;
- };
};
ufs_mem_hc: ufshc@1d84000 {
@@ -2118,7 +2080,7 @@
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -2157,10 +2119,8 @@
ufs_mem_phy: phy-wrapper@1d87000 {
compatible = "qcom,sc8180x-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x1c0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01d87000 0 0x1000>;
+
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clock-names = "ref",
@@ -2168,16 +2128,10 @@
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x108>,
- <0 0x01d87600 0 0x1e0>,
- <0 0x01d87c00 0 0x1dc>,
- <0 0x01d87800 0 0x108>,
- <0 0x01d87a00 0 0x1e0>;
- #phy-cells = <0>;
- };
+ #phy-cells = <0>;
+
+ status = "disabled";
};
ipa_virt: interconnect@1e00000 {
@@ -2606,14 +2560,14 @@
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
- <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
clock-names = "cfg_noc",
"core",
"iface",
- "mock_utmi",
"sleep",
+ "mock_utmi",
"xo";
resets = <&gcc GCC_USB30_PRIM_BCR>;
power-domains = <&gcc USB30_PRIM_GDSC>;
@@ -2657,14 +2611,14 @@
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
- <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
+ <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
clock-names = "cfg_noc",
"core",
"iface",
- "mock_utmi",
"sleep",
+ "mock_utmi",
"xo";
resets = <&gcc GCC_USB30_SEC_BCR>;
power-domains = <&gcc USB30_SEC_GDSC>;
@@ -3307,7 +3261,6 @@
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
- cell-index = <0>;
};
apps_smmu: iommu@15000000 {
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-13 10:53:58 +0300