diff options
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm6125.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm6125.dtsi | 68 |
1 files changed, 66 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 65033227718a..9484752fb850 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -737,6 +737,70 @@ status = "disabled"; }; + ufs_mem_hc: ufs@4804000 { + compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x04804000 0x3000>, <0x04810000 0x8000>; + reg-names = "std", "ice"; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "ice_core_clk"; + freq-table-hz = <50000000 240000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>, + <75000000 300000000>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + #reset-cells = <1>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + lanes-per-direction = <1>; + + iommus = <&apps_smmu 0x200 0x0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@4807000 { + compatible = "qcom,sm6125-qmp-ufs-phy"; + reg = <0x04807000 0xdb8>; + + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", + "ref_aux"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + #phy-cells = <0>; + + status = "disabled"; + }; + gpi_dma0: dma-controller@4a00000 { compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; reg = <0x04a00000 0x60000>; @@ -1134,7 +1198,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; apps_smmu: iommu@c600000 { @@ -1211,7 +1274,8 @@ }; apcs_glb: mailbox@f111000 { - compatible = "qcom,sm6125-apcs-hmss-global"; + compatible = "qcom,sm6125-apcs-hmss-global", + "qcom,msm8994-apcs-kpss-global"; reg = <0x0f111000 0x1000>; #mbox-cells = <1>; |