diff options
Diffstat (limited to 'arch/arm64/boot/dts/renesas')
18 files changed, 942 insertions, 157 deletions
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 2153842321ce..d17351cdbce0 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -1,14 +1,12 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb +dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb \ - r8a774c0-ek874-idk-2121wr.dtb -dtb-$(CONFIG_ARCH_R8A7795) += r8a77950-salvator-x.dtb -dtb-$(CONFIG_ARCH_R8A7795) += r8a77950-ulcb.dtb r8a77950-ulcb-kf.dtb -dtb-$(CONFIG_ARCH_R8A7795) += r8a77951-salvator-x.dtb r8a77951-salvator-xs.dtb -dtb-$(CONFIG_ARCH_R8A7795) += r8a77951-ulcb.dtb r8a77951-ulcb-kf.dtb + r8a774c0-ek874-idk-2121wr.dtb \ + r8a774c0-ek874-mipi-2.1.dtb dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb r8a77950-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x.dtb r8a77951-salvator-xs.dtb @@ -16,6 +14,7 @@ dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb.dtb r8a77951-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-x.dtb r8a77960-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb.dtb r8a77960-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-salvator-xs.dtb +dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb.dtb r8a77965-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb diff --git a/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi b/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi new file mode 100644 index 000000000000..dac6ff49020f --- /dev/null +++ b/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the AISTARVISION MIPI Adapter V2.1 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/ { + ov5645_vdddo_1v8: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "camera_vdddo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ov5645_vdda_2v8: 2p8v { + compatible = "regulator-fixed"; + regulator-name = "camera_vdda"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ov5645_vddd_1v5: 1p5v { + compatible = "regulator-fixed"; + regulator-name = "camera_vddd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + imx219_vana_2v8: 2p8v { + compatible = "regulator-fixed"; + regulator-name = "camera_vana"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + imx219_vdig_1v8: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "camera_vdig"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + imx219_vddl_1v2: 1p2v { + compatible = "regulator-fixed"; + regulator-name = "camera_vddl"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + osc25250_clk: osc25250_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&MIPI_PARENT_I2C { + ov5645: ov5645@3c { + compatible = "ovti,ov5645"; + reg = <0x3c>; + clock-names = "xclk"; + clocks = <&osc25250_clk>; + clock-frequency = <24000000>; + vdddo-supply = <&ov5645_vdddo_1v8>; + vdda-supply = <&ov5645_vdda_2v8>; + vddd-supply = <&ov5645_vddd_1v5>; + + port { + ov5645_ep: endpoint { + }; + }; + }; + + imx219: imx219@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&osc25250_clk>; + VANA-supply = <&imx219_vana_2v8>; + VDIG-supply = <&imx219_vdig_1v8>; + VDDL-supply = <&imx219_vddl_1v2>; + + port { + imx219_ep: endpoint { + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts new file mode 100644 index 000000000000..2ab5edd84e9b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2M sub board connected to an + * Advantech IDK-1110WR 10.1" LVDS panel + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include "r8a774a1-hihope-rzg2m-ex.dts" +#include "rzg2-advantech-idk-1110wr-panel.dtsi" + +/ { + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 50000>; + + brightness-levels = <0 2 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + +}; + +&gpio1 { + /* + * When GP1_20 is LOW LVDS0 is connected to the LVDS connector + * When GP1_20 is HIGH LVDS0 is connected to the LT8918L + */ + lvds-connector-en-gpio { + gpio-hog; + gpios = <20 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "lvds-connector-en-gpio"; + }; +}; + +&lvds0 { + status = "okay"; +}; + +&pfc { + pwm0_pins: pwm0 { + groups = "pwm0"; + function = "pwm0"; + }; +}; + +&pwm0 { + pinctrl-0 = <&pwm0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 8f950dabca54..a603d947970e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1000,7 +1000,7 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -1008,7 +1008,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -1016,7 +1016,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -1024,7 +1024,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xe67b0000 0 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, @@ -1033,7 +1033,7 @@ #iommu-cells = <1>; }; - ipmmu_mp: mmu@ec670000 { + ipmmu_mp: iommu@ec670000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -1041,7 +1041,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 5>; @@ -1049,7 +1049,7 @@ #iommu-cells = <1>; }; - ipmmu_pv1: mmu@fd950000 { + ipmmu_pv1: iommu@fd950000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xfd950000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -1057,7 +1057,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 8>; @@ -1065,7 +1065,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 9>; @@ -2634,13 +2634,14 @@ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>; clock-names = "du.0", "du.1", "du.2"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.2"; status = "disabled"; - vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; ports { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index c40ea300968e..1e51855c7cd3 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -874,7 +874,7 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -882,7 +882,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -890,7 +890,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -898,7 +898,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xe67b0000 0 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, @@ -907,7 +907,7 @@ #iommu-cells = <1>; }; - ipmmu_mp: mmu@ec670000 { + ipmmu_mp: iommu@ec670000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -915,7 +915,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -923,7 +923,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 12>; @@ -931,7 +931,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 14>; @@ -939,7 +939,7 @@ #iommu-cells = <1>; }; - ipmmu_vp0: mmu@fe990000 { + ipmmu_vp0: iommu@fe990000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xfe990000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 16>; @@ -2480,13 +2480,14 @@ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 721>; clock-names = "du.0", "du.1", "du.3"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.3"; status = "disabled"; - vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; ports { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts new file mode 100644 index 000000000000..f0829e905506 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874) + * connected with aistarvision-mipi-v2-adapter board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774c0-ek874.dts" +#define MIPI_PARENT_I2C i2c3 +#include "aistarvision-mipi-adapter-2.1.dtsi" + +/ { + model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875) with aistarvision-mipi-v2-adapter board"; + compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0"; +}; + +&i2c3 { + status = "okay"; +}; + +&vin4 { + status = "okay"; +}; + +&vin5 { + status = "okay"; +}; + +&csi40 { + status = "okay"; + + ports { + port { + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&ov5645_ep>; + }; + }; + }; +}; + +&ov5645 { + enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + + port { + ov5645_ep: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&csi40_in>; + }; + }; +}; + +&imx219 { + port { + imx219_ep: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + /* uncomment remote-endpoint property to tie imx219 to + * CSI2 also make sure remote-endpoint for ov5645 camera + * is commented and remote endpoint phandle in csi40_in + * is imx219_ep + */ + /* remote-endpoint = <&csi40_in>; */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index a53cd5fcc401..5c72a7efbb03 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -847,7 +847,7 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -855,7 +855,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -863,7 +863,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -871,7 +871,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xe67b0000 0 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, @@ -880,7 +880,7 @@ #iommu-cells = <1>; }; - ipmmu_mp: mmu@ec670000 { + ipmmu_mp: iommu@ec670000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -888,7 +888,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -896,7 +896,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 12>; @@ -904,7 +904,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 14>; @@ -912,7 +912,7 @@ #iommu-cells = <1>; }; - ipmmu_vp0: mmu@fe990000 { + ipmmu_vp0: iommu@fe990000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xfe990000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 16>; @@ -1810,10 +1810,12 @@ reg = <0 0xfeb00000 0 0x40000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; - vsps = <&vspd0 0>, <&vspd1 0>; + resets = <&cpg 724>; + reset-names = "du.0"; + renesas,vsps = <&vspd0 0>, <&vspd1 0>; + status = "disabled"; ports { diff --git a/arch/arm64/boot/dts/renesas/r8a77950.dtsi b/arch/arm64/boot/dts/renesas/r8a77950.dtsi index 15216495e1c8..d716c4386ae9 100644 --- a/arch/arm64/boot/dts/renesas/r8a77950.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77950.dtsi @@ -30,7 +30,7 @@ }; &du { - vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>; + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>; }; &fcpvb1 { @@ -77,7 +77,7 @@ /delete-node/ dma-controller@e6460000; /delete-node/ dma-controller@e6470000; - ipmmu_mp1: mmu@ec680000 { + ipmmu_mp1: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xec680000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 5>; @@ -85,7 +85,7 @@ #iommu-cells = <1>; }; - ipmmu_sy: mmu@e7730000 { + ipmmu_sy: iommu@e7730000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xe7730000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 8>; @@ -93,11 +93,11 @@ #iommu-cells = <1>; }; - /delete-node/ mmu@fd950000; - /delete-node/ mmu@fd960000; - /delete-node/ mmu@fd970000; - /delete-node/ mmu@febe0000; - /delete-node/ mmu@fe980000; + /delete-node/ iommu@fd950000; + /delete-node/ iommu@fd960000; + /delete-node/ iommu@fd970000; + /delete-node/ iommu@febe0000; + /delete-node/ iommu@fe980000; xhci1: usb@ee040000 { compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index a8729eb744db..61d67d9714ab 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -1073,7 +1073,7 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -1081,7 +1081,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -1089,7 +1089,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -1097,7 +1097,7 @@ #iommu-cells = <1>; }; - ipmmu_ir: mmu@ff8b0000 { + ipmmu_ir: iommu@ff8b0000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xff8b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 3>; @@ -1105,7 +1105,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xe67b0000 0 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, @@ -1114,7 +1114,7 @@ #iommu-cells = <1>; }; - ipmmu_mp0: mmu@ec670000 { + ipmmu_mp0: iommu@ec670000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -1122,7 +1122,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -1130,7 +1130,7 @@ #iommu-cells = <1>; }; - ipmmu_pv1: mmu@fd950000 { + ipmmu_pv1: iommu@fd950000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfd950000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 7>; @@ -1138,7 +1138,7 @@ #iommu-cells = <1>; }; - ipmmu_pv2: mmu@fd960000 { + ipmmu_pv2: iommu@fd960000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfd960000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 8>; @@ -1146,7 +1146,7 @@ #iommu-cells = <1>; }; - ipmmu_pv3: mmu@fd970000 { + ipmmu_pv3: iommu@fd970000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfd970000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 9>; @@ -1154,7 +1154,7 @@ #iommu-cells = <1>; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 10>; @@ -1162,7 +1162,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 12>; @@ -1170,7 +1170,7 @@ #iommu-cells = <1>; }; - ipmmu_vc1: mmu@fe6f0000 { + ipmmu_vc1: iommu@fe6f0000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfe6f0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 13>; @@ -1178,7 +1178,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 14>; @@ -1186,7 +1186,7 @@ #iommu-cells = <1>; }; - ipmmu_vi1: mmu@febe0000 { + ipmmu_vi1: iommu@febe0000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfebe0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 15>; @@ -1194,7 +1194,7 @@ #iommu-cells = <1>; }; - ipmmu_vp0: mmu@fe990000 { + ipmmu_vp0: iommu@fe990000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfe990000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 16>; @@ -1202,7 +1202,7 @@ #iommu-cells = <1>; }; - ipmmu_vp1: mmu@fe980000 { + ipmmu_vp1: iommu@fe980000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfe980000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 17>; @@ -3177,14 +3177,15 @@ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>; clock-names = "du.0", "du.1", "du.2", "du.3"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.2"; renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; - vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, + <&vspd0 1>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 60f156cfd2d6..33bf62acffbb 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -862,6 +862,15 @@ status = "disabled"; }; + arm_cc630p: crypto@e6601000 { + compatible = "arm,cryptocell-630p-ree"; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0xe6601000 0 0x1000>; + clocks = <&cpg CPG_MOD 229>; + resets = <&cpg 229>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7796", "renesas,rcar-dmac"; @@ -988,7 +997,7 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -996,7 +1005,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -1004,7 +1013,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -1012,7 +1021,7 @@ #iommu-cells = <1>; }; - ipmmu_ir: mmu@ff8b0000 { + ipmmu_ir: iommu@ff8b0000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xff8b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 3>; @@ -1020,7 +1029,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xe67b0000 0 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, @@ -1029,7 +1038,7 @@ #iommu-cells = <1>; }; - ipmmu_mp: mmu@ec670000 { + ipmmu_mp: iommu@ec670000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -1037,7 +1046,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 5>; @@ -1045,7 +1054,7 @@ #iommu-cells = <1>; }; - ipmmu_pv1: mmu@fd950000 { + ipmmu_pv1: iommu@fd950000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xfd950000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -1053,7 +1062,7 @@ #iommu-cells = <1>; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 7>; @@ -1061,7 +1070,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 8>; @@ -1069,7 +1078,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 9>; @@ -2818,13 +2827,14 @@ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>; clock-names = "du.0", "du.1", "du.2"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.2"; renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>; - vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts index 4abd78ac1cd5..2ffc7e31dd58 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts @@ -19,7 +19,7 @@ reg = <0x0 0x48000000 0x0 0x78000000>; }; - memory@400000000 { + memory@480000000 { device_type = "memory"; reg = <0x4 0x80000000 0x0 0x80000000>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts new file mode 100644 index 000000000000..7c6e60f6f32d --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board with R-Car + * M3-W+ + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a77961.dtsi" +#include "ulcb.dtsi" + +/ { + model = "Renesas M3ULCB board based on r8a77961"; + compatible = "renesas,m3ulcb", "renesas,r8a77961"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x1 0x00000000>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index be3824bda632..760e738b75b3 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -474,6 +474,20 @@ #power-domain-cells = <1>; }; + tsc: thermal@e6198000 { + compatible = "renesas,r8a77961-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + }; + intc_ex: interrupt-controller@e61c0000 { #interrupt-cells = <2>; interrupt-controller; @@ -612,21 +626,159 @@ status = "disabled"; }; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a77961", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a77961", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; reg = <0 0xe6550000 0 0x60>; - /* placeholder */ + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a77961", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a77961", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a77961", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 0x60>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; }; hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a77961", + "renesas,rcar-gen3-usbhs"; reg = <0 0xe6590000 0 0x200>; - /* placeholder */ + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 704>, <&cpg 703>; + status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a77961-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a77961-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; }; usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a77961-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 328>; #phy-cells = <0>; - /* placeholder */ + status = "disabled"; + }; + + arm_cc630p: crypto@e6601000 { + compatible = "arm,cryptocell-630p-ree"; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0xe6601000 0 0x1000>; + clocks = <&cpg CPG_MOD 229>; + resets = <&cpg 229>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; }; dmac0: dma-controller@e6700000 { @@ -776,15 +928,108 @@ status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + status = "disabled"; + }; + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; reg = <0 0xe6e31000 0 8>; #pwm-cells = <2>; - /* placeholder */ + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77961", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; }; scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a77961", + "renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6e68000 0 64>; - /* placeholder */ + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; }; scif2: serial@e6e88000 { @@ -796,11 +1041,63 @@ <&cpg CPG_CORE R8A77961_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 310>; status = "disabled"; }; + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a77961", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a77961", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a77961", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + vin0: video@e6ef0000 { reg = <0 0xe6ef0000 0 0x1000>; /* placeholder */ @@ -861,47 +1158,103 @@ rcar_sound,ssi { ssi0: ssi-0 { }; ssi1: ssi-1 { }; + ssi2: ssi-2 { }; }; }; xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a77961", + "renesas,rcar-gen3-xhci"; reg = <0 0xee000000 0 0xc00>; - /* placeholder */ + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; }; usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a77961-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; reg = <0 0xee020000 0 0x400>; - /* placeholder */ + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; }; ohci0: usb@ee080000 { + compatible = "generic-ohci"; reg = <0 0xee080000 0 0x100>; - /* placeholder */ + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + status = "disabled"; }; ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; reg = <0 0xee0a0000 0 0x100>; - /* placeholder */ + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; }; ehci0: usb@ee080100 { + compatible = "generic-ehci"; reg = <0 0xee080100 0 0x100>; - /* placeholder */ + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + status = "disabled"; }; ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; reg = <0 0xee0a0100 0 0x100>; - /* placeholder */ + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; }; usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a77961", + "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee080200 0 0x700>; - /* placeholder */ + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + #phy-cells = <1>; + status = "disabled"; }; usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a77961", + "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee0a0200 0 0x700>; - /* placeholder */ + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 702>; + #phy-cells = <1>; + status = "disabled"; }; sdhi0: sd@ee100000 { @@ -970,13 +1323,57 @@ }; pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a77961", + "renesas,pcie-rcar-gen3"; reg = <0 0xfe000000 0 0x80000>; - /* placeholder */ + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; }; pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a77961", + "renesas,pcie-rcar-gen3"; reg = <0 0xee800000 0 0x80000>; - /* placeholder */ + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, + <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, + <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, + <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; }; csi20: csi2@fea80000 { @@ -1064,6 +1461,71 @@ }; }; + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + sustainable-power = <3874>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + sustainable-power = <3874>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + sustainable-power = <3874>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&a57_0 2 4>; + contribution = <1024>; + }; + map1 { + trip = <&target>; + cooling-device = <&a53_0 0 2>; + contribution = <1024>; + }; + }; + trips { + target: trip-point1 { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index c17d90bd160e..6f7ab39fd282 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -111,6 +111,7 @@ power-domains = <&sysc R8A77965_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; #cooling-cells = <2>; dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A77965_CLK_Z>; @@ -124,6 +125,7 @@ power-domains = <&sysc R8A77965_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A77965_CLK_Z>; operating-points-v2 = <&cluster0_opp>; }; @@ -134,6 +136,19 @@ cache-unified; cache-level = <2>; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; + }; }; extal_clk: extal { @@ -717,6 +732,15 @@ status = "disabled"; }; + arm_cc630p: crypto@e6601000 { + compatible = "arm,cryptocell-630p-ree"; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0xe6601000 0 0x1000>; + clocks = <&cpg CPG_MOD 229>; + resets = <&cpg 229>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a77965", "renesas,rcar-dmac"; @@ -843,7 +867,7 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -851,7 +875,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -859,7 +883,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -867,7 +891,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xe67b0000 0 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, @@ -876,7 +900,7 @@ #iommu-cells = <1>; }; - ipmmu_mp: mmu@ec670000 { + ipmmu_mp: iommu@ec670000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -884,7 +908,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -892,7 +916,7 @@ #iommu-cells = <1>; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 10>; @@ -900,7 +924,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 12>; @@ -908,7 +932,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 14>; @@ -916,7 +940,7 @@ #iommu-cells = <1>; }; - ipmmu_vp0: mmu@fe990000 { + ipmmu_vp0: iommu@fe990000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xfe990000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 16>; @@ -2494,13 +2518,14 @@ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 721>; clock-names = "du.0", "du.1", "du.3"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.3"; renesas,cmms = <&cmm0>, <&cmm1>, <&cmm3>; - vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 664a73a2cc69..bd95ecb1b40d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -985,7 +985,7 @@ <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a77970"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -993,7 +993,7 @@ #iommu-cells = <1>; }; - ipmmu_ir: mmu@ff8b0000 { + ipmmu_ir: iommu@ff8b0000 { compatible = "renesas,ipmmu-r8a77970"; reg = <0 0xff8b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 3>; @@ -1001,7 +1001,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a77970"; reg = <0 0xe67b0000 0 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, @@ -1010,7 +1010,7 @@ #iommu-cells = <1>; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a77970"; reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 7>; @@ -1018,7 +1018,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a77970"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 9>; @@ -1121,7 +1121,9 @@ clock-names = "du.0"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 724>; - vsps = <&vspd0 0>; + reset-names = "du.0"; + renesas,vsps = <&vspd0 0>; + status = "disabled"; ports { diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index b340fb469999..224e57aea823 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -1266,7 +1266,7 @@ status = "disabled"; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a77980"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -1274,7 +1274,7 @@ #iommu-cells = <1>; }; - ipmmu_ir: mmu@ff8b0000 { + ipmmu_ir: iommu@ff8b0000 { compatible = "renesas,ipmmu-r8a77980"; reg = <0 0xff8b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 3>; @@ -1282,7 +1282,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a77980"; reg = <0 0xe67b0000 0 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, @@ -1291,7 +1291,7 @@ #iommu-cells = <1>; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a77980"; reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 10>; @@ -1299,7 +1299,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe990000 { + ipmmu_vc0: iommu@fe990000 { compatible = "renesas,ipmmu-r8a77980"; reg = <0 0xfe990000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 12>; @@ -1307,7 +1307,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a77980"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 14>; @@ -1315,14 +1315,14 @@ #iommu-cells = <1>; }; - ipmmu_vip0: mmu@e7b00000 { + ipmmu_vip0: iommu@e7b00000 { compatible = "renesas,ipmmu-r8a77980"; reg = <0 0xe7b00000 0 0x1000>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; #iommu-cells = <1>; }; - ipmmu_vip1: mmu@e7960000 { + ipmmu_vip1: iommu@e7960000 { compatible = "renesas,ipmmu-r8a77980"; reg = <0 0xe7960000 0 0x1000>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; @@ -1484,15 +1484,16 @@ }; du: display@feb00000 { - compatible = "renesas,du-r8a77980", - "renesas,du-r8a77970"; + compatible = "renesas,du-r8a77980"; reg = <0 0xfeb00000 0 0x80000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 724>; clock-names = "du.0"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 724>; - vsps = <&vspd0 0>; + reset-names = "du.0"; + renesas,vsps = <&vspd0 0>; + status = "disabled"; ports { diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 32d91f210246..cd11f24744d4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -88,6 +88,7 @@ power-domains = <&sysc R8A77990_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; dynamic-power-coefficient = <277>; clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; @@ -100,6 +101,7 @@ power-domains = <&sysc R8A77990_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; }; @@ -110,6 +112,19 @@ cache-unified; cache-level = <2>; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <700>; + exit-latency-us = <700>; + min-residency-us = <5000>; + }; + }; }; extal_clk: extal { @@ -667,6 +682,15 @@ dma-channels = <2>; }; + arm_cc630p: crypto@e6601000 { + compatible = "arm,cryptocell-630p-ree"; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0xe6601000 0 0x1000>; + clocks = <&cpg CPG_MOD 229>; + resets = <&cpg 229>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a77990", "renesas,rcar-dmac"; @@ -793,7 +817,7 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -801,7 +825,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -809,7 +833,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -817,7 +841,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xe67b0000 0 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, @@ -826,7 +850,7 @@ #iommu-cells = <1>; }; - ipmmu_mp: mmu@ec670000 { + ipmmu_mp: iommu@ec670000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -834,7 +858,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -842,7 +866,7 @@ #iommu-cells = <1>; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 10>; @@ -850,7 +874,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 12>; @@ -858,7 +882,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 14>; @@ -866,7 +890,7 @@ #iommu-cells = <1>; }; - ipmmu_vp0: mmu@fe990000 { + ipmmu_vp0: iommu@fe990000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xfe990000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 16>; @@ -1784,14 +1808,13 @@ reg = <0 0xfeb00000 0 0x40000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; resets = <&cpg 724>; reset-names = "du.0"; renesas,cmms = <&cmm0>, <&cmm1>; - vsps = <&vspd0 0>, <&vspd1 0>; + renesas,vsps = <&vspd0 0>, <&vspd1 0>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 9503007c34c0..e5617ec0f49c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -389,6 +389,15 @@ dma-channels = <2>; }; + arm_cc630p: crypto@e6601000 { + compatible = "arm,cryptocell-630p-ree"; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0xe6601000 0 0x1000>; + clocks = <&cpg CPG_MOD 229>; + resets = <&cpg 229>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + }; + canfd: can@e66c0000 { compatible = "renesas,r8a77995-canfd", "renesas,rcar-gen3-canfd"; @@ -498,7 +507,7 @@ <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -506,7 +515,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -514,7 +523,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -522,7 +531,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xe67b0000 0 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, @@ -531,7 +540,7 @@ #iommu-cells = <1>; }; - ipmmu_mp: mmu@ec670000 { + ipmmu_mp: iommu@ec670000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -539,7 +548,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -547,7 +556,7 @@ #iommu-cells = <1>; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 10>; @@ -555,7 +564,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 12>; @@ -563,7 +572,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 14>; @@ -571,7 +580,7 @@ #iommu-cells = <1>; }; - ipmmu_vp0: mmu@fe990000 { + ipmmu_vp0: iommu@fe990000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xfe990000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 16>; @@ -1017,14 +1026,13 @@ reg = <0 0xfeb00000 0 0x40000>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; resets = <&cpg 724>; reset-names = "du.0"; renesas,cmms = <&cmm0>, <&cmm1>; - vsps = <&vspd0 0>, <&vspd1 0>; + renesas,vsps = <&vspd0 0>, <&vspd1 0>; status = "disabled"; |