diff options
Diffstat (limited to 'arch/arm')
187 files changed, 5396 insertions, 737 deletions
diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40-feta40i.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40-feta40i.dtsi index 9f39b5a2bb35..c12361d0317f 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-r40-feta40i.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-r40-feta40i.dtsi @@ -42,6 +42,13 @@ vcc-pg-supply = <®_dldo1>; }; +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3-tv-usb"; +}; + ®_aldo2 { regulator-always-on; regulator-min-microvolt = <1800000>; diff --git a/arch/arm/boot/dts/amazon/alpine.dtsi b/arch/arm/boot/dts/amazon/alpine.dtsi index ff68dfb4eb78..90bd12feac01 100644 --- a/arch/arm/boot/dts/amazon/alpine.dtsi +++ b/arch/arm/boot/dts/amazon/alpine.dtsi @@ -167,7 +167,6 @@ msix: msix@fbe00000 { compatible = "al,alpine-msix"; reg = <0x0 0xfbe00000 0x0 0x100000>; - interrupt-controller; msi-controller; al,msi-base-spi = <96>; al,msi-num-spis = <64>; diff --git a/arch/arm/boot/dts/amlogic/meson.dtsi b/arch/arm/boot/dts/amlogic/meson.dtsi index 8e3860d5d916..8cb0fc78b2af 100644 --- a/arch/arm/boot/dts/amlogic/meson.dtsi +++ b/arch/arm/boot/dts/amlogic/meson.dtsi @@ -23,7 +23,7 @@ #size-cells = <1>; ranges; - cbus: cbus@c1100000 { + cbus: bus@c1100000 { compatible = "simple-bus"; reg = <0xc1100000 0x200000>; #address-cells = <1>; @@ -206,7 +206,7 @@ }; }; - aobus: aobus@c8100000 { + aobus: bus@c8100000 { compatible = "simple-bus"; reg = <0xc8100000 0x100000>; #address-cells = <1>; @@ -302,7 +302,7 @@ reg = <0xd9040000 0x10000>; }; - secbus: secbus@da000000 { + secbus: bus@da000000 { compatible = "simple-bus"; reg = <0xda000000 0x6000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi index 59932fbfd5d5..f57be9ae150f 100644 --- a/arch/arm/boot/dts/amlogic/meson8.dtsi +++ b/arch/arm/boot/dts/amlogic/meson8.dtsi @@ -645,7 +645,6 @@ }; &hwrng { - compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; clock-names = "core"; }; diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi index 5198f5177c2c..2d9d24d3a95d 100644 --- a/arch/arm/boot/dts/amlogic/meson8b.dtsi +++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi @@ -620,7 +620,6 @@ }; &hwrng { - compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; clock-names = "core"; }; diff --git a/arch/arm/boot/dts/arm/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts index efed325af88d..d99bac02232b 100644 --- a/arch/arm/boot/dts/arm/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts @@ -451,7 +451,7 @@ /* Direct-mapped development chip ROM */ pb1176_rom@10200000 { - compatible = "direct-mapped"; + compatible = "mtd-rom"; reg = <0x10200000 0x4000>; bank-width = <1>; }; diff --git a/arch/arm/boot/dts/arm/integratorap-im-pd1.dts b/arch/arm/boot/dts/arm/integratorap-im-pd1.dts index 7072a70da00d..367850ea0912 100644 --- a/arch/arm/boot/dts/arm/integratorap-im-pd1.dts +++ b/arch/arm/boot/dts/arm/integratorap-im-pd1.dts @@ -129,8 +129,6 @@ bridge { compatible = "ti,ths8134b", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; ports { #address-cells = <1>; @@ -154,6 +152,7 @@ vga { compatible = "vga-connector"; + label = "J30"; port { vga_con_in: endpoint { diff --git a/arch/arm/boot/dts/arm/versatile-ab.dts b/arch/arm/boot/dts/arm/versatile-ab.dts index f31dcf7e5862..de45aa99e260 100644 --- a/arch/arm/boot/dts/arm/versatile-ab.dts +++ b/arch/arm/boot/dts/arm/versatile-ab.dts @@ -32,8 +32,6 @@ bridge { compatible = "ti,ths8134b", "ti,ths8134"; - #address-cells = <1>; - #size-cells = <0>; ports { #address-cells = <1>; @@ -59,6 +57,7 @@ vga { compatible = "vga-connector"; + label = "J1"; port { vga_con_in: endpoint { diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts index e899de681f47..5be0e8fd2633 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts @@ -45,8 +45,8 @@ num-chipselects = <1>; cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; - tpmdev@0 { - compatible = "tcg,tpm_tis-spi"; + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; spi-max-frequency = <33000000>; reg = <0>; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts index a677c827e758..5a8169bbda87 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts @@ -80,8 +80,8 @@ gpio-miso = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>; num-chipselects = <1>; - tpmdev@0 { - compatible = "tcg,tpm_tis-spi"; + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; spi-max-frequency = <33000000>; reg = <0>; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts index 3f6010ef2b86..213023bc5aec 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts @@ -456,7 +456,7 @@ status = "okay"; tpm: tpm@2e { - compatible = "tcg,tpm-tis-i2c"; + compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c"; reg = <0x2e>; }; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi index 530491ae5eb2..857cb26ed6d7 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi @@ -466,7 +466,6 @@ i2c0: i2c-bus@40 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x40 0x40>; compatible = "aspeed,ast2400-i2c-bus"; @@ -482,7 +481,6 @@ i2c1: i2c-bus@80 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x80 0x40>; compatible = "aspeed,ast2400-i2c-bus"; @@ -498,7 +496,6 @@ i2c2: i2c-bus@c0 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0xc0 0x40>; compatible = "aspeed,ast2400-i2c-bus"; @@ -515,7 +512,6 @@ i2c3: i2c-bus@100 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x100 0x40>; compatible = "aspeed,ast2400-i2c-bus"; @@ -532,7 +528,6 @@ i2c4: i2c-bus@140 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x140 0x40>; compatible = "aspeed,ast2400-i2c-bus"; @@ -549,7 +544,6 @@ i2c5: i2c-bus@180 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x180 0x40>; compatible = "aspeed,ast2400-i2c-bus"; @@ -566,7 +560,6 @@ i2c6: i2c-bus@1c0 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x1c0 0x40>; compatible = "aspeed,ast2400-i2c-bus"; @@ -583,7 +576,6 @@ i2c7: i2c-bus@300 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x300 0x40>; compatible = "aspeed,ast2400-i2c-bus"; @@ -600,7 +592,6 @@ i2c8: i2c-bus@340 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x340 0x40>; compatible = "aspeed,ast2400-i2c-bus"; @@ -617,7 +608,6 @@ i2c9: i2c-bus@380 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x380 0x40>; compatible = "aspeed,ast2400-i2c-bus"; @@ -634,7 +624,6 @@ i2c10: i2c-bus@3c0 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x3c0 0x40>; compatible = "aspeed,ast2400-i2c-bus"; @@ -651,7 +640,6 @@ i2c11: i2c-bus@400 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x400 0x40>; compatible = "aspeed,ast2400-i2c-bus"; @@ -668,7 +656,6 @@ i2c12: i2c-bus@440 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x440 0x40>; compatible = "aspeed,ast2400-i2c-bus"; @@ -685,7 +672,6 @@ i2c13: i2c-bus@480 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x480 0x40>; compatible = "aspeed,ast2400-i2c-bus"; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi index 04f98d1dbb97..e6f3cf3c721e 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi @@ -363,6 +363,7 @@ interrupts = <40>; reg = <0x1e780200 0x0100>; clocks = <&syscon ASPEED_CLK_APB>; + #interrupt-cells = <2>; interrupt-controller; bus-frequency = <12000000>; pinctrl-names = "default"; @@ -594,7 +595,6 @@ i2c0: i2c-bus@40 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x40 0x40>; compatible = "aspeed,ast2500-i2c-bus"; @@ -610,7 +610,6 @@ i2c1: i2c-bus@80 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x80 0x40>; compatible = "aspeed,ast2500-i2c-bus"; @@ -626,7 +625,6 @@ i2c2: i2c-bus@c0 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0xc0 0x40>; compatible = "aspeed,ast2500-i2c-bus"; @@ -643,7 +641,6 @@ i2c3: i2c-bus@100 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x100 0x40>; compatible = "aspeed,ast2500-i2c-bus"; @@ -660,7 +657,6 @@ i2c4: i2c-bus@140 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x140 0x40>; compatible = "aspeed,ast2500-i2c-bus"; @@ -677,7 +673,6 @@ i2c5: i2c-bus@180 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x180 0x40>; compatible = "aspeed,ast2500-i2c-bus"; @@ -694,7 +689,6 @@ i2c6: i2c-bus@1c0 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x1c0 0x40>; compatible = "aspeed,ast2500-i2c-bus"; @@ -711,7 +705,6 @@ i2c7: i2c-bus@300 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x300 0x40>; compatible = "aspeed,ast2500-i2c-bus"; @@ -728,7 +721,6 @@ i2c8: i2c-bus@340 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x340 0x40>; compatible = "aspeed,ast2500-i2c-bus"; @@ -745,7 +737,6 @@ i2c9: i2c-bus@380 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x380 0x40>; compatible = "aspeed,ast2500-i2c-bus"; @@ -762,7 +753,6 @@ i2c10: i2c-bus@3c0 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x3c0 0x40>; compatible = "aspeed,ast2500-i2c-bus"; @@ -779,7 +769,6 @@ i2c11: i2c-bus@400 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x400 0x40>; compatible = "aspeed,ast2500-i2c-bus"; @@ -796,7 +785,6 @@ i2c12: i2c-bus@440 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x440 0x40>; compatible = "aspeed,ast2500-i2c-bus"; @@ -813,7 +801,6 @@ i2c13: i2c-bus@480 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x480 0x40>; compatible = "aspeed,ast2500-i2c-bus"; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index c4d1faade8be..29f94696d8b1 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -474,6 +474,7 @@ reg = <0x1e780500 0x100>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; clocks = <&syscon ASPEED_CLK_APB2>; + #interrupt-cells = <2>; interrupt-controller; bus-frequency = <12000000>; pinctrl-names = "default"; @@ -488,6 +489,7 @@ reg = <0x1e780600 0x100>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&syscon ASPEED_CLK_APB2>; + #interrupt-cells = <2>; interrupt-controller; bus-frequency = <12000000>; pinctrl-names = "default"; @@ -902,7 +904,6 @@ i2c0: i2c-bus@80 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x80 0x80>; compatible = "aspeed,ast2600-i2c-bus"; clocks = <&syscon ASPEED_CLK_APB2>; @@ -917,7 +918,6 @@ i2c1: i2c-bus@100 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x100 0x80>; compatible = "aspeed,ast2600-i2c-bus"; clocks = <&syscon ASPEED_CLK_APB2>; @@ -932,7 +932,6 @@ i2c2: i2c-bus@180 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x180 0x80>; compatible = "aspeed,ast2600-i2c-bus"; clocks = <&syscon ASPEED_CLK_APB2>; @@ -947,7 +946,6 @@ i2c3: i2c-bus@200 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x200 0x80>; compatible = "aspeed,ast2600-i2c-bus"; clocks = <&syscon ASPEED_CLK_APB2>; @@ -962,7 +960,6 @@ i2c4: i2c-bus@280 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x280 0x80>; compatible = "aspeed,ast2600-i2c-bus"; clocks = <&syscon ASPEED_CLK_APB2>; @@ -977,7 +974,6 @@ i2c5: i2c-bus@300 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x300 0x80>; compatible = "aspeed,ast2600-i2c-bus"; clocks = <&syscon ASPEED_CLK_APB2>; @@ -992,7 +988,6 @@ i2c6: i2c-bus@380 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x380 0x80>; compatible = "aspeed,ast2600-i2c-bus"; clocks = <&syscon ASPEED_CLK_APB2>; @@ -1007,7 +1002,6 @@ i2c7: i2c-bus@400 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x400 0x80>; compatible = "aspeed,ast2600-i2c-bus"; clocks = <&syscon ASPEED_CLK_APB2>; @@ -1022,7 +1016,6 @@ i2c8: i2c-bus@480 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x480 0x80>; compatible = "aspeed,ast2600-i2c-bus"; clocks = <&syscon ASPEED_CLK_APB2>; @@ -1037,7 +1030,6 @@ i2c9: i2c-bus@500 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x500 0x80>; compatible = "aspeed,ast2600-i2c-bus"; clocks = <&syscon ASPEED_CLK_APB2>; @@ -1052,7 +1044,6 @@ i2c10: i2c-bus@580 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x580 0x80>; compatible = "aspeed,ast2600-i2c-bus"; clocks = <&syscon ASPEED_CLK_APB2>; @@ -1067,7 +1058,6 @@ i2c11: i2c-bus@600 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x600 0x80>; compatible = "aspeed,ast2600-i2c-bus"; clocks = <&syscon ASPEED_CLK_APB2>; @@ -1082,7 +1072,6 @@ i2c12: i2c-bus@680 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x680 0x80>; compatible = "aspeed,ast2600-i2c-bus"; clocks = <&syscon ASPEED_CLK_APB2>; @@ -1097,7 +1086,6 @@ i2c13: i2c-bus@700 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x700 0x80>; compatible = "aspeed,ast2600-i2c-bus"; clocks = <&syscon ASPEED_CLK_APB2>; @@ -1112,7 +1100,6 @@ i2c14: i2c-bus@780 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x780 0x80>; compatible = "aspeed,ast2600-i2c-bus"; clocks = <&syscon ASPEED_CLK_APB2>; @@ -1127,7 +1114,6 @@ i2c15: i2c-bus@800 { #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; reg = <0x800 0x80>; compatible = "aspeed,ast2600-i2c-bus"; clocks = <&syscon ASPEED_CLK_APB2>; diff --git a/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi index 31590d3186a2..00e5887c926f 100644 --- a/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi +++ b/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi @@ -35,8 +35,8 @@ gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>; gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>; - tpmdev@0 { - compatible = "tcg,tpm_tis-spi"; + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; spi-max-frequency = <33000000>; reg = <0>; }; diff --git a/arch/arm/boot/dts/broadcom/bcm-cygnus.dtsi b/arch/arm/boot/dts/broadcom/bcm-cygnus.dtsi index f9f79ed82518..07ca0d993c9f 100644 --- a/arch/arm/boot/dts/broadcom/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm-cygnus.dtsi @@ -167,6 +167,7 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; + #interrupt-cells = <2>; interrupt-parent = <&mailbox>; interrupts = <0>; }; @@ -247,6 +248,7 @@ gpio-controller; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; + #interrupt-cells = <2>; }; i2c1: i2c@1800b000 { @@ -518,6 +520,7 @@ gpio-controller; interrupt-controller; + #interrupt-cells = <2>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; gpio-ranges = <&pinctrl 0 42 1>, <&pinctrl 1 44 3>, diff --git a/arch/arm/boot/dts/broadcom/bcm-hr2.dtsi b/arch/arm/boot/dts/broadcom/bcm-hr2.dtsi index 788a6806191a..75545b10ef2f 100644 --- a/arch/arm/boot/dts/broadcom/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm-hr2.dtsi @@ -200,6 +200,7 @@ gpio-controller; ngpios = <4>; interrupt-controller; + #interrupt-cells = <2>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi b/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi index 9d20ba3b1ffb..6a4482c93167 100644 --- a/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi @@ -180,6 +180,7 @@ gpio-controller; ngpios = <32>; interrupt-controller; + #interrupt-cells = <2>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; gpio-ranges = <&pinctrl 0 0 32>; }; @@ -352,6 +353,7 @@ gpio-controller; ngpios = <4>; interrupt-controller; + #interrupt-cells = <2>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts index 396149664297..b4dbcf8f168e 100644 --- a/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts @@ -27,10 +27,10 @@ gpio_keys { compatible = "gpio-keys"; - button-esc { + button-reset { debounce-interval = <100>; wakeup-source; - linux,code = <KEY_ESC>; + linux,code = <KEY_RESTART>; label = "reset"; /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */ gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; @@ -187,7 +187,7 @@ }; /* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */ - switch { + ethernet-switch { compatible = "realtek,rtl8366rb"; /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; @@ -204,36 +204,36 @@ #interrupt-cells = <1>; }; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + ethernet-port@0 { reg = <0>; label = "lan0"; phy-handle = <&phy0>; }; - port@1 { + ethernet-port@1 { reg = <1>; label = "lan1"; phy-handle = <&phy1>; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "lan2"; phy-handle = <&phy2>; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "lan3"; phy-handle = <&phy3>; }; - port@4 { + ethernet-port@4 { reg = <4>; label = "wan"; phy-handle = <&phy4>; }; - rtl8366rb_cpu_port: port@5 { + rtl8366rb_cpu_port: ethernet-port@5 { reg = <5>; label = "cpu"; ethernet = <&gmac0>; @@ -252,27 +252,27 @@ #address-cells = <1>; #size-cells = <0>; - phy0: phy@0 { + phy0: ethernet-phy@0 { reg = <0>; interrupt-parent = <&switch_intc>; interrupts = <0>; }; - phy1: phy@1 { + phy1: ethernet-phy@1 { reg = <1>; interrupt-parent = <&switch_intc>; interrupts = <1>; }; - phy2: phy@2 { + phy2: ethernet-phy@2 { reg = <2>; interrupt-parent = <&switch_intc>; interrupts = <2>; }; - phy3: phy@3 { + phy3: ethernet-phy@3 { reg = <3>; interrupt-parent = <&switch_intc>; interrupts = <3>; }; - phy4: phy@4 { + phy4: ethernet-phy@4 { reg = <4>; interrupt-parent = <&switch_intc>; interrupts = <12>; diff --git a/arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts index 138c47e1ac1b..8c54d3a5a721 100644 --- a/arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts +++ b/arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts @@ -33,10 +33,10 @@ gpio_keys { compatible = "gpio-keys"; - button-esc { + button-reset { debounce-interval = <100>; wakeup-source; - linux,code = <KEY_ESC>; + linux,code = <KEY_RESTART>; label = "reset"; gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/gemini/gemini-sl93512r.dts b/arch/arm/boot/dts/gemini/gemini-sl93512r.dts index 91c19e8ebfe8..4992ec276de9 100644 --- a/arch/arm/boot/dts/gemini/gemini-sl93512r.dts +++ b/arch/arm/boot/dts/gemini/gemini-sl93512r.dts @@ -43,7 +43,7 @@ button-setup { debounce-interval = <50>; wakeup-source; - linux,code = <KEY_SETUP>; + linux,code = <KEY_RESTART>; label = "factory reset"; /* Conflict with NAND flash */ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; @@ -93,7 +93,7 @@ cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; - switch@0 { + ethernet-switch@0 { compatible = "vitesse,vsc7385"; reg = <0>; /* Specified for 2.5 MHz or below */ @@ -101,27 +101,27 @@ gpio-controller; #gpio-cells = <2>; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + ethernet-port@0 { reg = <0>; label = "lan1"; }; - port@1 { + ethernet-port@1 { reg = <1>; label = "lan2"; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "lan3"; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "lan4"; }; - vsc: port@6 { + vsc: ethernet-port@6 { reg = <6>; label = "cpu"; ethernet = <&gmac1>; diff --git a/arch/arm/boot/dts/gemini/gemini-sq201.dts b/arch/arm/boot/dts/gemini/gemini-sq201.dts index d0efd76695da..f8c6f6e5cdea 100644 --- a/arch/arm/boot/dts/gemini/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini/gemini-sq201.dts @@ -30,7 +30,7 @@ button-setup { debounce-interval = <100>; wakeup-source; - linux,code = <KEY_SETUP>; + linux,code = <KEY_RESTART>; label = "factory reset"; /* Conflict with NAND flash */ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; @@ -78,7 +78,7 @@ cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; - switch@0 { + ethernet-switch@0 { compatible = "vitesse,vsc7395"; reg = <0>; /* Specified for 2.5 MHz or below */ @@ -86,27 +86,27 @@ gpio-controller; #gpio-cells = <2>; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + ethernet-port@0 { reg = <0>; label = "lan1"; }; - port@1 { + ethernet-port@1 { reg = <1>; label = "lan2"; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "lan3"; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "lan4"; }; - vsc: port@6 { + vsc: ethernet-port@6 { reg = <6>; label = "cpu"; ethernet = <&gmac1>; diff --git a/arch/arm/boot/dts/gemini/gemini-wbd111.dts b/arch/arm/boot/dts/gemini/gemini-wbd111.dts index 3c88c59ab481..6a0c89e0c918 100644 --- a/arch/arm/boot/dts/gemini/gemini-wbd111.dts +++ b/arch/arm/boot/dts/gemini/gemini-wbd111.dts @@ -10,7 +10,7 @@ / { model = "Wiliboard WBD-111"; - compatible = "wiliboard,wbd111", "cortina,gemini"; + compatible = "wiligear,wiliboard-wbd111", "cortina,gemini"; #address-cells = <1>; #size-cells = <1>; @@ -28,10 +28,10 @@ gpio_keys { compatible = "gpio-keys"; - button-setup { + button-reset { debounce-interval = <100>; wakeup-source; - linux,code = <KEY_SETUP>; + linux,code = <KEY_RESTART>; label = "reset"; /* Conflict with ICE */ gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/gemini/gemini-wbd222.dts b/arch/arm/boot/dts/gemini/gemini-wbd222.dts index ff72bbc4db3e..d8b34ebad4b0 100644 --- a/arch/arm/boot/dts/gemini/gemini-wbd222.dts +++ b/arch/arm/boot/dts/gemini/gemini-wbd222.dts @@ -10,7 +10,7 @@ / { model = "Wiliboard WBD-222"; - compatible = "wiliboard,wbd222", "cortina,gemini"; + compatible = "wiligear,wiliboard-wbd222", "cortina,gemini"; #address-cells = <1>; #size-cells = <1>; @@ -27,10 +27,10 @@ gpio_keys { compatible = "gpio-keys"; - button-setup { + button-reset { debounce-interval = <100>; wakeup-source; - linux,code = <KEY_SETUP>; + linux,code = <KEY_RESTART>; label = "reset"; /* Conflict with ICE */ gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateway-7001.dts index 4d70f6afd13a..6d5e69035f94 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateway-7001.dts +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-gateway-7001.dts @@ -60,6 +60,8 @@ * We have slots (IDSEL) 1 and 2 with one assigned IRQ * each handling all IRQs. */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = /* IDSEL 1 */ <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-goramo-multilink.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-goramo-multilink.dts index 9ec0169bacf8..5f4c849915db 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-goramo-multilink.dts +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-goramo-multilink.dts @@ -89,6 +89,8 @@ * The slots have Ethernet, Ethernet, NEC and MPCI. * The IDSELs are 11, 12, 13, 14. */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = /* IDSEL 11 - Ethernet A */ <0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */ diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts index 1707d1b01545..cb85f8e31dfc 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts @@ -4,6 +4,18 @@ / { model = "SolidRun Clearfog GTR L8"; + compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385", + "marvell,armada380"; + + /* CON25 */ + sfp1: sfp-1 { + compatible = "sff,sfp"; + pinctrl-0 = <&cf_gtr_sfp1_pins>; + pinctrl-names = "default"; + i2c-bus = <&i2c0>; + mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; + }; }; &mdio { @@ -20,57 +32,65 @@ ethernet-port@1 { reg = <1>; - label = "lan8"; + label = "lan1"; phy-handle = <&switch0phy0>; }; ethernet-port@2 { reg = <2>; - label = "lan7"; + label = "lan2"; phy-handle = <&switch0phy1>; }; ethernet-port@3 { reg = <3>; - label = "lan6"; + label = "lan3"; phy-handle = <&switch0phy2>; }; ethernet-port@4 { reg = <4>; - label = "lan5"; + label = "lan4"; phy-handle = <&switch0phy3>; }; ethernet-port@5 { reg = <5>; - label = "lan4"; + label = "lan5"; phy-handle = <&switch0phy4>; }; ethernet-port@6 { reg = <6>; - label = "lan3"; + label = "lan6"; phy-handle = <&switch0phy5>; }; ethernet-port@7 { reg = <7>; - label = "lan2"; + label = "lan7"; phy-handle = <&switch0phy6>; }; ethernet-port@8 { reg = <8>; - label = "lan1"; + label = "lan8"; phy-handle = <&switch0phy7>; }; + ethernet-port@9 { + reg = <9>; + label = "lan-sfp"; + phy-mode = "sgmii"; + sfp = <&sfp1>; + managed = "in-band-status"; + }; + ethernet-port@10 { reg = <10>; phy-mode = "2500base-x"; - ethernet = <ð1>; + fixed-link { speed = <2500>; full-duplex; diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts index a7678a784c18..5f83d981449a 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts @@ -4,6 +4,8 @@ / { model = "SolidRun Clearfog GTR S4"; + compatible = "solidrun,clearfog-gtr-s4", "marvell,armada385", + "marvell,armada380"; }; &sfp0 { diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi index d1452a04e904..f3a3cb6ac311 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi @@ -141,18 +141,13 @@ }; pinctrl@18000 { - cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus { - marvell,pins = "mpp22"; + cf_gtr_fan_pwm: cf-gtr-fan-pwm { + marvell,pins = "mpp23"; marvell,function = "gpio"; }; - cf_gtr_fan_pwm: cf-gtr-fan-pwm { - marvell,pins = "mpp23"; + cf_gtr_front_button_pins: cf-gtr-front-button-pins { + marvell,pins = "mpp53"; marvell,function = "gpio"; }; @@ -162,6 +157,37 @@ marvell,function = "i2c1"; }; + cf_gtr_isolation_pins: cf-gtr-isolation-pins { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + cf_gtr_led_pins: led-pins { + marvell,pins = "mpp42", "mpp52"; + marvell,function = "gpio"; + }; + + cf_gtr_lte_disable_pins: lte-disable-pins { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + cf_gtr_pci_pins: pci-pins { + // pci reset + marvell,pins = "mpp33", "mpp35", "mpp44"; + marvell,function = "gpio"; + }; + + cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + cf_gtr_rear_button_pins: cf-gtr-rear-button-pins { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + cf_gtr_sdhci_pins: cf-gtr-sdhci-pins { marvell,pins = "mpp21", "mpp28", "mpp37", "mpp38", @@ -169,13 +195,15 @@ marvell,function = "sd0"; }; - cf_gtr_isolation_pins: cf-gtr-isolation-pins { - marvell,pins = "mpp47"; + cf_gtr_sfp0_pins: sfp0-pins { + /* sfp modabs, txdisable */ + marvell,pins = "mpp25", "mpp46"; marvell,function = "gpio"; }; - cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins { - marvell,pins = "mpp48"; + cf_gtr_sfp1_pins: sfp1-pins { + /* sfp modabs, txdisable */ + marvell,pins = "mpp24", "mpp54"; marvell,function = "gpio"; }; @@ -184,13 +212,18 @@ marvell,function = "spi1"; }; - cf_gtr_front_button_pins: cf-gtr-front-button-pins { - marvell,pins = "mpp53"; + cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins { + marvell,pins = "mpp18"; marvell,function = "gpio"; }; - cf_gtr_rear_button_pins: cf-gtr-rear-button-pins { - marvell,pins = "mpp36"; + cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus { + marvell,pins = "mpp22"; + marvell,function = "gpio"; + }; + + cf_gtr_wifi_disable_pins: wifi-disable-pins { + marvell,pins = "mpp30", "mpp31"; marvell,function = "gpio"; }; }; @@ -221,21 +254,26 @@ }; pcie { + pinctrl-0 = <&cf_gtr_pci_pins>; + pinctrl-names = "default"; status = "okay"; /* * The PCIe units are accessible through * the mini-PCIe connectors on the board. */ + /* CON3 - serdes 0 */ pcie@1,0 { reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; status = "okay"; }; + /* CON4 - serdes 2 */ pcie@2,0 { reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; status = "okay"; }; + /* CON2 - serdes 4 */ pcie@3,0 { reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; status = "okay"; @@ -243,10 +281,12 @@ }; }; - sfp0: sfp { + /* CON5 */ + sfp0: sfp-0 { compatible = "sff,sfp"; + pinctrl-0 = <&cf_gtr_sfp0_pins>; + pinctrl-names = "default"; i2c-bus = <&i2c1>; - los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>; tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; @@ -273,6 +313,8 @@ gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&cf_gtr_led_pins>; + pinctrl-names = "default"; led1 { function = LED_FUNCTION_CPU; @@ -408,7 +450,7 @@ }; &gpio0 { - pinctrl-0 = <&cf_gtr_fan_pwm>; + pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>; pinctrl-names = "default"; wifi-disable { @@ -420,7 +462,7 @@ }; &gpio1 { - pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>; + pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>; pinctrl-names = "default"; lte-disable { diff --git a/arch/arm/boot/dts/marvell/armada-388-clearfog.dts b/arch/arm/boot/dts/marvell/armada-388-clearfog.dts index 3290ccad2374..09bf2e6d4ed0 100644 --- a/arch/arm/boot/dts/marvell/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/marvell/armada-388-clearfog.dts @@ -10,8 +10,9 @@ / { model = "SolidRun Clearfog A1"; - compatible = "solidrun,clearfog-a1", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; + compatible = "solidrun,clearfog-pro-a1", "solidrun,clearfog-a1", + "marvell,armada388", "marvell,armada385", + "marvell,armada380"; soc { internal-regs { diff --git a/arch/arm/boot/dts/marvell/dove-cubox.dts b/arch/arm/boot/dts/marvell/dove-cubox.dts index bfde99486a87..bcaaf8320c45 100644 --- a/arch/arm/boot/dts/marvell/dove-cubox.dts +++ b/arch/arm/boot/dts/marvell/dove-cubox.dts @@ -101,7 +101,7 @@ /* connect xtal input as source of pll0 and pll1 */ silabs,pll-source = <0 0>, <1 0>; - clkout0 { + clkout@0 { reg = <0>; silabs,drive-strength = <8>; silabs,multisynth-source = <0>; @@ -109,7 +109,7 @@ silabs,pll-master; }; - clkout2 { + clkout@2 { reg = <2>; silabs,drive-strength = <8>; silabs,multisynth-source = <1>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-l-50.dts b/arch/arm/boot/dts/marvell/kirkwood-l-50.dts index dffb9f84e67c..c841eb8e7fb1 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-l-50.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-l-50.dts @@ -65,6 +65,7 @@ gpio2: gpio-expander@20 { #gpio-cells = <2>; #interrupt-cells = <2>; + interrupt-controller; compatible = "semtech,sx1505q"; reg = <0x20>; @@ -79,6 +80,7 @@ gpio3: gpio-expander@21 { #gpio-cells = <2>; #interrupt-cells = <2>; + interrupt-controller; compatible = "semtech,sx1505q"; reg = <0x21>; diff --git a/arch/arm/boot/dts/marvell/mmp2-brownstone.dts b/arch/arm/boot/dts/marvell/mmp2-brownstone.dts index 04f1ae1382e7..bc64348b8218 100644 --- a/arch/arm/boot/dts/marvell/mmp2-brownstone.dts +++ b/arch/arm/boot/dts/marvell/mmp2-brownstone.dts @@ -28,7 +28,7 @@ &twsi1 { status = "okay"; pmic: max8925@3c { - compatible = "maxium,max8925"; + compatible = "maxim,max8925"; reg = <0x3c>; interrupts = <1>; interrupt-parent = <&intcmux4>; diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile index efde9546c8f4..0c45c8d17468 100644 --- a/arch/arm/boot/dts/microchip/Makefile +++ b/arch/arm/boot/dts/microchip/Makefile @@ -11,6 +11,7 @@ DTC_FLAGS_at91-sama5d2_xplained := -@ DTC_FLAGS_at91-sama5d3_eds := -@ DTC_FLAGS_at91-sama5d3_xplained := -@ DTC_FLAGS_at91-sama5d4_xplained := -@ +DTC_FLAGS_at91-sama7g54_curiosity := -@ DTC_FLAGS_at91-sama7g5ek := -@ dtb-$(CONFIG_SOC_AT91RM9200) += \ at91rm9200ek.dtb \ @@ -87,6 +88,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d4ek.dtb \ at91-vinco.dtb dtb-$(CONFIG_SOC_SAMA7G5) += \ + at91-sama7g54_curiosity.dtb \ at91-sama7g5ek.dtb dtb-$(CONFIG_SOC_LAN966) += \ diff --git a/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts new file mode 100644 index 000000000000..4f609e9e510e --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts @@ -0,0 +1,482 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama7g54_curiosity.dts - Device Tree file for SAMA7G54 Curiosity Board + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Mihai Sain <mihai.sain@microchip.com> + * + */ +/dts-v1/; +#include "sama7g5-pinfunc.h" +#include "sama7g5.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/mfd/atmel-flexcom.h> +#include <dt-bindings/pinctrl/at91.h> + +/ { + model = "Microchip SAMA7G54 Curiosity"; + compatible = "microchip,sama7g54-curiosity", "microchip,sama7g5", "microchip,sama7"; + + aliases { + serial0 = &uart3; + i2c0 = &i2c10; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + button-user { + label = "user-button"; + gpios = <&pioA PIN_PD19 GPIO_ACTIVE_LOW>; + linux,code = <KEY_PROG1>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + + led-red { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_POWER; + gpios = <&pioA PIN_PD13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-green { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_BOOT; + gpios = <&pioA PIN_PD14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-blue { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_CPU; + gpios = <&pioA PIN_PB15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x10000000>; /* 256 MiB DDR3L-1066 16-bit */ + }; +}; + +&adc { + vddana-supply = <&vddout25>; + vref-supply = <&vddout25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; +}; + +&dma0 { + status = "okay"; +}; + +&dma1 { + status = "okay"; +}; + +&dma2 { + status = "okay"; +}; + +&ebi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand_default>; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "nand: at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "nand: u-boot"; + reg = <0x40000 0x100000>; + }; + + bootloaderenv@140000 { + label = "nand: u-boot env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "nand: device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "nand: kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "nand: rootfs"; + reg = <0x800000 0x1f800000>; + }; + }; + }; + }; +}; + +&flx3 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; + status = "okay"; + + uart3: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx3_default>; + status = "okay"; + }; +}; + +&flx10 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; + status = "okay"; + + i2c10: i2c@600 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx10_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + size = <256>; + vcc-supply = <&vdd_3v3>; + }; + + pmic@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + + regulators { + vdd_3v3: VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vddioddr: VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1350000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1350000>; + regulator-mode = <4>; + }; + }; + + vddcore: VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-voltage = <1150000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vddcpu: VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1250000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-ramp-delay = <3125>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-voltage = <1050000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-standby { + regulator-suspend-voltage = <1800000>; + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-standby { + regulator-suspend-voltage = <3300000>; + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + }; +}; + +&main_xtal { + clock-frequency = <24000000>; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_default>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + }; +}; + +&pioA { + pinctrl_flx3_default: flx3-default { + pinmux = <PIN_PD16__FLEXCOM3_IO0>, + <PIN_PD17__FLEXCOM3_IO1>; + bias-pull-up; + }; + + pinctrl_flx10_default: flx10-default { + pinmux = <PIN_PC30__FLEXCOM10_IO0>, + <PIN_PC31__FLEXCOM10_IO1>; + bias-pull-up; + }; + + pinctrl_key_gpio_default: key-gpio-default { + pinmux = <PIN_PD19__GPIO>; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led-gpio-default { + pinmux = <PIN_PD13__GPIO>, + <PIN_PD14__GPIO>, + <PIN_PB15__GPIO>; + bias-pull-up; + }; + + pinctrl_mikrobus1_an_default: mikrobus1-an-default { + pinmux = <PIN_PC15__GPIO>; + bias-disable; + }; + + pinctrl_mikrobus2_an_default: mikrobus2-an-default { + pinmux = <PIN_PC13__GPIO>; + bias-disable; + }; + + pinctrl_nand_default: nand-default { + pinmux = <PIN_PD9__D0>, + <PIN_PD10__D1>, + <PIN_PD11__D2>, + <PIN_PC21__D3>, + <PIN_PC22__D4>, + <PIN_PC23__D5>, + <PIN_PC24__D6>, + <PIN_PD2__D7>, + <PIN_PD3__NANDRDY>, + <PIN_PD4__NCS3_NANDCS>, + <PIN_PD5__NWE_NWR0_NANDWE>, + <PIN_PD6__NRD_NANDOE>, + <PIN_PD7__A21_NANDALE>, + <PIN_PD8__A22_NANDCLE>; + bias-disable; + slew-rate = <0>; + }; + + pinctrl_qspi1_default: qspi1-default { + pinmux = <PIN_PB22__QSPI1_IO3>, + <PIN_PB23__QSPI1_IO2>, + <PIN_PB24__QSPI1_IO1>, + <PIN_PB25__QSPI1_IO0>, + <PIN_PB26__QSPI1_CS>, + <PIN_PB27__QSPI1_SCK>; + bias-pull-up; + slew-rate = <0>; + }; + + pinctrl_sdmmc0_default: sdmmc0-default { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_RSTN>, + <PIN_PA3__SDMMC0_DAT0>, + <PIN_PA4__SDMMC0_DAT1>, + <PIN_PA5__SDMMC0_DAT2>, + <PIN_PA6__SDMMC0_DAT3>; + bias-pull-up; + slew-rate = <0>; + }; + + pinctrl_sdmmc1_default: sdmmc1-default { + pinmux = <PIN_PB29__SDMMC1_CMD>, + <PIN_PB30__SDMMC1_CK>, + <PIN_PB31__SDMMC1_DAT0>, + <PIN_PC0__SDMMC1_DAT1>, + <PIN_PC1__SDMMC1_DAT2>, + <PIN_PC2__SDMMC1_DAT3>, + <PIN_PC4__SDMMC1_CD>; + bias-pull-up; + slew-rate = <0>; + }; +}; + +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +}; + +/* M.2 slot for wireless card */ +&sdmmc0 { + bus-width = <4>; + cd-gpios = <&pioA 31 GPIO_ACTIVE_LOW>; + disable-wp; + sdhci-caps-mask = <0x0 0x00200000>; + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&vdd_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + status = "okay"; +}; + +/* micro SD socket */ +&sdmmc1 { + bus-width = <4>; + disable-wp; + sdhci-caps-mask = <0x0 0x00200000>; + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&vdd_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + status = "okay"; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&shdwc { + debounce-delay-us = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&trng { + status = "okay"; +}; + +&vddout25 { + vin-supply = <&vdd_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts b/arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts index 92f2c05c873f..af70eb8a3a02 100644 --- a/arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts +++ b/arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts @@ -121,6 +121,8 @@ }; &usart3 { + atmel,use-dma-rx; + atmel,use-dma-tx; status = "okay"; pinctrl-0 = <&pinctrl_usart3 diff --git a/arch/arm/boot/dts/microchip/at91sam9x5ek.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5ek.dtsi index 5f4eaa618ab4..9618b8d965b0 100644 --- a/arch/arm/boot/dts/microchip/at91sam9x5ek.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9x5ek.dtsi @@ -39,6 +39,8 @@ }; &dbgu { + atmel,use-dma-rx; + atmel,use-dma-tx; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi index 73d570a17269..291540e5d81e 100644 --- a/arch/arm/boot/dts/microchip/sam9x60.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi @@ -179,7 +179,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(8))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(9))>; @@ -202,7 +202,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(8))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(9))>; @@ -220,7 +220,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(8))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(9))>; @@ -248,7 +248,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(10))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(11))>; @@ -271,7 +271,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(10))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(11))>; @@ -289,7 +289,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(10))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(11))>; @@ -377,7 +377,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(22))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(23))>; @@ -399,7 +399,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(22))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(23))>; @@ -426,7 +426,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(24))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; @@ -448,7 +448,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(24))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; @@ -583,7 +583,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(12))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(13))>; @@ -605,7 +605,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(12))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(13))>; @@ -632,7 +632,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(14))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(15))>; @@ -654,7 +654,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(14))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(15))>; @@ -681,7 +681,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(16))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(17))>; @@ -703,7 +703,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(16))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(17))>; @@ -730,7 +730,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(0))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(1))>; @@ -753,7 +753,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(0))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(1))>; @@ -771,7 +771,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(0))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(1))>; @@ -798,7 +798,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(2))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(3))>; @@ -821,7 +821,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(2))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(3))>; @@ -839,7 +839,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(2))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(3))>; @@ -866,7 +866,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(4))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(5))>; @@ -889,7 +889,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(4))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(5))>; @@ -907,7 +907,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(4))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(5))>; @@ -934,7 +934,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(6))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(7))>; @@ -957,7 +957,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(6))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(7))>; @@ -975,7 +975,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(6))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(7))>; @@ -1057,7 +1057,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(18))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(19))>; @@ -1079,7 +1079,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(18))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(19))>; @@ -1106,7 +1106,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(20))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(21))>; @@ -1128,7 +1128,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(20))>, - <&dma0 + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(21))>; diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi index 269e0a3ca269..75778be126a3 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -698,7 +698,7 @@ }; flx0: flexcom@e1818000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe1818000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; #address-cells = <1>; @@ -714,7 +714,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; clock-names = "usart"; dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, - <&dma1 AT91_XDMAC_DT_PERID(5)>; + <&dma1 AT91_XDMAC_DT_PERID(5)>; dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; @@ -723,7 +723,7 @@ }; flx1: flexcom@e181c000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe181c000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; #address-cells = <1>; @@ -740,14 +740,14 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; atmel,fifo-size = <32>; dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, - <&dma0 AT91_XDMAC_DT_PERID(7)>; + <&dma0 AT91_XDMAC_DT_PERID(7)>; dma-names = "tx", "rx"; status = "disabled"; }; }; flx3: flexcom@e1824000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe1824000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; #address-cells = <1>; @@ -763,7 +763,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; clock-names = "usart"; dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, - <&dma1 AT91_XDMAC_DT_PERID(11)>; + <&dma1 AT91_XDMAC_DT_PERID(11)>; dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; @@ -791,7 +791,7 @@ }; flx4: flexcom@e2018000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe2018000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; #address-cells = <1>; @@ -807,7 +807,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; clock-names = "usart"; dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, - <&dma1 AT91_XDMAC_DT_PERID(13)>; + <&dma1 AT91_XDMAC_DT_PERID(13)>; dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; @@ -817,7 +817,7 @@ }; flx7: flexcom@e2024000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe2024000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; #address-cells = <1>; @@ -833,7 +833,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; clock-names = "usart"; dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, - <&dma1 AT91_XDMAC_DT_PERID(19)>; + <&dma1 AT91_XDMAC_DT_PERID(19)>; dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; @@ -911,7 +911,7 @@ }; flx8: flexcom@e2818000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe2818000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; #address-cells = <1>; @@ -928,14 +928,14 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; atmel,fifo-size = <32>; dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, - <&dma0 AT91_XDMAC_DT_PERID(21)>; + <&dma0 AT91_XDMAC_DT_PERID(21)>; dma-names = "tx", "rx"; status = "disabled"; }; }; flx9: flexcom@e281c000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe281c000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; #address-cells = <1>; @@ -952,14 +952,38 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; atmel,fifo-size = <32>; dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, - <&dma0 AT91_XDMAC_DT_PERID(23)>; + <&dma0 AT91_XDMAC_DT_PERID(23)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + flx10: flexcom@e2820000 { + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe2820000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe2820000 0x800>; + status = "disabled"; + + i2c10: i2c@600 { + compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; + atmel,fifo-size = <32>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>, + <&dma0 AT91_XDMAC_DT_PERID(25)>; dma-names = "tx", "rx"; status = "disabled"; }; }; flx11: flexcom@e2824000 { - compatible = "atmel,sama5d2-flexcom"; + compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe2824000 0x200>; clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; #address-cells = <1>; @@ -977,7 +1001,7 @@ #size-cells = <0>; atmel,fifo-size = <32>; dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>, - <&dma0 AT91_XDMAC_DT_PERID(27)>; + <&dma0 AT91_XDMAC_DT_PERID(27)>; dma-names = "tx", "rx"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi index fd671c7a1e5d..6e1f0f164cb4 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi @@ -120,6 +120,7 @@ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; interrupt-controller; }; @@ -128,6 +129,7 @@ gpio-controller; #gpio-cells = <2>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; interrupt-controller; }; diff --git a/arch/arm/boot/dts/nvidia/Makefile b/arch/arm/boot/dts/nvidia/Makefile index 60091bf7e48b..96972559253c 100644 --- a/arch/arm/boot/dts/nvidia/Makefile +++ b/arch/arm/boot/dts/nvidia/Makefile @@ -39,5 +39,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ tegra30-colibri-eval-v3.dtb \ + tegra30-lg-p880.dtb \ + tegra30-lg-p895.dtb \ tegra30-ouya.dtb \ tegra30-pegatron-chagall.dtb diff --git a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi index a2ee37180200..8125c1b3e8d7 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi @@ -338,6 +338,7 @@ interrupt-parent = <&gpio>; interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; reg = <0>; + wakeup-source; google,cros-ec-spi-msg-delay = <2000>; diff --git a/arch/arm/boot/dts/nvidia/tegra124-venice2.dts b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts index 3924ee385dee..df98dc2a67b8 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-venice2.dts +++ b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts @@ -857,6 +857,7 @@ interrupt-parent = <&gpio>; interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; reg = <0>; + wakeup-source; google,cros-ec-spi-msg-delay = <2000>; diff --git a/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1.dtsi index 1640763fd4af..ff0d684622f7 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1.dtsi @@ -997,7 +997,6 @@ compatible = "st,stmpe811"; reg = <0x41>; irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; - interrupt-controller; id = <0>; blocks = <0x5>; irq-trigger = <0x1>; diff --git a/arch/arm/boot/dts/nvidia/tegra30-apalis.dtsi b/arch/arm/boot/dts/nvidia/tegra30-apalis.dtsi index 3b6fad273cab..d38f1dd38a90 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-apalis.dtsi @@ -980,7 +980,6 @@ compatible = "st,stmpe811"; reg = <0x41>; irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; - interrupt-controller; id = <0>; blocks = <0x5>; irq-trigger = <0x1>; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi index a9342e04b14b..15f53babdc21 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi @@ -915,6 +915,9 @@ reg = <0x1c>; realtek,dmic1-data-pin = <1>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "mclk"; }; nct72: temperature-sensor@4c { diff --git a/arch/arm/boot/dts/nvidia/tegra30-colibri.dtsi b/arch/arm/boot/dts/nvidia/tegra30-colibri.dtsi index 4eb526fe9c55..81c8a5fd92cc 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-colibri.dtsi @@ -861,7 +861,6 @@ compatible = "st,stmpe811"; reg = <0x41>; irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; - interrupt-controller; id = <0>; blocks = <0x5>; irq-trigger = <0x1>; diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts new file mode 100644 index 000000000000..2f7754fd42a1 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts @@ -0,0 +1,489 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-lg-x3.dtsi" + +/ { + model = "LG Optimus 4X HD P880"; + compatible = "lg,p880", "nvidia,tegra30"; + + aliases { + mmc1 = &sdmmc3; /* uSD slot */ + mmc2 = &sdmmc1; /* WiFi */ + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* WLAN SDIO pinmux */ + host-wlan-wake { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GNSS UART-B pinmux */ + uartb-rxd { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartb-txd { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gps-reset { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* MicroSD pinmux */ + sdmmc3-clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3-data { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + microsd-detect { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO keys pinmux */ + volume-up { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + current-alert-irq { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* AUDIO pinmux */ + sub-mic-ldo { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + }; + }; + + i2c@7000c400 { + touchscreen@20 { + rmi4-f11@11 { + syna,clip-x-high = <1110>; + syna,clip-y-high = <1973>; + + touchscreen-inverted-y; + }; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */ + nvidia,ram-code = <0>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < 0x00050001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x77230303 0x001f0000 >; + }; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-266500000 { + clock-frequency = <266500000>; + + nvidia,emem-configuration = < 0x00000004 0xC0000030 + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000006 0x00000001 0x00000002 0x00000005 + 0x00000001 0x00000000 0x00000003 0x00000003 + 0x03030001 0x00090608 0x70040c09 0x001f0000 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emem-configuration = < 0x00000008 0xC0000060 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000d 0x00000002 0x00000002 0x00000008 + 0x00000002 0x00000000 0x00000004 0x00000005 + 0x05040002 0x00110b10 0x70281811 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */ + nvidia,ram-code = <0>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000000 + 0x00000001 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x0000002f 0x00000000 0x0000000b + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000002 0x00000002 + 0x00000003 0x00000008 0x00000004 0x00000001 + 0x00000002 0x00000036 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000009 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000164 0xe0000000 0xff00ff00 >; + }; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000001 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000001 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000001 + 0x00000002 0x000001a9 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000001 + 0x00000002 0x00000351 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-266500000 { + clock-frequency = <266500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020002>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000018>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000f + 0x00000022 0x0000000b 0x00000004 0x00000005 + 0x00000005 0x00000001 0x00000007 0x00000004 + 0x00000004 0x00000002 0x00000002 0x00000000 + 0x00000002 0x00000005 0x00000002 0x0000000c + 0x0000000b 0x000003ef 0x00000000 0x000000fb + 0x00000001 0x00000001 0x00000004 0x00000000 + 0x00000001 0x00000009 0x00000026 0x00000026 + 0x00000004 0x0000000e 0x00000006 0x00000001 + 0x00000002 0x00000455 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0x003200a4 + 0x00008000 0x00050000 0x00050000 0x00050000 + 0x00050000 0x00050000 0x00050000 0x00050000 + 0x00050000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00060000 0x00060000 0x00060000 + 0x00060000 0x000b0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000060 0x000a000a 0xa0f10000 0x00000000 + 0x00000000 0x800008ee 0xe0000000 0xff00ff00 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020006>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000030>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000045 0x00000016 0x00000009 0x00000008 + 0x00000009 0x00000003 0x0000000d 0x00000009 + 0x00000009 0x00000005 0x00000003 0x00000000 + 0x00000004 0x00000009 0x00000006 0x0000000d + 0x00000010 0x000007df 0x00000000 0x000001f7 + 0x00000003 0x00000003 0x00000009 0x00000000 + 0x00000001 0x0000000f 0x0000004b 0x0000004b + 0x00000008 0x0000001b 0x0000000c 0x00000001 + 0x00000002 0x000008aa 0x00000000 0x00000006 + 0x00000000 0x00000000 0x00006282 0xf0120091 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00090220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000c0 0x000e000e 0xa0f10000 0x00000000 + 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >; + }; + }; + }; + + sdmmc3: mmc@78000400 { + status = "okay"; + + cd-gpios = <&gpio TEGRA_GPIO(W, 5) GPIO_ACTIVE_LOW>; + bus-width = <4>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + battery: battery-cell { + compatible = "simple-battery"; + device-chemistry = "lithium-ion"; + charge-full-design-microamp-hours = <2150000>; + energy-full-design-microwatt-hours = <8200000>; + operating-range-celsius = <0 45>; + }; + + gpio-keys { + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(O, 7) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + }; + + sound { + compatible = "lg,tegra-audio-max98089-p880", + "nvidia,tegra-audio-max98089"; + nvidia,model = "LG Optimus 4X HD MAX98089"; + + nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts new file mode 100644 index 000000000000..e32fafc7f5e0 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-lg-x3.dtsi" + +/ { + model = "LG Optimus Vu P895"; + compatible = "lg,p895", "nvidia,tegra30"; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* GNSS UART-B pinmux */ + uartb-cts-rxd { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartb-rts-txd { + nvidia,pins = "uart2_rts_n_pj6", + "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gps-reset { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* GPIO keys pinmux */ + memo-key { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + volume-up { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + current-alert-irq { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Panel pinmux */ + panel-vdd { + nvidia,pins = "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* AUDIO pinmux */ + sub-mic-ldo { + nvidia,pins = "gmi_dqs_pi2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Modem pinmux */ + usim-detect { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO power/drive control */ + drive-sdmmc4 { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + }; + }; + + i2c@7000c400 { + touchscreen@20 { + rmi4-f11@11 { + syna,clip-x-high = <1535>; + syna,clip-y-high = <2047>; + }; + }; + }; + + memory-controller@7000f000 { + emc-timings-2 { + /* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */ + nvidia,ram-code = <2>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x77230303 0x001f0000 >; + }; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00030003 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x73e30303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010003 0xc0000010 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060402 0x72c30303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000018 + 0x00000001 0x00000001 0x00000003 0x00000001 + 0x00000003 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000002 0x00000002 + 0x02020001 0x00060403 0x72430504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000006 0xc0000025 + 0x00000001 0x00000001 0x00000006 0x00000003 + 0x00000005 0x00000001 0x00000002 0x00000004 + 0x00000001 0x00000000 0x00000003 0x00000002 + 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; + }; + + timing-266500000 { + clock-frequency = <266500000>; + + nvidia,emem-configuration = < 0x00000008 0xc0000030 + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000006 0x00000001 0x00000002 0x00000005 + 0x00000001 0x00000000 0x00000003 0x00000003 + 0x03030001 0x00090608 0x70040c09 0x001f0000 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emem-configuration = < 0x0000000f 0xc0000060 + 0x00000003 0x00000004 0x00000010 0x0000000a + 0x0000000d 0x00000002 0x00000002 0x00000008 + 0x00000002 0x00000000 0x00000004 0x00000005 + 0x05040002 0x00110b10 0x70281811 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-2 { + /* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */ + nvidia,ram-code = <2>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000000 + 0x00000001 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x0000002f 0x00000000 0x0000000b + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000002 0x00000002 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x00000036 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000009 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000164 0xe0000000 0xff00ff00 >; + }; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000003 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000060 0x00000000 0x00000018 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000004 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x0000006b 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000000a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x800001c5 0xd0000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000009>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000003 + 0x00000006 0x00000002 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x000000c0 0x00000000 0x00000030 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x00000008 0x00000008 + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000000d5 0x00000004 0x00000004 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000013 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xd0000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010022>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x0000000a>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000006 + 0x0000000d 0x00000004 0x00000002 0x00000004 + 0x00000004 0x00000001 0x00000005 0x00000002 + 0x00000002 0x00000001 0x00000001 0x00000000 + 0x00000001 0x00000003 0x00000001 0x0000000b + 0x00000009 0x00000181 0x00000000 0x00000060 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000007 0x0000000f 0x0000000f + 0x00000003 0x00000008 0x00000004 0x00000004 + 0x00000002 0x000001a9 0x00000004 0x00000006 + 0x00000000 0x00000000 0x00004282 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00100220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000025 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xd0000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020001>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000013>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000c + 0x0000001a 0x00000008 0x00000003 0x00000005 + 0x00000004 0x00000001 0x00000006 0x00000003 + 0x00000003 0x00000002 0x00000002 0x00000000 + 0x00000001 0x00000004 0x00000001 0x0000000c + 0x0000000a 0x00000303 0x00000000 0x000000c0 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000007 0x0000001d 0x0000001d + 0x00000004 0x0000000b 0x00000005 0x00000004 + 0x00000002 0x00000351 0x00000005 0x00000004 + 0x00000000 0x00000000 0x00004282 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000e0220 0x0800201c 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x0000004a 0x00090009 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; + }; + + timing-266500000 { + clock-frequency = <266500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x00010042>; + nvidia,emc-mode-2 = <0x00020002>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000018>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000f + 0x00000022 0x0000000b 0x00000004 0x00000005 + 0x00000005 0x00000001 0x00000007 0x00000004 + 0x00000004 0x00000002 0x00000002 0x00000000 + 0x00000002 0x00000005 0x00000002 0x0000000c + 0x0000000b 0x000003ef 0x00000000 0x000000fb + 0x00000001 0x00000001 0x00000004 0x00000000 + 0x00000001 0x00000009 0x00000026 0x00000026 + 0x00000004 0x0000000e 0x00000006 0x00000004 + 0x00000002 0x00000455 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0x003200a4 + 0x00008000 0x00070000 0x00070000 0x00070000 + 0x00070000 0x00072000 0x00072000 0x00072000 + 0x00072000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080002 0x00080002 0x00080002 + 0x00080002 0x000e0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f008 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x00000060 0x000a000a 0xa0f10000 0x00000000 + 0x00000000 0x800008ee 0xe0000000 0xff00ff00 >; + }; + + timing-533000000 { + clock-frequency = <533000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x000100c2>; + nvidia,emc-mode-2 = <0x00020006>; + nvidia,emc-mode-reset = <0x00000000>; + nvidia,emc-zcal-cnt-long = <0x00000030>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000045 0x00000016 0x00000009 0x00000008 + 0x00000009 0x00000003 0x0000000d 0x00000009 + 0x00000009 0x00000005 0x00000003 0x00000000 + 0x00000004 0x0000000a 0x00000006 0x0000000d + 0x00000010 0x000007df 0x00000000 0x000001f7 + 0x00000003 0x00000003 0x00000009 0x00000000 + 0x00000001 0x0000000f 0x0000004b 0x0000004b + 0x00000008 0x0000001b 0x0000000c 0x00000004 + 0x00000002 0x000008aa 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00006282 0xf0120091 + 0x00008000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000c0220 0x0800003d 0x00000000 + 0x77ffc004 0x01f1f408 0x00000000 0x00000007 + 0x08000068 0x08000000 0x00000802 0x00064000 + 0x000000c0 0x000e000e 0xa0f10000 0x00000000 + 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >; + }; + }; + }; + + battery: battery-cell { + compatible = "simple-battery"; + device-chemistry = "lithium-ion"; + charge-full-design-microamp-hours = <2080000>; + energy-full-design-microwatt-hours = <7700000>; + operating-range-celsius = <0 45>; + }; + + gpio-keys { + key-memo { + label = "Memo"; + gpios = <&gpio TEGRA_GPIO(B, 6) GPIO_ACTIVE_LOW>; + linux,code = <KEY_MEMO>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + }; + + gpio-leds { + led-power { + label = "power::white"; + gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>; + + linux,default-trigger = "battery-charging"; + + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_CHARGING; + }; + }; + + regulator-lcd3v { + gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "lg,tegra-audio-max98089-p895", + "nvidia,tegra-audio-max98089"; + nvidia,model = "LG Optimus Vu MAX98089"; + + nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(I, 2) GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi new file mode 100644 index 000000000000..909260a5d0fb --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi @@ -0,0 +1,1812 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/mfd/max77620.h> +#include <dt-bindings/thermal/thermal.h> + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" + +/ { + chassis-type = "handset"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc1; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + serial0 = &uartd; /* Console */ + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen { }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + + ramoops@bed00000 { + compatible = "ramoops"; + reg = <0xbed00000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; /* 2MB */ + no-map; + }; + }; + + vde@6001a000 { + assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; + assigned-clock-rates = <408000000>; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* WLAN SDIO pinmux */ + sdmmc1-clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1-cmd { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + wlan-reset { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + wlan-host-wake { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GNSS UART-B pinmux */ + gps-pwr-en { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gps-ldo-en { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gps-clk-ref { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Bluetooth UART-C pinmux */ + uartc-cts-rxd { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartc-rts-txd { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt-reset { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt-dev-wake { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt-host-wake { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bt-pcm-dap4 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* EMMC pinmux */ + sdmmc4-clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4-data { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4-reset { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* I2C pinmux */ + gen1-i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + gen2-i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + cam-i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + ddc-i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + pwr-i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + mhl-i2c { + nvidia,pins = "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO keys pinmux */ + power-key { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + volume-down { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + sen-vdd { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + proxi-vdd { + nvidia,pins = "spi2_miso_px1"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sen-vio { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + nct-irq { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bat-irq { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + charger-irq { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mpu-irq { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + compass-irq { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + light-irq { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* LED pinmux */ + backlight-en { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + flash-led-en { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + keypad-led { + nvidia,pins = "kb_row2_pr2", + "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* NFC pinmux */ + nfc-irq { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + nfc-ven { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + nfc-firm { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* DC pinmux */ + lcd-pwr { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pwr1_pc1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd-wr-n { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd-id { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd-pclk { + nvidia,pins = "lcd_pclk_pb3", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd-rgb-blue { + nvidia,pins = "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d18_pm2", + "lcd_d19_pm3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd-rgb-green { + nvidia,pins = "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d20_pm4", + "lcd_d21_pm5"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd-rgb-red { + nvidia,pins = "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d22_pm6", + "lcd_d23_pm7"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Bridge pinmux */ + bridge-reset { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + rgb-ic-en { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bridge-clk { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + rgb-bridge { + nvidia,pins = "lcd_sdin_pz2", + "lcd_sdout_pn5", + "lcd_cs0_n_pn4", + "lcd_sck_pz4"; + nvidia,function = "spi5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Panel pinmux */ + panel-reset { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + panel-vio { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Touchscreen pinmux */ + touch-vdd { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + touch-vio { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + touch-irq-n { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + touch-rst-n { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + touch-maker-id { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* MHL pinmux */ + mhl-vio { + nvidia,pins = "pv2"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mhl-rst-n { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mhl-irq { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mhl-sel { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + hdmi-hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* AUDIO pinmux */ + hp-detect { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hp-hook { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ear-mic-en { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + audio-irq { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + audio-mclk { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap-i2s0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap-i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* MUIC pinmux */ + muic-irq { + nvidia,pins = "gmi_cs0_n_pj0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + muic-dp2t { + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + muic-usif { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ifx-usb-vbus-en { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pcb-rev { + nvidia,pins = "gmi_wait_pi7", + "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + jtag-rtck { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Camera pinmux */ + cam-mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam-pmic-en { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + front-cam-rst { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + front-cam-vio { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + rear-cam-rst { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + rear-cam-eprom-pr { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + rear-cam-vcm-pwdn { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Haptic pinmux */ + haptic-en { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + haptic-osc { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Modem pinmux */ + cp2ap-ack1-host-active { + nvidia,pins = "pu5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cp2ap-ack2-host-wakeup { + nvidia,pins = "pv0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ap2cp-ack2-suspend-req { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ap2cp-ack1-slave-wakeup { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cp-kkp { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cp-crash-irq { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ap2cp-uarta-tx-ipc { + nvidia,pins = "pu0"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ap2cp-uarta-rx-ipc { + nvidia,pins = "pu1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + fota-ap-cts-cp-rts { + nvidia,pins = "pu2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + fota-ap-rts-cp-cts { + nvidia,pins = "pu3"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + modem-enable { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "hsi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + modem-reset { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap-i2s2 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO power/drive control */ + drive-i2c { + nvidia,pins = "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive-uart3 { + nvidia,pins = "drive_uart3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive-gmi { + nvidia,pins = "drive_at3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + }; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; + /delete-property/ reg-shift; + status = "okay"; + + /* GNSS GSD5T */ + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; + /delete-property/ reg-shift; + status = "okay"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + /* BCM4330B1 37.4 MHz Class 1.5 ExtLNA */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(S, 4) IRQ_TYPE_EDGE_RISING>; + interrupt-names = "host-wakeup"; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; + + vbat-supply = <&vdd_3v3_vbat>; + vddio-supply = <&vdd_1v8_vio>; + }; + }; + + uartd: serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; + status = "okay"; + + /* Console */ + }; + + pwm@7000a000 { + status = "okay"; + }; + + gen1_i2c: i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* Aichi AMI306 digital compass */ + magnetometer@e { + compatible = "asahi-kasei,ak8974"; + reg = <0x0e>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(H, 5) IRQ_TYPE_EDGE_RISING>; + + avdd-supply = <&vdd_3v0_sen>; + dvdd-supply = <&vdd_1v8_vio>; + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; + + max98089: audio-codec@10 { + compatible = "maxim,max98089"; + reg = <0x10>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "mclk"; + + assigned-clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + nfc@28 { + compatible = "nxp,pn544-i2c"; + reg = <0x28>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_HIGH>; + firmware-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + }; + + imu@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&vdd_3v0_sen>; + vddio-supply = <&vdd_1v8_sen>; + + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; + }; + + gen2_i2c: i2c@7000c400 { + status = "okay"; + clock-frequency = <400000>; + + /* Synaptics RMI4 S3203B touchcreen */ + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(Q, 3) IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&vdd_3v0_touch>; + vio-supply = <&vdd_1v8_touch>; + + syna,reset-delay-ms = <20>; + syna,startup-delay-ms = <200>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + syna,sensor-type = <1>; + + syna,clip-x-low = <0>; + syna,clip-y-low = <0>; + }; + }; + }; + + cam_i2c: i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + + dw9714: coil@c { + compatible = "dongwoon,dw9714"; + reg = <0x0c>; + + enable-gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_HIGH>; + + vcc-supply = <&vcc_focuser>; + }; + + camera-pmic@7d { + compatible = "ti,lp8720"; + reg = <0x7d>; + + enable-gpios = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; + + vt_1v2_front: ldo1 { + regulator-name = "vt_1v2_dig"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vt_2v7_front: ldo2 { + regulator-name = "vt_2v7_vana"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + vdd_2v7_rear: ldo3 { + regulator-name = "8m_2v7_vana"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + vio_1v8_rear: ldo4 { + regulator-name = "vio_1v8_cam"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_focuser: ldo5 { + regulator-name = "8m_2v8_vcm"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vdd_1v2_rear: buck { + regulator-name = "8m_1v2_cam"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: max77663@1c { + compatible = "maxim,max77663"; + reg = <0x1c>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + system-power-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&max77663_default>; + + max77663_default: pinmux { + gpio1 { + pins = "gpio1"; + function = "gpio"; + drive-open-drain = <1>; + }; + + gpio4 { + pins = "gpio4"; + function = "32k-out1"; + }; + }; + + fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + }; + + regulators { + in-sd0-supply = <&vdd_5v0_vbus>; + in-sd1-supply = <&vdd_5v0_vbus>; + in-sd2-supply = <&vdd_5v0_vbus>; + in-sd3-supply = <&vdd_5v0_vbus>; + + in-ldo0-1-supply = <&vdd_1v8_vio>; + in-ldo2-supply = <&vdd_3v3_vbat>; + in-ldo3-5-supply = <&vdd_3v3_vbat>; + in-ldo4-6-supply = <&vdd_3v3_vbat>; + in-ldo7-8-supply = <&vdd_1v8_vio>; + + vdd_cpu: sd0 { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-cpu-regulator; + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + + vdd_core: sd1 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-core-regulator; + maxim,active-fps-source = <MAX77620_FPS_SRC_1>; + }; + + vdd_1v8_vio: sd2 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + + sd3 { + regulator-name = "vddio_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + + ldo0 { + regulator-name = "avdd_pll"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = <MAX77620_FPS_SRC_1>; + }; + + ldo1 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + + avdd_3v3_periph: ldo2 { + regulator-name = "avdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + + vdd_usd: ldo3 { + regulator-name = "vdd_sdmmc3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + + ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = <MAX77620_FPS_SRC_0>; + }; + + vcore_emmc: ldo5 { + regulator-name = "vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = <MAX77620_FPS_SRC_0>; + }; + + avdd_1v8_hdmi_pll: ldo6 { + regulator-name = "avdd_osc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + + vdd_1v2_mhl: ldo7 { + regulator-name = "vdd_1v2_mhl"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1250000>; + + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + + ldo8 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; + }; + }; + }; + + fuel-gauge@36 { + compatible = "maxim,max17043"; + reg = <0x36>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_EDGE_FALLING>; + + monitored-battery = <&battery>; + + maxim,alert-low-soc-level = <10>; + wakeup-source; + }; + + power-sensor@40 { + compatible = "ti,ina230"; + reg = <0x40>; + + vs-supply = <&vdd_3v0_sen>; + }; + + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(I, 5) IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <&vdd_3v0_sen>; + #thermal-sensor-cells = <1>; + }; + }; + + i2c-mhl { + compatible = "i2c-gpio"; + + sda-gpios = <&gpio TEGRA_GPIO(Q, 7) (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio TEGRA_GPIO(Q, 6) (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + i2c-gpio,delay-us = <5>; + + #address-cells = <1>; + #size-cells = <0>; + }; + + spi@7000dc00 { + status = "okay"; + spi-max-frequency = <25000000>; + + /* DSI bridge */ + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <2>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x1c>; + nvidia,reg-addr = <0x41>; + nvidia,reg-data = <0x02>; + }; + }; + + hda@70030000 { + status = "okay"; + }; + + ahub@70080000 { + /* HIFI CODEC */ + i2s@70080300 { /* i2s0 */ + status = "okay"; + }; + + /* BASEBAND */ + i2s@70080500 { /* i2s2 */ + status = "okay"; + }; + + /* BT SCO */ + i2s@70080600 { /* i2s3 */ + status = "okay"; + }; + }; + + sdmmc1: mmc@78000000 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_vbat>; + vqmmc-supply = <&vdd_1v8_vio>; + + /* BCM4330B1 37.4 MHz Class 1.5 ExtLNA */ + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; + }; + + sdmmc4: mmc@78000600 { + status = "okay"; + bus-width = <8>; + + non-removable; + mmc-ddr-1_8v; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + /* Micro USB */ + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&avdd_3v3_periph>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + gps_refclk: clock-gps { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + clock-accuracy = <100>; + #clock-cells = <0>; + }; + + gps_osc: clock-gps-osc-gate { + compatible = "gpio-gate-clock"; + enable-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; + clocks = <&gps_refclk>; + #clock-cells = <0>; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu2: cpu@2 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + cpu3: cpu@3 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(O, 4) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-keypad { + label = "keypad::white"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_KBD_BACKLIGHT; + }; + }; + + opp-table-actmon { + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; + + brcm_wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + vdd_5v0_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_vbat: regulator-vbat { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbat"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v0_vbus>; + }; + + vdd_3v0_sen: regulator-sen3v { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v0_sensor"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vdd_3v0_proxi: regulator-proxi { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v0_proxi"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vdd_1v8_sen: regulator-sen1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_sensor"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vcc_3v0_lcd: regulator-lcd3v { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v0_lcd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + vin-supply = <&vdd_3v3_vbat>; + }; + + iovcc_1v8_lcd: regulator-lcd1v8 { + compatible = "regulator-fixed"; + regulator-name = "iovcc_1v8_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vio_1v8_mhl: regulator-mhl1v8 { + compatible = "regulator-fixed"; + regulator-name = "vio_1v8_mhl"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vdd_3v0_touch: regulator-touchpwr { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v0_touch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vdd_1v8_touch: regulator-touchvio { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_touch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(X, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vcc_1v8_gps: regulator-gps { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_gps"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(Y, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + vio_1v8_front: regulator-frontvio { + compatible = "regulator-fixed"; + regulator-name = "vt_1v8_cam_vio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(Y, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + + sound { + nvidia,audio-routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Int Spk", "SPKL", + "Int Spk", "SPKR", + "Earpiece", "RECL", + "Earpiece", "RECR", + "INA1", "Mic Jack", + "MIC1", "MICBIAS", + "MICBIAS", "Internal Mic 1", + "MIC2", "Internal Mic 2"; + + nvidia,i2s-controller = <&tegra_i2s0>; + nvidia,audio-codec = <&max98089>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(BB, 6) GPIO_ACTIVE_LOW>; + nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_HIGH>; + nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>; + nvidia,coupled-mic-hp-det; + + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + thermal-zones { + /* + * NCT72 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone exists as a simpler solution which prevents + * this device from getting too hot from a user's + * tactile perspective. The CPU zone is intended to + * protect silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 0>; + + trips { + trip0: skin-alert { + /* throttle at 50C until temperature drops to 49.8C */ + temperature = <50000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 60C */ + temperature = <60000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct72 1>; + + trips { + trip2: cpu-alert { + /* throttle at 75C until temperature drops to 74.8C */ + temperature = <75000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index a724d1a7a9a0..4052cad859fa 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -45,7 +45,9 @@ dtb-$(CONFIG_SOC_IMX53) += \ imx53-mba53.dtb \ imx53-ppd.dtb \ imx53-qsb.dtb \ + imx53-qsb-hdmi.dtb \ imx53-qsrb.dtb \ + imx53-qsrb-hdmi.dtb \ imx53-sk-imx53.dtb \ imx53-sk-imx53-atm0700d4-lvds.dtb \ imx53-sk-imx53-atm0700d4-rgb.dtb \ @@ -54,6 +56,8 @@ dtb-$(CONFIG_SOC_IMX53) += \ imx53-tx53-x13x.dtb \ imx53-usbarmory.dtb \ imx53-voipac-bsb.dtb +imx53-qsb-hdmi-dtbs := imx53-qsb.dtb imx53-qsb-hdmi.dtbo +imx53-qsrb-hdmi-dtbs := imx53-qsrb.dtb imx53-qsb-hdmi.dtbo dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-alti6p.dtb \ imx6dl-apf6dev.dtb \ @@ -118,6 +122,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-sabrelite.dtb \ imx6dl-sabresd.dtb \ imx6dl-savageboard.dtb \ + imx6dl-sielaff.dtb \ imx6dl-skov-revc-lt2.dtb \ imx6dl-skov-revc-lt6.dtb \ imx6dl-solidsense.dtb \ @@ -147,6 +152,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-yapp4-phoenix.dtb \ imx6dl-yapp4-ursa.dtb \ imx6q-apalis-eval.dtb \ + imx6q-apalis-eval-v1.2.dtb \ imx6q-apalis-ixora.dtb \ imx6q-apalis-ixora-v1.1.dtb \ imx6q-apalis-ixora-v1.2.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts index e66eef87a7a4..058e9435524f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts +++ b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts @@ -54,7 +54,7 @@ #size-cells = <1>; }; - eth: eth@4,c00000 { + eth: ethernet@4,c00000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eth>; compatible = "davicom,dm9000"; diff --git a/arch/arm/boot/dts/nxp/imx/imx1.dtsi b/arch/arm/boot/dts/nxp/imx/imx1.dtsi index 1ac10965fdfd..389ecb1ebf8f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx1.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx1.dtsi @@ -251,7 +251,7 @@ }; }; - weim: weim@220000 { + weim: memory-controller@220000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx1-weim"; diff --git a/arch/arm/boot/dts/nxp/imx/imx27.dtsi b/arch/arm/boot/dts/nxp/imx/imx27.dtsi index ec472695c71e..ec3ccc8f4095 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx27.dtsi @@ -568,7 +568,7 @@ status = "disabled"; }; - weim: weim@d8002000 { + weim: memory-controller@d8002000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx27-weim"; diff --git a/arch/arm/boot/dts/nxp/imx/imx31.dtsi b/arch/arm/boot/dts/nxp/imx/imx31.dtsi index e1ae7c175f7d..00006c90d9a7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx31.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx31.dtsi @@ -352,7 +352,7 @@ status = "disabled"; }; - weim: weim@b8002000 { + weim: memory-controller@b8002000 { compatible = "fsl,imx31-weim", "fsl,imx27-weim"; reg = <0xb8002000 0x1000>; clocks = <&clks 56>; diff --git a/arch/arm/boot/dts/nxp/imx/imx35.dtsi b/arch/arm/boot/dts/nxp/imx/imx35.dtsi index 2d20e5541acc..442dc15677b8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx35.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx35.dtsi @@ -374,7 +374,7 @@ status = "disabled"; }; - weim: weim@b8002000 { + weim: memory-controller@b8002000 { #address-cells = <2>; #size-cells = <1>; clocks = <&clks 0>; diff --git a/arch/arm/boot/dts/nxp/imx/imx51.dtsi b/arch/arm/boot/dts/nxp/imx/imx51.dtsi index c96d6311dfa7..4efce49022e4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx51.dtsi @@ -578,7 +578,7 @@ reg = <0x83fd8000 0x1000>; }; - weim: weim@83fda000 { + weim: memory-controller@83fda000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx51-weim"; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-qsb-hdmi.dtso b/arch/arm/boot/dts/nxp/imx/imx53-qsb-hdmi.dtso new file mode 100644 index 000000000000..c84e9b052527 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-qsb-hdmi.dtso @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT overlay for MCIMXHDMICARD as used with the iMX53 QSB or QSRB boards + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + +&{/} { + /delete-node/ panel; + + hdmi: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "1P2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + vin-supply = <®_3p2v>; + }; +}; + +&display0 { + status = "okay"; +}; + +&display0 { + port@1 { + display0_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + sii9022: bridge-hdmi@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + interrupts-extended = <&gpio3 31 IRQ_TYPE_LEVEL_LOW>; + iovcc-supply = <®_3p2v>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&display0_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&tve { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-sielaff.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-sielaff.dts new file mode 100644 index 000000000000..7de8d5f26518 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-sielaff.dts @@ -0,0 +1,533 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include <dt-bindings/clock/imx6qdl-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Sielaff i.MX6 Solo"; + compatible = "sielaff,imx6dl-board", "fsl,imx6dl"; + + chosen { + stdout-path = &uart2; + }; + + backlight: pwm-backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm3 0 50000 0>; + brightness-levels = <0 0 64 88 112 136 184 232 255>; + default-brightness-level = <4>; + enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + power-supply = <®_backlight>; + }; + + cec { + compatible = "cec-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + hdmi-phandle = <&hdmi>; + }; + + enet_ref: clock-enet-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet-ref"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-0 { + gpios = <&gpio2 16 0>; + debounce-interval = <10>; + linux,code = <1>; + }; + + key-1 { + gpios = <&gpio3 27 0>; + debounce-interval = <10>; + linux,code = <2>; + }; + + key-2 { + gpios = <&gpio5 4 0>; + debounce-interval = <10>; + linux,code = <3>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-debug { + label = "debug-led"; + gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + device_type = "memory"; + }; + + osc_eth_phy: clock-osc-eth-phy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "osc-eth-phy"; + }; + + panel { + compatible = "lg,lb070wv8"; + backlight = <&backlight>; + power-supply = <®_3v3>; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_backlight>; + enable-active-high; + gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; + regulator-name = "backlight"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + enable-active-high; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&fec { + /* + * Set PTP clock to external instead of internal reference, as the + * REF_CLK from the PHY is fed back into the i.MX6 and the GPR + * register needs to be set accordingly (see mach-imx6q.c). + */ + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&enet_ref>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_out"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-connection-type = "rmii"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@1 { + reg = <1>; + clocks = <&osc_eth_phy>; + clock-names = "rmii-ref"; + micrel,led-mode = <1>; + reset-assert-us = <500>; + reset-deassert-us = <100>; + reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "key-out", "key-in", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "lan9500a-rst", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c4>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; + status = "okay"; + + touchscreen@55 { + compatible = "sitronix,st1633"; + reg = <0x55>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio5>; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + touchscreen@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio5>; + irq-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clock-frequency = <100000>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds_out: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + disable-over-current; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + usb1@1 { + compatible = "usb4b4,6570"; + reg = <1>; + clocks = <&clks IMX6QDL_CLK_CKO>; + + assigned-clocks = <&clks IMX6QDL_CLK_CKO>, + <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_OSC>; + assigned-clock-rates = <12000000 0>; + }; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "host"; + over-current-active-low; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3v3>; + voltage-ranges = <3300 3300>; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x1b0b0 /* PMIC_IRQ */ + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b080 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b080 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b080 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_reg_backlight: regbacklightgrp { + fsl,pins = < + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b1 + >; + }; + + pinctrl_reg_usbotg_vbus: regusbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b1 + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x100b1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi index 3be38a3c4bb1..c32ea040fecd 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi @@ -117,17 +117,9 @@ #address-cells = <1>; #size-cells = <0>; - phy_port2: phy@1 { - reg = <1>; - }; - - phy_port3: phy@2 { - reg = <2>; - }; - switch@10 { compatible = "qca,qca8334"; - reg = <10>; + reg = <0x10>; reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; switch_ports: ports { @@ -149,15 +141,30 @@ eth2: port@2 { reg = <2>; label = "eth2"; + phy-mode = "internal"; phy-handle = <&phy_port2>; }; eth1: port@3 { reg = <3>; label = "eth1"; + phy-mode = "internal"; phy-handle = <&phy_port3>; }; }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port2: ethernet-phy@1 { + reg = <1>; + }; + + phy_port3: ethernet-phy@2 { + reg = <2>; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval-v1.2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval-v1.2.dts new file mode 100644 index 000000000000..15d4a98ee976 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval-v1.2.dts @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +/dts-v1/; + +#include "imx6q-apalis-eval.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board v1.2"; + compatible = "toradex,apalis_imx6q-eval-v1.2", "toradex,apalis_imx6q", + "fsl,imx6q"; + + reg_3v3_mmc: regulator-3v3-mmc { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_mmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_MMC"; + startup-delay-us = <10000>; + }; + + reg_3v3_sd: regulator-3v3-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_sd>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_SD"; + startup-delay-us = <10000>; + }; + + reg_can1: regulator-can1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can1_power>; + regulator-name = "5V_SW_CAN1"; + startup-delay-us = <10000>; + }; + + reg_can2: regulator-can2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can2_power>; + regulator-name = "5V_SW_CAN2"; + startup-delay-us = <10000>; + }; + + sound-carrier { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,name = "apalis-nau8822"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "Line Out", "AUXOUT1", + "Line Out", "AUXOUT2", + "LAUX", "Line In", + "RAUX", "Line In", + "LMICP", "Mic In", + "RMICP", "Mic In"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Line Out", "Line Out", + "Speaker", "Speaker", + "Microphone", "Mic In", + "Line", "Line In"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&nau8822_1a>; + system-clock-frequency = <12288000>; + }; + + simple-audio-card,cpu { + sound-dai = <&ssi2>; + }; + }; +}; + +&can1 { + xceiver-supply = <®_can1>; + status = "okay"; +}; + +&can2 { + xceiver-supply = <®_can2>; + status = "okay"; +}; + +/* I2C1_SDA/SCL on MXM3 209/211 */ +&i2c1 { + /* Audio Codec */ + nau8822_1a: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nau8822>; + #sound-dai-cells = <0>; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + + /* Temperature Sensor */ + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + /* EEPROM */ + eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + size = <256>; + }; +}; + +&pcie { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +/* MMC1 */ +&usdhc1 { + bus-width = <4>; + pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>; + vmmc-supply = <®_3v3_mmc>; + status = "okay"; +}; + +/* SD1 */ +&usdhc2 { + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>; + vmmc-supply = <®_3v3_sd>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enable_3v3_mmc: enable3v3mmcgrp { + fsl,pins = < + /* MMC1_PWR_CTRL */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + >; + }; + + pinctrl_enable_3v3_sd: enable3v3sdgrp { + fsl,pins = < + /* SD1_PWR_CTRL */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + pinctrl_enable_can1_power: enablecan1powergrp { + fsl,pins = < + /* CAN1_PWR_EN */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + >; + }; + + pinctrl_enable_can2_power: enablecan2powergrp { + fsl,pins = < + /* CAN2_PWR_EN */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + >; + }; + + pinctrl_nau8822: nau8822grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x130b0 + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts index 3fc079dfd61e..e1077e2da5f4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts @@ -7,29 +7,13 @@ /dts-v1/; -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include "imx6q.dtsi" -#include "imx6qdl-apalis.dtsi" +#include "imx6q-apalis-eval.dtsi" / { model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board"; compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q", "fsl,imx6q"; - aliases { - i2c0 = &i2c1; - i2c1 = &i2c3; - i2c2 = &i2c2; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - reg_pcie_switch: regulator-pcie-switch { compatible = "regulator-fixed"; enable-active-high; @@ -40,14 +24,6 @@ startup-delay-us = <100000>; status = "okay"; }; - - reg_3v3_sw: regulator-3v3-sw { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "3.3V_SW"; - }; }; &can1 { @@ -62,102 +38,22 @@ /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ &i2c1 { - status = "okay"; - + /* PCIe Switch */ pcie-switch@58 { compatible = "plx,pex8605"; reg = <0x58>; }; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -/* - * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier - * board) - */ -&i2c3 { - status = "okay"; }; &pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_moci>; - /* active-high meaning opposite of regular PERST# active-low polarity */ - reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - reset-gpio-active-high; vpcie-supply = <®_pcie_switch>; status = "okay"; }; -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -®_usb_host_vbus { - status = "okay"; -}; - -®_usb_otg_vbus { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - &sound_spdif { status = "okay"; }; -&spdif { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&uart5 { - status = "okay"; -}; - -&usbh1 { - disable-over-current; - vbus-supply = <®_usb_host_vbus>; - status = "okay"; -}; - -&usbotg { - disable-over-current; - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; -}; - /* MMC1 */ &usdhc1 { status = "okay"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dtsi new file mode 100644 index 000000000000..b6c45ad3f430 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2014-2024 Toradex + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx6q.dtsi" +#include "imx6qdl-apalis.dtsi" + +/ { + aliases { + i2c0 = &i2c1; + i2c1 = &i2c3; + i2c2 = &i2c2; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_3v3_sw: regulator-3v3-sw { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_SW"; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* + * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier + * board) + */ +&i2c3 { + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; + /* active-high meaning opposite of regular PERST# active-low polarity */ + reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + reset-gpio-active-high; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +®_usb_otg_vbus { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbh1 { + disable-over-current; + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + disable-over-current; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts index db8c332df6a1..cad112e05475 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts @@ -227,7 +227,6 @@ #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <1>; bridge@2,1 { compatible = "pci10b5,8605"; @@ -235,7 +234,6 @@ #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <1>; /* Intel Corporation I210 Gigabit Network Connection */ ethernet@3,0 { @@ -250,7 +248,6 @@ #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <1>; /* Intel Corporation I210 Gigabit Network Connection */ switch_nic: ethernet@4,0 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi index 99f4f6ac71d4..c1ae7c47b442 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi @@ -245,6 +245,7 @@ reg = <0x74>; gpio-controller; #gpio-cells = <2>; + #interrupt-cells = <2>; interrupt-controller; interrupt-parent = <&gpio2>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; @@ -390,7 +391,6 @@ #address-cells = <3>; #size-cells = <2>; - #interrupt-cells = <1>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi index 2ae93f57fe5a..ea40623d12e5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi @@ -626,7 +626,6 @@ blocks = <0x5>; id = <0>; interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; interrupt-parent = <&gpio4>; irq-trigger = <0x1>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi index 55c90f6393ad..d3a7a6eeb8e0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi @@ -550,7 +550,6 @@ blocks = <0x5>; interrupts = <20 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio6>; - interrupt-controller; id = <0>; irq-trigger = <0x1>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi index a63e73adc1fc..42b2ba23aefc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi @@ -225,7 +225,6 @@ pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio2>; interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; onkey { compatible = "dlg,da9063-onkey"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi index bfade7149080..a955c77cd499 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi @@ -41,6 +41,11 @@ #include <dt-bindings/sound/fsl-imx-audmux.h> / { + aliases { + rtc0 = &carrier_rtc; + rtc1 = &snvs_rtc; + }; + /* Will be filled by the bootloader */ memory@10000000 { device_type = "memory"; @@ -187,7 +192,7 @@ status = "okay"; /* Pro baseboard model */ - rtc@68 { + carrier_rtc: rtc@68 { compatible = "nxp,pcf8523"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2.dtsi index 0883ef99cded..e6017f9bf640 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2.dtsi @@ -41,6 +41,11 @@ #include <dt-bindings/sound/fsl-imx-audmux.h> / { + aliases { + rtc0 = &pcf8523; + rtc1 = &snvs_rtc; + }; + /* Will be filled by the bootloader */ memory@10000000 { device_type = "memory"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi index 113974520d54..c0c47adc5866 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi @@ -124,6 +124,7 @@ reg = <0x58>; interrupt-parent = <&gpio2>; interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */ + #interrupt-cells = <2>; interrupt-controller; regulators { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi index 86b4269e0e01..85e278eb2016 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi @@ -100,6 +100,7 @@ interrupt-parent = <&gpio1>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; + #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi index 2731faede1cb..d59d5d0e1d19 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi @@ -13,10 +13,14 @@ aliases { can0 = &can1; can1 = &can2; + ethernet0 = &fec; + ethernet1 = &lan1; + ethernet2 = &lan2; mdio-gpio0 = &mdio; nand = &gpmi; rtc0 = &i2c_rtc; rtc1 = &snvs; + switch0 = &switch; usb0 = &usbh1; usb1 = &usbotg; }; @@ -60,7 +64,7 @@ gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>, <&gpio1 22 GPIO_ACTIVE_HIGH>; - switch@0 { + switch: switch@0 { compatible = "microchip,ksz8873"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_switch>; @@ -73,13 +77,13 @@ #address-cells = <1>; #size-cells = <0>; - ports@0 { + lan1: ports@0 { reg = <0>; phy-mode = "internal"; label = "lan1"; }; - ports@1 { + lan2: ports@1 { reg = <1>; phy-mode = "internal"; label = "lan2"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi index 81142c523fa8..8431b8a994f4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi @@ -1158,7 +1158,7 @@ status = "disabled"; }; - weim: weim@21b8000 { + weim: memory-controller@21b8000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx6q-weim"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts index 815119c12bd4..5636fb3661e8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts @@ -141,8 +141,10 @@ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; vdd-supply = <&ldo1_reg>; reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - x-size = <1072>; - y-size = <1448>; + touchscreen-size-x = <1072>; + touchscreen-size-y = <1448>; + touchscreen-swapped-x-y; + touchscreen-inverted-x; }; /* TODO: TPS65185 PMIC for E Ink at 0x68 */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi index 28111efb19a6..6aa61235e39e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi @@ -949,7 +949,7 @@ clocks = <&clks IMX6SL_CLK_DUMMY>; }; - weim: weim@21b8000 { + weim: memory-controller@21b8000 { #address-cells = <2>; #size-cells = <1>; reg = <0x021b8000 0x4000>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi index df3a375f0a3e..0de359d62a47 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi @@ -1107,7 +1107,7 @@ status = "disabled"; }; - weim: weim@21b8000 { + weim: memory-controller@21b8000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi index 2ac40d69425b..f10f0525490b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi @@ -321,7 +321,7 @@ &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; measure-delay-time = <0xffff>; pre-charge-time = <0xfff>; status = "okay"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts index 875ae699c5cb..2ca18f3dad0a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts @@ -203,7 +203,7 @@ &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; }; &sai2 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi index 18cac19aa9b0..af337f18a266 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi @@ -156,7 +156,7 @@ &tsc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; measure-delay-time = <0xffff>; pre-charge-time = <0xffff>; status = "okay"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi index a27a7554c2e7..235aa676618b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi @@ -370,7 +370,7 @@ }; }; - tsc: tsc@2040000 { + tsc: touchscreen@2040000 { compatible = "fsl,imx6ul-tsc"; reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, @@ -538,6 +538,8 @@ fsl,num-rx-queues = <1>; fsl,stop-mode = <&gpr 0x10 4>; fsl,magic-packet; + nvmem-cells = <&fec2_mac_addr>; + nvmem-cell-names = "mac-address"; status = "disabled"; }; @@ -638,6 +640,7 @@ nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; nvmem-cell-names = "calib", "temp_grade"; clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; + #thermal-sensor-cells = <0>; }; }; @@ -855,7 +858,6 @@ clocks = <&clks IMX6UL_CLK_USBOH3>; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc 0>; - fsl,anatop = <&anatop>; ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; @@ -897,6 +899,8 @@ fsl,num-rx-queues = <1>; fsl,stop-mode = <&gpr 0x10 3>; fsl,magic-packet; + nvmem-cells = <&fec1_mac_addr>; + nvmem-cell-names = "mac-address"; status = "disabled"; }; @@ -975,7 +979,7 @@ clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; }; - weim: weim@21b8000 { + weim: memory-controller@21b8000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; @@ -1004,6 +1008,14 @@ cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + fec1_mac_addr: mac-addr@88 { + reg = <0x88 6>; + }; + + fec2_mac_addr: mac-addr@8e { + reg = <0x8e 6>; + }; }; csi: csi@21c4000 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi index 040421f9c970..5e39f8dc1351 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi @@ -14,10 +14,12 @@ */ /* - * To use usdhc1 as SD card, the WiFi node must be deleted. + * To use usdhc1 as SD card, the WiFi node must be deleted. The associated + * pwrseq node is also deleted in order to ensure that GPIO H is released. * BT is also not available, so remove BT from the UART node. */ /delete-node/ &brcmf; +/delete-node/ &usdhc1_pwrseq; /delete-node/ &bluetooth; / { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som.dtsi index 830b5a5064f2..a74f5273f9b3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som.dtsi @@ -52,7 +52,7 @@ }; /* SoM with WiFi/BT: WiFi pin WL_REG_ON is connected to a DHCOM GPIO */ - /omit-if-no-ref/ usdhc1_pwrseq: usdhc1-pwrseq { + usdhc1_pwrseq: usdhc1-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; /* GPIO H */ }; @@ -273,7 +273,7 @@ pinctrl-names = "default"; pre-charge-time = <0xfff>; touchscreen-average-samples = <32>; - xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; }; /* DHCOM UART1 */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi index 45315adfaa86..75486e1b0c15 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi @@ -28,10 +28,14 @@ /* * Due to the design as a solderable SOM, there are no capacitors * below the SoC, therefore higher voltages are required. + * Due to CPU lifetime consideration of the SoC manufacturer and + * the preferred area of operation in the industrial related + * environment, set the maximum frequency for each DHCOM i.MX6ULL + * to 792MHz, as with the industrial type. */ + clock-frequency = <792000000>; operating-points = < /* kHz uV */ - 900000 1275000 792000 1250000 /* Voltage increased */ 528000 1175000 396000 1025000 @@ -39,7 +43,6 @@ >; fsl,soc-operating-points = < /* KHz uV */ - 900000 1250000 792000 1250000 /* Voltage increased */ 528000 1175000 396000 1175000 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi index 44cc4ff1d0df..d12fb44aeb14 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi @@ -116,7 +116,7 @@ tpm_tis: tpm@1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tpm>; - compatible = "tcg,tpm_tis-spi"; + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <1>; spi-max-frequency = <20000000>; interrupt-parent = <&gpio5>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi index 2bccd45e9fc2..8a1776067ecc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi @@ -75,7 +75,7 @@ clocks = <&clks IMX6UL_CLK_DUMMY>; }; - iomuxc_snvs: iomuxc-snvs@2290000 { + iomuxc_snvs: pinctrl@2290000 { compatible = "fsl,imx6ull-iomuxc-snvs"; reg = <0x02290000 0x4000>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi index 3df6dff7734a..1235a71c6abe 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi @@ -18,6 +18,8 @@ mmc0 = &usdhc3; mmc1 = &usdhc1; /delete-property/ mmc2; + rtc0 = &ds1339; + rtc1 = &snvs_rtc; }; beeper { @@ -32,11 +34,18 @@ gpio_buttons: gpio-keys { compatible = "gpio-keys"; + /* + * NOTE: These buttons are attached to a GPIO-expander. + * Enabling wakeup-source, enables wakeup on all inputs. + * If PE_GPIO[3..6] are used as inputs, they cause a + * wakeup as well. + */ button-0 { /* #SWITCH_A */ label = "S11"; linux,code = <KEY_1>; gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; + wakeup-source; }; button-1 { @@ -44,6 +53,7 @@ label = "S12"; linux,code = <KEY_2>; gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + wakeup-source; }; button-2 { @@ -51,6 +61,7 @@ label = "S13"; linux,code = <KEY_3>; gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; @@ -171,6 +182,14 @@ regulator-always-on; }; + reg_vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + sound { compatible = "fsl,imx-audio-tlv320aic32x4"; model = "imx-audio-tlv320aic32x4"; @@ -198,9 +217,9 @@ &ecspi1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_ss0>; cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>, - <&gpio4 2 GPIO_ACTIVE_LOW>; + <&gpio4 2 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -214,8 +233,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; phy-supply = <®_fec1_pwdn>; phy-handle = <ðphy1_0>; fsl,magic-packet; @@ -228,10 +245,15 @@ ethphy1_0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_phy>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <500>; }; }; }; @@ -290,13 +312,17 @@ lm75: temperature-sensor@49 { compatible = "national,lm75"; reg = <0x49>; + vs-supply = <®_vcc_3v3>; }; }; &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_recovery>; + scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; tlv320aic32x4: audio-codec@18 { @@ -319,13 +345,17 @@ interrupts = <12 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; + vcc-supply = <®_vcc_3v3>; }; }; &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_recovery>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -334,213 +364,213 @@ pinctrl-0 = <&pinctrl_hog_mba7_1>; pinctrl_ecspi1: ecspi1grp { + fsl,pins = + <MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c>, + <MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74>, + <MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74>, + <MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74>, + <MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74>, + <MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74>; + }; + + pinctrl_ecspi1_ss0: ecspi1ss0grp { fsl,pins = < - MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c - MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74 - MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74 - MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74 - MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74 - MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74 + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x74 >; }; pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c - MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74 - MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74 - MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74 - >; + fsl,pins = + <MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c>, + <MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74>, + <MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74>, + <MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74>; }; pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02 - MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79 + fsl,pins = + <MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02>, + <MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00>, + <MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71>, + <MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71>, + <MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71>, + <MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71>, + <MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71>, + <MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71>, + <MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79>, + <MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79>, + <MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79>, + <MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79>, + <MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79>, + <MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79>; + }; + + pinctrl_enet1_phy: enet1phygrp { + fsl,pins = /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ - MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070 + <MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070>, /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078 - >; + <MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078>; }; pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a - MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52 - >; + fsl,pins = + <MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a>, + <MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52>; }; pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52 - >; + fsl,pins = + <MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a>, + <MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52>; }; pinctrl_hog_mba7_1: hogmba71grp { - fsl,pins = < + fsl,pins = /* Limitation: WDOG2_B / WDOG2_RESET not usable */ - MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c - MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074 + <MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c>, + <MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074>, /* #BOOT_EN */ - MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010 - >; + <MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010>; }; pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078 - MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078 - >; + fsl,pins = + <MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078>, + <MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078>; + }; + + pinctrl_i2c2_recovery: i2c2recoverygrp { + fsl,pins = + <MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x40000078>, + <MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x40000078>; }; pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078 - MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078 - >; + fsl,pins = + <MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078>, + <MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078>; + }; + + pinctrl_i2c3_recovery: i2c3recoverygrp { + fsl,pins = + <MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x40000078>, + <MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x40000078>; }; pinctrl_pca9555: pca95550grp { - fsl,pins = < - MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78 - >; + fsl,pins = + <MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78>; }; pinctrl_sai1: sai1grp { - fsl,pins = < - MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11 - MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c - MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c - MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c - - MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c - MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14 - MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14 - >; + fsl,pins = + <MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11>, + <MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c>, + <MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c>, + <MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c>, + + <MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c>, + <MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14>, + <MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14>; }; pinctrl_uart3: uart3grp { - fsl,pins = < - MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e - MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76 - MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76 - MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e - >; + fsl,pins = + <MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e>, + <MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76>, + <MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76>, + <MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e>; }; pinctrl_uart4: uart4grp { - fsl,pins = < - MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e - MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76 - MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76 - MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e - >; + fsl,pins = + <MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e>, + <MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76>, + <MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76>, + <MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e>; }; pinctrl_uart5: uart5grp { - fsl,pins = < - MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e - MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76 - >; + fsl,pins = + <MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e>, + <MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76>; }; pinctrl_uart6: uart6grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d - MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75 - MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75 - MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d - >; + fsl,pins = + <MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d>, + <MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75>, + <MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75>, + <MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d>; }; pinctrl_uart7: uart7grp { - fsl,pins = < - MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e - MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76 - MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76 + fsl,pins = + <MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e>, + <MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76>, + <MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76>, /* Limitation: RTS is not connected */ - MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e - >; + <MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e>; }; - pinctrl_usdhc1_gpio: usdhc1grp_gpio { - fsl,pins = < + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = /* WP */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c + <MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c>, /* CD */ - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c + <MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c>, /* VSELECT */ - MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 - >; + <MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59>; }; pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5e - MX7D_PAD_SD1_CLK__SD1_CLK 0x57 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x57 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x57 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b - >; + fsl,pins = + <MX7D_PAD_SD1_CMD__SD1_CMD 0x5e>, + <MX7D_PAD_SD1_CLK__SD1_CLK 0x57>, + <MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e>, + <MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e>, + <MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e>, + <MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e>; + }; + + pinctrl_usdhc1_100mhz: usdhc1_100mhzgrp { + fsl,pins = + <MX7D_PAD_SD1_CMD__SD1_CMD 0x5a>, + <MX7D_PAD_SD1_CLK__SD1_CLK 0x57>, + <MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a>, + <MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a>, + <MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a>, + <MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a>; + }; + + pinctrl_usdhc1_200mhz: usdhc1_200mhzgrp { + fsl,pins = + <MX7D_PAD_SD1_CMD__SD1_CMD 0x5b>, + <MX7D_PAD_SD1_CLK__SD1_CLK 0x57>, + <MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b>, + <MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b>, + <MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b>, + <MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b>; }; }; &iomuxc_lpsr { pinctrl_pwm1: pwm1grp { - fsl,pins = < + fsl,pins = /* LCD_CONTRAST */ - MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50 - >; + <MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50>; }; pinctrl_usbotg1: usbotg1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c - MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 - >; + fsl,pins = + <MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c>, + <MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59>; }; pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 - >; + fsl,pins = + <MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30>; }; }; @@ -560,6 +590,10 @@ status = "okay"; }; +&snvs_pwrkey { + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; @@ -605,6 +639,7 @@ }; &usbh { + disable-over-current; status = "okay"; }; @@ -630,6 +665,8 @@ vmmc-supply = <®_sd1_vmmc>; bus-width = <4>; no-1-8-v; + no-sdio; + no-emmc; status = "okay"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi index 3fc3130f9def..028961eb7108 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi @@ -30,8 +30,11 @@ }; &i2c1 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_recovery>; + scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; status = "okay"; @@ -109,7 +112,7 @@ }; vgen4_reg: v33 { - regulator-min-microvolt = <2850000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; @@ -135,7 +138,7 @@ }; /* NXP SE97BTP with temperature sensor + eeprom, TQMa7x 02xx */ - se97b: temperature-sensor-eeprom@1e { + se97b: temperature-sensor@1e { compatible = "nxp,se97b", "jedec,jc-42.4-temp"; reg = <0x1e>; }; @@ -143,15 +146,18 @@ /* ST M24C64 */ m24c64: eeprom@50 { compatible = "atmel,24c64"; + read-only; reg = <0x50>; pagesize = <32>; + vcc-supply = <&vgen4_reg>; status = "okay"; }; at24c02: eeprom@56 { - compatible = "atmel,24c02"; + compatible = "nxp,se97b", "atmel,24c02"; reg = <0x56>; pagesize = <16>; + vcc-supply = <&vgen4_reg>; status = "okay"; }; @@ -163,91 +169,89 @@ &iomuxc { pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078 - MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078 - >; + fsl,pins = + <MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078>, + <MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078>; + }; + + pinctrl_i2c1_recovery: i2c1recoverygrp { + fsl,pins = + <MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x40000078>, + <MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x40000078>; }; pinctrl_pmic1: pmic1grp { - fsl,pins = < - MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C - >; + fsl,pins = + <MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C>; }; pinctrl_qspi: qspigrp { - fsl,pins = < - MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A - MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A - MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A - MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A - MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11 - MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54 - MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54 - >; + fsl,pins = + <MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A>, + <MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A>, + <MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A>, + <MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A>, + <MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11>, + <MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54>, + <MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54>; }; pinctrl_qspi_reset: qspi_resetgrp { - fsl,pins = < + fsl,pins = /* #QSPI_RESET */ - MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52 - >; + <MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52>; }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x59 - MX7D_PAD_SD3_CLK__SD3_CLK 0x56 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 - >; + fsl,pins = + <MX7D_PAD_SD3_CMD__SD3_CMD 0x59>, + <MX7D_PAD_SD3_CLK__SD3_CLK 0x56>, + <MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59>, + <MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59>, + <MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59>, + <MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59>, + <MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59>, + <MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59>, + <MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59>, + <MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59>, + <MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19>; }; - pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5a - MX7D_PAD_SD3_CLK__SD3_CLK 0x51 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a - >; + pinctrl_usdhc3_100mhz: usdhc3_100mhzgrp { + fsl,pins = + <MX7D_PAD_SD3_CMD__SD3_CMD 0x5a>, + <MX7D_PAD_SD3_CLK__SD3_CLK 0x51>, + <MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a>, + <MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a>, + <MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a>, + <MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a>, + <MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a>, + <MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a>, + <MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a>, + <MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a>, + <MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a>; }; - pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { - fsl,pins = < - MX7D_PAD_SD3_CMD__SD3_CMD 0x5b - MX7D_PAD_SD3_CLK__SD3_CLK 0x51 - MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b - MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b - MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b - MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b - MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b - MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b - MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b - MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b - MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b - >; + pinctrl_usdhc3_200mhz: usdhc3_200mhzgrp { + fsl,pins = + <MX7D_PAD_SD3_CMD__SD3_CMD 0x5b>, + <MX7D_PAD_SD3_CLK__SD3_CLK 0x51>, + <MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b>, + <MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b>, + <MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b>, + <MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b>, + <MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b>, + <MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b>, + <MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b>, + <MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b>, + <MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b>; }; }; &iomuxc_lpsr { pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 - >; + fsl,pins = + <MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30>; }; }; @@ -265,10 +269,6 @@ }; }; -&sdma { - status = "okay"; -}; - &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -278,6 +278,8 @@ assigned-clock-rates = <400000000>; bus-width = <8>; non-removable; + no-sd; + no-sdio; vmmc-supply = <&vgen4_reg>; vqmmc-supply = <&sw2_reg>; status = "okay"; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator.dts b/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator.dts index 3a723843d562..9984b343cdf0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator.dts @@ -130,7 +130,7 @@ * TCG specification - Section 6.4.1 Clocking: * TPM shall support a SPI clock frequency range of 10-24 MHz. */ - st33htph: tpm-tis@0 { + st33htph: tpm@0 { compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <24000000>; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts index 32bf9fa9d00e..0443faa3dfae 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts @@ -21,8 +21,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; phy-supply = <®_fec2_pwdn>; phy-handle = <ðphy2_0>; fsl,magic-packet; @@ -35,59 +33,85 @@ ethphy2_0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_phy>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <500>; }; }; }; +&gpio2 { + pcie-dis-hog { + gpio-hog; + gpios = <29 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "pcie-dis"; + }; + + pcie-rst-hog { + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "pcie-rst"; + }; +}; + &iomuxc { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_mba7_1>; + pinctrl-0 = <&pinctrl_hog_mba7_1>, <&pinctrl_hog_pcie>; pinctrl_enet2: enet2grp { - fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02 - MX7D_PAD_SD2_WP__ENET2_MDC 0x00 - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71 - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71 - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71 - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71 - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71 - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71 - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79 - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79 - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79 - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79 - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79 - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79 + fsl,pins = + <MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02>, + <MX7D_PAD_SD2_WP__ENET2_MDC 0x00>, + <MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71>, + <MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71>, + <MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71>, + <MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71>, + <MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71>, + <MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71>, + <MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79>, + <MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79>, + <MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79>, + <MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79>, + <MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79>, + <MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79>; + }; + + pinctrl_enet2_phy: enet2phygrp { + fsl,pins = /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070 + <MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070>, /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ - MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078 - >; + <MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078>; }; - pinctrl_pcie: pciegrp { - fsl,pins = < - /* #pcie_wake */ - MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70 + pinctrl_hog_pcie: hogpciegrp { + fsl,pins = /* #pcie_rst */ - MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70 + <MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70>, /* #pcie_dis */ - MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70 - >; + <MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70>; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = + /* #pcie_wake */ + <MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70>; }; }; &iomuxc_lpsr { pinctrl_usbotg2: usbotg2grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c - MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 - >; + fsl,pins = + <MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c>, + <MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59>; }; }; @@ -98,16 +122,14 @@ /* probe deferral not supported */ /* pcie-bus-supply = <®_mpcie_1v5>; */ reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; - status = "okay"; + status = "disabled"; }; &usbotg2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg2>; vbus-supply = <®_usb_otg2_vbus>; - srp-disable; - hnp-disable; - adp-disable; + disable-over-current; dr_mode = "host"; status = "okay"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts index 12361fcbe24a..1b965652291b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts @@ -63,6 +63,7 @@ gpio-controller; #gpio-cells = <2>; #interrupt-cells = <2>; + interrupt-controller; reg = <0x25>; }; diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi index d471cc5efa94..e86998ca77d6 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi @@ -808,7 +808,9 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; snps,dis_rxdet_inp3_quirk; + usb3-lpm-capable; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + snps,host-vbus-glitches; }; pcie@3400000 { diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts b/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts index 9ebb7371e235..330d3aff6b6c 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts @@ -198,7 +198,7 @@ clocks = <&saif0>; }; - at24@51 { + eeprom@51 { compatible = "atmel,24c32"; pagesize = <32>; reg = <0x51>; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts index b0ed68af0546..029f49be40e3 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts @@ -338,6 +338,7 @@ reg = <0x22>; gpio-controller; #gpio-cells = <2>; + #interrupt-cells = <2>; interrupt-controller; interrupt-parent = <&gpio3>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 2045fc779f88..c1ab65f43cb8 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -340,10 +340,10 @@ "msi8"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_PIPE_CLK>, <&gcc GCC_PCIE_AUX_CLK>, @@ -580,12 +580,16 @@ <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 51 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc 11 IRQ_TYPE_EDGE_BOTH>, - <&pdc 10 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + <&pdc 51 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc USB30_GDSC>; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 40591a4da6a4..2b8635f0e38d 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -501,14 +501,16 @@ <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 19 IRQ_TYPE_EDGE_BOTH>, <&pdc 18 IRQ_TYPE_EDGE_BOTH>, - <&pdc 19 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 76 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc USB30_GDSC>; diff --git a/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts index ed75c01dbee1..3d02f065f71c 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts @@ -209,6 +209,18 @@ status = "okay"; }; +&extal1_clk { + clock-frequency = <26000000>; +}; + +&extal2_clk { + clock-frequency = <48000000>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + &pfc { scifa0_pins: scifa0 { groups = "scifa0_data"; diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi index c39066967053..ac654ff45d0e 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4.dtsi +++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi @@ -450,17 +450,20 @@ extalr_clk: extalr { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; extal1_clk: extal1 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <25000000>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; extal2_clk: extal2 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <48000000>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; fsiack_clk: fsiack { compatible = "fixed-clock"; @@ -621,6 +624,13 @@ clock-div = <2>; clock-mult = <1>; }; + cp_clk: cp { + compatible = "fixed-factor-clock"; + clocks = <&main_div2_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; pll0_div2_clk: pll0_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; @@ -686,9 +696,8 @@ mstp4_clks: mstp4_clks@e6150140 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, - <&main_div2_clk>, - <&cpg_clocks R8A73A4_CLK_HP>, + clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, + <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks R8A73A4_CLK_HP>; #clock-cells = <1>; clock-indices = < @@ -702,7 +711,7 @@ mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; + clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; #clock-cells = <1>; clock-indices = < R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi index 55884ec701f8..d13ab86c3ab4 100644 --- a/arch/arm/boot/dts/renesas/r8a7740.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi @@ -459,6 +459,7 @@ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp1_clks R8A7740_CLK_TMU0>; clock-names = "fck"; power-domains = <&pd_a4r>; @@ -474,6 +475,7 @@ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp1_clks R8A7740_CLK_TMU1>; clock-names = "fck"; power-domains = <&pd_a4r>; diff --git a/arch/arm/boot/dts/renesas/r8a7778.dtsi b/arch/arm/boot/dts/renesas/r8a7778.dtsi index 8d4530ed2fc6..b80e832c9277 100644 --- a/arch/arm/boot/dts/renesas/r8a7778.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7778.dtsi @@ -199,7 +199,9 @@ reg = <0xffd80000 0x30>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7778_CLK_TMU0>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -214,7 +216,9 @@ reg = <0xffd81000 0x30>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7778_CLK_TMU1>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -230,6 +234,7 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp0_clks R8A7778_CLK_TMU2>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -250,6 +255,8 @@ reg = <0xffd90000 0x1000>, /* SRU */ <0xffd91000 0x240>, /* SSI */ <0xfffe0000 0x24>; /* ADG */ + reg-names = "sru", "ssi", "adg"; + clocks = <&mstp3_clks R8A7778_CLK_SSI8>, <&mstp3_clks R8A7778_CLK_SSI7>, <&mstp3_clks R8A7778_CLK_SSI6>, diff --git a/arch/arm/boot/dts/renesas/r8a7779.dtsi b/arch/arm/boot/dts/renesas/r8a7779.dtsi index 7743af5e2a6f..1944703cba4f 100644 --- a/arch/arm/boot/dts/renesas/r8a7779.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7779.dtsi @@ -402,7 +402,9 @@ reg = <0xffd80000 0x30>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7779_CLK_TMU0>; clock-names = "fck"; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; @@ -417,7 +419,9 @@ reg = <0xffd81000 0x30>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7779_CLK_TMU1>; clock-names = "fck"; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; @@ -433,6 +437,7 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp0_clks R8A7779_CLK_TMU2>; clock-names = "fck"; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; diff --git a/arch/arm/boot/dts/renesas/r8a7790-lager.dts b/arch/arm/boot/dts/renesas/r8a7790-lager.dts index 2fba4d084001..8590981245a6 100644 --- a/arch/arm/boot/dts/renesas/r8a7790-lager.dts +++ b/arch/arm/boot/dts/renesas/r8a7790-lager.dts @@ -447,6 +447,7 @@ interrupt-parent = <&irqc0>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; + #interrupt-cells = <2>; rtc { compatible = "dlg,da9063-rtc"; diff --git a/arch/arm/boot/dts/renesas/r8a7790-stout.dts b/arch/arm/boot/dts/renesas/r8a7790-stout.dts index f9bc5b4f019d..683f7395fab0 100644 --- a/arch/arm/boot/dts/renesas/r8a7790-stout.dts +++ b/arch/arm/boot/dts/renesas/r8a7790-stout.dts @@ -347,6 +347,7 @@ interrupt-parent = <&irqc0>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; + #interrupt-cells = <2>; onkey { compatible = "dlg,da9063-onkey"; diff --git a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts index e9c13bb03772..0efd9f98c75a 100644 --- a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts @@ -819,6 +819,7 @@ interrupt-parent = <&irqc0>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; + #interrupt-cells = <2>; rtc { compatible = "dlg,da9063-rtc"; diff --git a/arch/arm/boot/dts/renesas/r8a7791-porter.dts b/arch/arm/boot/dts/renesas/r8a7791-porter.dts index 7e8bc06715f6..93c86e921645 100644 --- a/arch/arm/boot/dts/renesas/r8a7791-porter.dts +++ b/arch/arm/boot/dts/renesas/r8a7791-porter.dts @@ -413,6 +413,7 @@ interrupt-parent = <&irqc0>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; + #interrupt-cells = <2>; watchdog { compatible = "dlg,da9063-watchdog"; diff --git a/arch/arm/boot/dts/renesas/r8a7792-blanche.dts b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts index 4f9838cf97ee..540a9ad28f28 100644 --- a/arch/arm/boot/dts/renesas/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts @@ -381,6 +381,7 @@ interrupt-parent = <&irqc>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; + #interrupt-cells = <2>; rtc { compatible = "dlg,da9063-rtc"; diff --git a/arch/arm/boot/dts/renesas/r8a7793-gose.dts b/arch/arm/boot/dts/renesas/r8a7793-gose.dts index 1744fdbf9e0c..1ea6c757893b 100644 --- a/arch/arm/boot/dts/renesas/r8a7793-gose.dts +++ b/arch/arm/boot/dts/renesas/r8a7793-gose.dts @@ -759,6 +759,7 @@ interrupt-parent = <&irqc0>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; + #interrupt-cells = <2>; rtc { compatible = "dlg,da9063-rtc"; diff --git a/arch/arm/boot/dts/renesas/r8a7794-alt.dts b/arch/arm/boot/dts/renesas/r8a7794-alt.dts index c0d067df22a0..b5ecafbb2e4d 100644 --- a/arch/arm/boot/dts/renesas/r8a7794-alt.dts +++ b/arch/arm/boot/dts/renesas/r8a7794-alt.dts @@ -453,6 +453,7 @@ interrupt-parent = <&gpio3>; interrupts = <31 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; + #interrupt-cells = <2>; rtc { compatible = "dlg,da9063-rtc"; diff --git a/arch/arm/boot/dts/renesas/r8a7794-silk.dts b/arch/arm/boot/dts/renesas/r8a7794-silk.dts index 43d480a7f3ea..595e074085eb 100644 --- a/arch/arm/boot/dts/renesas/r8a7794-silk.dts +++ b/arch/arm/boot/dts/renesas/r8a7794-silk.dts @@ -439,6 +439,7 @@ interrupt-parent = <&gpio3>; interrupts = <31 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; + #interrupt-cells = <2>; onkey { compatible = "dlg,da9063-onkey"; diff --git a/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts b/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts index 03a97881519a..21c1678f4e91 100644 --- a/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts +++ b/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts @@ -47,6 +47,17 @@ regulator-boot-on; }; + hdmi-connnector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_connector_out>; + }; + }; + }; + /* * This is a vbus-supply, which also supplies the GL852G usb hub, * thus has to be always-on @@ -239,6 +250,10 @@ cpu-supply = <&vdd_arm>; }; +&display_subsystem { + status = "okay"; +}; + &emmc { bus-width = <8>; vmmc-supply = <&vcc_io>; @@ -328,6 +343,16 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_connector_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + &mdio { phy0: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -423,3 +448,7 @@ &usb2phy_otg { status = "okay"; }; + +&vop { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index e2264c40b924..fb98873fd94e 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -115,6 +115,12 @@ }; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + status = "disabled"; + }; + gpu_opp_table: opp-table-1 { compatible = "operating-points-v2"; @@ -246,6 +252,32 @@ }; }; + vop: vop@1010e000 { + compatible = "rockchip,rk3126-vop"; + reg = <0x1010e000 0x300>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>, + <&cru HCLK_LCDC0>; + clock-names = "aclk_vop", "dclk_vop", + "hclk_vop"; + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, + <&cru SRST_VOP_D>; + reset-names = "axi", "ahb", + "dclk"; + power-domains = <&power RK3128_PD_VIO>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop>; + }; + }; + }; + qos_gpu: qos@1012d000 { compatible = "rockchip,rk3128-qos", "syscon"; reg = <0x1012d000 0x20>; @@ -436,6 +468,34 @@ }; }; + hdmi: hdmi@20034000 { + compatible = "rockchip,rk3128-inno-hdmi"; + reg = <0x20034000 0x4000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_HDMI>, <&cru DCLK_VOP>; + clock-names = "pclk", "ref"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; + power-domains = <&power RK3128_PD_VIO>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + hdmi_in_vop: endpoint { + remote-endpoint = <&vop_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + timer0: timer@20044000 { compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; reg = <0x20044000 0x20>; diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi index 831561fc1814..96421355c274 100644 --- a/arch/arm/boot/dts/rockchip/rk322x.dtsi +++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi @@ -736,14 +736,20 @@ status = "disabled"; ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vop: endpoint@0 { - reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_vop: endpoint { remote-endpoint = <&vop_out_hdmi>; }; }; + + hdmi_out: port@1 { + reg = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi index ead343dc3df1..3f1d640afafa 100644 --- a/arch/arm/boot/dts/rockchip/rk3288.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi @@ -1240,27 +1240,37 @@ compatible = "rockchip,rk3288-dw-hdmi"; reg = <0x0 0xff980000 0x0 0x20000>; reg-io-width = <4>; - #sound-dai-cells = <0>; - rockchip,grf = <&grf>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; clock-names = "iahb", "isfr", "cec"; power-domains = <&power RK3288_PD_VIO>; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; status = "disabled"; ports { - hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; + hdmi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_hdmi>; }; + hdmi_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_hdmi>; }; }; + + hdmi_out: port@1 { + reg = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/rockchip/rv1108.dtsi b/arch/arm/boot/dts/rockchip/rv1108.dtsi index abf3006f0a84..f3291f3bbc6f 100644 --- a/arch/arm/boot/dts/rockchip/rv1108.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1108.dtsi @@ -196,7 +196,6 @@ pwm4: pwm@10280000 { compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; reg = <0x10280000 0x10>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; clock-names = "pwm", "pclk"; pinctrl-names = "default"; @@ -208,7 +207,6 @@ pwm5: pwm@10280010 { compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; reg = <0x10280010 0x10>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; clock-names = "pwm", "pclk"; pinctrl-names = "default"; @@ -220,7 +218,6 @@ pwm6: pwm@10280020 { compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; reg = <0x10280020 0x10>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; clock-names = "pwm", "pclk"; pinctrl-names = "default"; @@ -232,7 +229,6 @@ pwm7: pwm@10280030 { compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; reg = <0x10280030 0x10>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; clock-names = "pwm", "pclk"; pinctrl-names = "default"; @@ -386,7 +382,6 @@ pwm0: pwm@20040000 { compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; reg = <0x20040000 0x10>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; clock-names = "pwm", "pclk"; pinctrl-names = "default"; @@ -398,7 +393,6 @@ pwm1: pwm@20040010 { compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; reg = <0x20040010 0x10>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; clock-names = "pwm", "pclk"; pinctrl-names = "default"; @@ -410,7 +404,6 @@ pwm2: pwm@20040020 { compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; reg = <0x20040020 0x10>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; clock-names = "pwm", "pclk"; pinctrl-names = "default"; @@ -422,7 +415,6 @@ pwm3: pwm@20040030 { compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; reg = <0x20040030 0x10>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; clock-names = "pwm", "pclk"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi index d7954ff466b4..e5254e32aa8f 100644 --- a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi @@ -434,6 +434,7 @@ }; &fimd { + samsung,invert-vclk; status = "okay"; }; diff --git a/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi b/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi index 0b89d5682f85..39a3d1cbe4c3 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4412-p4note.dtsi @@ -362,6 +362,39 @@ status = "okay"; }; +&i2c_1 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c1_bus>; + pinctrl-names = "default"; + status = "okay"; + + accelerometer@19 { + compatible = "st,lsm330dlc-accel"; + reg = <0x19>; + interrupt-parent = <&gpx0>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 = <&accelerometer_irq>; + pinctrl-names = "default"; + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; + + gyro@6b { + compatible = "st,lsm330dlc-gyro"; + reg = <0x6b>; + interrupt-parent = <&gpx0>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 = <&gyro_data_enable &gyro_irq>; + pinctrl-names = "default"; + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; + }; +}; + &i2c_3 { samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; @@ -844,6 +877,12 @@ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; + gyro_data_enable: gyro-data-enable-pins { + samsung,pins = "gpl2-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + }; + uart_sel: uart-sel-pins { samsung,pins = "gpl2-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; @@ -894,12 +933,24 @@ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; }; + accelerometer_irq: accelerometer-irq-pins { + samsung,pins = "gpx0-0"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + stmpe_adc_irq: stmpe-adc-irq-pins { samsung,pins = "gpx0-1"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; }; + gyro_irq: gyro-irq-pins { + samsung,pins = "gpx0-6"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + max77686_irq: max77686-irq-pins { samsung,pins = "gpx0-7"; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; diff --git a/arch/arm/boot/dts/samsung/exynos5420-galaxy-tab-common.dtsi b/arch/arm/boot/dts/samsung/exynos5420-galaxy-tab-common.dtsi index f525b2f5e4e0..246040967082 100644 --- a/arch/arm/boot/dts/samsung/exynos5420-galaxy-tab-common.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5420-galaxy-tab-common.dtsi @@ -30,6 +30,7 @@ aliases { mmc0 = &mmc_0; + mmc1 = &mmc_1; mmc2 = &mmc_2; }; @@ -39,7 +40,7 @@ memory@20000000 { device_type = "memory"; - reg = <0x20000000 0xc0000000>; + reg = <0x20000000 0xbfa00000>; }; firmware@2073000 { @@ -87,6 +88,13 @@ linux,code = <KEY_VOLUMEDOWN>; }; }; + + mmc1_pwrseq: pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpy7 7 GPIO_ACTIVE_LOW>; + clocks = <&s2mps11_osc S2MPS11_CLK_BT>; + clock-names = "ext_clock"; + }; }; &cci { @@ -620,6 +628,25 @@ vqmmc-supply = <&ldo3_reg>; }; +/* WiFi */ +&mmc_1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + card-detect-delay = <200>; + keep-power-in-suspend; + mmc-pwrseq = <&mmc1_pwrseq>; + non-removable; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>, + <&sd1_bus4>, <&wifi_en>; + pinctrl-names = "default"; + vqmmc-supply = <&ldo2_reg>; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-sdr-timing = <0 1>; + status = "okay"; +}; + /* External sdcard */ &mmc_2 { status = "okay"; @@ -649,6 +676,11 @@ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; }; + + wifi_en: wifi-en-pins { + samsung,pins = "gpy7-7"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; }; &rtc { diff --git a/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts b/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts index 4e757b6e28e1..3759742d38ca 100644 --- a/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts @@ -967,6 +967,7 @@ reg = <0>; spi-max-frequency = <3125000>; google,has-vbc-nvram; + wakeup-source; controller-data { samsung,spi-feedback-delay = <1>; diff --git a/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-common.dtsi index b4a851aa8881..4a4c55a4beb3 100644 --- a/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-common.dtsi @@ -55,7 +55,7 @@ thermal-zones { cpu0_thermal: cpu0-thermal { thermal-sensors = <&tmu_cpu0>; - polling-delay-passive = <250>; + polling-delay-passive = <0>; polling-delay = <0>; trips { cpu0_alert0: cpu-alert-0 { @@ -78,12 +78,6 @@ hysteresis = <0>; /* millicelsius */ type = "critical"; }; - /* - * Exynos542x supports only 4 trip-points - * so for these polling mode is required. - * Start polling at temperature level of last - * interrupt-driven trip: cpu0_alert2 - */ cpu0_alert3: cpu-alert-3 { temperature = <70000>; /* millicelsius */ hysteresis = <10000>; /* millicelsius */ @@ -144,7 +138,7 @@ }; cpu1_thermal: cpu1-thermal { thermal-sensors = <&tmu_cpu1>; - polling-delay-passive = <250>; + polling-delay-passive = <0>; polling-delay = <0>; trips { cpu1_alert0: cpu-alert-0 { @@ -217,7 +211,7 @@ }; cpu2_thermal: cpu2-thermal { thermal-sensors = <&tmu_cpu2>; - polling-delay-passive = <250>; + polling-delay-passive = <0>; polling-delay = <0>; trips { cpu2_alert0: cpu-alert-0 { @@ -290,7 +284,7 @@ }; cpu3_thermal: cpu3-thermal { thermal-sensors = <&tmu_cpu3>; - polling-delay-passive = <250>; + polling-delay-passive = <0>; polling-delay = <0>; trips { cpu3_alert0: cpu-alert-0 { @@ -363,7 +357,7 @@ }; gpu_thermal: gpu-thermal { thermal-sensors = <&tmu_gpu>; - polling-delay-passive = <250>; + polling-delay-passive = <0>; polling-delay = <0>; trips { gpu_alert0: gpu-alert-0 { diff --git a/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts b/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts index f91bc4ae008e..9bbbdce9103a 100644 --- a/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts @@ -949,6 +949,7 @@ reg = <0>; spi-max-frequency = <3125000>; google,has-vbc-nvram; + wakeup-source; controller-data { samsung,spi-feedback-delay = <1>; diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index 7892ad69b441..9fedd6776208 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -23,6 +23,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32f469-disco.dtb \ stm32f746-disco.dtb \ stm32f769-disco.dtb \ + stm32f769-disco-mb1166-reva09.dtb \ stm32429i-eval.dtb \ stm32746g-eval.dtb \ stm32h743i-eval.dtb \ diff --git a/arch/arm/boot/dts/st/stih407-pinctrl.dtsi b/arch/arm/boot/dts/st/stih407-pinctrl.dtsi index 7815669fe813..dcb821f567fa 100644 --- a/arch/arm/boot/dts/st/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stih407-pinctrl.dtsi @@ -462,14 +462,14 @@ serial0 { pinctrl_serial0: serial0-0 { st,pins { - tx = <&pio17 0 ALT1 OUT>; - rx = <&pio17 1 ALT1 IN>; + tx = <&pio17 0 ALT1 OUT>; + rx = <&pio17 1 ALT1 IN>; }; }; pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl { st,pins { - tx = <&pio17 0 ALT1 OUT>; - rx = <&pio17 1 ALT1 IN>; + tx = <&pio17 0 ALT1 OUT>; + rx = <&pio17 1 ALT1 IN>; cts = <&pio17 2 ALT1 IN>; rts = <&pio17 3 ALT1 OUT>; }; diff --git a/arch/arm/boot/dts/st/stm32429i-eval.dts b/arch/arm/boot/dts/st/stm32429i-eval.dts index 576235ec3c51..afa417b34b25 100644 --- a/arch/arm/boot/dts/st/stm32429i-eval.dts +++ b/arch/arm/boot/dts/st/stm32429i-eval.dts @@ -222,7 +222,6 @@ reg = <0x42>; interrupts = <8 3>; interrupt-parent = <&gpioi>; - interrupt-controller; wakeup-source; stmpegpio: stmpe_gpio { diff --git a/arch/arm/boot/dts/st/stm32f769-disco-mb1166-reva09.dts b/arch/arm/boot/dts/st/stm32f769-disco-mb1166-reva09.dts new file mode 100644 index 000000000000..ff7ff32371d0 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f769-disco-mb1166-reva09.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Dario Binacchi <dario.binacchi@amarulasolutions.com> + */ + +#include "stm32f769-disco.dts" + +&panel0 { + compatible = "frida,frd400b25025", "novatek,nt35510"; + vddi-supply = <&vcc_3v3>; + vdd-supply = <&vcc_3v3>; + /delete-property/power-supply; +}; diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts index 5d12ae25b327..52c5baf58ab9 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -41,7 +41,7 @@ */ /dts-v1/; -#include "stm32f746.dtsi" +#include "stm32f769.dtsi" #include "stm32f769-pinctrl.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> @@ -60,6 +60,19 @@ reg = <0xC0000000 0x1000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,dma { + compatible = "shared-dma-pool"; + linux,dma-default; + no-map; + size = <0x100000>; + }; + }; + aliases { serial0 = &usart1; }; @@ -92,9 +105,9 @@ clock-names = "main_clk"; }; - mmc_vcard: mmc_vcard { + vcc_3v3: vcc-3v3 { compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; + regulator-name = "vcc_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -114,6 +127,45 @@ clock-frequency = <25000000>; }; +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; + }; + + panel0: panel@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; /* dsi virtual channel (0..3) */ + reset-gpios = <&gpioj 15 GPIO_ACTIVE_LOW>; + power-supply = <&vcc_3v3>; + status = "okay"; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + &i2c1 { pinctrl-0 = <&i2c1_pins_b>; pinctrl-names = "default"; @@ -122,13 +174,23 @@ status = "okay"; }; +<dc { + status = "okay"; + + port { + ltdc_out_dsi: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; +}; + &rtc { status = "okay"; }; &sdio2 { status = "okay"; - vmmc-supply = <&mmc_vcard>; + vmmc-supply = <&vcc_3v3>; cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; broken-cd; pinctrl-names = "default", "opendrain", "sleep"; diff --git a/arch/arm/boot/dts/st/stm32f769.dtsi b/arch/arm/boot/dts/st/stm32f769.dtsi new file mode 100644 index 000000000000..4e7d9032149c --- /dev/null +++ b/arch/arm/boot/dts/st/stm32f769.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Dario Binacchi <dario.binacchi@amarulasolutions.com> + */ + +#include "stm32f746.dtsi" + +/ { + soc { + dsi: dsi@40016c00 { + compatible = "st,stm32-dsi"; + reg = <0x40016c00 0x800>; + clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>; + clock-names = "pclk", "ref"; + resets = <&rcc STM32F7_APB2_RESET(DSI)>; + reset-names = "apb"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index b04d24c939c3..3900f32da797 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -1315,6 +1315,13 @@ status = "disabled"; }; + crc1: crc@58009000 { + compatible = "st,stm32f7-crc"; + reg = <0x58009000 0x400>; + clocks = <&rcc CRC1>; + status = "disabled"; + }; + usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index eea740d097c7..52171214a308 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -93,6 +93,14 @@ }; }; +&crc1 { + status = "okay"; +}; + +&cryp { + status = "okay"; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32mp157.dtsi b/arch/arm/boot/dts/st/stm32mp157.dtsi index 6197d878894d..97cd24227cef 100644 --- a/arch/arm/boot/dts/st/stm32mp157.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157.dtsi @@ -20,7 +20,7 @@ dsi: dsi@5a000000 { compatible = "st,stm32-dsi"; reg = <0x5a000000 0x800>; - clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + clocks = <&rcc DSI>, <&clk_hse>, <&rcc DSI_PX>; clock-names = "pclk", "ref", "px_clk"; phy-dsi-supply = <®18>; resets = <&rcc DSI_R>; diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts index ce5937270aa1..306e1bc2a514 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts @@ -30,7 +30,7 @@ }; &dsi { - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; + clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; }; &gpioz { diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts index c20a73841c1f..956da5f26c1c 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts @@ -36,7 +36,7 @@ &dsi { phy-dsi-supply = <&scmi_reg18>; - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; + clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; }; &gpioz { diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts index 510cca5acb79..7a701f7ef0c7 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -64,7 +64,6 @@ reg = <0x38>; interrupts = <2 2>; interrupt-parent = <&gpiof>; - interrupt-controller; touchscreen-size-x = <480>; touchscreen-size-y = <800>; status = "okay"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts index 5e2eaf57ce22..8e4b0db198c2 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts @@ -35,7 +35,7 @@ }; &dsi { - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; + clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; }; &gpioz { diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts index 3226fb945a8e..72b9cab2d990 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts @@ -36,7 +36,7 @@ &dsi { phy-dsi-supply = <&scmi_reg18>; - clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; + clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; }; &gpioz { diff --git a/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen2.dts b/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen2.dts index 8a34d15e9005..4cc177031661 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen2.dts @@ -148,7 +148,7 @@ compatible = "ti,lmp92064"; reg = <0>; - reset-gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpioa 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; shunt-resistor-micro-ohms = <15000>; spi-max-frequency = <5000000>; vdd-supply = <®_pb_3v3>; diff --git a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi index fc3a2386dbb9..cfaf8adde319 100644 --- a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi @@ -409,7 +409,7 @@ baseboard_eeprom: &sip_eeprom { &spi2 { pinctrl-names = "default"; pinctrl-0 = <&spi2_pins_c>; - cs-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpiof 12 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -471,6 +471,10 @@ baseboard_eeprom: &sip_eeprom { interrupt-parent = <&gpioa>; interrupts = <6 IRQ_TYPE_EDGE_RISING>; + /* Reduce RGMII EMI emissions by reducing drive strength */ + microchip,hi-drive-strength-microamp = <2000>; + microchip,lo-drive-strength-microamp = <8000>; + ports { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/ti/davinci/da850.dtsi b/arch/arm/boot/dts/ti/davinci/da850.dtsi index f759fdfe1b10..1d3fb5397ce3 100644 --- a/arch/arm/boot/dts/ti/davinci/da850.dtsi +++ b/arch/arm/boot/dts/ti/davinci/da850.dtsi @@ -536,7 +536,7 @@ reg = <0x40000 0x1000>; cap-sd-highspeed; cap-mmc-highspeed; - interrupts = <16>; + interrupts = <16>, <17>; dmas = <&edma0 16 0>, <&edma0 17 0>; dma-names = "rx", "tx"; clocks = <&psc0 5>; @@ -566,7 +566,7 @@ reg = <0x21b000 0x1000>; cap-sd-highspeed; cap-mmc-highspeed; - interrupts = <72>; + interrupts = <72>, <73>; dmas = <&edma1 28 0>, <&edma1 29 0>; dma-names = "rx", "tx"; clocks = <&psc1 18>; diff --git a/arch/arm/boot/dts/ti/omap/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir2110.dts index ea5882ed7010..f82d2231dfaa 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-baltos-ir2110.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir2110.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir3220.dts index ea4f8dde6424..74a2191af146 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-baltos-ir3220.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir3220.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir5221.dts index ec914f27d11d..723ff88f76ac 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-baltos-ir5221.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos-ir5221.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi index 6a52e42b9e81..049fd8e1b40f 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /*#include "am33xx.dtsi"*/ diff --git a/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi b/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi index c14d5b70c72f..a4beb718559c 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ #include "am33xx.dtsi" diff --git a/arch/arm/boot/dts/ti/omap/am335x-base0033.dts b/arch/arm/boot/dts/ti/omap/am335x-base0033.dts index eba843e22ea1..46078af4b7a3 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-base0033.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-base0033.dts @@ -2,7 +2,7 @@ /* * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION * - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz + * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz */ #include "am335x-igep0033.dtsi" diff --git a/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi index 96451c8a815c..2d0216840ff5 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi @@ -289,8 +289,8 @@ * For details, see linux-omap mailing list May 2015 thread * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller * In particular, messages: - * http://www.spinics.net/lists/linux-omap/msg118585.html - * http://www.spinics.net/lists/linux-omap/msg118615.html + * https://www.spinics.net/lists/linux-omap/msg118585.html + * https://www.spinics.net/lists/linux-omap/msg118615.html * * You can override this later with * &tps { /delete-property/ ti,pmic-shutdown-controller; } diff --git a/arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts b/arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts index 72990e7ffe10..06767ea164b5 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts @@ -2,7 +2,7 @@ /* * am335x-cm-t335.dts - Device Tree file for Compulab CM-T335 * - * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2014 - 2015 CompuLab Ltd. - https://www.compulab.co.il/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts b/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts index 57f78846c42d..eba888dcd60e 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-evmsk.dts @@ -5,7 +5,7 @@ /* * AM335x Starter Kit - * http://www.ti.com/tool/tmdssk3358 + * https://www.ti.com/tool/tmdssk3358 */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am335x-guardian.dts b/arch/arm/boot/dts/ti/omap/am335x-guardian.dts index 205fe0ed7352..56e5d954a490 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-guardian.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-guardian.dts @@ -303,8 +303,8 @@ * For details, see linux-omap mailing list May 2015 thread * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller * In particular, messages: - * http://www.spinics.net/lists/linux-omap/msg118585.html - * http://www.spinics.net/lists/linux-omap/msg118615.html + * https://www.spinics.net/lists/linux-omap/msg118585.html + * https://www.spinics.net/lists/linux-omap/msg118615.html * * You can override this later with * &tps { /delete-property/ ti,pmic-shutdown-controller; } diff --git a/arch/arm/boot/dts/ti/omap/am335x-icev2.dts b/arch/arm/boot/dts/ti/omap/am335x-icev2.dts index 3c4228927f56..6f0f4fba043b 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-icev2.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-icev2.dts @@ -5,7 +5,7 @@ /* * AM335x ICE V2 board - * http://www.ti.com/tool/tmdsice3359 + * https://www.ti.com/tool/tmdsice3359 */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am335x-igep0033.dtsi b/arch/arm/boot/dts/ti/omap/am335x-igep0033.dtsi index e85c33fd42f0..c7a4a5476489 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-igep0033.dtsi @@ -2,7 +2,7 @@ /* * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x * - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz + * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2100-common.dtsi index b8730aa52ce6..a59331aa58e5 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2100-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2100-common.dtsi @@ -217,7 +217,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi1_pins>; - tpm_spi_tis@0 { + tpm@0 { compatible = "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <500000>; diff --git a/arch/arm/boot/dts/ti/omap/am335x-myirtech-myc.dtsi b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myc.dtsi index 584599269217..9c9359844a20 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-myirtech-myc.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myc.dtsi @@ -2,7 +2,7 @@ /* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */ /* Based on code by myc_c335x.dts, MYiRtech.com */ -/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ +/* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts index d3bba79b9358..fd91a3c01a63 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */ /* Based on code by myd_c335x.dts, MYiRtech.com */ -/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */ +/* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am335x-nano.dts b/arch/arm/boot/dts/ti/omap/am335x-nano.dts index a475c0d91306..26b5510cb3d1 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-nano.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-nano.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ + * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am335x-netcan-plus-1xx.dts b/arch/arm/boot/dts/ti/omap/am335x-netcan-plus-1xx.dts index f7fad48e36ed..546e88f8fbad 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-netcan-plus-1xx.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-netcan-plus-1xx.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-2xx.dts b/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-2xx.dts index 76751a324ad7..f66d57bb685e 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-2xx.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-2xx.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-8xx.dts b/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-8xx.dts index 5a9fcec040fa..5fb2c629f35c 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-8xx.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-netcom-plus-8xx.dts @@ -5,7 +5,7 @@ /* * VScom OnRISC - * http://www.vscom.de + * https://www.vscom.de */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts b/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts index 3c9444e98c14..f38f5bff2b96 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts @@ -3,7 +3,7 @@ * * EETS GmbH PDU001 board device tree file * - * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ + * Copyright (C) 2018 EETS GmbH - https://www.eets.ch/ * * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ * diff --git a/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-extended-wifi.dts index 5522759def26..7c9f65126c63 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-extended-wifi.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-extended-wifi.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2021 Sancloud Ltd - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-lite.dts b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-lite.dts index b1b400226d83..c6c96f6182a8 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-lite.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-sancloud-bbe-lite.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * Copyright (C) 2021 SanCloud Ltd */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts b/arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts index 596774c84744..2841e95d9a09 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-sbc-t335.dts @@ -2,7 +2,7 @@ /* * am335x-sbc-t335.dts - Device Tree file for Compulab SBC-T335 * - * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2014 - 2015 CompuLab Ltd. - https://www.compulab.co.il/ */ #include "am335x-cm-t335.dts" diff --git a/arch/arm/boot/dts/ti/omap/am335x-sl50.dts b/arch/arm/boot/dts/ti/omap/am335x-sl50.dts index 1115c812f6c8..757ebd96b3f0 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-sl50.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-sl50.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/ + * Copyright (C) 2015 Toby Churchill - https://www.toby-churchill.com/ + * url above is defunct */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am33xx.dtsi b/arch/arm/boot/dts/ti/omap/am33xx.dtsi index 5b9e01a8aa5d..989d5a6edeed 100644 --- a/arch/arm/boot/dts/ti/omap/am33xx.dtsi +++ b/arch/arm/boot/dts/ti/omap/am33xx.dtsi @@ -640,10 +640,11 @@ #size-cells = <1>; ranges = <0 0x56000000 0x1000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap3630-gpu", "img,powervr-sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <37>; + }; }; }; }; diff --git a/arch/arm/boot/dts/ti/omap/am3517.dtsi b/arch/arm/boot/dts/ti/omap/am3517.dtsi index 77e58e686fb1..19aad715dff7 100644 --- a/arch/arm/boot/dts/ti/omap/am3517.dtsi +++ b/arch/arm/boot/dts/ti/omap/am3517.dtsi @@ -162,12 +162,13 @@ clock-names = "fck", "ick"; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x50000000 0x4000>; + ranges = <0 0x50000000 0x10000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap3430-gpu", "img,powervr-sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <21>; + }; }; }; }; diff --git a/arch/arm/boot/dts/ti/omap/am4372.dtsi b/arch/arm/boot/dts/ti/omap/am4372.dtsi index 9d2c064534f7..5fd1b380ece6 100644 --- a/arch/arm/boot/dts/ti/omap/am4372.dtsi +++ b/arch/arm/boot/dts/ti/omap/am4372.dtsi @@ -719,6 +719,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x56000000 0x1000000>; + + gpu@0 { + compatible = "ti,omap3630-gpu", "img,powervr-sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + }; }; }; }; diff --git a/arch/arm/boot/dts/ti/omap/am437x-cm-t43.dts b/arch/arm/boot/dts/ti/omap/am437x-cm-t43.dts index 9ec75d03eaff..172516a7667e 100644 --- a/arch/arm/boot/dts/ti/omap/am437x-cm-t43.dts +++ b/arch/arm/boot/dts/ti/omap/am437x-cm-t43.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2015 CompuLab, Ltd. - https://www.compulab.co.il/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/am437x-sbc-t43.dts b/arch/arm/boot/dts/ti/omap/am437x-sbc-t43.dts index 34a5407bee15..5ec57dcb0659 100644 --- a/arch/arm/boot/dts/ti/omap/am437x-sbc-t43.dts +++ b/arch/arm/boot/dts/ti/omap/am437x-sbc-t43.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2015 CompuLab, Ltd. - https://www.compulab.co.il/ */ #include "am437x-cm-t43.dts" diff --git a/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts index c8e55642f9c6..eb1ec85aba28 100644 --- a/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts +++ b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2019 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -415,7 +415,6 @@ reg = <0x41>; interrupts = <30 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio2>; - interrupt-controller; id = <0>; blocks = <0x5>; irq-trigger = <0x1>; diff --git a/arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts index 4fd831ff206f..d6e3152b02f7 100644 --- a/arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/ti/omap/am57xx-cl-som-am57x.dts @@ -2,7 +2,7 @@ /* * Support for CompuLab CL-SOM-AM57x System-on-Module * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2015 CompuLab Ltd. - https://www.compulab.co.il/ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il> */ diff --git a/arch/arm/boot/dts/ti/omap/am57xx-sbc-am57x.dts b/arch/arm/boot/dts/ti/omap/am57xx-sbc-am57x.dts index 363115afb0a4..64675f4edb60 100644 --- a/arch/arm/boot/dts/ti/omap/am57xx-sbc-am57x.dts +++ b/arch/arm/boot/dts/ti/omap/am57xx-sbc-am57x.dts @@ -2,7 +2,7 @@ /* * Support for CompuLab SBC-AM57x single board computer * - * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2015 CompuLab Ltd. - https://www.compulab.co.il/ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il> */ diff --git a/arch/arm/boot/dts/ti/omap/compulab-sb-som.dtsi b/arch/arm/boot/dts/ti/omap/compulab-sb-som.dtsi index f5e6216718d8..8a8fa1b2b26c 100644 --- a/arch/arm/boot/dts/ti/omap/compulab-sb-som.dtsi +++ b/arch/arm/boot/dts/ti/omap/compulab-sb-som.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/ + * Copyright (C) 2015 CompuLab, Ltd. - https://www.compulab.co.il/ */ / { diff --git a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi index 5733e3a4ea8e..6e67d99832ac 100644 --- a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi @@ -80,7 +80,7 @@ }; }; - phy_gmii_sel: phy-gmii-sel { + phy_gmii_sel: phy-gmii-sel@554 { compatible = "ti,dra7xx-phy-gmii-sel"; reg = <0x554 0x4>; #phy-cells = <1>; diff --git a/arch/arm/boot/dts/ti/omap/dra7.dtsi b/arch/arm/boot/dts/ti/omap/dra7.dtsi index 6509c742fb58..164fa88c459e 100644 --- a/arch/arm/boot/dts/ti/omap/dra7.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7.dtsi @@ -638,7 +638,7 @@ }; }; - abb_mpu: regulator-abb-mpu { + abb_mpu: regulator-abb-mpu@4ae07ddc { compatible = "ti,abb-v3"; regulator-name = "abb_mpu"; #address-cells = <0>; @@ -671,7 +671,7 @@ >; }; - abb_ivahd: regulator-abb-ivahd { + abb_ivahd: regulator-abb-ivahd@4ae07e34 { compatible = "ti,abb-v3"; regulator-name = "abb_ivahd"; #address-cells = <0>; @@ -704,7 +704,7 @@ >; }; - abb_dspeve: regulator-abb-dspeve { + abb_dspeve: regulator-abb-dspeve@4ae07e30 { compatible = "ti,abb-v3"; regulator-name = "abb_dspeve"; #address-cells = <0>; @@ -737,7 +737,7 @@ >; }; - abb_gpu: regulator-abb-gpu { + abb_gpu: regulator-abb-gpu@4ae07de4 { compatible = "ti,abb-v3"; regulator-name = "abb_gpu"; #address-cells = <0>; @@ -850,12 +850,19 @@ <SYSC_IDLE_SMART>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; + + gpu@0 { + compatible = "ti,am5728-gpu", "img,powervr-sgx544"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + }; }; crossbar_mpu: crossbar@4a002a48 { diff --git a/arch/arm/boot/dts/ti/omap/dra74x-p.dtsi b/arch/arm/boot/dts/ti/omap/dra74x-p.dtsi index 006189dad7a7..bb5239ae164d 100644 --- a/arch/arm/boot/dts/ti/omap/dra74x-p.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra74x-p.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi index 04a7a6d1d529..06466d36caa9 100644 --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -1685,7 +1685,7 @@ reg = <0x0558>; }; - sys_32k_ck: clock-sys-32k { + sys_32k_ck: clock-sys-32k@6c4 { #clock-cells = <0>; compatible = "ti,mux-clock"; clock-output-names = "sys_32k_ck"; diff --git a/arch/arm/boot/dts/ti/omap/omap34xx.dtsi b/arch/arm/boot/dts/ti/omap/omap34xx.dtsi index fc7233ac183a..acdd0ee34421 100644 --- a/arch/arm/boot/dts/ti/omap/omap34xx.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap34xx.dtsi @@ -164,12 +164,13 @@ clock-names = "fck", "ick"; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x50000000 0x4000>; + ranges = <0 0x50000000 0x10000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap3430-gpu", "img,powervr-sgx530"; + reg = <0x0 0x10000>; /* 64kB */ + interrupts = <21>; + }; }; }; diff --git a/arch/arm/boot/dts/ti/omap/omap36xx.dtsi b/arch/arm/boot/dts/ti/omap/omap36xx.dtsi index e6d8070c1bf8..c3d79ecd56e3 100644 --- a/arch/arm/boot/dts/ti/omap/omap36xx.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap36xx.dtsi @@ -211,10 +211,11 @@ #size-cells = <1>; ranges = <0 0x50000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap3630-gpu", "img,powervr-sgx530"; + reg = <0x0 0x2000000>; /* 32MB */ + interrupts = <21>; + }; }; }; diff --git a/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts index 24f7d0285f79..339e52ba3614 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts +++ b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts @@ -85,6 +85,7 @@ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ interrupt-controller; #interrupt-cells = <1>; + system-power-controller; rtc { compatible = "ti,twl4030-rtc"; diff --git a/arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi b/arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi index f528511c2537..97706d6296a6 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi @@ -408,6 +408,7 @@ reg = <0x48>; /* IRQ# = 7 */ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ + system-power-controller; }; twl6040: twl@4b { diff --git a/arch/arm/boot/dts/ti/omap/omap4-sdp.dts b/arch/arm/boot/dts/ti/omap/omap4-sdp.dts index b2cb93edbc3a..b535d24c6140 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-sdp.dts +++ b/arch/arm/boot/dts/ti/omap/omap4-sdp.dts @@ -439,7 +439,7 @@ /* * Ambient Light Sensor - * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf + * https://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf (defunct) */ bh1780@29 { compatible = "rohm,bh1780"; diff --git a/arch/arm/boot/dts/ti/omap/omap4.dtsi b/arch/arm/boot/dts/ti/omap/omap4.dtsi index 2bbff9032be3..559b2bfe4ca7 100644 --- a/arch/arm/boot/dts/ti/omap/omap4.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4.dtsi @@ -501,10 +501,11 @@ #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap4430-gpu", "img,powervr-sgx540"; + reg = <0x0 0x2000000>; /* 32MB */ + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + }; }; /* diff --git a/arch/arm/boot/dts/ti/omap/omap5-igep0050.dts b/arch/arm/boot/dts/ti/omap/omap5-igep0050.dts index d4ca2e3a14dd..0368e32f67e7 100644 --- a/arch/arm/boot/dts/ti/omap/omap5-igep0050.dts +++ b/arch/arm/boot/dts/ti/omap/omap5-igep0050.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz/ + * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz/ */ /dts-v1/; diff --git a/arch/arm/boot/dts/ti/omap/omap5.dtsi b/arch/arm/boot/dts/ti/omap/omap5.dtsi index bac6fa838793..6a66214ad0e2 100644 --- a/arch/arm/boot/dts/ti/omap/omap5.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap5.dtsi @@ -453,10 +453,11 @@ #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap5432-gpu", "img,powervr-sgx544"; + reg = <0x0 0x2000000>; /* 32MB */ + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + }; }; target-module@58000000 { diff --git a/arch/arm/boot/dts/ti/omap/twl4030.dtsi b/arch/arm/boot/dts/ti/omap/twl4030.dtsi index 93e07c18781b..a5d9c5738317 100644 --- a/arch/arm/boot/dts/ti/omap/twl4030.dtsi +++ b/arch/arm/boot/dts/ti/omap/twl4030.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /* diff --git a/arch/arm/boot/dts/ti/omap/twl6030.dtsi b/arch/arm/boot/dts/ti/omap/twl6030.dtsi index 9d588cfaa5cb..8da969035c41 100644 --- a/arch/arm/boot/dts/ti/omap/twl6030.dtsi +++ b/arch/arm/boot/dts/ti/omap/twl6030.dtsi @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /* * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/twl6030.pdf + * https://www.ti.com/lit/ds/symlink/twl6030.pdf */ &twl { compatible = "ti,twl6030"; diff --git a/arch/arm/include/asm/jump_label.h b/arch/arm/include/asm/jump_label.h index e12d7d096fc0..e4eb54f6cd9f 100644 --- a/arch/arm/include/asm/jump_label.h +++ b/arch/arm/include/asm/jump_label.h @@ -11,7 +11,7 @@ static __always_inline bool arch_static_branch(struct static_key *key, bool branch) { - asm_volatile_goto("1:\n\t" + asm goto("1:\n\t" WASM(nop) "\n\t" ".pushsection __jump_table, \"aw\"\n\t" ".word 1b, %l[l_yes], %c0\n\t" @@ -25,7 +25,7 @@ l_yes: static __always_inline bool arch_static_branch_jump(struct static_key *key, bool branch) { - asm_volatile_goto("1:\n\t" + asm goto("1:\n\t" WASM(b) " %l[l_yes]\n\t" ".pushsection __jump_table, \"aw\"\n\t" ".word 1b, %l[l_yes], %c0\n\t" diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 71b113976420..8b1ec60a9a46 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -339,6 +339,7 @@ static struct gpiod_lookup_table ep93xx_i2c_gpiod_table = { GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), GPIO_LOOKUP_IDX("G", 0, NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), + { } }, }; diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index e96fb40b9cc3..07565b593ed6 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -298,6 +298,8 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) goto done; } count_vm_vma_lock_event(VMA_LOCK_RETRY); + if (fault & VM_FAULT_MAJOR) + flags |= FAULT_FLAG_TRIED; /* Quick path to respond to signals */ if (fault_signal_pending(fault, regs)) { |