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-rw-r--r--arch/x86/include/asm/msr-index.h2
-rw-r--r--arch/x86/include/asm/perf_event_p4.h10
2 files changed, 12 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 1cd58cdbc03f..aef562c0a647 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -357,6 +357,8 @@
#define MSR_P4_U2L_ESCR0 0x000003b0
#define MSR_P4_U2L_ESCR1 0x000003b1
+#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
+
/* Intel Core-based CPU performance counters */
#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index 7d3406a2773c..871249cf4d2b 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -708,4 +708,14 @@ enum P4_EVENTS_ATTR {
P4_MAKE_EVENT_ATTR(P4_INSTR_COMPLETED, BOGUS, 1),
};
+enum {
+ KEY_P4_L1D_OP_READ_RESULT_MISS,
+ KEY_P4_LL_OP_READ_RESULT_MISS,
+ KEY_P4_DTLB_OP_READ_RESULT_MISS,
+ KEY_P4_DTLB_OP_WRITE_RESULT_MISS,
+ KEY_P4_ITLB_OP_READ_RESULT_ACCESS,
+ KEY_P4_ITLB_OP_READ_RESULT_MISS,
+ KEY_P4_UOP_TYPE,
+};
+
#endif /* PERF_EVENT_P4_H */