diff options
Diffstat (limited to 'arch')
882 files changed, 28917 insertions, 6107 deletions
diff --git a/arch/alpha/Kbuild b/arch/alpha/Kbuild new file mode 100644 index 000000000000..c2302017403a --- /dev/null +++ b/arch/alpha/Kbuild @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += kernel/ mm/ +obj-$(CONFIG_MATHEMU) += math-emu/ diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index a6d4c2f744e3..6c50877841df 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -531,7 +531,7 @@ config SMP will run faster if you say N here. See also the SMP-HOWTO available at - <http://www.tldp.org/docs.html#howto>. + <https://www.tldp.org/docs.html#howto>. If you don't know what to do here, say N. diff --git a/arch/alpha/Makefile b/arch/alpha/Makefile index c2946431d88d..52529ee42dac 100644 --- a/arch/alpha/Makefile +++ b/arch/alpha/Makefile @@ -38,8 +38,6 @@ KBUILD_CFLAGS += $(cflags-y) -Wa,-mev6 head-y := arch/alpha/kernel/head.o -core-y += arch/alpha/kernel/ arch/alpha/mm/ -core-$(CONFIG_MATHEMU) += arch/alpha/math-emu/ libs-y += arch/alpha/lib/ # export what is needed by arch/alpha/boot/Makefile diff --git a/arch/alpha/boot/bootp.c b/arch/alpha/boot/bootp.c index 00266e6e1b71..b4faba2432d5 100644 --- a/arch/alpha/boot/bootp.c +++ b/arch/alpha/boot/bootp.c @@ -23,7 +23,7 @@ #include "ksize.h" extern unsigned long switch_to_osf_pal(unsigned long nr, - struct pcb_struct * pcb_va, struct pcb_struct * pcb_pa, + struct pcb_struct *pcb_va, struct pcb_struct *pcb_pa, unsigned long *vptb); extern void move_stack(unsigned long new_stack); diff --git a/arch/alpha/boot/bootpz.c b/arch/alpha/boot/bootpz.c index 43af71835adf..90a2b341e9c0 100644 --- a/arch/alpha/boot/bootpz.c +++ b/arch/alpha/boot/bootpz.c @@ -200,7 +200,7 @@ extern char _end; START_ADDR KSEG address of the entry point of kernel code. ZERO_PGE KSEG address of page full of zeroes, but - upon entry to kerne cvan be expected + upon entry to kernel, it can be expected to hold the parameter list and possible INTRD information. diff --git a/arch/alpha/boot/misc.c b/arch/alpha/boot/misc.c index d65192202703..325d4dd4f904 100644 --- a/arch/alpha/boot/misc.c +++ b/arch/alpha/boot/misc.c @@ -30,7 +30,7 @@ extern long srm_printk(const char *, ...) __attribute__ ((format (printf, 1, 2))); /* - * gzip delarations + * gzip declarations */ #define OF(args) args #define STATIC static diff --git a/arch/alpha/configs/defconfig b/arch/alpha/configs/defconfig index dd2dd9f0861f..7f1ca30b115b 100644 --- a/arch/alpha/configs/defconfig +++ b/arch/alpha/configs/defconfig @@ -70,3 +70,4 @@ CONFIG_DEBUG_INFO=y CONFIG_ALPHA_LEGACY_START_ADDRESS=y CONFIG_MATHEMU=y CONFIG_CRYPTO_HMAC=y +CONFIG_DEVTMPFS=y diff --git a/arch/alpha/include/asm/compiler.h b/arch/alpha/include/asm/compiler.h index 5159ba259d65..ae645959018a 100644 --- a/arch/alpha/include/asm/compiler.h +++ b/arch/alpha/include/asm/compiler.h @@ -4,15 +4,4 @@ #include <uapi/asm/compiler.h> -/* Some idiots over in <linux/compiler.h> thought inline should imply - always_inline. This breaks stuff. We'll include this file whenever - we run into such problems. */ - -#include <linux/compiler.h> -#undef inline -#undef __inline__ -#undef __inline -#undef __always_inline -#define __always_inline inline __attribute__((always_inline)) - #endif /* __ALPHA_COMPILER_H */ diff --git a/arch/alpha/include/asm/pgtable.h b/arch/alpha/include/asm/pgtable.h index ff690846465e..02f0429f1068 100644 --- a/arch/alpha/include/asm/pgtable.h +++ b/arch/alpha/include/asm/pgtable.h @@ -236,8 +236,10 @@ pmd_page_vaddr(pmd_t pmd) #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> 32)) #define pud_page(pud) (pfn_to_page(pud_val(pud) >> 32)) -extern inline unsigned long pud_page_vaddr(pud_t pgd) -{ return PAGE_OFFSET + ((pud_val(pgd) & _PFN_MASK) >> (32-PAGE_SHIFT)); } +extern inline pmd_t *pud_pgtable(pud_t pgd) +{ + return (pmd_t *)(PAGE_OFFSET + ((pud_val(pgd) & _PFN_MASK) >> (32-PAGE_SHIFT))); +} extern inline int pte_none(pte_t pte) { return !pte_val(pte); } extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_VALID; } @@ -287,7 +289,7 @@ extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= __ACCESS_BITS; retu /* Find an entry in the second-level page table.. */ extern inline pmd_t * pmd_offset(pud_t * dir, unsigned long address) { - pmd_t *ret = (pmd_t *) pud_page_vaddr(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1)); + pmd_t *ret = pud_pgtable(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1)); smp_rmb(); /* see above */ return ret; } diff --git a/arch/alpha/include/asm/syscall.h b/arch/alpha/include/asm/syscall.h index 11c688c1d7ec..f21babaeed85 100644 --- a/arch/alpha/include/asm/syscall.h +++ b/arch/alpha/include/asm/syscall.h @@ -9,4 +9,10 @@ static inline int syscall_get_arch(struct task_struct *task) return AUDIT_ARCH_ALPHA; } +static inline long syscall_get_return_value(struct task_struct *task, + struct pt_regs *regs) +{ + return regs->r0; +} + #endif /* _ASM_ALPHA_SYSCALL_H */ diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c index d5367a1c6300..d31167e3269c 100644 --- a/arch/alpha/kernel/osf_sys.c +++ b/arch/alpha/kernel/osf_sys.c @@ -834,7 +834,7 @@ SYSCALL_DEFINE5(osf_setsysinfo, unsigned long, op, void __user *, buffer, return -EFAULT; state = ¤t_thread_info()->ieee_state; - /* Update softare trap enable bits. */ + /* Update software trap enable bits. */ *state = (*state & ~IEEE_SW_MASK) | (swcr & IEEE_SW_MASK); /* Update the real fpcr. */ @@ -854,7 +854,7 @@ SYSCALL_DEFINE5(osf_setsysinfo, unsigned long, op, void __user *, buffer, state = ¤t_thread_info()->ieee_state; exc &= IEEE_STATUS_MASK; - /* Update softare trap enable bits. */ + /* Update software trap enable bits. */ swcr = (*state & IEEE_SW_MASK) | exc; *state |= exc; diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c index e7a59d927d78..efcf7321701b 100644 --- a/arch/alpha/kernel/perf_event.c +++ b/arch/alpha/kernel/perf_event.c @@ -574,7 +574,7 @@ static void alpha_pmu_start(struct perf_event *event, int flags) * Check that CPU performance counters are supported. * - currently support EV67 and later CPUs. * - actually some later revisions of the EV6 have the same PMC model as the - * EV67 but we don't do suffiently deep CPU detection to detect them. + * EV67 but we don't do sufficiently deep CPU detection to detect them. * Bad luck to the very few people who might have one, I guess. */ static int supported_cpu(void) diff --git a/arch/alpha/kernel/process.c b/arch/alpha/kernel/process.c index ef0c08ed0481..a5123ea426ce 100644 --- a/arch/alpha/kernel/process.c +++ b/arch/alpha/kernel/process.c @@ -256,7 +256,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, childstack->r26 = (unsigned long) ret_from_kernel_thread; childstack->r9 = usp; /* function */ childstack->r10 = kthread_arg; - childregs->hae = alpha_mv.hae_cache, + childregs->hae = alpha_mv.hae_cache; childti->pcb.usp = 0; return 0; } diff --git a/arch/alpha/kernel/setup.c b/arch/alpha/kernel/setup.c index 7d56c217b235..b4fbbba30aa2 100644 --- a/arch/alpha/kernel/setup.c +++ b/arch/alpha/kernel/setup.c @@ -319,18 +319,19 @@ setup_memory(void *kernel_end) i, cluster->usage, cluster->start_pfn, cluster->start_pfn + cluster->numpages); - /* Bit 0 is console/PALcode reserved. Bit 1 is - non-volatile memory -- we might want to mark - this for later. */ - if (cluster->usage & 3) - continue; - end = cluster->start_pfn + cluster->numpages; if (end > max_low_pfn) max_low_pfn = end; memblock_add(PFN_PHYS(cluster->start_pfn), cluster->numpages << PAGE_SHIFT); + + /* Bit 0 is console/PALcode reserved. Bit 1 is + non-volatile memory -- we might want to mark + this for later. */ + if (cluster->usage & 3) + memblock_reserve(PFN_PHYS(cluster->start_pfn), + cluster->numpages << PAGE_SHIFT); } /* diff --git a/arch/alpha/kernel/smp.c b/arch/alpha/kernel/smp.c index 4b2575f936d4..cb64e4797d2a 100644 --- a/arch/alpha/kernel/smp.c +++ b/arch/alpha/kernel/smp.c @@ -582,7 +582,7 @@ void smp_send_stop(void) { cpumask_t to_whom; - cpumask_copy(&to_whom, cpu_possible_mask); + cpumask_copy(&to_whom, cpu_online_mask); cpumask_clear_cpu(smp_processor_id(), &to_whom); #ifdef DEBUG_IPI_MSG if (hard_smp_processor_id() != boot_cpu_id) diff --git a/arch/alpha/kernel/sys_nautilus.c b/arch/alpha/kernel/sys_nautilus.c index 53adf43dcd44..96fd6ff3fe81 100644 --- a/arch/alpha/kernel/sys_nautilus.c +++ b/arch/alpha/kernel/sys_nautilus.c @@ -212,7 +212,7 @@ nautilus_init_pci(void) /* Use default IO. */ pci_add_resource(&bridge->windows, &ioport_resource); - /* Irongate PCI memory aperture, calculate requred size before + /* Irongate PCI memory aperture, calculate required size before setting it up. */ pci_add_resource(&bridge->windows, &irongate_mem); diff --git a/arch/alpha/kernel/traps.c b/arch/alpha/kernel/traps.c index 921d4b6e4d95..5398f982bdd1 100644 --- a/arch/alpha/kernel/traps.c +++ b/arch/alpha/kernel/traps.c @@ -730,7 +730,7 @@ do_entUnaUser(void __user * va, unsigned long opcode, long error; /* Check the UAC bits to decide what the user wants us to do - with the unaliged access. */ + with the unaligned access. */ if (!(current_thread_info()->status & TS_UAC_NOPRINT)) { if (__ratelimit(&ratelimit)) { diff --git a/arch/alpha/math-emu/math.c b/arch/alpha/math-emu/math.c index d568cd9a3e43..f7cef66af88d 100644 --- a/arch/alpha/math-emu/math.c +++ b/arch/alpha/math-emu/math.c @@ -65,7 +65,7 @@ static long (*save_emul) (unsigned long pc); long do_alpha_fp_emul_imprecise(struct pt_regs *, unsigned long); long do_alpha_fp_emul(unsigned long); -int init_module(void) +static int alpha_fp_emul_init_module(void) { save_emul_imprecise = alpha_fp_emul_imprecise; save_emul = alpha_fp_emul; @@ -73,12 +73,14 @@ int init_module(void) alpha_fp_emul = do_alpha_fp_emul; return 0; } +module_init(alpha_fp_emul_init_module); -void cleanup_module(void) +static void alpha_fp_emul_cleanup_module(void) { alpha_fp_emul_imprecise = save_emul_imprecise; alpha_fp_emul = save_emul; } +module_exit(alpha_fp_emul_cleanup_module); #undef alpha_fp_emul_imprecise #define alpha_fp_emul_imprecise do_alpha_fp_emul_imprecise @@ -401,3 +403,5 @@ alpha_fp_emul_imprecise (struct pt_regs *regs, unsigned long write_mask) egress: return si_code; } + +EXPORT_SYMBOL(__udiv_qrnnd); diff --git a/arch/arc/Makefile b/arch/arc/Makefile index e47adc97a89b..c0d87ac2e221 100644 --- a/arch/arc/Makefile +++ b/arch/arc/Makefile @@ -85,9 +85,6 @@ KBUILD_LDFLAGS += $(ldflags-y) head-y := arch/arc/kernel/head.o -# See arch/arc/Kbuild for content of core part of the kernel -core-y += arch/arc/ - # w/o this dtb won't embed into kernel binary core-y += arch/arc/boot/dts/ diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c index abfeef7bf6f8..c083bf660cec 100644 --- a/arch/arc/mm/init.c +++ b/arch/arc/mm/init.c @@ -89,10 +89,7 @@ void __init setup_arch_memory(void) { unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 }; - init_mm.start_code = (unsigned long)_text; - init_mm.end_code = (unsigned long)_etext; - init_mm.end_data = (unsigned long)_edata; - init_mm.brk = (unsigned long)_end; + setup_initial_init_mm(_text, _etext, _edata, _end); /* first page of system - kernel .vector starts here */ min_low_pfn = virt_to_pfn(CONFIG_LINUX_RAM_BASE); diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f2ce83e643e7..2fb7012c3246 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -392,7 +392,8 @@ config ARCH_IXP4XX select HAVE_PCI select IXP4XX_IRQ select IXP4XX_TIMER - select NEED_MACH_IO_H + # With the new PCI driver this is not needed + select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY select USB_EHCI_BIG_ENDIAN_DESC select USB_EHCI_BIG_ENDIAN_MMIO help diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 7902bc2096e0..1c4384db223d 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -609,6 +609,14 @@ choice when u-boot hands over to the kernel, the system silently crashes, with no serial output at all. + config DEBUG_MSTARV7_PMUART + bool "Kernel low-level debugging messages via MSTARV7 PM UART" + depends on ARCH_MSTARV7 + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + for MSTAR ARMv7-based platforms on PM UART. + config DEBUG_MT6589_UART0 bool "Mediatek mt6589 UART0" depends on ARCH_MEDIATEK @@ -1607,6 +1615,7 @@ config DEBUG_UART_PHYS default 0x18000400 if DEBUG_BCM_HR2 default 0x18023000 if DEBUG_BCM_IPROC_UART3 default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1 + default 0x1f221000 if DEBUG_MSTARV7_PMUART default 0x20001000 if DEBUG_HIP01_UART default 0x20060000 if DEBUG_RK29_UART0 default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 @@ -1724,6 +1733,7 @@ config DEBUG_UART_VIRT default 0xf0100000 if DEBUG_DIGICOLOR_UA0 default 0xf01fb000 if DEBUG_NOMADIK_UART default 0xf0201000 if DEBUG_BCM2835 || DEBUG_BCM2836 + default 0xf0221000 if DEBUG_MSTARV7_PMUART default 0xf1000300 if DEBUG_BCM_5301X default 0xf1000400 if DEBUG_BCM_HR2 default 0xf1002000 if DEBUG_MT8127_UART0 @@ -1805,8 +1815,8 @@ config DEBUG_UART_VIRT default 0xfedc0000 if DEBUG_EP93XX default 0xfee003f8 if DEBUG_FOOTBRIDGE_COM1 default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART - default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN - default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN + default 0xfec00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN + default 0xfec00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN default 0xfef36000 if DEBUG_HIGHBANK_UART default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1 default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2 @@ -1829,6 +1839,7 @@ config DEBUG_UART_8250_SHIFT default 0 if DEBUG_FOOTBRIDGE_COM1 || ARCH_IOP32X || DEBUG_BCM_5301X || \ DEBUG_BCM_HR2 || DEBUG_OMAP7XXUART1 || DEBUG_OMAP7XXUART2 || \ DEBUG_OMAP7XXUART3 + default 3 if DEBUG_MSTARV7_PMUART default 2 config DEBUG_UART_8250_WORD diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 415c3514573a..173da685a52e 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -252,7 +252,6 @@ endif export TEXT_OFFSET GZFLAGS MMUEXT -core-y += arch/arm/ # If we have a machine-specific directory, then include it in the build. core-y += $(machdirs) $(platdirs) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f8f09c5066e7..863347b6b65e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -88,6 +88,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ bcm2837-rpi-cm3-io3.dtb \ + bcm2711-rpi-400.dtb \ bcm2711-rpi-4-b.dtb \ bcm2835-rpi-zero.dtb \ bcm2835-rpi-zero-w.dtb @@ -240,6 +241,7 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += \ integratorcp.dtb dtb-$(CONFIG_ARCH_IXP4XX) += \ intel-ixp42x-linksys-nslu2.dtb \ + intel-ixp42x-welltech-epbx100.dtb \ intel-ixp43x-gateworks-gw2358.dtb dtb-$(CONFIG_ARCH_KEYSTONE) += \ keystone-k2hk-evm.dtb \ @@ -513,8 +515,14 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \ imx6q-dms-ba16.dtb \ + imx6q-ds.dtb \ imx6q-emcon-avari.dtb \ imx6q-evi.dtb \ + imx6dl-b105pv2.dtb \ + imx6dl-b105v2.dtb \ + imx6dl-b125v2.dtb \ + imx6dl-b125pv2.dtb \ + imx6dl-b155v2.dtb \ imx6q-gk802.dtb \ imx6q-gw51xx.dtb \ imx6q-gw52xx.dtb \ @@ -725,7 +733,8 @@ dtb-$(CONFIG_ARCH_MXS) += \ imx28-m28evk.dtb \ imx28-sps1.dtb \ imx28-ts4600.dtb \ - imx28-tx28.dtb + imx28-tx28.dtb \ + imx28-xea.dtb dtb-$(CONFIG_ARCH_NOMADIK) += \ ste-nomadik-s8815.dtb \ ste-nomadik-nhk15.dtb @@ -1234,6 +1243,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-r16-nintendo-super-nes-classic.dtb \ sun8i-r16-parrot.dtb \ sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-r40-oka40i-c.dtb \ sun8i-s3-elimo-initium.dtb \ sun8i-s3-lichee-zero-plus.dtb \ sun8i-s3-pinecube.dtb \ @@ -1415,6 +1425,7 @@ dtb-$(CONFIG_ARCH_MSTARV7) += \ mstar-mercury5-ssc8336n-midrived08.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ + aspeed-ast2600-evb-a1.dtb \ aspeed-ast2600-evb.dtb \ aspeed-bmc-amd-ethanolx.dtb \ aspeed-bmc-ampere-mtjade.dtb \ diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index 3ea286180382..1103a2cb836f 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -393,10 +393,10 @@ status = "okay"; }; -&gpio0 { +&gpio0_target { ti,no-reset-on-init; }; -&gpio3 { +&gpio3_target { ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts index 86cad9912906..80116646a3fe 100644 --- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts +++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts @@ -101,7 +101,7 @@ }; &gpio3 { - ls_buf_en { + ls-buf-en-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts index 69acaf4ea0f3..0afcc2ee0b63 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -436,7 +436,7 @@ }; &gpio3 { - ls_buf_en { + ls-buf-en-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts index 7615327d906a..74db0fc39397 100644 --- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts +++ b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts @@ -101,7 +101,7 @@ }; &gpio1 { - ls_buf_en { + ls-buf-en-hog { gpio-hog; gpios = <29 GPIO_ACTIVE_HIGH>; output-high; @@ -118,7 +118,7 @@ /* an external pulldown on U21 pin 4. */ &gpio3 { - bt_aud_in { + bt-aud-in-hog { gpio-hog; gpios = <16 GPIO_ACTIVE_HIGH>; output-low; diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index 36d963db4026..688e14e82eba 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -333,7 +333,7 @@ status = "okay"; &epwmss0 { status = "okay"; - ecap0: ecap@100 { + ecap0: pwm@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins>; @@ -496,7 +496,7 @@ status = "okay"; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; /* WLS1271 WiFi */ wlcore: wlcore@1 { compatible = "ti,wl1271"; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 902e295b309e..9cf39c93defb 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -495,7 +495,7 @@ &epwmss0 { status = "okay"; - ecap0: ecap@100 { + ecap0: pwm@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins>; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index d5f8d5e2eb5d..001657be0381 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -510,7 +510,7 @@ &epwmss2 { status = "okay"; - ecap2: ecap@100 { + ecap2: pwm@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap2_pins>; @@ -646,7 +646,7 @@ status = "okay"; }; -&gpio0 { +&gpio0_target { ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index e923d065304d..5e598ac96dcc 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -458,14 +458,14 @@ }; &gpio3 { - p4 { + pr1-mii-ctl-hog { gpio-hog; gpios = <4 GPIO_ACTIVE_HIGH>; output-high; line-name = "PR1_MII_CTRL"; }; - p10 { + mux-mii-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */ diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi index 4e90f9c23d2e..8121a199607c 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi @@ -150,7 +150,7 @@ status = "okay"; }; -&gpio0 { +&gpio0_target { ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi index 98d8ed4ad967..39e5d2ce600a 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi @@ -353,7 +353,7 @@ status = "okay"; }; -&gpio0 { +&gpio0_target { ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts index f841afb27844..5403e47c07e2 100644 --- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts +++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts @@ -25,10 +25,6 @@ regulator-always-on; }; -&mmc1 { - vmmc-supply = <&vmmcsd_fixed>; -}; - &mmc2 { vmmc-supply = <&vmmcsd_fixed>; pinctrl-names = "default"; @@ -37,68 +33,6 @@ status = "okay"; }; -&am33xx_pinmux { - nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) - >; - }; - - mcasp0_pins: mcasp0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ - >; - }; - - flash_enable: flash-enable { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ - >; - }; - - imu_interrupt: imu-interrupt { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */ - >; - }; - - ethernet_interrupt: ethernet-interrupt{ - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */ - >; - }; -}; - &lcdc { status = "okay"; @@ -167,10 +101,6 @@ }; }; -&rtc { - system-power-controller; -}; - &mcasp0 { #sound-dai-cells = <0>; pinctrl-names = "default"; @@ -267,6 +197,66 @@ pinctrl-names = "default"; pinctrl-0 = <&clkout2_pin>; + nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) + >; + }; + + mcasp0_pins: mcasp0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ + >; + }; + + flash_enable: flash-enable { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */ + >; + }; + + imu_interrupt: imu-interrupt { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */ + >; + }; + + ethernet_interrupt: ethernet-interrupt{ + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */ + >; + }; + user_leds_s0: user-leds-s0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ @@ -427,6 +417,7 @@ &mmc1 { status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; bus-width = <0x4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; @@ -434,6 +425,7 @@ }; &rtc { + system-power-controller; clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts index 1eaa26533466..2bfe60d32783 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/am335x-shc.dts @@ -140,14 +140,14 @@ }; &gpio1 { - hmtc_rst { + hmtc-rst-hog { gpio-hog; gpios = <24 GPIO_ACTIVE_LOW>; output-high; line-name = "homematic_reset"; }; - hmtc_prog { + hmtc-prog-hog { gpio-hog; gpios = <27 GPIO_ACTIVE_LOW>; output-high; @@ -156,14 +156,14 @@ }; &gpio3 { - zgb_rst { + zgb-rst-hog { gpio-hog; gpios = <18 GPIO_ACTIVE_LOW>; output-low; line-name = "zigbee_reset"; }; - zgb_boot { + zgb-boot-hog { gpio-hog; gpios = <19 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 039a9ab4c7ea..859e760df4c8 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -1486,7 +1486,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; - mbox_wkupm3: wkup_m3 { + mbox_wkupm3: mbox-wkup-m3 { ti,mbox-send-noirq; ti,mbox-tx = <0 0 0>; ti,mbox-rx = <0 0 3>; @@ -1789,7 +1789,7 @@ }; }; - target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ + gpio3_target: target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0xae000 0x4>, <0xae010 0x4>, @@ -1995,15 +1995,12 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap0: ecap@100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; + ecap0: pwm@100 { + compatible = "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; - interrupts = <31>; - interrupt-names = "ecap0"; status = "disabled"; }; @@ -2017,8 +2014,7 @@ }; ehrpwm0: pwm@200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; @@ -2056,15 +2052,12 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap1: ecap@100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; + ecap1: pwm@100 { + compatible = "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; - interrupts = <47>; - interrupt-names = "ecap1"; status = "disabled"; }; @@ -2078,8 +2071,7 @@ }; ehrpwm1: pwm@200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; @@ -2117,15 +2109,12 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap2: ecap@100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; + ecap2: pwm@100 { + compatible = "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; - interrupts = <61>; - interrupt-names = "ecap2"; status = "disabled"; }; @@ -2139,8 +2128,7 @@ }; ehrpwm2: pwm@200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 6e4d05d649e9..e2677682b540 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -786,7 +786,7 @@ pinctrl-0 = <&gpio0_pins>; status = "okay"; - p23 { + sel-emmc-nand-hog { gpio-hog; gpios = <23 GPIO_ACTIVE_HIGH>; /* SelEMMCorNAND selects between eMMC and NAND: @@ -813,13 +813,16 @@ status = "okay"; }; +&gpio5_target { + ti,no-reset-on-init; +}; + &gpio5 { pinctrl-names = "default"; pinctrl-0 = <&display_mux_pins>; status = "okay"; - ti,no-reset-on-init; - p8 { + sel-lcd-hdmi-hog { /* * SelLCDorHDMI selects between display and audio paths: * Low: HDMI display with audio via HDMI diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index e217ffc09770..40ef3973f2a9 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -194,7 +194,7 @@ ranges = <0x0 0x9000 0x1000>; uart0: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; }; @@ -712,7 +712,7 @@ ranges = <0x0 0x22000 0x1000>; uart1: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -740,7 +740,7 @@ ranges = <0x0 0x24000 0x1000>; uart2: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -1168,7 +1168,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; - mbox_wkupm3: wkup_m3 { + mbox_wkupm3: mbox-wkup-m3 { ti,mbox-send-noirq; ti,mbox-tx = <0 0 0>; ti,mbox-rx = <0 0 3>; @@ -1399,7 +1399,7 @@ ranges = <0x0 0xa6000 0x1000>; uart3: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -1427,7 +1427,7 @@ ranges = <0x0 0xa8000 0x1000>; uart4: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -1455,7 +1455,7 @@ ranges = <0x0 0xaa000 0x1000>; uart5: serial@0 { - compatible = "ti,am4372-uart","ti,omap2-uart"; + compatible = "ti,am4372-uart"; reg = <0x0 0x2000>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -1747,10 +1747,9 @@ ranges = <0 0 0x1000>; status = "disabled"; - ecap0: ecap@100 { + ecap0: pwm@100 { compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; + "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; @@ -1760,8 +1759,7 @@ ehrpwm0: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; @@ -1799,10 +1797,9 @@ ranges = <0 0 0x1000>; status = "disabled"; - ecap1: ecap@100 { + ecap1: pwm@100 { compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; + "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; @@ -1812,8 +1809,7 @@ ehrpwm1: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; @@ -1851,10 +1847,9 @@ ranges = <0 0 0x1000>; status = "disabled"; - ecap2: ecap@100 { + ecap2: pwm@100 { compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; + "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x100 0x80>; clocks = <&l4ls_gclk>; @@ -1864,8 +1859,7 @@ ehrpwm2: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; @@ -1905,8 +1899,7 @@ ehrpwm3: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; @@ -1946,8 +1939,7 @@ ehrpwm4: pwm@48308200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; @@ -1987,8 +1979,7 @@ ehrpwm5: pwm@200 { compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x200 0x80>; clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; @@ -2070,7 +2061,7 @@ }; }; - target-module@22000 { /* 0x48322000, ap 116 64.0 */ + gpio5_target: target-module@22000 { /* 0x48322000, ap 116 64.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x22000 0x4>, <0x22010 0x4>, diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index f517d1e843cf..aae0af10a5b1 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -725,7 +725,7 @@ pinctrl-0 = <&display_mux_pins>; status = "okay"; - p1 { + sel-lcd-hdmi-hog { /* * SelLCDorHDMI selects between display and audio paths: * Low: HDMI display with audio via HDMI @@ -860,7 +860,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi0_pins_default>; pinctrl-1 = <&spi0_pins_sleep>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; }; &spi1 { @@ -868,7 +868,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi1_pins_default>; pinctrl-1 = <&spi1_pins_sleep>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; }; &usb2_phy1 { diff --git a/arch/arm/boot/dts/am5718.dtsi b/arch/arm/boot/dts/am5718.dtsi index ebf4d3cc1cfb..6d7530a48c73 100644 --- a/arch/arm/boot/dts/am5718.dtsi +++ b/arch/arm/boot/dts/am5718.dtsi @@ -17,17 +17,13 @@ * VCP1, VCP2 * MLB * ISS - * USB3, USB4 + * USB3 */ &usb3_tm { status = "disabled"; }; -&usb4_tm { - status = "disabled"; -}; - &atl_tm { status = "disabled"; }; diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts index 0d5fe2bfb683..aed81568a297 100644 --- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts @@ -454,20 +454,20 @@ &mailbox5 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { status = "okay"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { status = "okay"; }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { status = "okay"; }; }; @@ -610,12 +610,11 @@ >; }; -&gpio3 { - status = "okay"; +&gpio3_target { ti,no-reset-on-init; }; -&gpio2 { +&gpio2_target { status = "okay"; ti,no-reset-on-init; }; diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index 8bec21ed0de5..583a241f1151 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -13,7 +13,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts new file mode 100644 index 000000000000..dd7148060c4a --- /dev/null +++ b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2021 IBM Corp. + +#include "aspeed-ast2600-evb.dts" + +/ { + model = "AST2600 A1 EVB"; + + /delete-node/regulator-vcc-sdhci0; + /delete-node/regulator-vcc-sdhci1; + /delete-node/regulator-vccq-sdhci0; + /delete-node/regulator-vccq-sdhci1; +}; + +/delete-node/ &sdc; diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 2772796e215e..b7eb552640cb 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -4,6 +4,7 @@ /dts-v1/; #include "aspeed-g6.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> / { model = "AST2600 EVB"; @@ -21,6 +22,46 @@ device_type = "memory"; reg = <0x80000000 0x80000000>; }; + + vcc_sdhci0: regulator-vcc-sdhci0 { + compatible = "regulator-fixed"; + regulator-name = "SDHCI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhci0: regulator-vccq-sdhci0 { + compatible = "regulator-gpio"; + regulator-name = "SDHCI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, + <1800000 0>; + }; + + vcc_sdhci1: regulator-vcc-sdhci1 { + compatible = "regulator-fixed"; + regulator-name = "SDHCI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhci1: regulator-vccq-sdhci1 { + compatible = "regulator-gpio"; + regulator-name = "SDHCI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, + <1800000 0>; + }; }; &mdio0 { @@ -107,7 +148,8 @@ &emmc { non-removable; bus-width = <4>; - max-frequency = <52000000>; + max-frequency = <100000000>; + clk-phase-mmc-hs200 = <9>, <225>; }; &rtc { @@ -121,37 +163,7 @@ m25p,fast-read; label = "bmc"; spi-max-frequency = <50000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - u-boot@0 { - reg = <0x0 0xe0000>; // 896KB - label = "u-boot"; - }; - - u-boot-env@e0000 { - reg = <0xe0000 0x20000>; // 128KB - label = "u-boot-env"; - }; - - kernel@100000 { - reg = <0x100000 0x900000>; // 9MB - label = "kernel"; - }; - - rofs@a00000 { - reg = <0xa00000 0x2000000>; // 32MB - label = "rofs"; - }; - - rwfs@6000000 { - reg = <0x2a00000 0x1600000>; // 22MB - label = "rwfs"; - }; - }; +#include "openbmc-flash-layout-64.dtsi" }; }; @@ -245,3 +257,46 @@ &uhci { status = "okay"; }; + +&sdc { + status = "okay"; +}; + +/* + * The signal voltage of sdhci0 and sdhci1 on AST2600-A2 EVB is able to be + * toggled by GPIO pins. + * In the reference design, GPIOV0 of AST2600-A2 EVB is connected to the + * power load switch that provides 3.3v to sdhci0 vdd, GPIOV1 is connected to + * a 1.8v and a 3.3v power load switch that provides signal voltage to + * sdhci0 bus. + * If GPIOV0 is active high, sdhci0 is enabled, otherwise, sdhci0 is disabled. + * If GPIOV1 is active high, 3.3v power load switch is enabled, sdhci0 signal + * voltage is 3.3v, otherwise, 1.8v power load switch will be enabled, + * sdhci0 signal voltage becomes 1.8v. + * AST2600-A2 EVB also supports toggling signal voltage for sdhci1. + * The design is the same as sdhci0, it uses GPIOV2 as power-gpio and GPIOV3 + * as power-switch-gpio. + */ +&sdhci0 { + status = "okay"; + bus-width = <4>; + max-frequency = <100000000>; + sdhci-drive-type = /bits/ 8 <3>; + sdhci-caps-mask = <0x7 0x0>; + sdhci,wp-inverted; + vmmc-supply = <&vcc_sdhci0>; + vqmmc-supply = <&vccq_sdhci0>; + clk-phase-sd-hs = <7>, <200>; +}; + +&sdhci1 { + status = "okay"; + bus-width = <4>; + max-frequency = <100000000>; + sdhci-drive-type = /bits/ 8 <3>; + sdhci-caps-mask = <0x7 0x0>; + sdhci,wp-inverted; + vmmc-supply = <&vcc_sdhci1>; + vqmmc-supply = <&vccq_sdhci1>; + clk-phase-sd-hs = <7>, <200>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index 6aeb47c44eba..79d17841b3d7 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -34,7 +34,7 @@ }; chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; leds { compatible = "gpio-leds"; diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index 8f5ec22e51c2..57b0c45a2298 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -9,7 +9,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { @@ -110,6 +110,30 @@ linux,code = <ASPEED_GPIO(Q, 5)>; }; + psu1_vin_good { + label = "PSU1_VIN_GOOD"; + gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(H, 4)>; + }; + + psu2_vin_good { + label = "PSU2_VIN_GOOD"; + gpios = <&gpio ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(H, 5)>; + }; + + psu1_present { + label = "PSU1_PRESENT"; + gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(I, 0)>; + }; + + psu2_present { + label = "PSU2_PRESENT"; + gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(I, 1)>; + }; + }; gpioA0mux: mux-controller { @@ -280,7 +304,7 @@ m25p,fast-read; label = "bmc"; /* spi-max-frequency = <50000000>; */ -#include "openbmc-flash-layout.dtsi" +#include "openbmc-flash-layout-64.dtsi" }; }; @@ -332,6 +356,16 @@ status = "okay"; }; +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + &mac1 { status = "okay"; pinctrl-names = "default"; @@ -426,6 +460,19 @@ status = "okay"; }; +&i2c10 { + status = "okay"; + adm1278@10 { + compatible = "adi,adm1278"; + reg = <0x10>; + }; + + adm1278@11 { + compatible = "adi,adm1278"; + reg = <0x11>; + }; +}; + &gfx { status = "okay"; memory-region = <&gfx_memory>; @@ -529,8 +576,9 @@ "S1_DDR_SAVE","","", /*G0-G7*/ "S0_FW_BOOT_OK","SHD_REQ_L","","S0_OVERTEMP_L","","", "","", - /*H0-H7*/ "","","","","","","","", - /*I0-I7*/ "","","S1_BMC_SPECIAL_BOOT","","","","","", + /*H0-H7*/ "","","","","PSU1_VIN_GOOD","PSU2_VIN_GOOD","","", + /*I0-I7*/ "PSU1_PRESENT","PSU2_PRESENT","S1_BMC_SPECIAL_BOOT", + "","","","","", /*J0-J7*/ "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","", "","","","", /*K0-K7*/ "","","","","","","","", @@ -540,7 +588,8 @@ /*O0-O7*/ "","","","","","","","", /*P0-P7*/ "","","","","","","","", /*Q0-Q7*/ "","","","","","UID_BUTTON","","", - /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","","","RESET_BUTTON","","", + /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN", + "OCP_MAIN_PWREN","RESET_BUTTON","","", /*S0-S7*/ "","","","","","","","", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts index c2ece0b91885..3395de96ee11 100644 --- a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts +++ b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts index 2c29ac037d32..7c6af7f226e7 100644 --- a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts index dcab6e78dfa4..9b4cf5ebe6d5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts @@ -4,6 +4,7 @@ #include "aspeed-g5.dtsi" #include <dt-bindings/gpio/aspeed-gpio.h> #include <dt-bindings/i2c/i2c.h> +#include <dt-bindings/interrupt-controller/irq.h> /{ model = "ASRock E3C246D4I BMC"; @@ -15,7 +16,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; }; memory@80000000 { @@ -73,7 +74,8 @@ &vuart { status = "okay"; - aspeed,sirq-active-high; + aspeed,lpc-io-reg = <0x2f8>; + aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; }; &mac0 { diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts index 5ef88c377358..01dace8f5e5f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts +++ b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts @@ -55,7 +55,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts index 2fb8b147f489..90a3f485c67a 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts @@ -280,7 +280,7 @@ chosen { stdout-path = &uart1; - bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlyprintk"; + bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlycon"; }; ast-adc-hwmon { diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index 7b4b2b126ad8..b6b16356f571 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -37,7 +37,7 @@ }; chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 3295c8c7c05c..aa24cac8e5be 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -202,6 +202,35 @@ linux,code = <12>; }; }; + + leds { + compatible = "gpio-leds"; + + /* RTC battery fault LED at the back */ + led-rtc-battery { + gpios = <&gpio0 ASPEED_GPIO(H, 0) GPIO_ACTIVE_LOW>; + }; + + /* BMC Card fault LED at the back */ + led-bmc { + gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>; + }; + + /* Enclosure Identify LED at the back */ + led-rear-enc-id0 { + gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; + }; + + /* Enclosure fault LED at the back */ + led-rear-enc-fault0 { + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + }; + + /* PCIE slot power LED */ + led-pcieslot-power { + gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_LOW>; + }; + }; }; &gpio0 { @@ -214,7 +243,7 @@ /*F0-F7*/ "PIN_HOLE_RESET_IN_N","","", "PIN_HOLE_RESET_OUT_N","","","","", /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","","","","","","","", + /*H0-H7*/ "led-rtc-battery","led-bmc","led-rear-enc-id0","led-rear-enc-fault0","","","","", /*I0-I7*/ "","","","","","","","", /*J0-J7*/ "","","","","","","","", /*K0-K7*/ "","","","","","","","", @@ -222,7 +251,7 @@ /*M0-M7*/ "","","","","","","","", /*N0-N7*/ "","","","","","","","", /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","","","","","", + /*P0-P7*/ "","","","","led-pcieslot-power","","","", /*Q0-Q7*/ "","","","","","","","", /*R0-R7*/ "","","","","","I2C_FLASH_MICRO_N","","", /*S0-S7*/ "","","","","","","","", @@ -353,10 +382,47 @@ &i2c1 { status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; + + power-supply@68 { + compatible = "ibm,cffps"; + reg = <0x68>; + }; - pca2: pca9552@61 { + power-supply@69 { + compatible = "ibm,cffps"; + reg = <0x69>; + }; + + power-supply@6b { + compatible = "ibm,cffps"; + reg = <0x6b>; + }; + + power-supply@6d { + compatible = "ibm,cffps"; + reg = <0x6d>; + }; +}; + +&i2c4 { + status = "okay"; + + pca2: pca9552@65 { compatible = "nxp,pca9552"; - reg = <0x61>; + reg = <0x65>; #address-cells = <1>; #size-cells = <0>; @@ -424,12 +490,222 @@ reg = <9>; type = <PCA955X_TYPE_GPIO>; }; + }; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c4mux0chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + + pca_cable_card_c01: pca9551@62 { + compatible = "nxp,pca9551"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c01-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c01-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + }; + + i2c4mux0chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca_cable_card_c02: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c02-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c02-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + }; + + i2c4mux0chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + pca_cable_card_c03: pca9551@61 { + compatible = "nxp,pca9551"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c03-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c03-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + }; }; +}; + +&i2c5 { + status = "okay"; - pca3: pca9552@62 { + pca3: pca9552@66 { compatible = "nxp,pca9552"; - reg = <0x62>; + reg = <0x66>; #address-cells = <1>; #size-cells = <0>; @@ -512,44 +788,6 @@ }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - - eeprom@54 { - compatible = "atmel,24c128"; - reg = <0x54>; - }; - - power-supply@68 { - compatible = "ibm,cffps"; - reg = <0x68>; - }; - - power-supply@69 { - compatible = "ibm,cffps"; - reg = <0x69>; - }; - - power-supply@6a { - compatible = "ibm,cffps"; - reg = <0x6a>; - }; - - power-supply@6b { - compatible = "ibm,cffps"; - reg = <0x6b>; - }; -}; - -&i2c4 { - status = "okay"; - i2c-switch@70 { compatible = "nxp,pca9546"; reg = <0x70>; @@ -558,56 +796,69 @@ status = "okay"; i2c-mux-idle-disconnect; - i2c4mux0chn0: i2c@0 { + i2c5mux0chn0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; - eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - }; - }; - - i2c4mux0chn1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; }; - }; - i2c4mux0chn2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - eeprom@51 { - compatible = "atmel,24c64"; - reg = <0x51>; - }; - }; - }; -}; + pca_cable_card_c04: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; -&i2c5 { - status = "okay"; + gpio-controller; + #gpio-cells = <2>; - i2c-switch@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - i2c-mux-idle-disconnect; + led@0 { + label = "cablecard-c04-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; - i2c5mux0chn0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; + led@1 { + label = "cablecard-c04-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; }; }; @@ -619,6 +870,62 @@ compatible = "atmel,24c64"; reg = <0x51>; }; + + pca_cable_card_c05: pca9551@61 { + compatible = "nxp,pca9551"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c05-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c05-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; i2c5mux0chn2: i2c@2 { @@ -629,6 +936,62 @@ compatible = "atmel,24c64"; reg = <0x52>; }; + + pca_cable_card_c06: pca9551@62 { + compatible = "nxp,pca9551"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c06-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c06-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; i2c5mux0chn3: i2c@3 { @@ -639,6 +1002,62 @@ compatible = "atmel,24c64"; reg = <0x53>; }; + + pca_cable_card_c07: pca9551@63 { + compatible = "nxp,pca9551"; + reg = <0x63>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c07-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c07-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; }; }; @@ -659,8 +1078,64 @@ #size-cells = <0>; reg = <0>; eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca_cable_card_c08: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c08-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c08-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; }; }; @@ -672,6 +1147,62 @@ compatible = "atmel,24c64"; reg = <0x52>; }; + + pca_cable_card_c09: pca9551@62 { + compatible = "nxp,pca9551"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c09-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c09-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; i2c6mux0chn2: i2c@2 { @@ -682,6 +1213,62 @@ compatible = "atmel,24c64"; reg = <0x53>; }; + + pca_cable_card_c10: pca9551@63 { + compatible = "nxp,pca9551"; + reg = <0x63>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c10-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c10-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; }; i2c6mux0chn3: i2c@3 { @@ -692,12 +1279,1013 @@ compatible = "atmel,24c64"; reg = <0x51>; }; + + pca_cable_card_c11: pca9551@61 { + compatible = "nxp,pca9551"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard-c11-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard-c11-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + }; + }; + + pca_pcie_slot: pca9552@65 { + compatible = "nxp,pca9552"; + reg = <0x65>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + led@1 { + label = "pcieslot-c01"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "pcieslot-c02"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "pcieslot-c03"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@4 { + label = "pcieslot-c04"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@5 { + label = "pcieslot-c05"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@6 { + label = "pcieslot-c06"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@7 { + label = "pcieslot-c07"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@8 { + label = "pcieslot-c08"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@9 { + label = "pcieslot-c09"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@10 { + label = "pcieslot-c10"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@11 { + label = "pcieslot-c11"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; }; }; }; &i2c7 { status = "okay"; + + pic0_dimm: pca9552@31 { + compatible = "ibm,pca9552"; + reg = <0x31>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "ddimm1"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "ddimm2"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "ddimm3"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@4 { + label = "ddimm4"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@5 { + label = "ddimm5"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@6 { + label = "ddimm6"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@7 { + label = "ddimm7"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@8 { + label = "ddimm8"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@9 { + label = "ddimm9"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@10 { + label = "ddimm10"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@11 { + label = "ddimm11"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@12 { + label = "ddimm12"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@13 { + label = "ddimm13"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@14 { + label = "ddimm14"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@15 { + label = "ddimm15"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; + + pic1_dimm: pca9552@32 { + compatible = "ibm,pca9552"; + reg = <0x32>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm16"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "ddimm17"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "ddimm18"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "ddimm19"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@4 { + label = "ddimm20"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@5 { + label = "ddimm21"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@6 { + label = "ddimm22"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@7 { + label = "ddimm23"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@8 { + label = "ddimm24"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@9 { + label = "ddimm25"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@10 { + label = "ddimm26"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@11 { + label = "ddimm27"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@12 { + label = "ddimm28"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@13 { + label = "ddimm29"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@14 { + label = "ddimm30"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@15 { + label = "ddimm31"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; + + pic2_dimm: pca9552@33 { + compatible = "ibm,pca9552"; + reg = <0x33>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm32"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "ddimm33"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "ddimm34"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "ddimm35"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@4 { + label = "ddimm36"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@5 { + label = "ddimm37"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@6 { + label = "ddimm38"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@7 { + label = "ddimm39"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@8 { + label = "ddimm40"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@9 { + label = "ddimm41"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@10 { + label = "ddimm42"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@11 { + label = "ddimm43"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@12 { + label = "ddimm44"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@13 { + label = "ddimm45"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@14 { + label = "ddimm46"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@15 { + label = "ddimm47"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; + + pic3_dimm: pca9552@30 { + compatible = "ibm,pca9552"; + reg = <0x30>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "ddimm48"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "ddimm49"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "ddimm50"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "ddimm51"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@4 { + label = "ddimm52"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@5 { + label = "ddimm53"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@6 { + label = "ddimm54"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@7 { + label = "ddimm55"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@8 { + label = "ddimm56"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@9 { + label = "ddimm57"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@10 { + label = "ddimm58"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@11 { + label = "ddimm59"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@12 { + label = "ddimm60"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@13 { + label = "ddimm61"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@14 { + label = "ddimm62"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@15 { + label = "ddimm63"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; + + pic0_vrm_misc: pca9552@34 { + compatible = "ibm,pca9552"; + reg = <0x34>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "planar"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "tpm"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "cpu3-c61"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "cpu0-c14"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@4 { + label = "opencapi-connector3"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@5 { + label = "opencapi-connector4"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@6 { + label = "opencapi-connector5"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + led@8 { + label = "vrm4"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@9 { + label = "vrm5"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@10 { + label = "vrm6"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@11 { + label = "vrm7"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@12 { + label = "vrm12"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@13 { + label = "vrm13"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@14 { + label = "vrm14"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@15 { + label = "vrm15"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; + + pic1_vrm_misc: pca9552@35 { + compatible = "ibm,pca9552"; + reg = <0x35>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "dasd-backplane"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "power-distribution"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "cpu1-c19"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "cpu2-c56"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@4 { + label = "opencapi-connector0"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@5 { + label = "opencapi-connector1"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@6 { + label = "opencapi-connector2"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + led@8 { + label = "vrm0"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@9 { + label = "vrm1"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@10 { + label = "vrm2"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@11 { + label = "vrm3"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@12 { + label = "vrm8"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@13 { + label = "vrm9"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@14 { + label = "vrm10"; + reg = <14>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@15 { + label = "vrm11"; + reg = <15>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; }; &i2c8 { @@ -863,6 +2451,48 @@ compatible = "atmel,24c32"; reg = <0x50>; }; + + pca_oppanel: pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "front-sys-id0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "front-check-log0"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "front-enc-fault1"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "front-sys-pwron0"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; }; i2c14mux0chn3: i2c@3 { @@ -901,6 +2531,138 @@ }; }; + pca_fan_nvme: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "nvme0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "nvme1"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "nvme2"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "nvme3"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@4 { + label = "nvme4"; + reg = <4>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@5 { + label = "nvme5"; + reg = <5>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@6 { + label = "nvme6"; + reg = <6>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@7 { + label = "nvme7"; + reg = <7>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@8 { + label = "nvme8"; + reg = <8>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@9 { + label = "nvme9"; + reg = <9>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@10 { + label = "fan0"; + reg = <10>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@11 { + label = "fan1"; + reg = <11>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@12 { + label = "fan2"; + reg = <12>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@13 { + label = "fan3"; + reg = <13>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + pca0: pca9552@61 { compatible = "nxp,pca9552"; #address-cells = <1>; @@ -1070,6 +2832,7 @@ &emmc { status = "okay"; + clk-phase-mmc-hs200 = <180>, <180>; }; &fsim0 { diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts index f7fd3b3c90d0..342546a3c0f5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts @@ -19,33 +19,3 @@ reg = <0x6b>; }; }; - -&fan0 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; - -&fan1 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; - -&fan2 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; - -&fan3 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; - -&fan4 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; - -&fan5 { - tach-pulses = <4>; - /delete-property/ maxim,fan-dual-tach; -}; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 941c0489479a..481d0ee1f85f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -280,10 +280,7 @@ /*W0-W7*/ "","","","","","","","", /*X0-X7*/ "","","","","","","","", /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","","", - /*AA0-AA7*/ "","","","","","","","", - /*AB0-AB7*/ "","","","","","","","", - /*AC0-AC7*/ "","","","","","","",""; + /*Z0-Z7*/ "","","","","","","",""; pin_mclr_vpp { gpio-hog; diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts index 07593897fc9a..1752f3250e44 100644 --- a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts index 80c92e065a10..5a98a19f445e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts +++ b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "earlyprintk"; + bootargs = "earlycon"; }; memory { diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts index 6e9baf3bba53..d5b7d28cda88 100644 --- a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts +++ b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "earlyprintk"; + bootargs = "earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts index c29e5f4d86ad..8f543cca7c21 100644 --- a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts +++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts @@ -27,7 +27,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts index 084c455ad4cb..bcc1820f5c07 100644 --- a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts @@ -27,7 +27,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts b/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts index 73319917cb74..3ef8358ff764 100644 --- a/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-microsoft-olympus.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@40000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts index 42b37a204241..c0847636f20b 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts index 15c1f0ac81dc..a52a289cee85 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts @@ -57,7 +57,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts index 8503152faaf0..7d38d121ec6d 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts index 91dced7e7849..3d4bdad27c2d 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index eb4e93a57ff4..cd660c1ff3f5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@40000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index fd2e014dae75..084f54866f38 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -9,7 +9,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts index d56b5ed09b37..4816486c0c9e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index c1478d2db602..e33153dcaea8 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -13,7 +13,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200n8"; + bootargs = "console=ttyS4,115200n8 earlycon"; }; memory@80000000 { @@ -136,10 +136,7 @@ /*W0-W7*/ "","","","","","","","", /*X0-X7*/ "","","","","","","","", /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","","", - /*AA0-AA7*/ "","","","","","","","", - /*AB0-AB7*/ "","","","","","","","", - /*AC0-AC7*/ "","","","","","","",""; + /*Z0-Z7*/ "","","","","","","",""; }; &fmc { @@ -189,6 +186,7 @@ &emmc { status = "okay"; + clk-phase-mmc-hs200 = <36>, <270>; }; &fsim0 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts index 01074b6e3e03..328ef472c479 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@40000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index 85d58a63ae90..230f3584bcab 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -10,7 +10,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts index 4bcc82046362..7ae4ea0d2931 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -17,7 +17,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts index 03c161493ffc..61bc74b423cf 100644 --- a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts +++ b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts @@ -14,7 +14,7 @@ }; chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts index a68ff0675c28..9605e53f5bbf 100644 --- a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts @@ -28,7 +28,7 @@ chosen { stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlyprintk"; + bootargs = "console=ttyS4,115200 earlycon"; }; memory@40000000 { diff --git a/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts b/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts index bc16ad2b5c80..50f3c6a5c0c8 100644 --- a/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts +++ b/arch/arm/boot/dts/aspeed-bmc-supermicro-x11spi.dts @@ -11,7 +11,7 @@ chosen { stdout-path = &uart5; - bootargs = "earlyprintk"; + bootargs = "earlycon"; }; memory@80000000 { diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index d733c1f161c1..329eaeef66fb 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -264,6 +264,7 @@ reg-io-width = <4>; clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; resets = <&syscon ASPEED_RESET_CRT1>; + syscon = <&syscon>; status = "disabled"; interrupts = <0x19>; }; diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi index 7028e21bdd98..7e90d713f5e5 100644 --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi @@ -862,11 +862,21 @@ groups = "SGPM1"; }; + pinctrl_sgpm2_default: sgpm2_default { + function = "SGPM2"; + groups = "SGPM2"; + }; + pinctrl_sgps1_default: sgps1_default { function = "SGPS1"; groups = "SGPS1"; }; + pinctrl_sgps2_default: sgps2_default { + function = "SGPS2"; + groups = "SGPS2"; + }; + pinctrl_sioonctrl_default: sioonctrl_default { function = "SIOONCTRL"; groups = "SIOONCTRL"; diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 0025c88f660c..8ecb7861ce10 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -460,7 +460,7 @@ status = "disabled"; }; - nand: nand@18046000 { + nand_controller: nand-controller@18046000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x18046000 0x600>, <0xf8105408 0x600>, <0x18046f00 0x20>; diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi index e8df458aad39..84cda16f68a2 100644 --- a/arch/arm/boot/dts/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/bcm-hr2.dtsi @@ -179,7 +179,7 @@ status = "disabled"; }; - nand: nand@26000 { + nand_controller: nand-controller@26000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x26000 0x600>, <0x11b408 0x600>, diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index b4d2cc70afb1..748df7955ae6 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -269,7 +269,7 @@ dma-coherent; }; - nand: nand@26000 { + nand_controller: nand-controller@26000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x026000 0x600>, <0x11b408 0x600>, diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index 3b4ab947492a..f24bdd0870a5 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -1,11 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; #include "bcm2711.dtsi" -#include "bcm2835-rpi.dtsi" +#include "bcm2711-rpi.dtsi" #include "bcm283x-rpi-usb-peripheral.dtsi" -#include <dt-bindings/reset/raspberrypi,firmware-reset.h> - / { compatible = "raspberrypi,4-model-b", "brcm,bcm2711"; model = "Raspberry Pi 4 Model B"; @@ -15,25 +13,12 @@ stdout-path = "serial1:115200n8"; }; - /* Will be filled by the bootloader */ - memory@0 { - device_type = "memory"; - reg = <0 0 0>; - }; - - aliases { - emmc2bus = &emmc2bus; - ethernet0 = &genet; - pcie0 = &pcie0; - blconfig = &blconfig; - }; - leds { - act { + led-act { gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; default-state = "keep"; @@ -79,31 +64,15 @@ status = "okay"; }; -&firmware { - firmware_clocks: clocks { - compatible = "raspberrypi,firmware-clocks"; - #clock-cells = <1>; - }; - - expgpio: gpio { - compatible = "raspberrypi,firmware-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "BT_ON", - "WL_ON", - "PWR_LED_OFF", - "GLOBAL_RESET", - "VDD_SD_IO_SEL", - "CAM_GPIO", - "SD_PWR_ON", - ""; - status = "okay"; - }; - - reset: reset { - compatible = "raspberrypi,firmware-reset"; - #reset-cells = <1>; - }; +&expgpio { + gpio-line-names = "BT_ON", + "WL_ON", + "PWR_LED_OFF", + "GLOBAL_RESET", + "VDD_SD_IO_SEL", + "CAM_GPIO", + "SD_PWR_ON", + ""; }; &gpio { @@ -180,23 +149,13 @@ }; &hdmi0 { - clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; - clock-names = "hdmi", "bvb", "audio", "cec"; - wifi-2.4ghz-coexistence; status = "okay"; }; &hdmi1 { - clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; - clock-names = "hdmi", "bvb", "audio", "cec"; - wifi-2.4ghz-coexistence; status = "okay"; }; -&hvs { - clocks = <&firmware_clocks 4>; -}; - &pixelvalve0 { status = "okay"; }; @@ -219,22 +178,6 @@ status = "okay"; }; -&rmem { - /* - * RPi4's co-processor will copy the board's bootloader configuration - * into memory for the OS to consume. It'll also update this node with - * its placement information. - */ - blconfig: nvram@0 { - compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x0 0x0>; - no-map; - status = "disabled"; - }; -}; - /* SDHCI is used to control the SDIO for wireless */ &sdhci { #address-cells = <1>; @@ -309,10 +252,6 @@ status = "okay"; }; -&vchiq { - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; -}; - &vc4 { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm2711-rpi-400.dts b/arch/arm/boot/dts/bcm2711-rpi-400.dts new file mode 100644 index 000000000000..f4d2fc20397c --- /dev/null +++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2711-rpi-4-b.dts" + +/ { + compatible = "raspberrypi,400", "brcm,bcm2711"; + model = "Raspberry Pi 400"; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + leds { + /delete-node/ led-act; + + led-pwr { + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&expgpio 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&expgpio { + gpio-line-names = "BT_ON", + "WL_ON", + "", + "GLOBAL_RESET", + "VDD_SD_IO_SEL", + "CAM_GPIO", + "SD_PWR_ON", + "SD_OC_N"; +}; + +&genet_mdio { + clock-frequency = <1950000>; +}; + +&pm { + /delete-property/ system-power-controller; +}; diff --git a/arch/arm/boot/dts/bcm2711-rpi.dtsi b/arch/arm/boot/dts/bcm2711-rpi.dtsi new file mode 100644 index 000000000000..ca266c5d9f9b --- /dev/null +++ b/arch/arm/boot/dts/bcm2711-rpi.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "bcm2835-rpi.dtsi" + +#include <dt-bindings/reset/raspberrypi,firmware-reset.h> + +/ { + /* Will be filled by the bootloader */ + memory@0 { + device_type = "memory"; + reg = <0 0 0>; + }; + + aliases { + emmc2bus = &emmc2bus; + ethernet0 = &genet; + pcie0 = &pcie0; + blconfig = &blconfig; + }; +}; + +&firmware { + firmware_clocks: clocks { + compatible = "raspberrypi,firmware-clocks"; + #clock-cells = <1>; + }; + + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + reset: reset { + compatible = "raspberrypi,firmware-reset"; + #reset-cells = <1>; + }; +}; + +&hdmi0 { + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; + clock-names = "hdmi", "bvb", "audio", "cec"; + wifi-2.4ghz-coexistence; +}; + +&hdmi1 { + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; + clock-names = "hdmi", "bvb", "audio", "cec"; + wifi-2.4ghz-coexistence; +}; + +&hvs { + clocks = <&firmware_clocks 4>; +}; + +&rmem { + /* + * RPi4's co-processor will copy the board's bootloader configuration + * into memory for the OS to consume. It'll also update this node with + * its placement information. + */ + blconfig: nvram@0 { + compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x0>; + no-map; + status = "disabled"; + }; +}; + +&vchiq { + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index 720beec54d61..b8a4096192aa 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -413,7 +413,7 @@ ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; - emmc2: emmc2@7e340000 { + emmc2: mmc@7e340000 { compatible = "brcm,bcm2711-emmc2"; reg = <0x0 0x7e340000 0x100>; interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; @@ -1087,5 +1087,6 @@ }; &vec { + compatible = "brcm,bcm2711-vec"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index 6c8ce39833bf..40b9405f1a8e 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -14,11 +14,11 @@ }; leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts index 17fdd48346ff..11edb581dbaf 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts @@ -14,7 +14,7 @@ }; leds { - act { + led-act { gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index b0355c229cdc..1b435c64bd9c 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -15,11 +15,11 @@ }; leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts index 33b3b5c02521..a23c25c00eea 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts @@ -15,7 +15,7 @@ }; leds { - act { + led-act { gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 2b69957e0113..1b63d6b19750 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -15,7 +15,7 @@ }; leds { - act { + led-act { gpios = <&gpio 16 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi index 58059c2ce129..e4e6b6abbfc1 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi @@ -5,7 +5,7 @@ / { leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts index f65448c01e31..33b2b77aa47d 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts @@ -23,7 +23,7 @@ }; leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts index 6dd93c6f4966..6f9b3a908f28 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts @@ -18,7 +18,7 @@ }; leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index d94357b21f7e..87ddcad76083 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -4,7 +4,7 @@ leds { compatible = "gpio-leds"; - act { + led-act { label = "ACT"; default-state = "keep"; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index 0455a680394a..d8af8eeac7b6 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -15,11 +15,11 @@ }; leds { - act { + led-act { gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; default-state = "keep"; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts index 28be0332c1c8..77099a7871b0 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts @@ -19,11 +19,11 @@ }; leds { - act { + led-act { gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; default-state = "keep"; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index 37343148643d..61010266ca9a 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -20,11 +20,11 @@ }; leds { - act { + led-act { gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; }; - pwr { + led-pwr { label = "PWR"; gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; default-state = "keep"; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index 054ecaa355c9..dd4a48604097 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -20,7 +20,7 @@ }; leds { - act { + led-act { gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi index 925cb37c22f0..828a20561b96 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi +++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi @@ -14,7 +14,7 @@ * Since there is no upstream GPIO driver yet, * remove the incomplete node. */ - /delete-node/ act; + /delete-node/ led-act; }; reg_3v3: fixed-regulator { diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi index 20322de2f8bf..e2fd9610e125 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 &usb { dr_mode = "otg"; - g-rx-fifo-size = <558>; + g-rx-fifo-size = <256>; g-np-tx-fifo-size = <32>; /* * According to dwc2 the sum of all device EP diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi index 1409d1b559c1..0ff0e9e25327 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 &usb { dr_mode = "peripheral"; - g-rx-fifo-size = <558>; + g-rx-fifo-size = <256>; g-np-tx-fifo-size = <32>; g-tx-fifo-size = <256 256 512 512 512 768 768>; }; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index b83a864e2e8b..0f3be55201a5 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -420,7 +420,7 @@ status = "disabled"; }; - sdhci: sdhci@7e300000 { + sdhci: mmc@7e300000 { compatible = "brcm,bcm2835-sdhci"; reg = <0x7e300000 0x100>; interrupts = <2 30>; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index 8636600385fd..c81944cd6d0b 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -24,8 +24,8 @@ reg = <0x00000000 0x08000000>; }; - nand: nand@18028000 { - nandcs@0 { + nand_controller: nand-controller@18028000 { + nand@0 { partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index e635a15041dd..a6e2aeb28675 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -25,8 +25,8 @@ <0x88000000 0x08000000>; }; - nand: nand@18028000 { - nandcs@0 { + nand_controller: nand-controller@18028000 { + nand@0 { partitions { compatible = "fixed-partitions"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi index 2a8f7312d1be..6282363313e1 100644 --- a/arch/arm/boot/dts/bcm47094.dtsi +++ b/arch/arm/boot/dts/bcm47094.dtsi @@ -11,7 +11,7 @@ &pinctrl { compatible = "brcm,bcm4709-pinmux"; - pinmux_mdio: mdio { + pinmux_mdio: mdio-pins { groups = "mdio_grp"; function = "mdio"; }; diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi index 925a7c9ce5b7..be9a00ff752d 100644 --- a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi +++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi @@ -6,8 +6,8 @@ */ / { - nand@18028000 { - nandcs: nandcs@0 { + nand-controller@18028000 { + nandcs: nand@0 { compatible = "brcm,nandcs"; reg = <0>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 7db72a2f1020..f92089290ccd 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -458,18 +458,18 @@ function = "spi"; }; - pinmux_i2c: i2c { + pinmux_i2c: i2c-pins { groups = "i2c_grp"; function = "i2c"; }; - pinmux_pwm: pwm { + pinmux_pwm: pwm-pins { groups = "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"; function = "pwm"; }; - pinmux_uart1: uart1 { + pinmux_uart1: uart1-pins { groups = "uart1_grp"; function = "uart1"; }; @@ -501,7 +501,7 @@ reg = <0x18004000 0x14>; }; - nand: nand@18028000 { + nand_controller: nand-controller@18028000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; reg-names = "nand", "iproc-idm", "iproc-ext"; @@ -520,27 +520,27 @@ <0x1811b408 0x004>, <0x180293a0 0x01c>; reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "spi_lr_fullness_reached", + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mspi_done", + "mspi_halted", + "spi_lr_fullness_reached", "spi_lr_session_aborted", "spi_lr_impatient", "spi_lr_session_done", - "spi_lr_overhead", - "mspi_done", - "mspi_halted"; + "spi_lr_overread"; clocks = <&iprocmed>; clock-names = "iprocmed"; num-cs = <2>; #address-cells = <1>; #size-cells = <0>; - spi_nor: spi-nor@0 { + spi_nor: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi index 9c0325cf9e22..cca49a2e2d62 100644 --- a/arch/arm/boot/dts/bcm63138.dtsi +++ b/arch/arm/boot/dts/bcm63138.dtsi @@ -203,7 +203,7 @@ status = "disabled"; }; - nand: nand@2000 { + nand_controller: nand-controller@2000 { #address-cells = <1>; #size-cells = <0>; compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand"; diff --git a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts index 8313b7cad542..f92d2cf85972 100644 --- a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts +++ b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts @@ -14,10 +14,10 @@ }; }; -&nand { +&nand_controller { status = "okay"; - nandcs@1 { + nand@1 { compatible = "brcm,nandcs"; reg = <1>; nand-ecc-step-size = <512>; diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi index 58f67c9b830b..5ac2042515b8 100644 --- a/arch/arm/boot/dts/bcm7445.dtsi +++ b/arch/arm/boot/dts/bcm7445.dtsi @@ -148,7 +148,7 @@ reg-names = "aon-ctrl", "aon-sram"; }; - nand: nand@3e2800 { + nand_controller: nand-controller@3e2800 { status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts index b2d323f4a5ab..a76c74b44bba 100644 --- a/arch/arm/boot/dts/bcm911360_entphn.dts +++ b/arch/arm/boot/dts/bcm911360_entphn.dts @@ -82,8 +82,8 @@ status = "okay"; }; -&nand { - nandcs@1 { +&nand_controller { + nand@1 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm953012k.dts b/arch/arm/boot/dts/bcm953012k.dts index 046c59fb4846..de40bd59a5fa 100644 --- a/arch/arm/boot/dts/bcm953012k.dts +++ b/arch/arm/boot/dts/bcm953012k.dts @@ -49,8 +49,8 @@ }; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts index b4a1392bd5a6..dda3e11b711f 100644 --- a/arch/arm/boot/dts/bcm958300k.dts +++ b/arch/arm/boot/dts/bcm958300k.dts @@ -60,8 +60,8 @@ status = "okay"; }; -&nand { - nandcs@1 { +&nand_controller { + nand@1 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958305k.dts b/arch/arm/boot/dts/bcm958305k.dts index 3378683321d3..ea3c6b88b313 100644 --- a/arch/arm/boot/dts/bcm958305k.dts +++ b/arch/arm/boot/dts/bcm958305k.dts @@ -68,8 +68,8 @@ status = "okay"; }; -&nand { - nandcs@1 { +&nand_controller { + nand@1 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts index 5443fc079e6e..1f73885ec274 100644 --- a/arch/arm/boot/dts/bcm958522er.dts +++ b/arch/arm/boot/dts/bcm958522er.dts @@ -74,8 +74,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts index e1e3c26cef19..b6b9ca8b0972 100644 --- a/arch/arm/boot/dts/bcm958525er.dts +++ b/arch/arm/boot/dts/bcm958525er.dts @@ -74,8 +74,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index f161ba2e7e5e..ecf426f6ad5d 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -90,8 +90,8 @@ }; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts index 83cb877d63db..8ca18da981ad 100644 --- a/arch/arm/boot/dts/bcm958622hr.dts +++ b/arch/arm/boot/dts/bcm958622hr.dts @@ -78,8 +78,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts index 4e106ce1384a..9747378db531 100644 --- a/arch/arm/boot/dts/bcm958623hr.dts +++ b/arch/arm/boot/dts/bcm958623hr.dts @@ -78,8 +78,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index cda6cc281e18..0f92b773afb8 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -89,8 +89,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index ffbff0014c65..9e984ca0e6df 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -68,8 +68,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts index 5b177274f182..df5c8ab90627 100644 --- a/arch/arm/boot/dts/bcm963138dvt.dts +++ b/arch/arm/boot/dts/bcm963138dvt.dts @@ -31,10 +31,10 @@ status = "okay"; }; -&nand { +&nand_controller { status = "okay"; - nandcs@0 { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-ecc-strength = <4>; diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts index 3fd39c479a3c..5475dab8181d 100644 --- a/arch/arm/boot/dts/bcm988312hr.dts +++ b/arch/arm/boot/dts/bcm988312hr.dts @@ -74,8 +74,8 @@ status = "okay"; }; -&nand { - nandcs@0 { +&nand_controller { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 7cf31b6e48b7..c3942b4e82ad 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -574,8 +574,7 @@ status = "disabled"; }; ehrpwm0: pwm@300000 { - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x300000 0x2000>; clocks = <&psc1 17>, <&ehrpwm_tbclk>; @@ -584,8 +583,7 @@ status = "disabled"; }; ehrpwm1: pwm@302000 { - compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; reg = <0x302000 0x2000>; clocks = <&psc1 17>, <&ehrpwm_tbclk>; @@ -593,9 +591,8 @@ power-domains = <&psc1 17>; status = "disabled"; }; - ecap0: ecap@306000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap", - "ti,am33xx-ecap"; + ecap0: pwm@306000 { + compatible = "ti,da850-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x306000 0x80>; clocks = <&psc1 20>; @@ -603,9 +600,8 @@ power-domains = <&psc1 20>; status = "disabled"; }; - ecap1: ecap@307000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap", - "ti,am33xx-ecap"; + ecap1: pwm@307000 { + compatible = "ti,da850-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x307000 0x80>; clocks = <&psc1 20>; @@ -613,9 +609,8 @@ power-domains = <&psc1 20>; status = "disabled"; }; - ecap2: ecap@308000 { - compatible = "ti,da850-ecap", "ti,am3352-ecap", - "ti,am33xx-ecap"; + ecap2: pwm@308000 { + compatible = "ti,da850-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; reg = <0x308000 0x80>; clocks = <&psc1 20>; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index 3551a64963f8..a9e7274806f4 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -314,8 +314,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <70>; - dmas = <&edma 58 0 &edma 59 0>; - dma-names = "tx", "rx"; }; i2c2: i2c@4802a000 { @@ -325,8 +323,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <71>; - dmas = <&edma 60 0 &edma 61 0>; - dma-names = "tx", "rx"; }; intc: interrupt-controller@48200000 { @@ -351,7 +347,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; - mbox_dsp: mbox_dsp { + mbox_dsp: mbox-dsp { ti,mbox-tx = <3 0 0>; ti,mbox-rx = <0 0 0>; }; diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 38530dbb89a0..87deb6a76eff 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -319,7 +319,7 @@ }; pcf_lcd: gpio@20 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; @@ -330,7 +330,7 @@ }; pcf_gpio_21: gpio@21 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x21>; lines-initial-states = <0x1408>; gpio-controller; @@ -362,11 +362,11 @@ clock-frequency = <400000>; pcf_hdmi: gpio@26 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x26>; gpio-controller; #gpio-cells = <2>; - p1 { + hdmi-audio-hog { /* vin6_sel_s0: high: VIN6, low: audio */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi index a25749a1c365..a5bdc6431d8d 100644 --- a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi +++ b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi @@ -5,17 +5,17 @@ &mailbox5 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { status = "okay"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 149144cdff35..956a26d52a4c 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -1159,7 +1159,7 @@ ranges = <0x0 0x20000 0x1000>; uart3: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -1343,7 +1343,7 @@ }; }; - target-module@55000 { /* 0x48055000, ap 13 0e.0 */ + gpio2_target: target-module@55000 { /* 0x48055000, ap 13 0e.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x55000 0x4>, <0x55010 0x4>, @@ -1376,7 +1376,7 @@ }; }; - target-module@57000 { /* 0x48057000, ap 15 06.0 */ + gpio3_target: target-module@57000 { /* 0x48057000, ap 15 06.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x57000 0x4>, <0x57010 0x4>, @@ -1562,7 +1562,7 @@ ranges = <0x0 0x66000 0x1000>; uart5: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -1594,7 +1594,7 @@ ranges = <0x0 0x68000 0x1000>; uart6: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -1626,7 +1626,7 @@ ranges = <0x0 0x6a000 0x1000>; uart1: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -1658,7 +1658,7 @@ ranges = <0x0 0x6c000 0x1000>; uart2: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -1690,7 +1690,7 @@ ranges = <0x0 0x6e000 0x1000>; uart4: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -2424,7 +2424,7 @@ ranges = <0x0 0x20000 0x1000>; uart7: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -2454,7 +2454,7 @@ ranges = <0x0 0x22000 0x1000>; uart8: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -2484,7 +2484,7 @@ ranges = <0x0 0x24000 0x1000>; uart9: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; @@ -2561,7 +2561,7 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap0: ecap@100 { + ecap0: pwm@100 { compatible = "ti,dra746-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; @@ -2607,7 +2607,7 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap1: ecap@100 { + ecap1: pwm@100 { compatible = "ti,dra746-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; @@ -2653,7 +2653,7 @@ status = "disabled"; ranges = <0 0 0x1000>; - ecap2: ecap@100 { + ecap2: pwm@100 { compatible = "ti,dra746-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; @@ -4129,28 +4129,6 @@ }; }; - usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */ - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x140000 0x4>, - <0x140010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ - clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x140000 0x20000>; - }; - target-module@170000 { /* 0x48970000, ap 21 0a.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x170010 0x4>; @@ -4530,7 +4508,7 @@ ranges = <0x0 0xb000 0x1000>; uart10: serial@0 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; + compatible = "ti,dra742-uart"; reg = <0x0 0x100>; interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts index 6d2cca6b4488..a64364443031 100644 --- a/arch/arm/boot/dts/dra71-evm.dts +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -187,7 +187,7 @@ }; &pcf_hdmi { - p0 { + hdmi-i2c-disable-hog { /* * PM_OEn to High: Disable routing I2C3 to PM_I2C * With this PM_SEL(p3) should not matter diff --git a/arch/arm/boot/dts/dra71x.dtsi b/arch/arm/boot/dts/dra71x.dtsi index cad0e4a2bd8d..9c270d8f75d5 100644 --- a/arch/arm/boot/dts/dra71x.dtsi +++ b/arch/arm/boot/dts/dra71x.dtsi @@ -11,7 +11,3 @@ &rtctarget { status = "disabled"; }; - -&usb4_tm { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index b65b2dd094d0..f12825268188 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -226,7 +226,7 @@ }; pcf_gpio_21: gpio@21 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x21>; lines-initial-states = <0x1408>; gpio-controller; @@ -256,7 +256,7 @@ clock-frequency = <400000>; pcf_hdmi: pcf8575@26 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x26>; gpio-controller; #gpio-cells = <2>; @@ -268,7 +268,7 @@ */ lines-initial-states = <0x0f2b>; - p1 { + hdmi-audio-hog { /* vin6_sel_s0: high: VIN6, low: audio */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index d403acc754b6..90617261373c 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -77,12 +77,12 @@ }; &mailbox5 { - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { ti,mbox-tx = <5 2 2>; ti,mbox-rx = <1 2 2>; status = "disabled"; @@ -90,7 +90,7 @@ }; &mailbox6 { - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; @@ -108,7 +108,3 @@ &pcie2_rc { compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; }; - -&usb4_tm { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi index b1147a4b77f9..3256631510c5 100644 --- a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi +++ b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi @@ -6,7 +6,7 @@ #include "dra7-ipu-dsp-common.dtsi" &mailbox6 { - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index e1850d6c841a..cfb39dde4930 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -49,49 +49,6 @@ reg = <0x41500000 0x100>; }; - target-module@48940000 { - compatible = "ti,sysc-omap4", "ti,sysc"; - reg = <0x48940000 0x4>, - <0x48940010 0x4>; - reg-names = "rev", "sysc"; - ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x48940000 0x20000>; - - omap_dwc3_4: omap_dwc3_4@0 { - compatible = "ti,dwc3"; - reg = <0 0x10000>; - interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; - status = "disabled"; - usb4: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x17000>; - interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "peripheral", - "host", - "otg"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - }; - }; - }; target-module@41501000 { compatible = "ti,sysc-omap2", "ti,sysc"; @@ -188,12 +145,12 @@ }; &mailbox5 { - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { ti,mbox-tx = <5 2 2>; ti,mbox-rx = <1 2 2>; status = "disabled"; @@ -201,12 +158,12 @@ }; &mailbox6 { - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { ti,mbox-tx = <6 2 2>; ti,mbox-rx = <4 2 2>; status = "disabled"; }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + mbox_dsp2_ipc3x: mbox-dsp2-ipc3x { ti,mbox-tx = <5 2 2>; ti,mbox-rx = <1 2 2>; status = "disabled"; @@ -224,3 +181,52 @@ &pcie2_rc { compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie"; }; + +&l4_per3 { + segment@0 { + usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x140000 0x4>, + <0x140010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x140000 0x20000>; + + omap_dwc3_4: omap_dwc3_4@0 { + compatible = "ti,dwc3"; + reg = <0 0x10000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges; + status = "disabled"; + usb4: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x17000>; + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "peripheral", + "host", + "otg"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index 9bd01ae40b1d..e2b7fcb061cf 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -158,12 +158,6 @@ regulator-max-microvolt = <1800000>; }; - clk_ov5640_fixed: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - hdmi0: connector { compatible = "hdmi-connector"; label = "hdmi"; @@ -355,7 +349,7 @@ }; pcf_lcd: pcf8757@20 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; @@ -366,7 +360,7 @@ }; pcf_gpio_21: pcf8757@21 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; @@ -377,11 +371,11 @@ }; pcf_hdmi: pcf8575@26 { - compatible = "ti,pcf8575", "nxp,pcf8575"; + compatible = "nxp,pcf8575"; reg = <0x26>; gpio-controller; #gpio-cells = <2>; - p1 { + hdmi-audio-hog { /* vin6_sel_s0: high: VIN6, low: audio */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; @@ -406,27 +400,6 @@ }; }; -&i2c5 { - status = "okay"; - clock-frequency = <400000>; - - ov5640@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - - clocks = <&clk_ov5640_fixed>; - clock-names = "xclk"; - - port { - csi2_cam0: endpoint { - remote-endpoint = <&csi2_phy0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; -}; - &cpu0 { vdd-supply = <&buck10_reg>; }; @@ -573,14 +546,6 @@ }; }; -&csi2_0 { - csi2_phy0: endpoint { - remote-endpoint = <&csi2_cam0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; -}; - &ipu2 { status = "okay"; memory-region = <&ipu2_cma_pool>; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index c52b9cf4f74c..f6ba5e426040 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -653,7 +653,7 @@ mmc-pwrseq = <&wlan_pwrseq>; brcmf: wifi@1 { - compatible = "brcm,bcm4334-fmac"; + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpx1>; diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 525ff3d2fac3..55922176807e 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -314,7 +314,8 @@ }; &fimc_1 { - status = "okay"; + /* Back camera not implemented */ + status = "disabled"; assigned-clocks = <&clock CLK_MOUT_FIMC1>, <&clock CLK_SCLK_FIMC1>; assigned-clock-parents = <&clock CLK_SCLK_MPLL>; @@ -330,7 +331,8 @@ }; &fimc_3 { - status = "okay"; + /* Back camera not implemented */ + status = "disabled"; assigned-clocks = <&clock CLK_MOUT_FIMC3>, <&clock CLK_SCLK_FIMC3>; assigned-clock-parents = <&clock CLK_SCLK_MPLL>; @@ -806,7 +808,7 @@ pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; brcmf: wifi@1 { - compatible = "brcm,bcm4330-fmac"; + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpx2>; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index d2406c9146b8..3eb8df319246 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -521,7 +521,7 @@ pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; brcmf: wifi@1 { - compatible = "brcm,bcm4330-fmac"; + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpx2>; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index dd44ad2c6ad6..f052853244a4 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -614,7 +614,7 @@ pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; brcmf: wifi@1 { - compatible = "brcm,bcm4330-fmac"; + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpx2>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index 4583d342af39..b3726d4d7d93 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -163,6 +163,7 @@ <1025000>, <950000>, <918750>, <900000>, <875000>, <831250>; + wakeup-source; regulators { ldo1_reg: LDO1 { diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index fc77c1bfd844..968c7943653e 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -668,6 +668,7 @@ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&max77686_irq>; pinctrl-names = "default"; + wakeup-source; reg = <0x09>; #clock-cells = <1>; diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/exynos4412-n710x.dts index c49dbb7847b8..2c792142605c 100644 --- a/arch/arm/boot/dts/exynos4412-n710x.dts +++ b/arch/arm/boot/dts/exynos4412-n710x.dts @@ -50,8 +50,8 @@ reg = <0x48>; interrupt-parent = <&gpm2>; interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - x-size = <720>; - y-size = <1280>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; avdd-supply = <&ldo23_reg>; vdd-supply = <&ldo24_reg>; }; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 5bd05866d7a3..5b1d4591b35c 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -282,6 +282,7 @@ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&max77686_irq>; + wakeup-source; reg = <0x09>; #clock-cells = <1>; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index e1f6de53e20e..5479ef09f9f3 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -144,6 +144,7 @@ <1200000>, <1200000>, <1200000>, <1200000>, <1200000>, <1200000>; + wakeup-source; s5m8767_osc: clocks { compatible = "samsung,s5m8767-clk"; diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi index 9e750890edb8..22c3086e0076 100644 --- a/arch/arm/boot/dts/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi @@ -325,6 +325,7 @@ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&max77686_irq>; pinctrl-names = "default"; + wakeup-source; reg = <0x09>; #clock-cells = <1>; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index a161f6237c7f..a771542e28b8 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -218,6 +218,7 @@ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&s5m8767_irq>; + wakeup-source; vinb1-supply = <&main_dc_reg>; vinb2-supply = <&main_dc_reg>; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 949c0721cdb4..884fef55836c 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -190,6 +190,7 @@ pinctrl-names = "default"; pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; + wakeup-source; #clock-cells = <1>; inl1-supply = <&buck5_reg>; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 1aad4859c5f1..dfc7f14f5772 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -352,6 +352,7 @@ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&s2mps11_irq>; + wakeup-source; s2mps11_osc: clocks { compatible = "samsung,s2mps11-clk"; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index d506da9fa661..a4f0e3ffedbd 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -132,6 +132,7 @@ pmic@66 { compatible = "samsung,s2mps11-pmic"; reg = <0x66>; + wakeup-source; s2mps11_osc: clocks { compatible = "samsung,s2mps11-clk"; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 6d690b1db099..e7958dbecfd2 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -512,6 +512,7 @@ interrupts = <4 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&s2mps11_irq>; + wakeup-source; s2mps11_osc: clocks { compatible = "samsung,s2mps11-clk"; diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts index 20c222b33f98..d91f7fa2cf80 100644 --- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts +++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts @@ -22,7 +22,7 @@ label = "blue:heartbeat"; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; - max_brightness = <255>; + max-brightness = <255>; linux,default-trigger = "heartbeat"; }; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index ede782257643..1c24f9b35973 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -24,7 +24,7 @@ label = "blue:heartbeat"; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; - max_brightness = <255>; + max-brightness = <255>; linux,default-trigger = "heartbeat"; }; }; diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi index 2fc3e86dc5f7..982752e1df24 100644 --- a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi +++ b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi @@ -22,7 +22,7 @@ * Green LED is much brighter than the others * so limit its max brightness */ - max_brightness = <127>; + max-brightness = <127>; linux,default-trigger = "mmc0"; }; @@ -30,7 +30,7 @@ label = "blue:heartbeat"; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; - max_brightness = <255>; + max-brightness = <255>; linux,default-trigger = "heartbeat"; }; }; diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts index cc39289e99dd..c79a2a02dd6b 100644 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts @@ -61,9 +61,9 @@ #size-cells = <0>; /* Collides with IDE pins, that's cool (we do not use them) */ - gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; num-chipselects = <1>; @@ -169,7 +169,7 @@ * The touchpad input is connected to a GPIO bit-banged * I2C bus. */ - gpio-i2c { + i2c { compatible = "i2c-gpio"; /* Collides with ICE */ sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; @@ -492,8 +492,7 @@ display-controller@6a000000 { status = "okay"; - port@0 { - reg = <0>; + port { display_out: endpoint { remote-endpoint = <&panel_in>; }; diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini-dlink-dns-313.dts index c6f3d90e3e90..eba1c94ed7f7 100644 --- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts +++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts @@ -82,7 +82,7 @@ /* Global Mixed-Mode Technology G751 mounted on GPIO I2C */ - gpio-i2c { + i2c { compatible = "i2c-gpio"; sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; @@ -140,7 +140,7 @@ }; }; - mdio0: ethernet-phy { + mdio0: mdio { compatible = "virtual,mdio-gpio"; /* Uses MDC and MDIO */ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts index 43c45f7e1e0a..13112a8a5dd8 100644 --- a/arch/arm/boot/dts/gemini-nas4220b.dts +++ b/arch/arm/boot/dts/gemini-nas4220b.dts @@ -62,7 +62,7 @@ }; }; - mdio0: ethernet-phy { + mdio0: mdio { compatible = "virtual,mdio-gpio"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ diff --git a/arch/arm/boot/dts/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini-rut1xx.dts index 9611ddf06792..0ebda4efd9d0 100644 --- a/arch/arm/boot/dts/gemini-rut1xx.dts +++ b/arch/arm/boot/dts/gemini-rut1xx.dts @@ -56,7 +56,7 @@ }; }; - mdio0: ethernet-phy { + mdio0: mdio { compatible = "virtual,mdio-gpio"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ @@ -125,18 +125,6 @@ }; }; - ethernet@60000000 { - status = "okay"; - - ethernet-port@0 { - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet-port@1 { - /* Not used in this platform */ - }; - }; - usb@68000000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/gemini-sl93512r.dts b/arch/arm/boot/dts/gemini-sl93512r.dts index a0916d3c1059..c78e55fd2562 100644 --- a/arch/arm/boot/dts/gemini-sl93512r.dts +++ b/arch/arm/boot/dts/gemini-sl93512r.dts @@ -87,9 +87,9 @@ #address-cells = <1>; #size-cells = <0>; /* Check pin collisions */ - gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts index 0c6e6d35bfaa..1b64cc80b55a 100644 --- a/arch/arm/boot/dts/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini-sq201.dts @@ -72,9 +72,9 @@ #address-cells = <1>; #size-cells = <0>; /* Check pin collisions */ - gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini-wbd111.dts index 3a2761dd460f..5602ba8f30f2 100644 --- a/arch/arm/boot/dts/gemini-wbd111.dts +++ b/arch/arm/boot/dts/gemini-wbd111.dts @@ -68,7 +68,7 @@ }; }; - mdio0: ethernet-phy { + mdio0: mdio { compatible = "virtual,mdio-gpio"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini-wbd222.dts index 52b4dbc0c072..a4a260c36d75 100644 --- a/arch/arm/boot/dts/gemini-wbd222.dts +++ b/arch/arm/boot/dts/gemini-wbd222.dts @@ -67,7 +67,7 @@ }; }; - mdio0: ethernet-phy { + mdio0: mdio { compatible = "virtual,mdio-gpio"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index 065ed10a79fa..cc053af3c347 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -191,7 +191,7 @@ }; rtc@45000000 { - compatible = "cortina,gemini-rtc"; + compatible = "cortina,gemini-rtc", "faraday,ftrtc010"; reg = <0x45000000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; resets = <&syscon GEMINI_RESET_RTC>; @@ -286,6 +286,7 @@ clock-names = "PCLK", "PCICLK"; pinctrl-names = "default"; pinctrl-0 = <&pci_default_pins>; + device_type = "pci"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; @@ -356,6 +357,14 @@ }; }; + crypto: crypto@62000000 { + compatible = "cortina,sl3516-crypto"; + reg = <0x62000000 0x10000>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + resets = <&syscon GEMINI_RESET_SECURITY>; + clocks = <&syscon GEMINI_CLK_GATE_SECURITY>; + }; + ide@63000000 { compatible = "cortina,gemini-pata", "faraday,ftide010"; reg = <0x63000000 0x1000>; @@ -409,8 +418,6 @@ clock-names = "PCLK", "TVE"; pinctrl-names = "default"; pinctrl-0 = <&tvc_default_pins>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index 905900bf3e82..cf48ec14af43 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Hisilicon Ltd. Hi3620 SoC + * HiSilicon Ltd. Hi3620 SoC * - * Copyright (C) 2012-2013 Hisilicon Ltd. + * Copyright (C) 2012-2013 HiSilicon Ltd. * Copyright (C) 2012-2013 Linaro Ltd. * * Author: Haojian Zhuang <haojian.zhuang@linaro.org> diff --git a/arch/arm/boot/dts/hip01-ca9x2.dts b/arch/arm/boot/dts/hip01-ca9x2.dts index 031476304d94..f3faf247cd61 100644 --- a/arch/arm/boot/dts/hip01-ca9x2.dts +++ b/arch/arm/boot/dts/hip01-ca9x2.dts @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Hisilicon Ltd. HiP01 SoC + * HiSilicon Ltd. HiP01 SoC * - * Copyright (C) 2014 Hisilicon Ltd. + * Copyright (C) 2014 HiSilicon Ltd. * Copyright (C) 2014 Huawei Ltd. * * Author: Wang Long <long.wanglong@huawei.com> diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi index 2a7963605390..e17f36bd9006 100644 --- a/arch/arm/boot/dts/hip01.dtsi +++ b/arch/arm/boot/dts/hip01.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Hisilicon Ltd. HiP01 SoC + * HiSilicon Ltd. HiP01 SoC * - * Copyright (c) 2014 Hisilicon Ltd. + * Copyright (c) 2014 HiSilicon Ltd. * Copyright (c) 2014 Huawei Ltd. * * Author: Wang Long <long.wanglong@huawei.com> diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index bccf5ba3d855..2424cc545c9c 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Hisilicon Ltd. HiP04 SoC + * HiSilicon Ltd. HiP04 SoC * - * Copyright (C) 2013-2014 Hisilicon Ltd. + * Copyright (C) 2013-2014 HiSilicon Ltd. * Copyright (C) 2013-2014 Linaro Ltd. * * Author: Haojian Zhuang <haojian.zhuang@linaro.org> diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts index 22b122d3f514..7758c19038f0 100644 --- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts +++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2014 Linaro Ltd. - * Copyright (c) 2013-2014 Hisilicon Limited. + * Copyright (c) 2013-2014 HiSilicon Limited. */ /dts-v1/; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 97211385dc89..dc991ba2a9fb 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2014 Linaro Ltd. - * Copyright (c) 2013-2014 Hisilicon Limited. + * Copyright (c) 2013-2014 HiSilicon Limited. */ #include <dt-bindings/clock/hix5hd2-clock.h> diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h index f984b702efc5..908caf810351 100644 --- a/arch/arm/boot/dts/imx25-pinfunc.h +++ b/arch/arm/boot/dts/imx25-pinfunc.h @@ -563,15 +563,15 @@ #define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x00 0x000 #define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x05 0x000 -#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x00 0x000 +#define MX25_PAD_GPIO_A__GPIO_1_0 0x1f4 0x3f0 0x000 0x00 0x000 #define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x06 0x000 #define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x02 0x000 -#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x00 0x000 +#define MX25_PAD_GPIO_B__GPIO_1_1 0x1f8 0x3f4 0x000 0x00 0x000 #define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x02 0x001 #define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x06 0x001 -#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x00 0x000 +#define MX25_PAD_GPIO_C__GPIO_1_2 0x1fc 0x3f8 0x000 0x00 0x000 #define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000 #define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001 #define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001 @@ -580,18 +580,18 @@ #define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000 #define MX25_PAD_GPIO_C__CSPI2_SS2 0x1fc 0x3f8 0x000 0x07 0x000 -#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x00 0x000 +#define MX25_PAD_GPIO_D__GPIO_1_3 0x200 0x3fc 0x000 0x00 0x000 #define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001 #define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001 #define MX25_PAD_GPIO_D__CSPI3_SS2 0x200 0x3fc 0x4c4 0x07 0x001 -#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x00 0x000 +#define MX25_PAD_GPIO_E__GPIO_1_4 0x204 0x400 0x000 0x00 0x000 #define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002 #define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000 #define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x04 0x000 #define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x06 0x002 -#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x00 0x000 +#define MX25_PAD_GPIO_F__GPIO_1_5 0x208 0x404 0x000 0x00 0x000 #define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000 #define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x04 0x000 #define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x06 0x000 diff --git a/arch/arm/boot/dts/imx28-lwe.dtsi b/arch/arm/boot/dts/imx28-lwe.dtsi new file mode 100644 index 000000000000..bb971e660db8 --- /dev/null +++ b/arch/arm/boot/dts/imx28-lwe.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2021 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28.dtsi" + +/ { + aliases { + spi2 = &ssp3; + }; + + chosen { + bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait console=ttyAMA0,115200 panic=1"; + }; + + memory@40000000 { + reg = <0x40000000 0x08000000>; + }; + + reg_3v3: regulator-reg-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_5v: regulator-reg-usb-5v { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_fec_3v3: regulator-reg-fec-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fec-phy"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + #sound-dai-cells = <0>; + assigned-clocks = <&clks 53>; + assigned-clock-rates = <12000000>; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&spi3_pins_a { + fsl,pinmux-ids = < + MX28_PAD_AUART2_RX__SSP3_D4 + MX28_PAD_AUART2_TX__SSP3_D5 + MX28_PAD_SSP3_SCK__SSP3_SCK + MX28_PAD_SSP3_MOSI__SSP3_CMD + MX28_PAD_SSP3_MISO__SSP3_D0 + MX28_PAD_SSP3_SS0__SSP3_D3 + MX28_PAD_AUART2_TX__GPIO_3_9 + >; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_8bit_pins_a>; + bus-width = <8>; + vmmc-supply = <®_3v3>; + non-removable; + status = "okay"; +}; + +&ssp2 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; +}; + +&ssp3 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins_a>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <40000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0 0x80000>; + read-only; + }; + + partition@80000 { + label = "env0"; + reg = <0x80000 0x10000>; + }; + + partition@90000 { + label = "env1"; + reg = <0x90000 0x10000>; + }; + + partition@100000 { + label = "kernel"; + reg = <0x100000 0x400000>; + }; + + partition@500000 { + label = "swupdate"; + reg = <0x500000 0x800000>; + }; + }; + }; +}; + +&usb0 { + vbus-supply = <®_usb_5v>; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_b>, <&usb0_id_pins_a>; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb_5v>; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_b>; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx28-xea.dts b/arch/arm/boot/dts/imx28-xea.dts new file mode 100644 index 000000000000..a400c108f66a --- /dev/null +++ b/arch/arm/boot/dts/imx28-xea.dts @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2021 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28-lwe.dtsi" + +/ { + compatible = "lwn,imx28-xea", "fsl,imx28"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a &hog_pins_tiva>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D00__GPIO_0_0 + MX28_PAD_GPMI_D02__GPIO_0_2 + MX28_PAD_GPMI_D05__GPIO_0_5 + MX28_PAD_GPMI_CE1N__GPIO_0_17 + MX28_PAD_GPMI_RDY0__GPIO_0_20 + MX28_PAD_GPMI_RDY1__GPIO_0_21 + MX28_PAD_GPMI_RDY2__GPIO_0_22 + MX28_PAD_GPMI_RDN__GPIO_0_24 + MX28_PAD_GPMI_CLE__GPIO_0_27 + MX28_PAD_LCD_VSYNC__GPIO_1_28 + MX28_PAD_SSP1_SCK__GPIO_2_12 + MX28_PAD_SSP1_CMD__GPIO_2_13 + MX28_PAD_SSP2_SS1__GPIO_2_20 + MX28_PAD_SSP2_SS2__GPIO_2_21 + MX28_PAD_LCD_D00__GPIO_1_0 + MX28_PAD_LCD_D01__GPIO_1_1 + MX28_PAD_LCD_D02__GPIO_1_2 + MX28_PAD_LCD_D03__GPIO_1_3 + MX28_PAD_LCD_D04__GPIO_1_4 + MX28_PAD_LCD_D05__GPIO_1_5 + MX28_PAD_LCD_D06__GPIO_1_6 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + hog_pins_tiva: hog@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY3__GPIO_0_23 + MX28_PAD_GPMI_WRN__GPIO_0_25 + >; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + hog_pins_coding: hog@2 { + reg = <2>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D01__GPIO_0_1 + MX28_PAD_GPMI_D03__GPIO_0_3 + MX28_PAD_GPMI_D04__GPIO_0_4 + MX28_PAD_GPMI_D06__GPIO_0_6 + MX28_PAD_GPMI_D07__GPIO_0_7 + >; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; +}; + +®_fec_3v3 { + gpio = <&gpio0 0 0>; +}; + +®_usb_5v { + gpio = <&gpio0 2 0>; +}; + +&spi2_pins_a { + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__SSP2_SCK + MX28_PAD_SSP2_MOSI__SSP2_CMD + MX28_PAD_SSP2_MISO__SSP2_D0 + MX28_PAD_SSP2_SS0__GPIO_2_19 + >; +}; diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index 16addb3a2a1b..7d4970417dce 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -206,7 +206,7 @@ pinctrl-0 = <&pinctrl_weim>; status = "okay"; - lan9221: lan9221@5,0 { + lan9221: ethernet@5,0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lan9221>; compatible = "smsc,lan9221", "smsc,lan9115"; diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts index 9a2e1fde7128..6208fbb2e741 100644 --- a/arch/arm/boot/dts/imx53-ard.dts +++ b/arch/arm/boot/dts/imx53-ard.dts @@ -24,7 +24,7 @@ reg = <0xf4000000 0x3ff0000>; ranges; - lan9220@f4000000 { + ethernet@f4000000 { compatible = "smsc,lan9220", "smsc,lan9115"; reg = <0xf4000000 0x2000000>; phy-mode = "mii"; diff --git a/arch/arm/boot/dts/imx6dl-b105pv2.dts b/arch/arm/boot/dts/imx6dl-b105pv2.dts new file mode 100644 index 000000000000..411aa72d344b --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b105pv2.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B105Pv2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5pv2.dtsi" + +/ { + model = "General Electric B105Pv2"; + compatible = "ge,imx6dl-b105pv2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g101evn010"; + }; +}; + +&i2c3 { + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b105v2.dts b/arch/arm/boot/dts/imx6dl-b105v2.dts new file mode 100644 index 000000000000..d011127c635b --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b105v2.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B105v2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5v2.dtsi" + +/ { + model = "General Electric B105v2"; + compatible = "ge,imx6dl-b105v2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g101evn010"; + }; +}; + +&i2c3 { + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b125pv2.dts b/arch/arm/boot/dts/imx6dl-b125pv2.dts new file mode 100644 index 000000000000..ca840fa84052 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b125pv2.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B125Pv2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5pv2.dtsi" + +/ { + model = "General Electric B125Pv2"; + compatible = "ge,imx6dl-b125pv2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g121ean01"; + }; +}; + +&i2c3 { + touchscreen@2a { + compatible = "eeti,exc80h60"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b125v2.dts b/arch/arm/boot/dts/imx6dl-b125v2.dts new file mode 100644 index 000000000000..81e5a9cb8900 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b125v2.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B125v2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5v2.dtsi" + +/ { + model = "General Electric B125v2"; + compatible = "ge,imx6dl-b125v2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g121ean01"; + }; +}; + +&i2c3 { + touchscreen@2a { + compatible = "eeti,exc80h60"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b155v2.dts b/arch/arm/boot/dts/imx6dl-b155v2.dts new file mode 100644 index 000000000000..c861937b30f6 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b155v2.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B155v2 +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +/dts-v1/; +#include "imx6dl-b1x5v2.dtsi" + +/ { + model = "General Electric B155v2"; + compatible = "ge,imx6dl-b155v2", "congatec,qmx6", "fsl,imx6dl"; + + panel { + compatible = "auo,g156xtn01"; + }; +}; + +&i2c3 { + touchscreen@2a { + compatible = "eeti,exc80h84"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_q7_gpio0>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + touchscreen-inverted-x; + touchscreen-inverted-y; + reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi new file mode 100644 index 000000000000..ec5b66453156 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B1x5Pv2 +// patient monitor series +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +#include <dt-bindings/input/input.h> +#include "imx6dl-qmx6.dtsi" + +/ { + chosen { + stdout-path = &uart3; + }; + + /* Do not allow frequencies above 800MHz */ + cpus { + cpu@0 { + operating-points = < + /* kHz uV */ + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 792000 1175000 + 396000 1175000 + >; + }; + + cpu@1 { + operating-points = < + /* kHz uV */ + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 792000 1175000 + 396000 1175000 + >; + }; + }; + + reg_syspwr: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "SYS_PWR"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + reg_5v_pmc: regulator-5v-pmc { + compatible = "regulator-fixed"; + regulator-name = "5V PMC"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_syspwr>; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_syspwr>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_syspwr>; + }; + + reg_5v0_audio: regulator-5v0-audio { + compatible = "regulator-fixed"; + regulator-name = "5V0_AUDIO"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v>; + gpio = <&tca6424a 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * This must be always-on for da7212, which has some not + * properly documented dependencies for it's speaker supply + * pin. The issue manifests as speaker volume being very low. + */ + regulator-always-on; + }; + + + reg_3v3_audio: regulator-3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "3V3_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_3v3>; + pinctrl-0 = <&pinctrl_q7_hda_reset>; + pinctrl-names = "default"; + gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_2v5_audio: regulator-2v5-audio { + compatible = "regulator-fixed"; + regulator-name = "2V5_AUDIO"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + vin-supply = <®_3v3_audio>; + + }; + + reg_wlan: regulator-wlan { + compatible = "regulator-fixed"; + regulator-name = "WLAN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_sdio_power>; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <70000>; + }; + + reg_bl: regulator-backlight { + compatible = "regulator-fixed"; + regulator-name = "LED_VCC"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <®_syspwr>; + pinctrl-0 = <&pinctrl_q7_lcd_power>; + pinctrl-names = "default"; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "LCD_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v>; + }; + + usb_power: regulator-usb-power { + compatible = "regulator-fixed"; + regulator-name = "USB POWER"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v>; + }; + + charger: battery-charger { + compatible = "gpio-charger"; /* ti,bq24172 */ + charger-type = "mains"; + gpios = <&tca6424a 3 GPIO_ACTIVE_LOW>; + charge-current-limit-gpios = <&tca6424a 11 GPIO_ACTIVE_HIGH>, + <&tca6424a 12 GPIO_ACTIVE_HIGH>; + charge-current-limit-mapping = <1300000 0x0>, + <700000 0x1>, + <0 0x2>; + charge-status-gpios = <&tca6424a 6 GPIO_ACTIVE_HIGH>; + }; + + poweroff { + compatible = "gpio-poweroff"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_spi_cs1>; + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + }; + + power-button-key { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_sleep_button>; + + power-button { + label = "power button"; + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + }; + }; + + rotary-encoder-key { + compatible = "gpio-keys"; + + rotary-encoder-press { + label = "rotary-encoder press"; + gpios = <&tca6424a 0 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_ENTER>; + linux,can-disable; + }; + }; + + rotary-encoder { + compatible = "rotary-encoder"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_gpio2 &pinctrl_q7_gpio4>; + gpios = <&gpio4 26 GPIO_ACTIVE_LOW>, <&gpio1 0 GPIO_ACTIVE_LOW>; + rotary-encoder,relative-axis; + rotary-encoder,steps-per-period = <2>; + wakeup-source; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_gpio1 &pinctrl_q7_gpio3 &pinctrl_q7_gpio5>; + + alarm1 { + label = "alarm:red"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + + alarm2 { + label = "alarm:yellow"; + gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; + }; + + alarm3 { + label = "alarm:blue"; + gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_backlight_enable>; + power-supply = <®_bl>; + pwms = <&pwm4 0 5000000 0>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <179>; + enable-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + panel { + backlight = <&backlight>; + power-supply = <®_lcd>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = "Speaker", "Ext Spk"; + simple-audio-card,audio-routing = "Ext Spk", "LINE"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + }; + }; + + clk_ext_audio_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; +}; + +&audmux { + status = "okay"; +}; + +&fec { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + battery: battery@b { + compatible = "ti,bq20z65", "sbs,sbs-battery"; + reg = <0x0b>; + sbs,battery-detect-gpios = <&tca6424a 5 GPIO_ACTIVE_LOW>; + sbs,i2c-retry-count = <5>; + power-supplies = <&charger>; + }; + + codec: audio-codec@1a { + compatible = "dlg,da7212"; + reg = <0x1a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_2v5_audio>; + VDDSP-supply = <®_5v0_audio>; + VDDMIC-supply = <®_3v3_audio>; + VDDIO-supply = <®_3v3_audio>; + clocks = <&clk_ext_audio_codec>; + clock-names = "mclk"; + }; +}; + +&i2c5 { + tca6424a: gpio-controller@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + interrupt-parent = <&gpio7>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_gpio6>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-line-names = "GPIO_ROTOR#", "ACM_IO_INT", "TMP_SENSOR_IRQ", "AC_IN", + "TF_S", "BATT_T", "LED_INC_CHAR", "ACM1_OCF", + "ACM2_OCF", "ACM_IO_RST", "USB1_POWER_EN", "EGPIO_CC_CTL0", + "EGPIO_CC_CTL1", "12V_OEMNBP_EN", "CP2105_RST", "", + "SPEAKER_PA_EN", "ARM7_UPI_RESET", "ARM7_PWR_RST", "NURSE_CALL", + "MARKER_EN", "EGPIO_TOUCH_RST", "PRESSURE_INT1", "PRESSURE_INT2"; + + }; + + tmp75: temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + vs-supply = <®_3v3>; + interrupt-parent = <&tca6424a>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + status = "okay"; + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm4 { + status = "okay"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <&usb_power>; + disable-over-current; + dr_mode = "host"; + status = "okay"; + + /* + * TPS2051BDGN fault-gpio is connected to Q7[86] USB_0_1_OC_N. + * On QMX6 this is not connceted to the i.MX6, but to the USB Hub + * from &usbh1. This means, that we cannot easily detect and handle + * over-current events. Fortunately the regulator limits the current + * automatically, so the hardware is still protected. + */ +}; + +&usdhc4 { + /* WiFi module */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + no-1-8-v; + non-removable; + wakeup-source; + keep-power-in-suspend; + cap-power-off-card; + max-frequency = <25000000>; + vmmc-supply = <®_wlan>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_q7_gpio7>; + + interrupt-parent = <&gpio4>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + + tcxo-clock-frequency = <26000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi new file mode 100644 index 000000000000..a326a331508e --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for General Electric B1x5v2 +// patient monitor series +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora + +#include <dt-bindings/input/input.h> +#include "imx6dl-b1x5pv2.dtsi" + +/ { + reg_3v3_acm: regulator-3v3-acm { + compatible = "regulator-fixed"; + regulator-name = "3V3 ACM"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_3v3>; + }; +}; + +&i2c1 { + tca6416: gpio-controller@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&tca6424a 9 GPIO_ACTIVE_LOW>; + vcc-supply = <®_3v3_acm>; + gpio-line-names = "ACM1_EN", "ACM1_CL0", "ACM1_CL1", "ACM1_CL2", + "", "ACM2_EN", "ACM2_CL0", "ACM2_CL1", + "ACM2_CL2", "", "", "", + "", "", "", ""; + + /* + * The interrupt pin is connected to &tca6424a pin 1, but the Linux + * TCA6424 driver cannot handle low type interrupts at the moment + * (and support cannot be added without some ugly hacks). Since this + * controller does not have any input type GPIOs, just pretend + * that the interrupt pin is unconnected. + */ + }; +}; + +&i2c5 { + mpl3115a2: pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + vcc-supply = <®_3v3_acm>; + + /* + * The MPL3115 interrupts are connected to pin 22 and 23 + * of &tca6424a, but the binding does not yet support + * interrupts. + */ + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/imx6dl-plym2m.dts index 4d0d3d3386af..60fe5f14666e 100644 --- a/arch/arm/boot/dts/imx6dl-plym2m.dts +++ b/arch/arm/boot/dts/imx6dl-plym2m.dts @@ -138,8 +138,6 @@ interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; touchscreen-inverted-x; touchscreen-inverted-y; touchscreen-max-pressure = <4095>; @@ -147,7 +145,9 @@ ti,vref-delay-usecs = /bits/ 16 <100>; ti,x-plate-ohms = /bits/ 16 <800>; ti,y-plate-ohms = /bits/ 16 <300>; - + ti,debounce-max = /bits/ 16 <3>; + ti,debounce-tol = /bits/ 16 <70>; + ti,debounce-rep = /bits/ 16 <3>; wakeup-source; }; }; diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index ae6da241f13e..190d26642bc8 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -21,14 +21,11 @@ backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm1 0 500000>; + pwms = <&pwm1 0 500000 0>; brightness-levels = <0 20 81 248 1000>; default-brightness-level = <20>; num-interpolated-steps = <21>; power-supply = <®_bl_12v0>; - enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; }; keys { @@ -223,6 +220,24 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; + + touchscreen@0 { + compatible = "ti,tsc2046"; + reg = <0>; + pinctrl-0 = <&pinctrl_tsc>; + pinctrl-names ="default"; + spi-max-frequency = <100000>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; + pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; + touchscreen-max-pressure = <4095>; + ti,vref-delay-usecs = /bits/ 16 <100>; + ti,x-plate-ohms = /bits/ 16 <800>; + ti,y-plate-ohms = /bits/ 16 <300>; + ti,debounce-max = /bits/ 16 <3>; + ti,debounce-tol = /bits/ 16 <70>; + ti,debounce-rep = /bits/ 16 <3>; + wakeup-source; + }; }; &i2c1 { @@ -261,7 +276,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; @@ -276,8 +290,6 @@ }; &ssi1 { - #sound-dai-cells = <0>; - fsl,mode = "ac97-slave"; status = "okay"; }; @@ -285,10 +297,6 @@ status = "disabled"; }; -&vpu { - status = "disabled"; -}; - &iomuxc { pinctrl_audmux: audmuxgrp { fsl,pins = < @@ -300,12 +308,6 @@ >; }; - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 - >; - }; - pinctrl_can1phy: can1phy { fsl,pins = < /* CAN1_SR */ diff --git a/arch/arm/boot/dts/imx6dl-qmx6.dtsi b/arch/arm/boot/dts/imx6dl-qmx6.dtsi new file mode 100644 index 000000000000..150d69858255 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-qmx6.dtsi @@ -0,0 +1,612 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +// +// Device Tree Source for i.MX6DL based congatec QMX6 +// System on Module +// +// Copyright 2018-2021 General Electric Company +// Copyright 2018-2021 Collabora +// Copyright 2016 congatec AG + +#include "imx6dl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> + +/ { + memory@10000000 { + reg = <0x10000000 0x40000000>; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; + i2c-parent = <&i2c2>; + + i2c5: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c6: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + + audmux_ssi1 { + fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT6) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT6) | + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT6) + >; + }; + + audmux_aud6 { + fsl,audmux-port = <MX51_AUDMUX_PORT6>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) + >; + }; +}; + +&clks { + clocks = <&rtc_sqw>; + clock-names = "ckil"; + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf032b", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + + partition@0 { + label = "bootloader"; + reg = <0x0000000 0x100000>; + }; + + partition@100000 { + label = "user"; + reg = <0x0100000 0x2fc000>; + }; + + partition@3fc000 { + label = "reserved"; + reg = <0x03fc000 0x4000>; + read-only; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet &pinctrl_phy_reset>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + fsl,magic-packet; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@6 { + reg = <6>; + qca,clk-out-frequency = <125000000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + rtc: m41t62@68 { + compatible = "st,m41t62"; + reg = <0x68>; + + rtc_sqw: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; + +&i2c6 { + pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + /* + * keep VGEN3, VGEN4 and VGEN5 enabled in order to + * maintain backward compatibility with hw-rev. A.0 + */ + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* supply voltage for eMMC */ + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&pcie { + reset-gpio = <&gpio1 20 0>; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; +}; + +®_pu { + vin-supply = <&sw1c_reg>; +}; + +®_soc { + vin-supply = <&sw1c_reg>; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + /* Connected to USB-Hub SMSC USB2514, provides P0, P2, P3, P4 on Qseven connector */ + vbus-supply = <®_5v>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; +}; + +&usdhc2 { + /* MicroSD card slot */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc3 { + /* eMMC module */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + bus-width = <8>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + qmx6mux: imx6qdl-qmx6 { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x110b0 /* Q7[67] HDA_SDO */ + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x30b0 /* Q7[59] HDA_SYNC */ + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x30b0 /* Q7[65] HDA_SDI */ + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x30b0 /* Q7[63] HDA_BITCLK */ + >; + }; + + /* PHY is on System on Module, Q7[3-15] have Ethernet lines */ + pinctrl_enet: enet { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* PCIE_WAKE_B */ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 /* I2C multiplexer */ + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* SD4_CD# */ + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* SD4_WP */ + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x80000000 /* Camera MCLK */ + >; + }; + + pinctrl_i2c1: i2c1 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 /* Q7[66] I2C_CLK */ + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 /* Q7[68] I2C_DAT */ + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /* Q7[66] I2C_CLK */ + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0 /* Q7[68] I2C_DAT */ + >; + }; + + pinctrl_i2c2: i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 /* Q7[152] SDVO_CTRL_CLK */ + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 /* Q7[150] SDVO_CTRL_DAT */ + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 /* Q7[152] SDVO_CTRL_CLK */ + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 /* Q7[150] SDVO_CTRL_DAT */ + >; + }; + + pinctrl_i2c3: i2c3 { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 /* Q7[60] SMB_CLK */ + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 /* Q7[62] SMB_DAT */ + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* Q7[60] SMB_CLK */ + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* Q7[62] SMB_DAT */ + >; + }; + + pinctrl_phy_reset: phy-reset { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* RGMII Phy Reset */ + >; + }; + + pinctrl_pwm4: pwm4 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */ + >; + }; + + pinctrl_q7_backlight_enable: q7-backlight-enable { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* Q7[112] LVDS_BLEN */ + >; + }; + + pinctrl_q7_gpio0: q7-gpio0 { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* Q7[185] GPIO0 */ + >; + }; + + pinctrl_q7_gpio1: q7-gpio1 { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* Q7[186] GPIO1 */ + >; + }; + + pinctrl_q7_gpio2: q7-gpio2 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* Q7[187] GPIO2 */ + >; + }; + + pinctrl_q7_gpio3: q7-gpio3 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 /* Q7[188] GPIO3 */ + >; + }; + + pinctrl_q7_gpio4: q7-gpio4 { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* Q7[189] GPIO4 */ + >; + }; + + pinctrl_q7_gpio5: q7-gpio5 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* Q7[190] GPIO5 */ + >; + }; + + pinctrl_q7_gpio6: q7-gpio6 { + fsl,pins = < + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /* Q7[191] GPIO6 */ + >; + }; + + pinctrl_q7_gpio7: q7-gpio7 { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* Q7[192] GPIO7 */ + >; + }; + + pinctrl_q7_hda_reset: q7-hda-reset { + fsl,pins = < + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* Q7[61] HDA_RST_N */ + >; + }; + + pinctrl_q7_lcd_power: lcd-power { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* Q7[111] LVDS_PPEN */ + >; + }; + + pinctrl_q7_sdio_power: q7-sdio-power { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 /* Q7[47] SDIO_PWR# */ + >; + }; + + pinctrl_q7_sleep_button: q7-sleep-button { + fsl,pins = < + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* Q7[21] SLP_BTN# */ + >; + }; + + pinctrl_q7_spi_cs1: spi-cs1 { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 /* Q7[202] SPI_CS1# */ + >; + }; + + /* SPI1 bus does not leave System on Module */ + pinctrl_spi1: spi1 { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 + >; + }; + + /* Debug connector on Q7 module */ + pinctrl_uart2: uart2 { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3 { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 /* Q7[177] UART0_RX */ + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 /* Q7[171] UART0_TX */ + >; + }; + + pinctrl_usbotg: usbotg { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 /* Q7[92] USB_ID */ + >; + }; + + /* µSD card slot on Q7 module */ + pinctrl_usdhc2: usdhc2 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2_CD */ + >; + }; + + /* eMMC module on Q7 module */ + pinctrl_usdhc3: usdhc3 { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4 { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 /* Q7[45] SDIO_CMD */ + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 /* Q7[42] SDIO_CLK */ + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 /* Q7[48] SDIO_DAT1 */ + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 /* Q7[49] SDIO_DAT0 */ + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 /* Q7[50] SDIO_DAT3 */ + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 /* Q7[51] SDIO_DAT2 */ + >; + }; + + pinctrl_wdog: wdog { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 /* Watchdog output signal */ + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 065d3ab0f50a..e7d9bfbfd0e4 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -106,6 +106,8 @@ reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <1000>; + qca,smarteee-tw-us-1g = <24>; + qca,clk-out-frequency = <125000000>; }; }; }; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index 9148a01ed6d9..cb8b539eb29d 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -11,6 +11,8 @@ aliases: aliases { ethernet1 = ð1; ethernet2 = ð2; + mmc0 = &usdhc3; + mmc1 = &usdhc4; }; backlight: backlight { @@ -345,6 +347,7 @@ solomon,height = <64>; solomon,width = <128>; solomon,page-offset = <0>; + solomon,col-offset = <4>; solomon,prechargep2 = <15>; reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; vbat-supply = <&sw2_reg>; diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi index d0768ae429fa..4bf51f3ce003 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi @@ -12,10 +12,20 @@ / { aliases { + i2c0 = &i2c2; + i2c1 = &i2c1; + i2c2 = &i2c3; mmc0 = &usdhc2; mmc1 = &usdhc3; mmc2 = &usdhc4; mmc3 = &usdhc1; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + serial0 = &uart1; + serial1 = &uart5; + serial2 = &uart4; + serial3 = &uart2; + serial4 = &uart3; }; memory@10000000 { @@ -23,6 +33,19 @@ reg = <0x10000000 0x40000000>; }; + reg_eth_vio: regulator-eth-vio { + compatible = "regulator-fixed"; + gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_enet_vio>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "eth_vio"; + vin-supply = <&sw2_reg>; + }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg_vbus"; @@ -96,30 +119,40 @@ reg = <0>; max-speed = <100>; reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - reset-delay-us = <1000>; - reset-post-delay-us = <1000>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + smsc,disable-energy-detect; /* Make plugin detection reliable */ }; }; }; &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; ltc3676: pmic@3c { @@ -203,7 +236,7 @@ pagesize = <16>; }; - rtc@56 { + rtc_i2c: rtc@56 { compatible = "microcrystal,rv3029"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rtc_hw300>; @@ -260,6 +293,11 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x000b0 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b1 + >; + }; + + pinctrl_enet_vio: enet-vio-grp { + fsl,pins = < MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0 >; }; @@ -285,6 +323,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + pinctrl_i2c2: i2c2-grp { fsl,pins = < MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 @@ -292,6 +337,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + pinctrl_i2c3: i2c3-grp { fsl,pins = < MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 @@ -299,6 +351,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 + >; + }; + pinctrl_pmic_hw300: pmic-hw300-grp { fsl,pins = < MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1B0B0 diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index fa2307d8ce86..c713ac03b3b9 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -112,7 +112,7 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; phy-supply = <&vgen2_1v2_eth>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-ds.dts b/arch/arm/boot/dts/imx6q-ds.dts new file mode 100644 index 000000000000..b0a63a133977 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-ds.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2021 Dillon Min <dillon.minfei@gmail.com> +// +// Based on imx6qdl-sabresd.dtsi which is: +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-ds.dtsi" + +/ { + model = "DaSheng i.MX6 Quad Com-9xx Board"; + compatible = "ds,imx6q-sbc", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-ds.dtsi b/arch/arm/boot/dts/imx6qdl-ds.dtsi new file mode 100644 index 000000000000..f7e517555697 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-ds.dtsi @@ -0,0 +1,458 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2021 Dillon Min <dillon.minfei@gmail.com> +// +// Based on imx6qdl-sabresd.dtsi which is: +// Copyright 2012 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. + +#include <dt-bindings/clock/imx6qdl-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + chosen { + stdout-path = &uart4; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x80000000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <8>; + data-shift = <12>; /* Lines 19:12 used */ + hsync-active = <1>; + vsync-active = <1>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&ov2659_to_ipu1_csi0_mux>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_gpio>; + status = "okay"; + + m25p80: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p80", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&phy>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + reg = <1>; + qca,clk-out-frequency = <125000000>; + reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + ov2659: camera@30 { + compatible = "ovti,ov2659"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov2659>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xvclk"; + reg = <0x30>; + powerdown-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + status = "okay"; + + port { + ov2659_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + link-frequencies = /bits/ 64 <70000000>; + bus-width = <8>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + >; + }; + + pinctrl_ecspi1_gpio: ecspi1grpgpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + + pinctrl_ov2659: ov2659grp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpiogrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 + >; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + bus-width = <4>; + cd-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 7bd658b7bdda..f3236204cb5a 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -322,8 +322,8 @@ fsl,pins = < MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 >; }; @@ -410,6 +410,7 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index f824c9abd11a..0c0105468a2f 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -97,8 +97,11 @@ compatible = "fsl,imx6q-sabresd-wm8962", "fsl,imx-audio-wm8962"; model = "wm8962-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hp>; ssi-controller = <&ssi2>; audio-codec = <&codec>; + audio-asrc = <&asrc>; audio-routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", @@ -545,6 +548,13 @@ >; }; + pinctrl_hp: hpgrp { + fsl,pins = < + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index eb25d21a2ace..b9e305774fed 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -40,6 +40,27 @@ }; }; + counter-0 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter0>; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + }; + + counter-1 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter1>; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + counter-2 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter2>; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -254,7 +275,7 @@ &gpio2 { gpio-line-names = - "", "", "", "", "", "", "", "", + "count0", "count1", "count2", "", "", "", "", "", "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", "", "", "", "", "", "", "", "ON_SWITCH", @@ -572,6 +593,24 @@ >; }; + pinctrl_counter0: counter0grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000 + >; + }; + + pinctrl_counter1: counter1grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000 + >; + }; + + pinctrl_counter2: counter2grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi index b9b698f72b26..bf86b639fdac 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi @@ -142,7 +142,6 @@ imx6qdl-wandboard { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x80000000 /* USB Power Enable */ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */ diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi index 5a1e10def6ef..779cc536566d 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi @@ -60,38 +60,26 @@ gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; }; - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "mx6ul-wm8960"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Line", "Line In", - "Line", "Line Out", - "Speaker", "Speaker", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = + sound-wm8960 { + compatible = "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai2>; + audio-codec = <&codec>; + audio-asrc = <&asrc>; + hp-det-gpio = <&gpio5 4 0>; + audio-routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", - "Speaker", "SPK_LP", - "Speaker", "SPK_LN", - "Speaker", "SPK_RP", - "Speaker", "SPK_RN", - "LINPUT1", "Mic Jack", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT2", "Mic Jack", "LINPUT3", "Mic Jack", - "RINPUT1", "Mic Jack", - "RINPUT2", "Mic Jack"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&clks IMX6UL_CLK_SAI2>; - }; + "RINPUT1", "AMIC", + "RINPUT2", "AMIC", + "Mic Jack", "MICB", + "AMIC", "MICB"; }; spi4 { @@ -145,6 +133,10 @@ compatible = "wlf,wm8960"; reg = <0x1a>; wlf,shared-lrclk; + wlf,hp-cfg = <3 2 3>; + wlf,gpio-cfg = <1 3>; + clocks = <&clks IMX6UL_CLK_SAI2>; + clock-names = "mclk"; }; camera@3c { diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index ac0751bc1177..4a0d83784d7d 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -164,6 +164,13 @@ "LINPUT1", "AMIC", "AMIC", "MICB"; }; + + sound-hdmi { + compatible = "fsl,imx-audio-sii902x"; + model = "sii902x-audio"; + audio-cpu = <&sai3>; + hdmi-out; + }; }; &adc1 { diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts index 8fcd95805ff4..5b8dcc19deee 100644 --- a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts +++ b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts @@ -90,20 +90,71 @@ timeout-ms = <5000>; }; - /* The first 16MB region on the expansion bus */ - flash@50000000 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* - * 8 MB of Flash in 0x20000 byte blocks - * mapped in at 0x50000000 - */ - reg = <0x50000000 0x800000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x7e0000 */ - fis-index-block = <0x3f>; + gpio-beeper { + compatible = "gpio-beeper"; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + }; + + soc { + bus@50000000 { + /* The first 16MB region at CS0 on the expansion bus */ + flash@0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 8 MB of Flash in 0x20000 byte blocks + * mapped in at CS0. + */ + reg = <0x00000000 0x800000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; + }; + }; + }; + + pci@c0000000 { + status = "ok"; + + /* + * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant + * We have slots (IDSEL) 1, 2 and 3. + */ + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */ + <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */ + <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */ + <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */ + <0x1000 0 0 3 &gpio0 11 3>, /* INT C on slot 2 is irq 11 */ + <0x1000 0 0 4 &gpio0 8 3>, /* INT D on slot 2 is irq 8 */ + /* IDSEL 3 */ + <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */ + <0x1800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */ + <0x1800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */ + <0x1800 0 0 4 &gpio0 8 3>; /* INT D on slot 3 is irq 8 */ + }; + + ethernet@c8009000 { + status = "ok"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts b/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts new file mode 100644 index 000000000000..84158503be2a --- /dev/null +++ b/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Corentin Labbe <clabbe@baylibre.com> + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" + +/ { + model = "Welltech EPBX100"; + compatible = "welltech,epbx100", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 64 MB SDRAM */ + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 root=/dev/ram0 initrd=0x00800000,9M"; + stdout-path = "uart0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; + + flash@50000000 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 16 MB of Flash + */ + reg = <0x50000000 0x1000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "RedBoot"; + reg = <0x00000000 0x00080000>; + read-only; + }; + partition@80000 { + label = "zImage"; + reg = <0x00080000 0x00100000>; + read-only; + }; + partition@180000 { + label = "ramdisk"; + reg = <0x00180000 0x00300000>; + read-only; + }; + partition@480000 { + label = "User"; + reg = <0x00480000 0x00b60000>; + read-only; + }; + partition@fe0000 { + label = "FIS directory"; + reg = <0x00fe0000 0x001f000>; + read-only; + }; + partition@fff000 { + label = "RedBoot config"; + reg = <0x00fff000 0x0001000>; + read-only; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel-ixp42x.dtsi b/arch/arm/boot/dts/intel-ixp42x.dtsi index a9622ca850cc..5fa063ed396c 100644 --- a/arch/arm/boot/dts/intel-ixp42x.dtsi +++ b/arch/arm/boot/dts/intel-ixp42x.dtsi @@ -7,6 +7,10 @@ / { soc { + pci@c0000000 { + compatible = "intel,ixp42x-pci"; + }; + interrupt-controller@c8003000 { compatible = "intel,ixp42x-interrupt"; }; diff --git a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts index ba1163a1e1e7..60a1228a970f 100644 --- a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts +++ b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts @@ -76,19 +76,97 @@ }; }; - flash@50000000 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - /* - * 32 MB of Flash in 0x20000 byte blocks - * mapped in at 0x50000000 - */ - reg = <0x50000000 0x2000000>; - - partitions { - compatible = "redboot-fis"; - /* Eraseblock at 0x1fe0000 */ - fis-index-block = <0xff>; + soc { + bus@50000000 { + flash@0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 32 MB of Flash in 0x20000 byte blocks + * mapped in at CS0. + */ + reg = <0x00000000 0x2000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x1fe0000 */ + fis-index-block = <0xff>; + }; + }; + }; + + pci@c0000000 { + status = "ok"; + + /* + * In the boardfile for the Cambria from OpenWRT the interrupts + * are assigned one per IDSEL, so all 4 interrupts from IDSEL + * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2 + * connected to IRQ 10 etc. I find this highly unlikely so I + * have instead assumed that they are rotated (swizzled) like + * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc. + */ + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */ + <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */ + <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */ + <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */ + <0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */ + <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */ + /* IDSEL 3 */ + <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */ + <0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */ + <0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */ + <0x1800 0 0 4 &gpio0 10 3>, /* INT D on slot 3 is irq 10 */ + /* IDSEL 4 */ + <0x2000 0 0 1 &gpio0 8 3>, /* INT A on slot 3 is irq 8 */ + <0x2000 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */ + <0x2000 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */ + <0x2000 0 0 4 &gpio0 9 3>, /* INT D on slot 3 is irq 9 */ + /* IDSEL 6 */ + <0x3000 0 0 1 &gpio0 10 3>, /* INT A on slot 3 is irq 10 */ + <0x3000 0 0 2 &gpio0 9 3>, /* INT B on slot 3 is irq 9 */ + <0x3000 0 0 3 &gpio0 8 3>, /* INT C on slot 3 is irq 8 */ + <0x3000 0 0 4 &gpio0 11 3>, /* INT D on slot 3 is irq 11 */ + /* IDSEL 15 */ + <0x7800 0 0 1 &gpio0 8 3>, /* INT A on slot 3 is irq 8 */ + <0x7800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */ + <0x7800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */ + <0x7800 0 0 4 &gpio0 9 3>; /* INT D on slot 3 is irq 9 */ + }; + + ethernet@c800a000 { + status = "ok"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + }; + }; + }; + + ethernet@c800c000 { + status = "ok"; + queue-rx = <&qmgr 2>; + queue-txready = <&qmgr 19>; + phy-mode = "rgmii"; + phy-handle = <&phy2>; + intel,npe-handle = <&npe 0>; }; }; }; diff --git a/arch/arm/boot/dts/intel-ixp43x.dtsi b/arch/arm/boot/dts/intel-ixp43x.dtsi index 494fb2ff57a0..1d0817c6e3f9 100644 --- a/arch/arm/boot/dts/intel-ixp43x.dtsi +++ b/arch/arm/boot/dts/intel-ixp43x.dtsi @@ -8,6 +8,10 @@ / { soc { + pci@c0000000 { + compatible = "intel,ixp43x-pci"; + }; + interrupt-controller@c8003000 { compatible = "intel,ixp43x-interrupt"; }; diff --git a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi index f8cd506659dc..cce49e809043 100644 --- a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi +++ b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi @@ -30,5 +30,38 @@ interrupts = <33 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; + + /* This is known as EthB1 */ + ethernet@c800d000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc800d000 0x1000>; + status = "disabled"; + intel,npe = <1>; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 0>; + queue-txready = <&qmgr 0>; + }; + + /* This is known as EthB2 */ + ethernet@c800e000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc800e000 0x1000>; + status = "disabled"; + intel,npe = <2>; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 0>; + queue-txready = <&qmgr 0>; + }; + + /* This is known as EthB3 */ + ethernet@c800f000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc800f000 0x1000>; + status = "disabled"; + intel,npe = <3>; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 0>; + queue-txready = <&qmgr 0>; + }; }; }; diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi index d4a09584f417..a50427ad05e7 100644 --- a/arch/arm/boot/dts/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi @@ -14,12 +14,61 @@ compatible = "simple-bus"; interrupt-parent = <&intcon>; + /* + * The IXP4xx expansion bus is a set of 16 or 32MB + * windows in the 256MB space from 0x50000000 to + * 0x5fffffff. + */ + bus@50000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x50000000 0x10000000>; + dma-ranges = <0x00000000 0x50000000 0x10000000>; + }; + qmgr: queue-manager@60000000 { compatible = "intel,ixp4xx-ahb-queue-manager"; reg = <0x60000000 0x4000>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>; }; + pci@c0000000 { + /* compatible filled in by per-soc device tree */ + reg = <0xc0000000 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, + <9 IRQ_TYPE_LEVEL_HIGH>, + <10 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + status = "disabled"; + + ranges = + /* + * 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff + * done in 4 chunks of 16MB each. + */ + <0x02000000 0 0x48000000 0x48000000 0 0x04000000>, + /* 64KB I/O space at 0x4c000000 */ + <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>; + + /* + * This needs to map to the start of physical memory so + * PCI devices can see all (hopefully) memory. This is done + * using 4 1:1 16MB windows, so the RAM should not be more than + * 64 MB for this to work. If your memory is anywhere else + * than at 0x0 you need to alter this. + */ + dma-ranges = + <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + /* Each unique DTS using PCI must specify the swizzling */ + }; + uart0: serial@c8000000 { compatible = "intel,xscale-uart"; reg = <0xc8000000 0x1000>; @@ -61,9 +110,50 @@ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; }; - npe@c8006000 { + npe: npe@c8006000 { compatible = "intel,ixp4xx-network-processing-engine"; reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + + /* NPE-C contains a crypto accelerator */ + crypto { + compatible = "intel,ixp4xx-crypto"; + intel,npe-handle = <&npe 2>; + queue-rx = <&qmgr 30>; + queue-txready = <&qmgr 29>; + }; + }; + + /* This is known as EthB */ + ethernet@c8009000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc8009000 0x1000>; + status = "disabled"; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + intel,npe-handle = <&npe 1>; + }; + + /* This is known as EthC */ + ethernet@c800a000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc800a000 0x1000>; + status = "disabled"; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 0>; + queue-txready = <&qmgr 0>; + intel,npe-handle = <&npe 2>; + }; + + /* This is known as EthA */ + ethernet@c800c000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc800c000 0x1000>; + status = "disabled"; + intel,npe = <0>; + /* Dummy values that depend on firmware */ + queue-rx = <&qmgr 0>; + queue-txready = <&qmgr 0>; }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index 14e26a4fd62a..d800f26b6275 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -544,20 +544,15 @@ }; }; -&k2g_clks { - /* on the board 22.5792MHz is connected to AUDOSC_IN */ - assigned-clocks = <&k2g_clks 0x4c 2>; - assigned-clock-rates = <22579200>; -}; - &mcasp2 { #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcasp2_pins>; - assigned-clocks = <&k2g_clks 0x6 1>; - assigned-clock-parents = <&k2g_clks 0x6 2>; + assigned-clocks = <&k2g_clks 0x4c 2>, <&k2g_clks 0x6 1>; + assigned-clock-parents = <0>, <&k2g_clks 0x6 2>; + assigned-clock-rates = <22579200>, <0>; status = "okay"; diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 05a75019275e..37198294f4b2 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -242,7 +242,7 @@ status = "disabled"; }; - msgmgr: msgmgr@2a00000 { + msgmgr: mailbox@2a00000 { compatible = "ti,k2g-message-manager"; #mbox-cells = <2>; reg-names = "queue_proxy_region", @@ -254,7 +254,7 @@ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; }; - pmmc: pmmc@2921c00 { + pmmc: system-controller@2921c00 { compatible = "ti,k2g-sci"; /* * In case of rare platforms that does not use k2g as @@ -272,7 +272,7 @@ #power-domain-cells = <1>; }; - k2g_clks: clocks { + k2g_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 8bae6ed0abb2..bd0e864964e9 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -50,6 +50,7 @@ compatible = "amlogic,meson6-uart", "amlogic,meson-uart"; reg = <0x84c0 0x18>; interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; + fifo-size = <128>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 075d583d6f40..2273295e140f 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -60,6 +60,14 @@ clock-frequency = <32768>; status = "disabled"; }; + + xtal_div2: xtal_div2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&xtal>; + clock-div = <2>; + clock-mult = <1>; + }; }; soc: soc { @@ -101,6 +109,12 @@ mask = <0x79>; }; + watchdog@6000 { + compatible = "mstar,msc313e-wdt"; + reg = <0x6000 0x1f>; + clocks = <&xtal_div2>; + }; + intc_fiq: interrupt-controller@201310 { compatible = "mstar,mst-intc"; reg = <0x201310 0x40>; diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi index f9c2a9938898..5750ca1233cc 100644 --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi @@ -120,8 +120,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <56>; - dmas = <&sdma 27 &sdma 28>; - dma-names = "tx", "rx"; }; i2c2: i2c@48072000 { @@ -131,8 +129,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <57>; - dmas = <&sdma 29 &sdma 30>; - dma-names = "tx", "rx"; }; mcspi1: spi@48098000 { diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index 494bf6972005..bb529a2a295d 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -192,16 +192,15 @@ compatible = "ti,omap2-mailbox"; reg = <0x48094000 0x200>; interrupts = <26>, <34>; - interrupt-names = "dsp", "iva"; ti,hwmods = "mailbox"; #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <6>; - mbox_dsp: dsp { + mbox_dsp: mbox-dsp { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; - mbox_iva: iva { + mbox_iva: mbox-iva { ti,mbox-tx = <2 1 3>; ti,mbox-rx = <3 1 3>; }; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index d19d8ba3b607..23115ba61bc0 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -284,7 +284,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <6>; - mbox_dsp: dsp { + mbox_dsp: mbox-dsp { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; diff --git a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi index b4109f48ec18..e6ba30a21166 100644 --- a/arch/arm/boot/dts/omap3-evm-processor-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-processor-common.dtsi @@ -195,7 +195,7 @@ * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. */ &gpio2 { - en_usb2_port { + en-usb2-port-hog { gpio-hog; gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ output-low; diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts index fd84bbf3b9cc..9ce8d81250aa 100644 --- a/arch/arm/boot/dts/omap3-gta04a5.dts +++ b/arch/arm/boot/dts/omap3-gta04a5.dts @@ -37,7 +37,7 @@ }; &gpio5 { - irda_en { + irda-en-hog { gpio-hog; gpios = <(175-160) GPIO_ACTIVE_HIGH>; output-high; /* activate gpio_175 to disable IrDA receiver */ diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index c5b9da0d7e6c..64b7e6fddd1b 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -403,8 +403,6 @@ compatible = "ti,omap3-i2c"; reg = <0x48070000 0x80>; interrupts = <56>; - dmas = <&sdma 27 &sdma 28>; - dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; @@ -414,8 +412,6 @@ compatible = "ti,omap3-i2c"; reg = <0x48072000 0x80>; interrupts = <57>; - dmas = <&sdma 29 &sdma 30>; - dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; @@ -425,8 +421,6 @@ compatible = "ti,omap3-i2c"; reg = <0x48060000 0x80>; interrupts = <61>; - dmas = <&sdma 25 &sdma 26>; - dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; @@ -440,7 +434,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <2>; ti,mbox-num-fifos = <2>; - mbox_dsp: dsp { + mbox_dsp: mbox-dsp { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index 99721673d7af..46b8f9efd413 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -600,11 +600,11 @@ #mbox-cells = <1>; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; - mbox_ipu: mbox_ipu { + mbox_ipu: mbox-ipu { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; - mbox_dsp: mbox_dsp { + mbox_dsp: mbox-dsp { ti,mbox-tx = <3 0 0>; ti,mbox-rx = <2 0 0>; }; diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index d8f13626cfd1..45435bb88c89 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -149,7 +149,7 @@ &gpio8 { /* TI trees use GPIO instead of msecure, see also muxing */ - p234 { + msecure-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index b148b289e830..06cc3a19ddaa 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -616,11 +616,11 @@ #mbox-cells = <1>; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; - mbox_ipu: mbox_ipu { + mbox_ipu: mbox-ipu { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; - mbox_dsp: mbox_dsp { + mbox_dsp: mbox-dsp { ti,mbox-tx = <3 0 0>; ti,mbox-rx = <2 0 0>; }; diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi index 91163867be34..31f59de5190b 100644 --- a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi +++ b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi @@ -9,27 +9,27 @@ partitions { #size-cells = <1>; u-boot@0 { - reg = <0x0 0x60000>; // 384KB + reg = <0x0 0xe0000>; // 896KB label = "u-boot"; }; - u-boot-env@60000 { - reg = <0x60000 0x20000>; // 128KB + u-boot-env@e0000 { + reg = <0xe0000 0x20000>; // 128KB label = "u-boot-env"; }; - kernel@80000 { - reg = <0x80000 0x500000>; // 5MB + kernel@100000 { + reg = <0x100000 0x900000>; // 9MB label = "kernel"; }; - rofs@580000 { - reg = <0x580000 0x2a80000>; // 42.5MB + rofs@a00000 { + reg = <0xa00000 0x2000000>; // 32MB label = "rofs"; }; - rwfs@3000000 { - reg = <0x3000000 0x1000000>; // 16MB + rwfs@6000000 { + reg = <0x2a00000 0x1600000>; // 22MB label = "rwfs"; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index dace8ffeb991..0a4ffd10c484 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -581,7 +581,7 @@ * EBI2. This has a 25MHz chrystal next to it, so no * clocking is needed. */ - ethernet-ebi2@2,0 { + ethernet@2,0 { compatible = "smsc,lan9221", "smsc,lan9115"; reg = <2 0x0 0x100>; /* @@ -598,8 +598,6 @@ phy-mode = "mii"; reg-io-width = <2>; smsc,force-external-phy; - /* IRQ on edge falling = active low */ - smsc,irq-active-low; smsc,irq-push-pull; /* diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts index 282b89ce3d45..f7ea2e5dd191 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts @@ -216,6 +216,10 @@ }; }; +&adm_dma { + status = "okay"; +}; + &gmac0 { status = "okay"; @@ -251,6 +255,39 @@ status = "okay"; }; +&hs_phy_1 { + status = "okay"; +}; + +&nand { + status = "okay"; + + nandcs@0 { + compatible = "qcom,nandcs"; + reg = <0>; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + label = "RouterBoard NAND 1 Boot"; + reg = <0x0000000 0x0800000>; + }; + + main@800000 { + label = "RouterBoard NAND 1 Main"; + reg = <0x0800000 0x7800000>; + }; + }; + }; +}; + &qcom_pinmux { buttons_pins: buttons_pins { mux { @@ -305,4 +342,25 @@ input-disable; }; }; + + usb1_pwr_en_pins: usb1_pwr_en_pins { + mux { + pins = "gpio4"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + pinctrl-0 = <&usb1_pwr_en_pins>; + pinctrl-names = "default"; + + status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 98995ead4413..7bcf5ef92157 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -2,6 +2,8 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/mfd/qcom-rpm.h> +#include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/clock/qcom,gcc-ipq806x.h> #include <dt-bindings/clock/qcom,lcc-ipq806x.h> #include <dt-bindings/gpio/gpio.h> @@ -46,6 +48,228 @@ }; }; + thermal-zones { + tsens_tz_sensor0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 0>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 1>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 2>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 3>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor4 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 4>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor5 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 5>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor6 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 6>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor7 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 7>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor8 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 8>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor9 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 9>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + tsens_tz_sensor10 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 10>; + + trips { + cpu-critical { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu-hot { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; + memory { device_type = "memory"; reg = <0x0 0x0>; @@ -185,6 +409,31 @@ bias-pull-up; }; }; + + nand_pins: nand_pins { + mux { + pins = "gpio34", "gpio35", "gpio36", + "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "nand"; + drive-strength = <10>; + bias-disable; + }; + + pullups { + pins = "gpio39"; + bias-pull-up; + }; + + hold { + pins = "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47"; + bias-bus-hold; + }; + }; }; intc: interrupt-controller@2000000 { @@ -226,6 +475,26 @@ reg = <0x02098000 0x1000>, <0x02008000 0x1000>; }; + adm_dma: dma-controller@18300000 { + compatible = "qcom,adm"; + reg = <0x18300000 0x100000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; + clock-names = "core", "iface"; + + resets = <&gcc ADM0_RESET>, + <&gcc ADM0_PBUS_RESET>, + <&gcc ADM0_C0_RESET>, + <&gcc ADM0_C1_RESET>, + <&gcc ADM0_C2_RESET>; + reset-names = "clk", "pbus", "c0", "c1", "c2"; + qcom,ee = <0>; + + status = "disabled"; + }; + saw0: regulator@2089000 { compatible = "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; @@ -403,6 +672,28 @@ status = "disabled"; }; + nand: nand-controller@1ac00000 { + compatible = "qcom,ipq806x-nand"; + reg = <0x1ac00000 0x800>; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + clocks = <&gcc EBI2_CLK>, + <&gcc EBI2_AON_CLK>; + clock-names = "core", "aon"; + + dmas = <&adm_dma 3>; + dma-names = "rxtx"; + qcom,cmd-crci = <15>; + qcom,data-crci = <3>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + sata: sata@29000000 { compatible = "qcom,ipq806x-ahci", "generic-ahci"; reg = <0x29000000 0x180>; @@ -436,6 +727,12 @@ reg = <0x00700000 0x1000>; #address-cells = <1>; #size-cells = <1>; + tsens_calib: calib@400 { + reg = <0x400 0xb>; + }; + tsens_calib_backup: calib_backup@410 { + reg = <0x410 0xb>; + }; }; gcc: clock-controller@900000 { @@ -443,6 +740,38 @@ reg = <0x00900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; + + tsens: thermal-sensor@900000 { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + + #qcom,sensors = <11>; + #thermal-sensor-cells = <1>; + }; + }; + + rpm: rpm@108000 { + compatible = "qcom,rpm-ipq8064"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; + + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ack", "err", "wakeup"; + + clocks = <&gcc RPM_MSG_RAM_H_CLK>; + clock-names = "ram"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; + #clock-cells = <1>; + }; }; tcsr: syscon@1a400000 { @@ -450,6 +779,14 @@ reg = <0x1a400000 0x100>; }; + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu_l2_aux"; + }; + lcc: clock-controller@28000000 { compatible = "qcom,lcc-ipq8064"; reg = <0x28000000 0x1000>; @@ -718,6 +1055,94 @@ status = "disabled"; }; + hs_phy_0: phy@100f8800 { + compatible = "qcom,ipq806x-usb-phy-hs"; + reg = <0x100f8800 0x30>; + clocks = <&gcc USB30_0_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + ss_phy_0: phy@100f8830 { + compatible = "qcom,ipq806x-usb-phy-ss"; + reg = <0x100f8830 0x30>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + + status = "disabled"; + }; + + usb3_0: usb3@100f8800 { + compatible = "qcom,dwc3", "syscon"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x100f8800 0x8000>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "core"; + + ranges; + + resets = <&gcc USB30_0_MASTER_RESET>; + reset-names = "master"; + + status = "disabled"; + + dwc3_0: dwc3@10000000 { + compatible = "snps,dwc3"; + reg = <0x10000000 0xcd00>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + phys = <&hs_phy_0>, <&ss_phy_0>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + snps,dis_u3_susphy_quirk; + }; + }; + + hs_phy_1: phy@110f8800 { + compatible = "qcom,ipq806x-usb-phy-hs"; + reg = <0x110f8800 0x30>; + clocks = <&gcc USB30_1_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + }; + + ss_phy_1: phy@110f8830 { + compatible = "qcom,ipq806x-usb-phy-ss"; + reg = <0x110f8830 0x30>; + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + }; + + usb3_1: usb3@110f8800 { + compatible = "qcom,dwc3", "syscon"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x110f8800 0x8000>; + clocks = <&gcc USB30_1_MASTER_CLK>; + clock-names = "core"; + + ranges; + + resets = <&gcc USB30_1_MASTER_RESET>; + reset-names = "master"; + + status = "disabled"; + + dwc3_1: dwc3@11000000 { + compatible = "snps,dwc3"; + reg = <0x11000000 0xcd00>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + phys = <&hs_phy_1>, <&ss_phy_1>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + snps,dis_u3_susphy_quirk; + }; + }; + vsdcc_fixed: vsdcc-regulator { compatible = "regulator-fixed"; regulator-name = "SDCC Power"; diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts index ddcd53aa533d..2ffcd085904d 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -250,7 +250,7 @@ nand-ecc-step-size = <512>; nand-bus-width = <8>; /* efs2 partition is secured */ - secure-regions = <0x500000 0xb00000>; + secure-regions = /bits/ 64 <0x500000 0xb00000>; }; }; diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index 3065f84634b8..80c40da79604 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -250,8 +250,8 @@ nand-ecc-step-size = <512>; nand-bus-width = <8>; /* ico and efs2 partitions are secured */ - secure-regions = <0x500000 0x500000 - 0xa00000 0xb00000>; + secure-regions = /bits/ 64 <0x500000 0x500000 + 0xa00000 0xb00000>; }; }; diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index dd1b976d2a6c..a2279686ffcc 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -47,7 +47,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -56,6 +55,7 @@ clock-frequency = <1400000000>; clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; power-domains = <&sysc R8A7742_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -77,6 +77,7 @@ clock-frequency = <1400000000>; clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; power-domains = <&sysc R8A7742_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -98,6 +99,7 @@ clock-frequency = <1400000000>; clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; power-domains = <&sysc R8A7742_PD_CA15_CPU2>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -119,6 +121,7 @@ clock-frequency = <1400000000>; clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; power-domains = <&sysc R8A7742_PD_CA15_CPU3>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -750,6 +753,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 6e37b8da278b..7e5e09d210ec 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -49,7 +49,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -59,6 +58,7 @@ clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7743_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; /* kHz - uV - OPPs unknown yet */ @@ -78,6 +78,7 @@ clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7743_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; /* kHz - uV - OPPs unknown yet */ @@ -702,6 +703,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index ace20861c0c4..8419683a9d83 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -49,7 +49,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -59,6 +58,7 @@ clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7744_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; /* kHz - uV - OPPs unknown yet */ @@ -78,6 +78,7 @@ clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7744_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; /* kHz - uV - OPPs unknown yet */ @@ -702,6 +703,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index be33bdabe452..f877c51f769c 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -64,7 +64,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -73,6 +72,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; power-domains = <&sysc R8A7745_PD_CA7_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; }; @@ -83,6 +83,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; power-domains = <&sysc R8A7745_PD_CA7_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; }; @@ -645,6 +646,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index a1d7f6e7a2e3..13ef1e9bf4d5 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -25,7 +25,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -34,6 +33,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; power-domains = <&sysc R8A77470_PD_CA7_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; }; @@ -44,6 +44,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; power-domains = <&sysc R8A77470_PD_CA7_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; }; @@ -537,6 +538,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index c9f8735860bf..95efbafb0b70 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -166,6 +166,7 @@ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_I2C1>; power-domains = <&cpg_clocks>; + i2c-scl-internal-delay-ns = <5>; status = "disabled"; }; @@ -177,6 +178,7 @@ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_I2C2>; power-domains = <&cpg_clocks>; + i2c-scl-internal-delay-ns = <5>; status = "disabled"; }; @@ -188,6 +190,7 @@ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7778_CLK_I2C3>; power-domains = <&cpg_clocks>; + i2c-scl-internal-delay-ns = <5>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index d2240b89ee52..465845323495 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -145,7 +145,7 @@ status = "okay"; clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>; - clock-names = "du", "dclkin.0"; + clock-names = "du.0", "dclkin.0"; ports { port@0 { diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 74d7e9084eab..39fc58f32df6 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -198,6 +198,7 @@ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_I2C1>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <5>; status = "disabled"; }; @@ -209,6 +210,7 @@ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_I2C2>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <5>; status = "disabled"; }; @@ -220,6 +222,7 @@ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7779_CLK_I2C3>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <5>; status = "disabled"; }; @@ -463,6 +466,7 @@ reg = <0xfff80000 0x40000>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7779_CLK_DU>; + clock-names = "du.0"; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; status = "disabled"; diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 2dad0742d2ba..fa6d986b5d46 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -81,6 +81,9 @@ keyboard { compatible = "gpio-keys"; + pinctrl-0 = <&keyboard_pins>; + pinctrl-names = "default"; + one { linux,code = <KEY_1>; label = "SW2-1"; @@ -659,6 +662,11 @@ groups = "audio_clk_a"; function = "audio_clk"; }; + + keyboard_pins: keyboard { + pins = "GP_1_14", "GP_1_24", "GP_1_26", "GP_1_28"; + bias-pull-up; + }; }; ðer { diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index de29394eed63..ed6dd4fcc503 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -69,7 +69,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -78,6 +77,7 @@ clock-frequency = <1300000000>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -99,6 +99,7 @@ clock-frequency = <1300000000>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -120,6 +121,7 @@ clock-frequency = <1300000000>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU2>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -141,6 +143,7 @@ clock-frequency = <1300000000>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU3>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; voltage-tolerance = <1>; /* 1% */ @@ -162,6 +165,7 @@ clock-frequency = <780000000>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; capacity-dmips-mhz = <539>; }; @@ -173,6 +177,7 @@ clock-frequency = <780000000>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; capacity-dmips-mhz = <539>; }; @@ -184,6 +189,7 @@ clock-frequency = <780000000>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU2>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; capacity-dmips-mhz = <539>; }; @@ -195,6 +201,7 @@ clock-frequency = <780000000>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; power-domains = <&sysc R8A7790_PD_CA7_CPU3>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; capacity-dmips-mhz = <539>; }; @@ -768,6 +775,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 61e881bbbf6e..2a8b6fd9095c 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -81,7 +81,7 @@ keyboard { compatible = "gpio-keys"; - pinctrl-0 = <&sw2_pins>; + pinctrl-0 = <&keyboard_pins>; pinctrl-names = "default"; key-1 { @@ -622,7 +622,7 @@ function = "audio_clk"; }; - sw2_pins: sw2 { + keyboard_pins: keyboard { pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3"; bias-pull-up; }; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 9d8320f71a6a..0ccc162d3c2c 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -68,7 +68,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -77,6 +76,7 @@ clock-frequency = <1500000000>; clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; power-domains = <&sysc R8A7791_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; voltage-tolerance = <1>; /* 1% */ clock-latency = <300000>; /* 300 us */ @@ -97,6 +97,7 @@ clock-frequency = <1500000000>; clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; power-domains = <&sysc R8A7791_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; voltage-tolerance = <1>; /* 1% */ clock-latency = <300000>; /* 300 us */ @@ -728,6 +729,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index c100ae903a46..62aa9f61321b 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -112,6 +112,9 @@ keyboard { compatible = "gpio-keys"; + pinctrl-0 = <&keyboard_pins>; + pinctrl-names = "default"; + key-1 { linux,code = <KEY_1>; label = "SW2-1"; @@ -235,6 +238,11 @@ function = "du1"; }; + keyboard_pins: keyboard { + pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_02"; + bias-pull-up; + }; + pmic_irq_pins: pmicirq { groups = "intc_irq2"; function = "intc"; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 253e8bf643d1..9cdb73894ac2 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -45,7 +45,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -54,6 +53,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; power-domains = <&sysc R8A7792_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; }; @@ -64,6 +64,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; power-domains = <&sysc R8A7792_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA15>; }; @@ -537,6 +538,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 87fa57a99399..479e0fdf0c37 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -64,9 +64,12 @@ reg = <0 0x40000000 0 0x40000000>; }; - gpio-keys { + keyboard { compatible = "gpio-keys"; + pinctrl-0 = <&keyboard_pins>; + pinctrl-names = "default"; + key-1 { gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; linux,code = <KEY_1>; @@ -567,6 +570,11 @@ function = "audio_clk"; }; + keyboard_pins: keyboard { + pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3"; + bias-pull-up; + }; + vin0_pins: vin0 { groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk"; function = "vin0"; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 6d74475030ed..dea4b1e108af 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -60,7 +60,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -69,6 +68,7 @@ clock-frequency = <1500000000>; clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; power-domains = <&sysc R8A7793_PD_CA15_CPU0>; + enable-method = "renesas,apmu"; voltage-tolerance = <1>; /* 1% */ clock-latency = <300000>; /* 300 us */ @@ -89,6 +89,7 @@ clock-frequency = <1500000000>; clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; power-domains = <&sysc R8A7793_PD_CA15_CPU1>; + enable-method = "renesas,apmu"; voltage-tolerance = <1>; /* 1% */ clock-latency = <300000>; /* 300 us */ diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index f9dba5688d3f..f330d796a772 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "r8a7794.dtsi" #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> / { model = "Alt"; @@ -94,6 +95,42 @@ #size-cells = <1>; }; + keyboard { + compatible = "gpio-keys"; + + pinctrl-0 = <&keyboard_pins>; + pinctrl-names = "default"; + + one { + linux,code = <KEY_1>; + label = "SW2-1"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + }; + two { + linux,code = <KEY_2>; + label = "SW2-2"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; + }; + three { + linux,code = <KEY_3>; + label = "SW2-3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + }; + four { + linux,code = <KEY_4>; + label = "SW2-4"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + }; + }; + vga-encoder { compatible = "adi,adv7123"; @@ -319,6 +356,11 @@ groups = "usb1"; function = "usb1"; }; + + keyboard_pins: keyboard { + pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12"; + bias-pull-up; + }; }; &cmt0 { diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index eb89a27a6ed0..cafa3046daa4 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -45,9 +45,12 @@ reg = <0 0x40000000 0 0x40000000>; }; - gpio-keys { + keyboard { compatible = "gpio-keys"; + pinctrl-0 = <&keyboard_pins>; + pinctrl-names = "default"; + key-3 { gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; linux,code = <KEY_3>; @@ -358,6 +361,11 @@ function = "du1"; }; + keyboard_pins: keyboard { + pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12"; + bias-pull-up; + }; + ssi_pins: sound { groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; function = "ssi"; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 330dc516ecd1..eac9ed8df0be 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -62,7 +62,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -71,6 +70,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; power-domains = <&sysc R8A7794_PD_CA7_CPU0>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; }; @@ -81,6 +81,7 @@ clock-frequency = <1000000000>; clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; power-domains = <&sysc R8A7794_PD_CA7_CPU1>; + enable-method = "renesas,apmu"; next-level-cache = <&L2_CA7>; }; @@ -598,6 +599,7 @@ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 7154b827ea2f..e817eba8c622 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -390,7 +390,7 @@ }; }; - sleep { + suspend { global_pwroff: global-pwroff { rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; }; diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index e24230d50a78..ffa9bc7ed3d0 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3036-cru.h> #include <dt-bindings/soc/rockchip,boot-mode.h> +#include <dt-bindings/power/rk3036-power.h> / { #address-cells = <1>; @@ -111,10 +112,32 @@ assigned-clock-rates = <100000000>; clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; clock-names = "bus", "core"; + power-domains = <&power RK3036_PD_GPU>; resets = <&cru SRST_GPU>; status = "disabled"; }; + vpu: video-codec@10108000 { + compatible = "rockchip,rk3036-vpu"; + reg = <0x10108000 0x800>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3036_PD_VPU>; + }; + + vpu_mmu: iommu@10108800 { + compatible = "rockchip,iommu"; + reg = <0x10108800 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3036_PD_VPU>; + #iommu-cells = <0>; + }; + vop: vop@10118000 { compatible = "rockchip,rk3036-vop"; reg = <0x10118000 0x19c>; @@ -124,6 +147,7 @@ resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; reset-names = "axi", "ahb", "dclk"; iommus = <&vop_mmu>; + power-domains = <&power RK3036_PD_VIO>; status = "disabled"; vop_out: port { @@ -140,13 +164,28 @@ compatible = "rockchip,iommu"; reg = <0x10118300 0x100>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vop_mmu"; clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>; clock-names = "aclk", "iface"; + power-domains = <&power RK3036_PD_VIO>; #iommu-cells = <0>; status = "disabled"; }; + qos_gpu: qos@1012d000 { + compatible = "rockchip,rk3036-qos", "syscon"; + reg = <0x1012d000 0x20>; + }; + + qos_vpu: qos@1012e000 { + compatible = "rockchip,rk3036-qos", "syscon"; + reg = <0x1012e000 0x20>; + }; + + qos_vio: qos@1012f000 { + compatible = "rockchip,rk3036-qos", "syscon"; + reg = <0x1012f000 0x20>; + }; + gic: interrupt-controller@10139000 { compatible = "arm,gic-400"; interrupt-controller; @@ -302,6 +341,37 @@ compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; reg = <0x20008000 0x1000>; + power: power-controller { + compatible = "rockchip,rk3036-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3036_PD_VIO { + reg = <RK3036_PD_VIO>; + clocks = <&cru ACLK_LCDC>, + <&cru HCLK_LCDC>, + <&cru SCLK_LCDC>; + pm_qos = <&qos_vio>; + #power-domain-cells = <0>; + }; + + power-domain@RK3036_PD_VPU { + reg = <RK3036_PD_VPU>; + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3036_PD_GPU { + reg = <RK3036_PD_GPU>; + clocks = <&cru SCLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + }; + reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x1d8>; diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index eba7a1344976..390aa33cd55a 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -12,6 +12,11 @@ model = "bq Curie 2"; compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + }; + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts index 6b121658d93c..a66d915aa0f6 100644 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rk3066a-marsboard.dts @@ -10,6 +10,10 @@ model = "MarsBoard RK3066"; compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; + aliases { + mmc0 = &mmc0; + }; + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts index eed9e60cffa2..9790bc63b50a 100644 --- a/arch/arm/boot/dts/rk3066a-mk808.dts +++ b/arch/arm/boot/dts/rk3066a-mk808.dts @@ -10,6 +10,11 @@ model = "Rikomagic MK808"; compatible = "rikomagic,mk808", "rockchip,rk3066a"; + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + }; + chosen { stdout-path = "serial2:115200n8"; }; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 309518403d86..12b2e59aebc4 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -11,6 +11,12 @@ model = "Rayeager PX2"; compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + mmc2 = &emmc; + }; + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; @@ -58,7 +64,7 @@ }; /* input for 5V_STDBY is VSYS or DC5V, selectable by jumper J4 */ - vcc_stdby: 5v-stdby-regulator { + vcc_stdby: stdby-regulator { compatible = "regulator-fixed"; regulator-name = "5v_stdby"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 252750c97f97..f5a665b5d209 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -217,7 +217,7 @@ <150000000>, <75000000>; }; - timer@2000e000 { + timer2: timer@2000e000 { compatible = "snps,dw-apb-timer-osc"; reg = <0x2000e000 0x100>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; @@ -238,7 +238,7 @@ }; }; - timer@20038000 { + timer0: timer@20038000 { compatible = "snps,dw-apb-timer-osc"; reg = <0x20038000 0x100>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; @@ -246,7 +246,7 @@ clock-names = "timer", "pclk"; }; - timer@2003a000 { + timer1: timer@2003a000 { compatible = "snps,dw-apb-timer-osc"; reg = <0x2003a000 0x100>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -266,30 +266,6 @@ status = "disabled"; }; - usbphy: phy { - compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@17c { - #phy-cells = <0>; - reg = <0x17c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy1: usb-phy@188 { - #phy-cells = <0>; - reg = <0x188>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - }; - pinctrl: pinctrl { compatible = "rockchip,rk3066a-pinctrl"; rockchip,grf = <&grf>; @@ -702,6 +678,34 @@ power-domains = <&power RK3066_PD_GPU>; }; +&grf { + compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd"; + + usbphy: usbphy { + compatible = "rockchip,rk3066a-usb-phy", + "rockchip,rk3288-usb-phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@17c { + reg = <0x17c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + + usbphy1: usb-phy@188 { + reg = <0x188>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_xfer>; @@ -755,7 +759,7 @@ #address-cells = <1>; #size-cells = <0>; - pd_vio@RK3066_PD_VIO { + power-domain@RK3066_PD_VIO { reg = <RK3066_PD_VIO>; clocks = <&cru ACLK_LCDC0>, <&cru ACLK_LCDC1>, @@ -780,21 +784,24 @@ <&qos_cif1>, <&qos_ipp>, <&qos_rga>; + #power-domain-cells = <0>; }; - pd_video@RK3066_PD_VIDEO { + power-domain@RK3066_PD_VIDEO { reg = <RK3066_PD_VIDEO>; clocks = <&cru ACLK_VDPU>, <&cru ACLK_VEPU>, <&cru HCLK_VDPU>, <&cru HCLK_VEPU>; pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; }; - pd_gpu@RK3066_PD_GPU { + power-domain@RK3066_PD_GPU { reg = <RK3066_PD_GPU>; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; }; }; }; @@ -861,6 +868,10 @@ pinctrl-0 = <&uart3_xfer>; }; +&vpu { + power-domains = <&power RK3066_PD_VIDEO>; +}; + &wdt { compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; }; diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts index 66a0ff196eb1..85d3fce0142f 100644 --- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -13,6 +13,12 @@ model = "BQ Edison2 Quad-Core"; compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188"; + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + mmc2 = &emmc; + }; + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x80000000>; diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts index c32e1d441cf7..39c60426c9c9 100644 --- a/arch/arm/boot/dts/rk3188-px3-evb.dts +++ b/arch/arm/boot/dts/rk3188-px3-evb.dts @@ -11,6 +11,11 @@ model = "Rockchip PX3-EVB"; compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; + aliases { + mmc0 = &mmc0; + mmc1 = &emmc; + }; + chosen { stdout-path = "serial2:115200n8"; }; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index b0fef82c0a71..36c0945f43b2 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -11,6 +11,10 @@ model = "Radxa Rock"; compatible = "radxa,rock", "rockchip,rk3188"; + aliases { + mmc0 = &mmc0; + }; + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x80000000>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 2298a8d840ba..793a1b9117fe 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -150,16 +150,16 @@ compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; reg = <0x2000e000 0x20>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>; - clock-names = "timer", "pclk"; + clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>; + clock-names = "pclk", "timer"; }; timer6: timer@200380a0 { compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; reg = <0x200380a0 0x20>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>; - clock-names = "timer", "pclk"; + clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>; + clock-names = "pclk", "timer"; }; i2s0: i2s@1011a000 { @@ -214,30 +214,6 @@ }; }; - usbphy: phy { - compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@10c { - #phy-cells = <0>; - reg = <0x10c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy1: usb-phy@11c { - #phy-cells = <0>; - reg = <0x11c>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - }; - pinctrl: pinctrl { compatible = "rockchip,rk3188-pinctrl"; rockchip,grf = <&grf>; @@ -662,6 +638,34 @@ power-domains = <&power RK3188_PD_GPU>; }; +&grf{ + compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd"; + + usbphy: usbphy { + compatible = "rockchip,rk3188-usb-phy", + "rockchip,rk3288-usb-phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@10c { + reg = <0x10c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + + usbphy1: usb-phy@11c { + reg = <0x11c>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + }; +}; + &i2c0 { compatible = "rockchip,rk3188-i2c"; pinctrl-names = "default"; @@ -699,7 +703,7 @@ #address-cells = <1>; #size-cells = <0>; - pd_vio@RK3188_PD_VIO { + power-domain@RK3188_PD_VIO { reg = <RK3188_PD_VIO>; clocks = <&cru ACLK_LCDC0>, <&cru ACLK_LCDC1>, @@ -719,21 +723,24 @@ <&qos_cif0>, <&qos_ipp>, <&qos_rga>; + #power-domain-cells = <0>; }; - pd_video@RK3188_PD_VIDEO { + power-domain@RK3188_PD_VIDEO { reg = <RK3188_PD_VIDEO>; clocks = <&cru ACLK_VDPU>, <&cru ACLK_VEPU>, <&cru HCLK_VDPU>, <&cru HCLK_VEPU>; pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; }; - pd_gpu@RK3188_PD_GPU { + power-domain@RK3188_PD_GPU { reg = <RK3188_PD_GPU>; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; }; }; }; @@ -794,6 +801,11 @@ pinctrl-0 = <&uart3_xfer>; }; +&vpu { + compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu"; + power-domains = <&power RK3188_PD_VIDEO>; +}; + &wdt { compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; }; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 208f21245095..75af99c76d7e 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3228-cru.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/power/rk3228-power.h> / { #address-cells = <1>; @@ -190,7 +191,65 @@ status = "disabled"; }; - u2phy0: usb2-phy@760 { + power: power-controller { + compatible = "rockchip,rk3228-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3228_PD_VIO { + reg = <RK3228_PD_VIO>; + clocks = <&cru ACLK_HDCP>, + <&cru SCLK_HDCP>, + <&cru ACLK_IEP>, + <&cru HCLK_IEP>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>, + <&cru SCLK_RGA>; + pm_qos = <&qos_hdcp>, + <&qos_iep>, + <&qos_rga_r>, + <&qos_rga_w>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_VOP { + reg = <RK3228_PD_VOP>; + clocks =<&cru ACLK_VOP>, + <&cru DCLK_VOP>, + <&cru HCLK_VOP>; + pm_qos = <&qos_vop>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_VPU { + reg = <RK3228_PD_VPU>; + clocks = <&cru ACLK_VPU>, + <&cru HCLK_VPU>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_RKVDEC { + reg = <RK3228_PD_RKVDEC>; + clocks = <&cru ACLK_RKVDEC>, + <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + pm_qos = <&qos_rkvdec_r>, + <&qos_rkvdec_w>; + #power-domain-cells = <0>; + }; + + power-domain@RK3228_PD_GPU { + reg = <RK3228_PD_GPU>; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + }; + + u2phy0: usb2phy@760 { compatible = "rockchip,rk3228-usb2phy"; reg = <0x0760 0x0c>; clocks = <&cru SCLK_OTGPHY0>; @@ -217,7 +276,7 @@ }; }; - u2phy1: usb2-phy@800 { + u2phy1: usb2phy@800 { compatible = "rockchip,rk3228-usb2phy"; reg = <0x0800 0x0c>; clocks = <&cru SCLK_OTGPHY1>; @@ -379,7 +438,6 @@ reg = <0x110b0000 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; status = "disabled"; @@ -390,7 +448,6 @@ reg = <0x110b0010 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm1_pin>; status = "disabled"; @@ -401,7 +458,6 @@ reg = <0x110b0020 0x10>; #pwm-cells = <3>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin>; status = "disabled"; @@ -412,7 +468,6 @@ reg = <0x110b0030 0x10>; #pwm-cells = <2>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm3_pin>; status = "disabled"; @@ -517,7 +572,7 @@ pinctrl-0 = <&otp_pin>; pinctrl-1 = <&otp_out>; pinctrl-2 = <&otp_pin>; - #thermal-sensor-cells = <0>; + #thermal-sensor-cells = <1>; rockchip,hw-tshut-temp = <95000>; status = "disabled"; }; @@ -550,30 +605,54 @@ "ppmmu1"; clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; clock-names = "bus", "core"; + power-domains = <&power RK3228_PD_GPU>; resets = <&cru SRST_GPU_A>; status = "disabled"; }; + vpu: video-codec@20020000 { + compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu"; + reg = <0x20020000 0x800>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3228_PD_VPU>; + }; + vpu_mmu: iommu@20020800 { compatible = "rockchip,iommu"; reg = <0x20020800 0x100>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vpu_mmu"; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; clock-names = "aclk", "iface"; - iommu-cells = <0>; - status = "disabled"; + power-domains = <&power RK3228_PD_VPU>; + #iommu-cells = <0>; + }; + + vdec: video-codec@20030000 { + compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec"; + reg = <0x20030000 0x480>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + assigned-clock-rates = <300000000>, <300000000>; + iommus = <&vdec_mmu>; + power-domains = <&power RK3228_PD_RKVDEC>; }; vdec_mmu: iommu@20030480 { compatible = "rockchip,iommu"; reg = <0x20030480 0x40>, <0x200304c0 0x40>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vdec_mmu"; clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; clock-names = "aclk", "iface"; - iommu-cells = <0>; - status = "disabled"; + power-domains = <&power RK3228_PD_RKVDEC>; + #iommu-cells = <0>; }; vop: vop@20050000 { @@ -585,6 +664,7 @@ resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; reset-names = "axi", "ahb", "dclk"; iommus = <&vop_mmu>; + power-domains = <&power RK3228_PD_VOP>; status = "disabled"; vop_out: port { @@ -602,9 +682,9 @@ compatible = "rockchip,iommu"; reg = <0x20053f00 0x100>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vop_mmu"; clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; clock-names = "aclk", "iface"; + power-domains = <&power RK3228_PD_VOP>; #iommu-cells = <0>; status = "disabled"; }; @@ -615,6 +695,7 @@ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; clock-names = "aclk", "hclk", "sclk"; + power-domains = <&power RK3228_PD_VIO>; resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; reset-names = "core", "axi", "ahb"; }; @@ -623,10 +704,10 @@ compatible = "rockchip,iommu"; reg = <0x20070800 0x100>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "iep_mmu"; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; clock-names = "aclk", "iface"; - iommu-cells = <0>; + power-domains = <&power RK3228_PD_VIO>; + #iommu-cells = <0>; status = "disabled"; }; @@ -800,6 +881,51 @@ status = "disabled"; }; + qos_iep: qos@31030080 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030080 0x20>; + }; + + qos_rga_w: qos@31030100 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030100 0x20>; + }; + + qos_hdcp: qos@31030180 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030180 0x20>; + }; + + qos_rga_r: qos@31030200 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31030200 0x20>; + }; + + qos_vpu: qos@31040000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31040000 0x20>; + }; + + qos_gpu: qos@31050000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31050000 0x20>; + }; + + qos_vop: qos@31060000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31060000 0x20>; + }; + + qos_rkvdec_r: qos@31070000 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31070000 0x20>; + }; + + qos_rkvdec_w: qos@31070080 { + compatible = "rockchip,rk3228-qos", "syscon"; + reg = <0x31070080 0x20>; + }; + gic: interrupt-controller@32010000 { compatible = "arm,gic-400"; interrupt-controller; diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi index 44bb5e6f83b1..76363b8afcb9 100644 --- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi +++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi @@ -218,7 +218,7 @@ flash0-supply = <&vcc_flash>; flash1-supply = <&vccio_pmu>; gpio30-supply = <&vccio_pmu>; - gpio1830 = <&vcc_io>; + gpio1830-supply = <&vcc_io>; lcdc-supply = <&vcc_io>; sdcard-supply = <&vccio_sd>; wifi-supply = <&vcc_18>; diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts index aa50f8ed4ca0..b156a83eb7d7 100644 --- a/arch/arm/boot/dts/rk3288-vyasa.dts +++ b/arch/arm/boot/dts/rk3288-vyasa.dts @@ -379,10 +379,10 @@ audio-supply = <&vcc_18>; bb-supply = <&vcc_io>; dvp-supply = <&vcc_io>; - flash0-suuply = <&vcc_18>; + flash0-supply = <&vcc_18>; flash1-supply = <&vcc_lan>; gpio30-supply = <&vcc_io>; - gpio1830 = <&vcc_io>; + gpio1830-supply = <&vcc_io>; lcdc-supply = <&vcc_io>; sdcard-supply = <&vccio_sd>; wifi-supply = <&vcc_18>; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 05557ad02b33..9c5a7791a1ab 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -196,8 +196,8 @@ compatible = "rockchip,rk3288-timer"; reg = <0x0 0xff810000 0x0 0x20>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>, <&cru PCLK_TIMER>; - clock-names = "timer", "pclk"; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; }; display-subsystem { @@ -765,7 +765,7 @@ * *_HDMI HDMI * *_MIPI_* MIPI */ - pd_vio@RK3288_PD_VIO { + power-domain@RK3288_PD_VIO { reg = <RK3288_PD_VIO>; clocks = <&cru ACLK_IEP>, <&cru ACLK_ISP>, @@ -801,19 +801,21 @@ <&qos_vio2_rga_r>, <&qos_vio2_rga_w>, <&qos_vio1_isp_r>; + #power-domain-cells = <0>; }; /* * Note: The following 3 are HEVC(H.265) clocks, * and on the ACLK_HEVC_NIU (NOC). */ - pd_hevc@RK3288_PD_HEVC { + power-domain@RK3288_PD_HEVC { reg = <RK3288_PD_HEVC>; clocks = <&cru ACLK_HEVC>, <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>; pm_qos = <&qos_hevc_r>, <&qos_hevc_w>; + #power-domain-cells = <0>; }; /* @@ -821,22 +823,24 @@ * (video endecoder & decoder) clocks that on the * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). */ - pd_video@RK3288_PD_VIDEO { + power-domain@RK3288_PD_VIDEO { reg = <RK3288_PD_VIDEO>; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; pm_qos = <&qos_video>; + #power-domain-cells = <0>; }; /* * Note: ACLK_GPU is the GPU clock, * and on the ACLK_GPU_NIU (NOC). */ - pd_gpu@RK3288_PD_GPU { + power-domain@RK3288_PD_GPU { reg = <RK3288_PD_GPU>; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu_r>, <&qos_gpu_w>; + #power-domain-cells = <0>; }; }; @@ -1582,7 +1586,7 @@ drive-strength = <12>; }; - sleep { + suspend { global_pwroff: global-pwroff { rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; }; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 755c946f11de..616a828e0c6e 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -21,9 +21,6 @@ i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; - mshc0 = &emmc; - mshc1 = &mmc0; - mshc2 = &mmc1; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -50,6 +47,18 @@ status = "disabled"; }; + vpu: video-codec@10104000 { + compatible = "rockchip,rk3066-vpu"; + reg = <0x10104000 0x800>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, + <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; + clock-names = "aclk_vdpu", "hclk_vdpu", + "aclk_vepu", "hclk_vepu"; + }; + L2: cache-controller@10138000 { compatible = "arm,pl310-cache"; reg = <0x10138000 0x1000>; @@ -256,7 +265,7 @@ }; grf: grf@20008000 { - compatible = "syscon"; + compatible = "syscon", "simple-mfd"; reg = <0x20008000 0x200>; }; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 884872ca5207..9bd0acf3b708 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -265,7 +265,7 @@ #address-cells = <1>; #size-cells = <1>; - u2phy: usb2-phy@100 { + u2phy: usb2phy@100 { compatible = "rockchip,rv1108-usb2phy"; reg = <0x100 0x0c>; clocks = <&cru SCLK_USBPHY>; diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts index 5c1e12d39747..c6f39147cb96 100644 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ b/arch/arm/boot/dts/s5pv210-goni.dts @@ -358,15 +358,6 @@ reg = <0x4a>; interrupt-parent = <&gpj0>; interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - - atmel,x-line = <17>; - atmel,y-line = <11>; - atmel,x-size = <800>; - atmel,y-size = <480>; - atmel,burst-length = <0x21>; - atmel,threshold = <0x28>; - atmel,orientation = <1>; - vdd-supply = <&tsp_reg>; }; }; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index e47e1ca63043..f6e3e6f57252 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -794,7 +794,7 @@ 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ - 0x0003ff00 0x8002a800 0x00000000 /* pioD */ + 0xb003ff00 0x8002a800 0x00000000 /* pioD */ 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ >; diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts index 3cc9a23910be..a61a078ea042 100644 --- a/arch/arm/boot/dts/sd5203.dts +++ b/arch/arm/boot/dts/sd5203.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2020 Hisilicon Limited. + * Copyright (c) 2020 HiSilicon Limited. * * DTS file for Hisilicon SD5203 Board */ diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/ste-ab8500.dtsi index a16a00fb5fa5..d0fe3f9aa183 100644 --- a/arch/arm/boot/dts/ste-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-ab8500.dtsi @@ -34,7 +34,7 @@ #clock-cells = <1>; }; - ab8500_gpio: ab8500-gpio { + ab8500_gpio: ab8500-gpiocontroller { compatible = "stericsson,ab8500-gpio"; gpio-controller; #gpio-cells = <2>; @@ -42,15 +42,15 @@ ab8500-rtc { compatible = "stericsson,ab8500-rtc"; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH - 18 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <18 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "60S", "ALARM"; }; gpadc: ab8500-gpadc { compatible = "stericsson,ab8500-gpadc"; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH - 39 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH>, + <39 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "HW_CONV_END", "SW_CONV_END"; vddadc-supply = <&ab8500_ldo_tvout_reg>; #address-cells = <1>; @@ -219,13 +219,13 @@ ab8500_usb { compatible = "stericsson,ab8500-usb"; - interrupts = < 90 IRQ_TYPE_LEVEL_HIGH - 96 IRQ_TYPE_LEVEL_HIGH - 14 IRQ_TYPE_LEVEL_HIGH - 15 IRQ_TYPE_LEVEL_HIGH - 79 IRQ_TYPE_LEVEL_HIGH - 74 IRQ_TYPE_LEVEL_HIGH - 75 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, + <96 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>, + <74 IRQ_TYPE_LEVEL_HIGH>, + <75 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ID_WAKEUP_R", "ID_WAKEUP_F", "VBUS_DET_F", @@ -242,8 +242,8 @@ ab8500-ponkey { compatible = "stericsson,ab8500-poweron-key"; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH - 7 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, + <7 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; }; diff --git a/arch/arm/boot/dts/ste-ab8505.dtsi b/arch/arm/boot/dts/ste-ab8505.dtsi index cc045b2fc217..0defc15b9bbc 100644 --- a/arch/arm/boot/dts/ste-ab8505.dtsi +++ b/arch/arm/boot/dts/ste-ab8505.dtsi @@ -31,7 +31,7 @@ #clock-cells = <1>; }; - ab8505_gpio: ab8505-gpio { + ab8505_gpio: ab8505-gpiocontroller { compatible = "stericsson,ab8505-gpio"; gpio-controller; #gpio-cells = <2>; @@ -39,8 +39,8 @@ ab8500-rtc { compatible = "stericsson,ab8500-rtc"; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH - 18 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <18 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "60S", "ALARM"; }; @@ -182,13 +182,13 @@ ab8500_usb: ab8500_usb { compatible = "stericsson,ab8500-usb"; - interrupts = < 90 IRQ_TYPE_LEVEL_HIGH - 96 IRQ_TYPE_LEVEL_HIGH - 14 IRQ_TYPE_LEVEL_HIGH - 15 IRQ_TYPE_LEVEL_HIGH - 79 IRQ_TYPE_LEVEL_HIGH - 74 IRQ_TYPE_LEVEL_HIGH - 75 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, + <96 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>, + <74 IRQ_TYPE_LEVEL_HIGH>, + <75 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ID_WAKEUP_R", "ID_WAKEUP_F", "VBUS_DET_F", @@ -205,8 +205,8 @@ ab8500-ponkey { compatible = "stericsson,ab8500-poweron-key"; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH - 7 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, + <7 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; }; diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi index 4946743de7b9..3ccb7b5c7162 100644 --- a/arch/arm/boot/dts/ste-href-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi @@ -9,7 +9,7 @@ soc { prcmu@80157000 { ab8500 { - ab8500-gpio { + ab8500-gpiocontroller { /* Hog a few default settings */ pinctrl-names = "default"; pinctrl-0 = <&gpio2_default_mode>, diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi index 8d59202cebd6..37e59403c01f 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi @@ -104,6 +104,9 @@ * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>, * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>; */ + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; }; magnetometer@1e { /* Magnetometer */ @@ -136,6 +139,9 @@ /* INT2 would need to be open drain */ interrupts = <18 IRQ_TYPE_EDGE_RISING>, <19 IRQ_TYPE_EDGE_RISING>; + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; }; magnetometer@f { /* Magnetometer */ diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi index 70f058352efc..00ce9d79f540 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi @@ -89,10 +89,12 @@ <19 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&accel_tvk_mode>; + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; }; magnetometer@1e { compatible = "st,lsm303dlm-magn"; - st,drdy-int-pin = <1>; reg = <0x1e>; vdd-supply = <&ab8500_ldo_aux1_reg>; vddio-supply = <&db8500_vsmps2_reg>; diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 83b179692dff..c97e8d29004f 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> #include "ste-href-family-pinctrl.dtsi" / { @@ -64,17 +65,20 @@ reg = <0>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; + color = <LED_COLOR_ID_BLUE>; linux,default-trigger = "heartbeat"; }; chan@1 { reg = <1>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; + color = <LED_COLOR_ID_BLUE>; }; chan@2 { reg = <2>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; + color = <LED_COLOR_ID_BLUE>; }; }; lp5521@34 { @@ -88,16 +92,19 @@ reg = <0>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; + color = <LED_COLOR_ID_BLUE>; }; chan@1 { reg = <1>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; + color = <LED_COLOR_ID_BLUE>; }; chan@2 { reg = <2>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; + color = <LED_COLOR_ID_BLUE>; }; }; bh1780@29 { @@ -202,7 +209,7 @@ prcmu@80157000 { ab8500 { - ab8500-gpio { + ab8500-gpiocontroller { }; ab8500_usb { diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index b344b3748143..40f1d7c9c1d4 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -376,7 +376,7 @@ prcmu@80157000 { ab8500 { - ab8500-gpio { + ab8500-gpiocontroller { /* * AB8500 GPIOs are numbered starting from 1, so the first * index 0 is what in the datasheet is called "GPIO1", and diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index 0d43ee6583cf..40df7c61bf69 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -121,7 +121,7 @@ #size-cells = <0>; wifi@1 { - compatible = "brcm,bcm4329-fmac"; + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; reg = <1>; /* GPIO216 (WLAN_HOST_WAKE) */ @@ -162,6 +162,7 @@ pinctrl-1 = <&u0_a_1_sleep>; bluetooth { + /* BCM4334B0 actually */ compatible = "brcm,bcm4330-bt"; /* GPIO222 (BT_VREG_ON) */ shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts index f24369873ce2..25af066f6f3a 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts @@ -401,8 +401,7 @@ status = "okay"; wifi@1 { - /* Actually BRCM4330 */ - compatible = "brcm,bcm4329-fmac"; + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; reg = <1>; /* GPIO216 WL_HOST_WAKE */ interrupt-parent = <&gpio6>; @@ -436,6 +435,7 @@ status = "okay"; bluetooth { + /* BCM4330B1 actually */ compatible = "brcm,bcm4330-bt"; /* GPIO222 rail BT_VREG_EN to BT_REG_ON */ shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; @@ -583,10 +583,9 @@ accelerometer@08 { compatible = "bosch,bma222"; reg = <0x08>; - /* FIXME: no idea about this */ - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "1"; + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "-1"; vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V }; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index d28a00757d0b..94afd7a0fe1f 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -211,7 +211,7 @@ #size-cells = <0>; wifi@1 { - compatible = "brcm,bcm4329-fmac"; + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; reg = <1>; /* GPIO216 WL_HOST_WAKE */ interrupt-parent = <&gpio6>; @@ -247,6 +247,7 @@ /* FIXME: not quite working yet, probably needs regulators */ bluetooth { + /* BCM4334B0 actually */ compatible = "brcm,bcm4330-bt"; shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 7e10ae744c9d..9ac1ffe53413 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -119,17 +119,15 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "Wake up"; linux,code = <KEY_WAKEUP>; gpios = <&gpioa 0 0>; }; - button@1 { + button-1 { label = "Tamper"; linux,code = <KEY_RESTART>; gpios = <&gpioc 13 0>; diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts index ca8c192449ee..327613fd9666 100644 --- a/arch/arm/boot/dts/stm32746g-eval.dts +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -81,12 +81,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "Wake up"; linux,code = <KEY_WAKEUP>; gpios = <&gpioc 13 0>; diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 4774163af54b..155d9ffacc83 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -45,7 +45,7 @@ / { soc { - pinctrl: pin-controller { + pinctrl: pin-controller@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 3dc068b91ca1..075ac57d0bf4 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -81,12 +81,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "User"; linux,code = <KEY_HOME>; gpios = <&gpioa 0 0>; diff --git a/arch/arm/boot/dts/stm32f429-pinctrl.dtsi b/arch/arm/boot/dts/stm32f429-pinctrl.dtsi index 3e7a17d9112e..e10d7a1f3207 100644 --- a/arch/arm/boot/dts/stm32f429-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f429-pinctrl.dtsi @@ -42,54 +42,50 @@ #include "stm32f4-pinctrl.dtsi" -/ { - soc { - pinctrl: pin-controller { - compatible = "st,stm32f429-pinctrl"; +&pinctrl { + compatible = "st,stm32f429-pinctrl"; - gpioa: gpio@40020000 { - gpio-ranges = <&pinctrl 0 0 16>; - }; + gpioa: gpio@40020000 { + gpio-ranges = <&pinctrl 0 0 16>; + }; - gpiob: gpio@40020400 { - gpio-ranges = <&pinctrl 0 16 16>; - }; + gpiob: gpio@40020400 { + gpio-ranges = <&pinctrl 0 16 16>; + }; - gpioc: gpio@40020800 { - gpio-ranges = <&pinctrl 0 32 16>; - }; + gpioc: gpio@40020800 { + gpio-ranges = <&pinctrl 0 32 16>; + }; - gpiod: gpio@40020c00 { - gpio-ranges = <&pinctrl 0 48 16>; - }; + gpiod: gpio@40020c00 { + gpio-ranges = <&pinctrl 0 48 16>; + }; - gpioe: gpio@40021000 { - gpio-ranges = <&pinctrl 0 64 16>; - }; + gpioe: gpio@40021000 { + gpio-ranges = <&pinctrl 0 64 16>; + }; - gpiof: gpio@40021400 { - gpio-ranges = <&pinctrl 0 80 16>; - }; + gpiof: gpio@40021400 { + gpio-ranges = <&pinctrl 0 80 16>; + }; - gpiog: gpio@40021800 { - gpio-ranges = <&pinctrl 0 96 16>; - }; + gpiog: gpio@40021800 { + gpio-ranges = <&pinctrl 0 96 16>; + }; - gpioh: gpio@40021c00 { - gpio-ranges = <&pinctrl 0 112 16>; - }; + gpioh: gpio@40021c00 { + gpio-ranges = <&pinctrl 0 112 16>; + }; - gpioi: gpio@40022000 { - gpio-ranges = <&pinctrl 0 128 16>; - }; + gpioi: gpio@40022000 { + gpio-ranges = <&pinctrl 0 128 16>; + }; - gpioj: gpio@40022400 { - gpio-ranges = <&pinctrl 0 144 16>; - }; + gpioj: gpio@40022400 { + gpio-ranges = <&pinctrl 0 144 16>; + }; - gpiok: gpio@40022800 { - gpio-ranges = <&pinctrl 0 160 8>; - }; - }; + gpiok: gpio@40022800 { + gpio-ranges = <&pinctrl 0 160 8>; }; }; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index f6530d724d00..8748d5850298 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -283,8 +283,6 @@ }; timers13: timers@40001c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40001C00 0x400>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; @@ -299,8 +297,6 @@ }; timers14: timers@40002000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40002000 0x400>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; @@ -633,8 +629,6 @@ }; timers10: timers@40014400 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014400 0x400>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; @@ -649,8 +643,6 @@ }; timers11: timers@40014800 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014800 0x400>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; @@ -709,7 +701,7 @@ status = "disabled"; }; - rcc: rcc@40023810 { + rcc: rcc@40023800 { #reset-cells = <1>; #clock-cells = <2>; compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index 2e1b3bbbe4b5..8c982ae79f43 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -104,12 +104,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "User"; linux,code = <KEY_WAKEUP>; gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/stm32f469-pinctrl.dtsi b/arch/arm/boot/dts/stm32f469-pinctrl.dtsi index fff542662eea..6bf60263dff8 100644 --- a/arch/arm/boot/dts/stm32f469-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f469-pinctrl.dtsi @@ -42,55 +42,51 @@ #include "stm32f4-pinctrl.dtsi" -/ { - soc { - pinctrl: pin-controller { - compatible = "st,stm32f469-pinctrl"; +&pinctrl { + compatible = "st,stm32f469-pinctrl"; - gpioa: gpio@40020000 { - gpio-ranges = <&pinctrl 0 0 16>; - }; + gpioa: gpio@40020000 { + gpio-ranges = <&pinctrl 0 0 16>; + }; - gpiob: gpio@40020400 { - gpio-ranges = <&pinctrl 0 16 16>; - }; + gpiob: gpio@40020400 { + gpio-ranges = <&pinctrl 0 16 16>; + }; - gpioc: gpio@40020800 { - gpio-ranges = <&pinctrl 0 32 16>; - }; + gpioc: gpio@40020800 { + gpio-ranges = <&pinctrl 0 32 16>; + }; - gpiod: gpio@40020c00 { - gpio-ranges = <&pinctrl 0 48 16>; - }; + gpiod: gpio@40020c00 { + gpio-ranges = <&pinctrl 0 48 16>; + }; - gpioe: gpio@40021000 { - gpio-ranges = <&pinctrl 0 64 16>; - }; + gpioe: gpio@40021000 { + gpio-ranges = <&pinctrl 0 64 16>; + }; - gpiof: gpio@40021400 { - gpio-ranges = <&pinctrl 0 80 16>; - }; + gpiof: gpio@40021400 { + gpio-ranges = <&pinctrl 0 80 16>; + }; - gpiog: gpio@40021800 { - gpio-ranges = <&pinctrl 0 96 16>; - }; + gpiog: gpio@40021800 { + gpio-ranges = <&pinctrl 0 96 16>; + }; - gpioh: gpio@40021c00 { - gpio-ranges = <&pinctrl 0 112 16>; - }; + gpioh: gpio@40021c00 { + gpio-ranges = <&pinctrl 0 112 16>; + }; - gpioi: gpio@40022000 { - gpio-ranges = <&pinctrl 0 128 16>; - }; + gpioi: gpio@40022000 { + gpio-ranges = <&pinctrl 0 128 16>; + }; - gpioj: gpio@40022400 { - gpio-ranges = <&pinctrl 0 144 6>, - <&pinctrl 12 156 4>; - }; + gpioj: gpio@40022400 { + gpio-ranges = <&pinctrl 0 144 6>, + <&pinctrl 12 156 4>; + }; - gpiok: gpio@40022800 { - gpio-ranges = <&pinctrl 3 163 5>; - }; - }; + gpiok: gpio@40022800 { + gpio-ranges = <&pinctrl 3 163 5>; }; }; diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi index fe4cfda72a47..1cf8a23c2644 100644 --- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi @@ -9,7 +9,7 @@ / { soc { - pinctrl: pin-controller { + pinctrl: pin-controller@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index e1df603fc981..014b416f57e6 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -265,8 +265,6 @@ }; timers13: timers@40001c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40001C00 0x400>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; @@ -281,8 +279,6 @@ }; timers14: timers@40002000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40002000 0x400>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; @@ -364,9 +360,9 @@ status = "disabled"; }; - i2c3: i2c@40005C00 { + i2c3: i2c@40005c00 { compatible = "st,stm32f7-i2c"; - reg = <0x40005C00 0x400>; + reg = <0x40005c00 0x400>; interrupts = <72>, <73>; resets = <&rcc STM32F7_APB1_RESET(I2C3)>; @@ -531,8 +527,6 @@ }; timers10: timers@40014400 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014400 0x400>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; @@ -547,8 +541,6 @@ }; timers11: timers@40014800 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014800 0x400>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts index 0ce7fbc20fa4..be943b701980 100644 --- a/arch/arm/boot/dts/stm32f769-disco.dts +++ b/arch/arm/boot/dts/stm32f769-disco.dts @@ -75,12 +75,10 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "User"; linux,code = <KEY_HOME>; gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 05ecdf9ff03a..6e42ca2dada2 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -485,8 +485,6 @@ }; lptimer4: timer@58002c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58002c00 0x400>; clocks = <&rcc LPTIM4_CK>; @@ -501,8 +499,6 @@ }; lptimer5: timer@58003000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58003000 0x400>; clocks = <&rcc LPTIM5_CK>; diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 060baa8b7e9d..5b60ecbd718f 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -118,6 +118,39 @@ }; }; + dcmi_pins_b: dcmi-1 { + pins { + pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */ + <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ + <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ + <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */ + <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */ + <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */ + <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */ + <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */ + bias-disable; + }; + }; + + dcmi_sleep_pins_b: dcmi-sleep-1 { + pins { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */ + <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ + <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ + <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */ + <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */ + <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */ + <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */ + <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index fcd3230c469b..bd289bf5d269 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1369,8 +1369,8 @@ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; reg-names = "qspi", "qspi_mm"; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>, - <&mdma1 22 0x2 0x100008 0x0 0x0>; + dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, + <&mdma1 22 0x2 0x10100008 0x0 0x0>; dma-names = "tx", "rx"; clocks = <&rcc QSPI_K>; resets = <&rcc QSPI_R>; @@ -1416,12 +1416,6 @@ status = "disabled"; }; - stmmac_axi_config_0: stmmac-axi-config { - snps,wr_osr_lmt = <0x7>; - snps,rd_osr_lmt = <0x7>; - snps,blen = <0 0 0 0 16 8 4>; - }; - ethernet0: ethernet@5800a000 { compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; reg = <0x5800a000 0x2000>; @@ -1447,6 +1441,12 @@ snps,axi-config = <&stmmac_axi_config_0>; snps,tso; status = "disabled"; + + stmmac_axi_config_0: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; }; usbh_ohci: usb@5800c000 { diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts index 674b2d330dc4..5670b23812a2 100644 --- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -89,7 +89,7 @@ }; &pinctrl { - ltdc_pins: ltdc { + ltdc_pins: ltdc-0 { pins { pinmux = <STM32_PINMUX('G', 10, AF14)>, /* LTDC_B2 */ <STM32_PINMUX('H', 12, AF14)>, /* LTDC_R6 */ diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi index 113c48b2ef93..a4b14ef3caee 100644 --- a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi +++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi @@ -184,8 +184,6 @@ vdd_usb: ldo4 { regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; interrupts = <IT_CURLIM_LDO4 0>; }; @@ -208,7 +206,6 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -219,13 +216,13 @@ vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = <IT_OCP_OTG 0>; - regulator-active-discharge; + regulator-active-discharge = <1>; }; vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = <IT_OCP_SWOUT 0>; - regulator-active-discharge; + regulator-active-discharge = <1>; }; }; diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi index 6cf49a0a9e69..2d9461006810 100644 --- a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi @@ -173,8 +173,6 @@ vdd_usb: ldo4 { regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; interrupts = <IT_CURLIM_LDO4 0>; }; @@ -197,7 +195,6 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -213,7 +210,7 @@ vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = <IT_OCP_SWOUT 0>; - regulator-active-discharge; + regulator-active-discharge = <1>; }; }; @@ -269,7 +266,7 @@ st,neg-edge; bus-width = <8>; vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd>; mmc-ddr-3_3v; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts index a7ffec8f1516..be1dd5e9e744 100644 --- a/arch/arm/boot/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts @@ -64,7 +64,7 @@ pinctrl-0 = <&sdmmc1_b4_pins_a>; pinctrl-1 = <&sdmmc1_b4_od_pins_a>; pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + cd-gpios = <&gpioi 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; disable-wp; st,neg-edge; bus-width = <4>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index 5523f4138fd6..c5ea08fec535 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -34,7 +34,6 @@ gpio-keys-polled { compatible = "gpio-keys-polled"; - #size-cells = <0>; poll-interval = <20>; /* @@ -60,7 +59,6 @@ gpio-keys { compatible = "gpio-keys"; - #size-cells = <0>; button-1 { label = "TA2-GPIO-B"; @@ -184,12 +182,11 @@ }; - polytouch@38 { - compatible = "edt,edt-ft5x06"; + touchscreen@38 { + compatible = "edt,edt-ft5406"; reg = <0x38>; interrupt-parent = <&gpiog>; interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ - linux,wakeup; }; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 272a1a67a9ad..2af0a6752674 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -123,7 +123,6 @@ max-speed = <100>; phy-handle = <&phy0>; st,eth-ref-clk-sel; - phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; mdio0 { #address-cells = <1>; @@ -132,6 +131,13 @@ phy0: ethernet-phy@1 { reg = <1>; + /* LAN8710Ai */ + compatible = "ethernet-phy-id0007.c0f0", + "ethernet-phy-ieee802.3-c22"; + clocks = <&rcc ETHCK_K>; + reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <500>; + reset-deassert-us = <500>; interrupt-parent = <&gpioi>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; }; @@ -144,7 +150,7 @@ pinctrl-1 = <&fmc_sleep_pins_b>; status = "okay"; - ksz8851: ks8851mll@1,0 { + ksz8851: ethernet@1,0 { compatible = "micrel,ks8851-mll"; reg = <1 0x0 0x2>, <1 0x2 0x20000>; interrupt-parent = <&gpioc>; @@ -327,8 +333,6 @@ vdd_usb: ldo4 { regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; interrupts = <IT_CURLIM_LDO4 0>; }; @@ -350,7 +354,6 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -366,7 +369,7 @@ vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = <IT_OCP_SWOUT 0>; - regulator-active-discharge; + regulator-active-discharge = <1>; }; }; @@ -431,7 +434,7 @@ #size-cells = <0>; status = "okay"; - flash0: mx66l51235l@0 { + flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi index 013ae369791d..2b0ac605549d 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi @@ -198,7 +198,7 @@ #size-cells = <0>; status = "okay"; - flash0: spi-flash@0 { + flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi index 713485a95795..6706d8311a66 100644 --- a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi @@ -146,8 +146,6 @@ vdd_usb: ldo4 { regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; interrupts = <IT_CURLIM_LDO4 0>; }; @@ -171,7 +169,6 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -182,13 +179,13 @@ vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = <IT_OCP_OTG 0>; - regulator-active-discharge; + regulator-active-discharge = <1>; }; vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = <IT_OCP_SWOUT 0>; - regulator-active-discharge; + regulator-active-discharge = <1>; }; }; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 7344c37107c6..2beddbb3c518 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -198,7 +198,7 @@ }; link_codec: simple-audio-card,codec { - sound-dai = <&codec>; + sound-dai = <&codec 0>; }; }; @@ -238,7 +238,7 @@ }; codec: codec@1c22e00 { - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; compatible = "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x400>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts index 97f497854e05..d05fa679dcd3 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -85,7 +85,7 @@ pinctrl-0 = <&emac_rgmii_pins>; phy-supply = <®_gmac_3v3>; phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi new file mode 100644 index 000000000000..265e0fa57a32 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40-feta40i.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com> +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is: +// Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org> +// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> + +#include "sun8i-r40.dtsi" + +&i2c0 { + status = "okay"; + + axp22x: pmic@34 { + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +&mmc2 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_aldo2>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&pio { + pinctrl-names = "default"; + pinctrl-0 = <&clk_out_a_pin>; + vcc-pa-supply = <®_dcdc1>; + vcc-pc-supply = <®_aldo2>; + vcc-pd-supply = <®_dcdc1>; + vcc-pf-supply = <®_dldo4>; + vcc-pg-supply = <®_dldo1>; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pa"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_dldo4 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vdd2v5-sata"; +}; + +®_eldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd1v2-sata"; +}; + +®_eldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-pe"; +}; diff --git a/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts new file mode 100644 index 000000000000..0bd1336206b8 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com> +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is: +// Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org> +// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> + +/dts-v1/; +#include "sun8i-r40-feta40i.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Forlinx OKA40i-C"; + compatible = "forlinx,oka40i-c", "forlinx,feta40i-c", "allwinner,sun8i-r40"; + + aliases { + ethernet0 = &gmac; + serial0 = &uart0; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; /* RS485 */ + serial7 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-5 { /* this is how the leds are labeled on the board */ + gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */ + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + }; + + led-6 { + gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_STATUS; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN + clocks = <&ccu CLK_OUTA>; + clock-names = "ext_clock"; + }; +}; + +&ahci { + ahci-supply = <®_dldo4>; + phy-supply = <®_eldo2>; + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + phy-supply = <®_dcdc1>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 8 11 GPIO_ACTIVE_LOW>; // PI11 + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 8 10 GPIO_ACTIVE_LOW>; // PI10 + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +®_dc1sw { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-lcd"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +&tcon_tv0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pi_pins>, <&uart2_rts_cts_pi_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pg_pins>; + status = "okay"; +}; + +&uart5 { /* RS485 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart5_ph_pins>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pi_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v0>; + usb2_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index d5ad3b9efd12..291f4784e86c 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -357,6 +357,8 @@ clock-names = "ahb", "mmc"; resets = <&ccu RST_BUS_MMC3>; reset-names = "ahb"; + pinctrl-0 = <&mmc3_pins>; + pinctrl-names = "default"; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; #address-cells = <1>; @@ -602,6 +604,15 @@ }; /omit-if-no-ref/ + mmc3_pins: mmc3-pins { + pins = "PI4", "PI5", "PI6", + "PI7", "PI8", "PI9"; + function = "mmc3"; + drive-strength = <30>; + bias-pull-up; + }; + + /omit-if-no-ref/ spi0_pc_pins: spi0-pc-pins { pins = "PC0", "PC1", "PC2"; function = "spi0"; @@ -631,20 +642,65 @@ function = "spi1"; }; + /omit-if-no-ref/ uart0_pb_pins: uart0-pb-pins { pins = "PB22", "PB23"; function = "uart0"; }; + /omit-if-no-ref/ + uart2_pi_pins: uart2-pi-pins { + pins = "PI18", "PI19"; + function = "uart2"; + }; + + /omit-if-no-ref/ + uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{ + pins = "PI16", "PI17"; + function = "uart2"; + }; + + /omit-if-no-ref/ uart3_pg_pins: uart3-pg-pins { pins = "PG6", "PG7"; function = "uart3"; }; + /omit-if-no-ref/ uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { pins = "PG8", "PG9"; function = "uart3"; }; + + /omit-if-no-ref/ + uart4_pg_pins: uart4-pg-pins { + pins = "PG10", "PG11"; + function = "uart4"; + }; + + /omit-if-no-ref/ + uart5_ph_pins: uart5-ph-pins { + pins = "PH6", "PH7"; + function = "uart5"; + }; + + /omit-if-no-ref/ + uart7_pi_pins: uart7-pi-pins { + pins = "PI20", "PI21"; + function = "uart7"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; }; wdt: watchdog@1c20c90 { diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi index c279e13583ba..186c30cbe6ee 100644 --- a/arch/arm/boot/dts/sun8i-v3.dtsi +++ b/arch/arm/boot/dts/sun8i-v3.dtsi @@ -1,14 +1,40 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org> */ #include "sun8i-v3s.dtsi" +/ { + soc { + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-v3-i2s", + "allwinner,sun8i-h3-i2s"; + reg = <0x01c22000 0x400>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma 3>, <&dma 3>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_pins>; + resets = <&ccu RST_BUS_I2S0>; + status = "disabled"; + }; + }; +}; + &ccu { compatible = "allwinner,sun8i-v3-ccu"; }; +&codec_analog { + compatible = "allwinner,sun8i-v3-codec-analog", + "allwinner,sun8i-h3-codec-analog"; +}; + &emac { /delete-property/ phy-handle; /delete-property/ phy-mode; @@ -25,6 +51,11 @@ &pio { compatible = "allwinner,sun8i-v3-pinctrl"; + i2s0_pins: i2s0-pins { + pins = "PG10", "PG11", "PG12", "PG13"; + function = "i2s"; + }; + uart1_pg_pins: uart1-pg-pins { pins = "PG6", "PG7"; function = "uart1"; diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts index db5cd0b8574b..752ad05c8f83 100644 --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts @@ -49,16 +49,18 @@ compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero", "allwinner,sun8i-v3s"; + aliases { + ethernet0 = &emac; + }; + leds { /* The LEDs use PG0~2 pins, which conflict with MMC1 */ status = "disabled"; }; }; -&mmc1 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; +&emac { + allwinner,leds-active-low; status = "okay"; }; @@ -94,3 +96,10 @@ voltage = <800000>; }; }; + +&mmc1 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index eb4cb63fef13..b30bc1a25ebb 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> + * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -172,6 +173,15 @@ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; + dma: dma-controller@1c02000 { + compatible = "allwinner,sun8i-v3s-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DMA>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun8i-v3s-tcon"; reg = <0x01c0c000 0x1000>; @@ -275,6 +285,8 @@ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; clock-names = "ahb", "mod"; + dmas = <&dma 16>, <&dma 16>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_CE>; reset-names = "ahb"; }; @@ -422,6 +434,15 @@ clocks = <&osc24M>; }; + pwm: pwm@1c21400 { + compatible = "allwinner,sun8i-v3s-pwm", + "allwinner,sun7i-a20-pwm"; + reg = <0x01c21400 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x400>; @@ -429,6 +450,25 @@ status = "disabled"; }; + codec: codec@1c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-v3s-codec"; + reg = <0x01c22c00 0x400>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names = "apb", "codec"; + resets = <&ccu RST_BUS_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + allwinner,codec-analog-controls = <&codec_analog>; + status = "disabled"; + }; + + codec_analog: codec-analog@1c23000 { + compatible = "allwinner,sun8i-v3s-codec-analog"; + reg = <0x01c23000 0x4>; + }; + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; @@ -436,6 +476,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART0>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; @@ -447,6 +489,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART1>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; @@ -458,6 +502,8 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "rx", "tx"; resets = <&ccu RST_BUS_UART2>; pinctrl-0 = <&uart2_pins>; pinctrl-names = "default"; @@ -537,6 +583,8 @@ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; resets = <&ccu RST_BUS_SPI0>; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 0b678afb2a5c..8b38f123f554 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -283,7 +283,7 @@ reg = <0x0 0x60007000 0x0 0x1000>; }; - actmon@6000c800 { + actmon: actmon@6000c800 { compatible = "nvidia,tegra124-actmon"; reg = <0x0 0x6000c800 0x0 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -295,6 +295,7 @@ operating-points-v2 = <&emc_bw_dfs_opp_table>; interconnects = <&mc TEGRA124_MC_MPCORER &emc>; interconnect-names = "cpu-read"; + #cooling-cells = <2>; }; gpio: gpio@6000d000 { diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 2298fc034183..1976c383912a 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -420,11 +420,14 @@ reg = <0x1a>; interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_EDGE_BOTH>; gpio-controller; #gpio-cells = <2>; + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = < 0x0000 /* MIC_LR_OUT# GPIO, output, low */ 0x0000 /* FM2018-enable GPIO, output, low */ @@ -759,7 +762,7 @@ mmc-pwrseq = <&brcm_wifi_pwrseq>; vmmc-supply = <&vdd_3v3_sys>; - vqmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_1v8_sys>; /* Azurewave AW-NH611 BCM4329 */ wifi@1 { @@ -1030,7 +1033,7 @@ nvidia,audio-codec = <&wm8903>; nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>; nvidia,headset; @@ -1056,15 +1059,15 @@ trips { trip0: cpu-alert0 { - /* start throttling at 50C */ - temperature = <50000>; + /* start throttling at 60C */ + temperature = <60000>; hysteresis = <200>; type = "passive"; }; trip1: cpu-crit { - /* shut down at 60C */ - temperature = <60000>; + /* shut down at 70C */ + temperature = <70000>; hysteresis = <2000>; type = "critical"; }; @@ -1085,6 +1088,7 @@ emc-tables@0 { nvidia,ram-code = <0>; /* elpida-8gb */ + reg = <0>; #address-cells = <1>; #size-cells = <0>; @@ -1182,6 +1186,7 @@ emc-tables@1 { nvidia,ram-code = <1>; /* elpida-4gb */ + reg = <1>; #address-cells = <1>; #size-cells = <0>; @@ -1279,6 +1284,7 @@ emc-tables@2 { nvidia,ram-code = <2>; /* hynix-8gb */ + reg = <2>; #address-cells = <1>; #size-cells = <0>; @@ -1376,6 +1382,7 @@ emc-tables@3 { nvidia,ram-code = <3>; /* hynix-4gb */ + reg = <3>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 86494cb4d5a1..ae4312eedcbd 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -748,7 +748,7 @@ nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_HIGH>; + GPIO_ACTIVE_LOW>; nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>; nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index a348ca30e522..b31c9bca16e6 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -84,7 +84,7 @@ nvidia,audio-codec = <&wm8903>; nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; clocks = <&tegra_car TEGRA20_CLK_PLL_A>, <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 940a9f31cd86..3180bff90756 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -2,6 +2,8 @@ /dts-v1/; #include <dt-bindings/input/input.h> +#include <dt-bindings/thermal/thermal.h> + #include "tegra20.dtsi" #include "tegra20-cpu-opp.dtsi" #include "tegra20-cpu-opp-microvolt.dtsi" @@ -318,6 +320,7 @@ nvidia,ram-code = <0x0>; #address-cells = <1>; #size-cells = <0>; + reg = <0>; emc-table@166500 { reg = <166500>; @@ -497,9 +500,10 @@ }; }; - adt7461@4c { + adt7461: temperature-sensor@4c { compatible = "adi,adt7461"; reg = <0x4c>; + #thermal-sensor-cells = <1>; }; }; @@ -654,11 +658,46 @@ cpu0: cpu@0 { cpu-supply = <&cpu_vdd_reg>; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { cpu-supply = <&cpu_vdd_reg>; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <500>; /* milliseconds */ + polling-delay = <1500>; /* milliseconds */ + + thermal-sensors = <&adt7461 1>; + + trips { + trip0: cpu-alert0 { + /* start throttling at 80C */ + temperature = <80000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: cpu-crit { + /* shut down at 85C */ + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts index 378f23b2958b..5811b7006a9b 100644 --- a/arch/arm/boot/dts/tegra20-plutux.dts +++ b/arch/arm/boot/dts/tegra20-plutux.dts @@ -52,7 +52,7 @@ nvidia,audio-codec = <&wm8903>; nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; clocks = <&tegra_car TEGRA20_CLK_PLL_A>, <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index c24d4a37613e..92d494b8c3d2 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -911,7 +911,7 @@ nvidia,audio-codec = <&wm8903>; nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>; clocks = <&tegra_car TEGRA20_CLK_PLL_A>, <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index 44ced60315de..10ff09d86efa 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -61,7 +61,7 @@ nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_HIGH>; + GPIO_ACTIVE_LOW>; clocks = <&tegra_car TEGRA20_CLK_PLL_A>, <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 99a356c1ccec..5a2578b3707f 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -709,7 +709,7 @@ nvidia,audio-codec = <&wm8903>; nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>; nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index dc773b1bf8ee..ae8300baa2d4 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -927,7 +927,6 @@ compatible = "ti,bq27541"; reg = <0x55>; power-supplies = <&power_supply>; - monitored-battery = <&battery_cell>; }; power_supply: charger@6a { @@ -1252,13 +1251,6 @@ }; thermal-zones { - skin-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <0>; /* milliseconds */ - - thermal-sensors = <&nct72 0>; - }; - cpu-thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <5000>; /* milliseconds */ @@ -1274,8 +1266,8 @@ }; trip1: cpu-crit { - /* shut down at 60C */ - temperature = <60000>; + /* shut down at 65C */ + temperature = <65000>; hysteresis = <2000>; type = "critical"; }; @@ -1287,7 +1279,9 @@ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi index 17b6682ffce8..53966fa4eef2 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi @@ -182,4 +182,13 @@ enable-active-high; vin-supply = <&vdd_3v3_sys>; }; + + pmc@7000e400 { + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x3c>; + nvidia,reg-addr = <0x41>; + nvidia,reg-data = <0xe0>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi index b97da45ebdb4..9365ae607239 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi @@ -144,7 +144,16 @@ }; vdd_3v3_sys: regulator@1 { - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + pmc@7000e400 { + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x80>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 2dff14b87f3e..d9dd11569d4b 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -630,7 +630,7 @@ nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) - GPIO_ACTIVE_HIGH>; + GPIO_ACTIVE_LOW>; clocks = <&tegra_car TEGRA30_CLK_PLL_A>, <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index 9a10e0d69762..ab8744f3d72d 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -463,7 +463,9 @@ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 44a6dbba7081..c577c191be4b 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -410,7 +410,7 @@ reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ }; - actmon@6000c800 { + actmon: actmon@6000c800 { compatible = "nvidia,tegra30-actmon"; reg = <0x6000c800 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; @@ -422,6 +422,7 @@ operating-points-v2 = <&emc_bw_dfs_opp_table>; interconnects = <&mc TEGRA30_MC_MPCORER &emc>; interconnect-names = "cpu-read"; + #cooling-cells = <2>; }; gpio: gpio@6000d000 { diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts index 37bd41ff8dff..151c0220047d 100644 --- a/arch/arm/boot/dts/versatile-ab.dts +++ b/arch/arm/boot/dts/versatile-ab.dts @@ -195,16 +195,15 @@ #size-cells = <1>; ranges; - vic: intc@10140000 { + vic: interrupt-controller@10140000 { compatible = "arm,versatile-vic"; interrupt-controller; #interrupt-cells = <1>; reg = <0x10140000 0x1000>; - clear-mask = <0xffffffff>; valid-mask = <0xffffffff>; }; - sic: intc@10003000 { + sic: interrupt-controller@10003000 { compatible = "arm,versatile-sic"; interrupt-controller; #interrupt-cells = <1>; diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts index 06a0fdf24026..e7e751a858d8 100644 --- a/arch/arm/boot/dts/versatile-pb.dts +++ b/arch/arm/boot/dts/versatile-pb.dts @@ -7,7 +7,7 @@ amba { /* The Versatile PB is using more SIC IRQ lines than the AB */ - sic: intc@10003000 { + sic: interrupt-controller@10003000 { clear-mask = <0xffffffff>; /* * Valid interrupt lines mask according to diff --git a/arch/arm/configs/aspeed_g4_defconfig b/arch/arm/configs/aspeed_g4_defconfig index 58d293b63581..a3ee647b1ebb 100644 --- a/arch/arm/configs/aspeed_g4_defconfig +++ b/arch/arm/configs/aspeed_g4_defconfig @@ -254,6 +254,7 @@ CONFIG_DEBUG_INFO_REDUCED=y CONFIG_DEBUG_INFO_DWARF4=y CONFIG_GDB_SCRIPTS=y CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y CONFIG_SCHED_STACK_END_CHECK=y CONFIG_PANIC_ON_OOPS=y CONFIG_PANIC_TIMEOUT=-1 diff --git a/arch/arm/configs/aspeed_g5_defconfig b/arch/arm/configs/aspeed_g5_defconfig index 047975eccefb..2db48438c5d2 100644 --- a/arch/arm/configs/aspeed_g5_defconfig +++ b/arch/arm/configs/aspeed_g5_defconfig @@ -247,6 +247,7 @@ CONFIG_FSI_MASTER_ASPEED=y CONFIG_FSI_SCOM=y CONFIG_FSI_SBEFIFO=y CONFIG_FSI_OCC=y +CONFIG_EXT4_FS=y CONFIG_FANOTIFY=y CONFIG_OVERLAY_FS=y CONFIG_TMPFS=y @@ -276,6 +277,7 @@ CONFIG_DEBUG_INFO_REDUCED=y CONFIG_DEBUG_INFO_DWARF4=y CONFIG_GDB_SCRIPTS=y CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y CONFIG_SOFTLOCKUP_DETECTOR=y # CONFIG_DETECT_HUNG_TASK is not set CONFIG_WQ_WATCHDOG=y diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 06c888a45eb3..b1564e0aa000 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -1,6 +1,8 @@ # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_SWAP is not set CONFIG_SYSVIPC=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_BLK_DEV_INITRD=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 513f56b3c059..f4e1873912a3 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -236,6 +236,7 @@ CONFIG_DRM_SII9234=y CONFIG_DRM_TOSHIBA_TC358764=y CONFIG_DRM_LIMA=y CONFIG_DRM_PANFROST=y +CONFIG_FB=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_PWM=y diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 70928cc48939..079fcd8d1d11 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -150,6 +150,8 @@ CONFIG_USB_USBNET=y CONFIG_USB_NET_CDC_EEM=m CONFIG_USB_NET_SMSC95XX=y CONFIG_USB_NET_MCS7830=y +CONFIG_ATH10K=m +CONFIG_ATH10K_SDIO=m CONFIG_BRCMFMAC=m CONFIG_MWIFIEX=m CONFIG_MWIFIEX_SDIO=m diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig index b06e537d5149..4dfe321a79f6 100644 --- a/arch/arm/configs/integrator_defconfig +++ b/arch/arm/configs/integrator_defconfig @@ -57,10 +57,7 @@ CONFIG_DRM=y CONFIG_DRM_DISPLAY_CONNECTOR=y CONFIG_DRM_SIMPLE_BRIDGE=y CONFIG_DRM_PL111=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_MATROX=y -CONFIG_FB_MATROX_MILLENIUM=y -CONFIG_FB_MATROX_MYSTIQUE=y +CONFIG_FB=y CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_VGA_CONSOLE is not set CONFIG_LOGO=y diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig index 0d6edeb27659..9a7667383df9 100644 --- a/arch/arm/configs/ixp4xx_defconfig +++ b/arch/arm/configs/ixp4xx_defconfig @@ -109,6 +109,8 @@ CONFIG_MTD_REDBOOT_PARTS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_IXP4XX=y CONFIG_MTD_RAW_NAND=m @@ -152,6 +154,7 @@ CONFIG_INPUT_IXP4XX_BEEPER=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_OF_PLATFORM=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_SENSORS_W83781D=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 52a0400fdd92..d9abaae118dd 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -821,7 +821,7 @@ CONFIG_USB_ISP1760=y CONFIG_USB_HSIC_USB3503=y CONFIG_AB8500_USB=y CONFIG_KEYSTONE_USB_PHY=m -CONFIG_NOP_USB_XCEIV=m +CONFIG_NOP_USB_XCEIV=y CONFIG_AM335X_PHY_USB=m CONFIG_TWL6030_USB=m CONFIG_USB_GPIO_VBUS=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 77b4bea12feb..2ac2418084ab 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -276,6 +276,7 @@ CONFIG_BT_MRVL_SDIO=m CONFIG_AF_RXRPC=m CONFIG_RXKAD=y CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=m CONFIG_PCI=y CONFIG_PCI_MSI=y @@ -374,6 +375,8 @@ CONFIG_LIBERTAS_DEBUG=y CONFIG_MWIFIEX=m CONFIG_MWIFIEX_SDIO=m CONFIG_MWIFIEX_USB=m +CONFIG_WL1251=m +CONFIG_WL1251_SPI=m CONFIG_WL12XX=m CONFIG_WL18XX=m CONFIG_WLCORE_SPI=m @@ -617,6 +620,8 @@ CONFIG_LEDS_CLASS=m CONFIG_LEDS_CPCAP=m CONFIG_LEDS_LM3532=m CONFIG_LEDS_GPIO=m +CONFIG_LEDS_LP55XX_COMMON=m +CONFIG_LEDS_LP5523=m CONFIG_LEDS_PCA963X=m CONFIG_LEDS_PWM=m CONFIG_LEDS_TRIGGERS=y diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig index 483c400dd391..4c01e313099f 100644 --- a/arch/arm/configs/realview_defconfig +++ b/arch/arm/configs/realview_defconfig @@ -64,11 +64,9 @@ CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_DISPLAY_CONNECTOR=y CONFIG_DRM_SIMPLE_BRIDGE=y CONFIG_DRM_PL111=y -CONFIG_FB_MODE_HELPERS=y +CONFIG_FB=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_SOUND=y CONFIG_SND=y # CONFIG_SND_DRIVERS is not set diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index f25b09efb816..d9a27e4e0914 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -135,6 +135,7 @@ CONFIG_DRM_SII902X=y CONFIG_DRM_SIMPLE_BRIDGE=y CONFIG_DRM_I2C_ADV7511=y CONFIG_DRM_I2C_ADV7511_AUDIO=y +CONFIG_FB=y CONFIG_FB_SH_MOBILE_LCDC=y CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_AS3711=y @@ -202,7 +203,6 @@ CONFIG_AK8975=y CONFIG_PWM=y CONFIG_PWM_RCAR=y CONFIG_PWM_RENESAS_TPU=y -CONFIG_RESET_CONTROLLER=y CONFIG_PHY_RCAR_GEN2=y CONFIG_PHY_RCAR_GEN3_USB2=y # CONFIG_DNOTIFY is not set diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 13ef3e4dcbb7..3d8d8af9524d 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -167,6 +167,7 @@ CONFIG_SENSORS_LM95245=y CONFIG_THERMAL=y CONFIG_THERMAL_STATISTICS=y CONFIG_CPU_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y CONFIG_TEGRA_SOCTHERM=m CONFIG_WATCHDOG=y CONFIG_MAX77620_WATCHDOG=y diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index dbb1ef601762..3b30913d7d8d 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig @@ -61,6 +61,10 @@ CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ATMEL_MXT=y CONFIG_TOUCHSCREEN_BU21013=y CONFIG_TOUCHSCREEN_CY8CTMA140=y +CONFIG_TOUCHSCREEN_CYTTSP_CORE=y +CONFIG_TOUCHSCREEN_CYTTSP_SPI=y +CONFIG_TOUCHSCREEN_MMS114=y +CONFIG_TOUCHSCREEN_ZINITIX=y CONFIG_INPUT_MISC=y CONFIG_INPUT_AB8500_PONKEY=y CONFIG_INPUT_GPIO_VIBRA=y @@ -100,6 +104,7 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=y CONFIG_DRM_PANEL_SONY_ACX424AKP=y CONFIG_DRM_LIMA=y CONFIG_DRM_MCDE=y +CONFIG_FB=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_KTD253=y CONFIG_BACKLIGHT_GPIO=y diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig index e7ecfb365e91..b703f4757021 100644 --- a/arch/arm/configs/versatile_defconfig +++ b/arch/arm/configs/versatile_defconfig @@ -60,7 +60,7 @@ CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_DISPLAY_CONNECTOR=y CONFIG_DRM_SIMPLE_BRIDGE=y CONFIG_DRM_PL111=y -CONFIG_FB_MODE_HELPERS=y +CONFIG_FB=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_LOGO=y CONFIG_SOUND=y @@ -88,8 +88,6 @@ CONFIG_NFSD=y CONFIG_NFSD_V3=y CONFIG_NLS_CODEPAGE_850=m CONFIG_NLS_ISO8859_1=m -CONFIG_FONTS=y -CONFIG_FONT_ACORN_8x8=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig index 4479369540f2..b5e246dd23f4 100644 --- a/arch/arm/configs/vexpress_defconfig +++ b/arch/arm/configs/vexpress_defconfig @@ -11,9 +11,6 @@ CONFIG_CPUSETS=y # CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y CONFIG_PROFILING=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_VEXPRESS=y CONFIG_ARCH_VEXPRESS_DCSCB=y CONFIG_ARCH_VEXPRESS_TC2_PM=y @@ -23,14 +20,17 @@ CONFIG_MCPM=y CONFIG_VMSPLIT_2G=y CONFIG_NR_CPUS=8 CONFIG_ARM_PSCI=y -CONFIG_CMA=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="console=ttyAMA0" CONFIG_CPU_IDLE=y CONFIG_VFP=y CONFIG_NEON=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -43,7 +43,6 @@ CONFIG_IP_PNP_BOOTP=y CONFIG_NET_9P=y CONFIG_NET_9P_VIRTIO=y CONFIG_DEVTMPFS=y -CONFIG_DMA_CMA=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y @@ -59,7 +58,6 @@ CONFIG_VIRTIO_BLK=y CONFIG_BLK_DEV_SD=y CONFIG_SCSI_VIRTIO=y CONFIG_ATA=y -# CONFIG_SATA_PMP is not set CONFIG_NETDEVICES=y CONFIG_VIRTIO_NET=y CONFIG_SMC91X=y @@ -81,11 +79,9 @@ CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_SII902X=y CONFIG_DRM_PL111=y -CONFIG_FB_MODE_HELPERS=y +CONFIG_FB=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_SOUND=y CONFIG_SND=y # CONFIG_SND_DRIVERS is not set @@ -136,10 +132,11 @@ CONFIG_ROOT_NFS=y CONFIG_9P_FS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y +# CONFIG_CRYPTO_HW is not set +CONFIG_DMA_CMA=y CONFIG_DEBUG_INFO=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y CONFIG_DETECT_HUNG_TASK=y # CONFIG_SCHED_DEBUG is not set CONFIG_DEBUG_USER=y -# CONFIG_CRYPTO_HW is not set diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h index d4edab51a77c..eabe72ff7381 100644 --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h @@ -130,7 +130,7 @@ flush_pmd_entry(pudp); \ } while (0) -static inline pmd_t *pud_page_vaddr(pud_t pud) +static inline pmd_t *pud_pgtable(pud_t pud) { return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK); } diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 7693a1f05ecc..f97eb2371672 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -1130,10 +1130,7 @@ void __init setup_arch(char **cmdline_p) if (mdesc->reboot_mode != REBOOT_HARD) reboot_mode = mdesc->reboot_mode; - init_mm.start_code = (unsigned long) _text; - init_mm.end_code = (unsigned long) _etext; - init_mm.end_data = (unsigned long) _edata; - init_mm.brk = (unsigned long) _end; + setup_initial_init_mm(_text, _etext, _edata, _end); /* populate cmd_line too for later use, preserving boot_command_line */ strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE); diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 25b01da4771b..8b48326be9fd 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -55,6 +55,7 @@ void __init exynos_sysram_init(void) sysram_base_addr = of_iomap(node, 0); sysram_base_phys = of_translate_address(node, of_get_address(node, 0, NULL, NULL)); + of_node_put(node); break; } @@ -62,6 +63,7 @@ void __init exynos_sysram_init(void) if (!of_device_is_available(node)) continue; sysram_ns_base_addr = of_iomap(node, 0); + of_node_put(node); break; } } diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 9cebd360d58e..d1506ef7a537 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -35,7 +35,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o obj-$(CONFIG_HAVE_IMX_SRC) += src.o -ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),) +ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_IMX7D_CA7)$(CONFIG_SOC_LS1021A),) AFLAGS_headsmp.o :=-Wa,-march=armv7-a obj-$(CONFIG_SMP) += headsmp.o platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 474dedb73bc7..f0a073a71401 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -68,11 +68,13 @@ void imx_set_cpu_arg(int cpu, u32 arg); void v7_secondary_startup(void); void imx_scu_map_io(void); void imx_smp_prepare(void); +void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn); #else static inline void imx_scu_map_io(void) {} static inline void imx_smp_prepare(void) {} #endif void imx_src_init(void); +void imx7_src_init(void); void imx_gpc_pre_suspend(bool arm_power_off); void imx_gpc_post_resume(void); void imx_gpc_mask_all(void); @@ -131,6 +133,7 @@ static inline void imx_init_l2cache(void) {} #endif extern const struct smp_operations imx_smp_ops; +extern const struct smp_operations imx7_smp_ops; extern const struct smp_operations ls1021a_smp_ops; #endif diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S index 766dbdb2ae27..fcba58be8e79 100644 --- a/arch/arm/mach-imx/headsmp.S +++ b/arch/arm/mach-imx/headsmp.S @@ -21,6 +21,15 @@ diag_reg_offset: ENTRY(v7_secondary_startup) ARM_BE8(setend be) @ go BE8 if entered LE + mrc p15, 0, r0, c0, c0, 0 + lsl r0, r0, #16 + lsr r0, r0, #20 + /* 0xc07 is cortex A7's ID */ + mov r1, #0xc00 + orr r1, #0x7 + cmp r0, r1 + beq secondary_startup + set_diag_reg b secondary_startup ENDPROC(v7_secondary_startup) diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c index 82e22398d43d..e24a46dc5703 100644 --- a/arch/arm/mach-imx/hotplug.c +++ b/arch/arm/mach-imx/hotplug.c @@ -11,6 +11,7 @@ #include <asm/proc-fns.h> #include "common.h" +#include "hardware.h" /* * platform-specific code to shutdown a CPU @@ -40,5 +41,7 @@ int imx_cpu_kill(unsigned int cpu) return 0; imx_enable_cpu(cpu, false); imx_set_cpu_arg(cpu, 0); + if (cpu_is_imx7d()) + imx_gpcv2_set_core1_pdn_pup_by_software(true); return 1; } diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c index f4da205f57db..a2d35f9ba474 100644 --- a/arch/arm/mach-imx/mach-imx50.c +++ b/arch/arm/mach-imx/mach-imx50.c @@ -9,6 +9,12 @@ #include <asm/mach/arch.h> #include "common.h" +#include "hardware.h" + +static void __init imx50_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MX50); +} static const char * const imx50_dt_board_compat[] __initconst = { "fsl,imx50", @@ -16,5 +22,6 @@ static const char * const imx50_dt_board_compat[] __initconst = { }; DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)") + .init_early = imx50_init_early, .dt_compat = imx50_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 703998ebb52e..11dcc369ec14 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -40,27 +40,6 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev) return 0; } -static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val) -{ - phy_write(dev, 0x0d, device); - phy_write(dev, 0x0e, reg); - phy_write(dev, 0x0d, (1 << 14) | device); - phy_write(dev, 0x0e, val); -} - -static int ksz9031rn_phy_fixup(struct phy_device *dev) -{ - /* - * min rx data delay, max rx/tx clock delay, - * min rx/tx control delay - */ - mmd_write_reg(dev, 2, 4, 0); - mmd_write_reg(dev, 2, 5, 0); - mmd_write_reg(dev, 2, 8, 0x003ff); - - return 0; -} - /* * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High * as they are used for slots1-7 PERST# @@ -89,75 +68,11 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup); -static int ar8031_phy_fixup(struct phy_device *dev) -{ - u16 val; - - /* To enable AR8031 output a 125MHz clk from CLK_25M */ - phy_write(dev, 0xd, 0x7); - phy_write(dev, 0xe, 0x8016); - phy_write(dev, 0xd, 0x4007); - - val = phy_read(dev, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(dev, 0xe, val); - - /* introduce tx clock delay */ - phy_write(dev, 0x1d, 0x5); - val = phy_read(dev, 0x1e); - val |= 0x0100; - phy_write(dev, 0x1e, val); - - return 0; -} - -#define PHY_ID_AR8031 0x004dd074 - -static int ar8035_phy_fixup(struct phy_device *dev) -{ - u16 val; - - /* Ar803x phy SmartEEE feature cause link status generates glitch, - * which cause ethernet link down/up issue, so disable SmartEEE - */ - phy_write(dev, 0xd, 0x3); - phy_write(dev, 0xe, 0x805d); - phy_write(dev, 0xd, 0x4003); - - val = phy_read(dev, 0xe); - phy_write(dev, 0xe, val & ~(1 << 8)); - - /* - * Enable 125MHz clock from CLK_25M on the AR8031. This - * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad. - * Also, introduce a tx clock delay. - * - * This is the same as is the AR8031 fixup. - */ - ar8031_phy_fixup(dev); - - /*check phy power*/ - val = phy_read(dev, 0x0); - if (val & BMCR_PDOWN) - phy_write(dev, 0x0, val & ~BMCR_PDOWN); - - return 0; -} - -#define PHY_ID_AR8035 0x004dd072 - static void __init imx6q_enet_phy_init(void) { if (IS_BUILTIN(CONFIG_PHYLIB)) { phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, ksz9021rn_phy_fixup); - phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, - ksz9031rn_phy_fixup); - phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffef, - ar8031_phy_fixup); - phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef, - ar8035_phy_fixup); } } @@ -257,9 +172,6 @@ static void __init imx6q_init_machine(void) imx_get_soc_revision()); imx6q_enet_phy_init(); - - of_platform_default_populate(NULL, NULL, NULL); - imx_anatop_init(); cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init(); imx6q_1588_init(); diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c index 781e2a94fdd7..e65ed5218f53 100644 --- a/arch/arm/mach-imx/mach-imx6sx.c +++ b/arch/arm/mach-imx/mach-imx6sx.c @@ -15,31 +15,6 @@ #include "common.h" #include "cpuidle.h" -static int ar8031_phy_fixup(struct phy_device *dev) -{ - u16 val; - - /* Set RGMII IO voltage to 1.8V */ - phy_write(dev, 0x1d, 0x1f); - phy_write(dev, 0x1e, 0x8); - - /* introduce tx clock delay */ - phy_write(dev, 0x1d, 0x5); - val = phy_read(dev, 0x1e); - val |= 0x0100; - phy_write(dev, 0x1e, val); - - return 0; -} - -#define PHY_ID_AR8031 0x004dd074 -static void __init imx6sx_enet_phy_init(void) -{ - if (IS_BUILTIN(CONFIG_PHYLIB)) - phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, - ar8031_phy_fixup); -} - static void __init imx6sx_enet_clk_sel(void) { struct regmap *gpr; @@ -57,7 +32,6 @@ static void __init imx6sx_enet_clk_sel(void) static inline void imx6sx_enet_init(void) { - imx6sx_enet_phy_init(); imx6sx_enet_clk_sel(); } diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c index 879c35929a13..6fdd06bcf988 100644 --- a/arch/arm/mach-imx/mach-imx7d.c +++ b/arch/arm/mach-imx/mach-imx7d.c @@ -14,25 +14,6 @@ #include "common.h" -static int ar8031_phy_fixup(struct phy_device *dev) -{ - u16 val; - - /* Set RGMII IO voltage to 1.8V */ - phy_write(dev, 0x1d, 0x1f); - phy_write(dev, 0x1e, 0x8); - - /* disable phy AR8031 SmartEEE function. */ - phy_write(dev, 0xd, 0x3); - phy_write(dev, 0xe, 0x805d); - phy_write(dev, 0xd, 0x4003); - val = phy_read(dev, 0xe); - val &= ~(0x1 << 8); - phy_write(dev, 0xe, val); - - return 0; -} - static int bcm54220_phy_fixup(struct phy_device *dev) { /* enable RXC skew select RGMII copper mode */ @@ -44,14 +25,11 @@ static int bcm54220_phy_fixup(struct phy_device *dev) return 0; } -#define PHY_ID_AR8031 0x004dd074 #define PHY_ID_BCM54220 0x600d8589 static void __init imx7d_enet_phy_init(void) { if (IS_BUILTIN(CONFIG_PHYLIB)) { - phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, - ar8031_phy_fixup); phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff, bcm54220_phy_fixup); } @@ -91,7 +69,7 @@ static void __init imx7d_init_late(void) static void __init imx7d_init_irq(void) { imx_init_revision_from_anatop(); - imx_src_init(); + imx7_src_init(); irqchip_init(); } @@ -102,6 +80,7 @@ static const char *const imx7d_dt_compat[] __initconst = { }; DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)") + .smp = smp_ops(imx7_smp_ops), .init_irq = imx7d_init_irq, .init_machine = imx7d_init_machine, .init_late = imx7d_init_late, diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c index cf4e9335831c..972639038be5 100644 --- a/arch/arm/mach-imx/platsmp.c +++ b/arch/arm/mach-imx/platsmp.c @@ -92,6 +92,32 @@ const struct smp_operations imx_smp_ops __initconst = { #endif }; +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. + */ +static void __init imx7_smp_init_cpus(void) +{ + struct device_node *np; + int i, ncores = 0; + + /* The iMX7D SCU does not report core count, get it from DT */ + for_each_of_cpu_node(np) + ncores++; + + for (i = ncores; i < NR_CPUS; i++) + set_cpu_possible(i, false); +} + +const struct smp_operations imx7_smp_ops __initconst = { + .smp_init_cpus = imx7_smp_init_cpus, + .smp_boot_secondary = imx_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = imx_cpu_die, + .cpu_kill = imx_cpu_kill, +#endif +}; + #define DCFG_CCSR_SCRATCHRW1 0x200 static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle) diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index f52f371292ac..95fd1fbb0826 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c @@ -6,15 +6,19 @@ #include <linux/init.h> #include <linux/io.h> +#include <linux/iopoll.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/reset-controller.h> #include <linux/smp.h> #include <asm/smp_plat.h> #include "common.h" +#include "hardware.h" #define SRC_SCR 0x000 -#define SRC_GPR1 0x020 +#define SRC_GPR1_V1 0x020 +#define SRC_GPR1_V2 0x074 +#define SRC_GPR1(gpr_v2) ((gpr_v2) ? SRC_GPR1_V2 : SRC_GPR1_V1) #define BP_SRC_SCR_WARM_RESET_ENABLE 0 #define BP_SRC_SCR_SW_GPU_RST 1 #define BP_SRC_SCR_SW_VPU_RST 2 @@ -23,9 +27,18 @@ #define BP_SRC_SCR_SW_IPU2_RST 12 #define BP_SRC_SCR_CORE1_RST 14 #define BP_SRC_SCR_CORE1_ENABLE 22 +/* below is for i.MX7D */ +#define SRC_A7RCR1 0x008 +#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1 +#define GPC_CPU_PGC_SW_PUP_REQ 0xf0 +#define GPC_CPU_PGC_SW_PDN_REQ 0xfc +#define GPC_PGC_C1 0x840 +#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2 static void __iomem *src_base; static DEFINE_SPINLOCK(scr_lock); +static bool gpr_v2; +static void __iomem *gpc_base; static const int sw_reset_bits[5] = { BP_SRC_SCR_SW_GPU_RST, @@ -73,17 +86,64 @@ static struct reset_controller_dev imx_reset_controller = { .nr_resets = ARRAY_SIZE(sw_reset_bits), }; +static void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset) +{ + writel_relaxed(enable, gpc_base + offset); +} + +/* + * The motivation for bringing up the second i.MX7D core inside the kernel + * is that legacy vendor bootloaders usually do not implement PSCI support. + * This is a significant blocker for systems in the field that are running old + * bootloader versions to upgrade to a modern mainline kernel version, as only + * one CPU of the i.MX7D would be brought up. + * Bring up the second i.MX7D core inside the kernel to make the migration + * path to mainline kernel easier for the existing iMX7D users. + */ +void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn) +{ + u32 reg = pdn ? GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ; + u32 val, pup; + int ret; + + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1); + val = readl_relaxed(gpc_base + reg); + val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7; + writel_relaxed(val, gpc_base + reg); + + ret = readl_relaxed_poll_timeout_atomic(gpc_base + reg, pup, + !(pup & BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7), + 5, 1000000); + if (ret < 0) { + pr_err("i.MX7D: CORE1_A7 power up timeout\n"); + val &= ~BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7; + writel_relaxed(val, gpc_base + reg); + } + + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1); +} + void imx_enable_cpu(int cpu, bool enable) { u32 mask, val; cpu = cpu_logical_map(cpu); - mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); spin_lock(&scr_lock); - val = readl_relaxed(src_base + SRC_SCR); - val = enable ? val | mask : val & ~mask; - val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1); - writel_relaxed(val, src_base + SRC_SCR); + if (gpr_v2) { + if (enable) + imx_gpcv2_set_core1_pdn_pup_by_software(false); + + mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1); + val = readl_relaxed(src_base + SRC_A7RCR1); + val = enable ? val | mask : val & ~mask; + writel_relaxed(val, src_base + SRC_A7RCR1); + } else { + mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); + val = readl_relaxed(src_base + SRC_SCR); + val = enable ? val | mask : val & ~mask; + val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1); + writel_relaxed(val, src_base + SRC_SCR); + } spin_unlock(&scr_lock); } @@ -91,19 +151,19 @@ void imx_set_cpu_jump(int cpu, void *jump_addr) { cpu = cpu_logical_map(cpu); writel_relaxed(__pa_symbol(jump_addr), - src_base + SRC_GPR1 + cpu * 8); + src_base + SRC_GPR1(gpr_v2) + cpu * 8); } u32 imx_get_cpu_arg(int cpu) { cpu = cpu_logical_map(cpu); - return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4); + return readl_relaxed(src_base + SRC_GPR1(gpr_v2) + cpu * 8 + 4); } void imx_set_cpu_arg(int cpu, u32 arg) { cpu = cpu_logical_map(cpu); - writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4); + writel_relaxed(arg, src_base + SRC_GPR1(gpr_v2) + cpu * 8 + 4); } void __init imx_src_init(void) @@ -131,3 +191,26 @@ void __init imx_src_init(void) writel_relaxed(val, src_base + SRC_SCR); spin_unlock(&scr_lock); } + +void __init imx7_src_init(void) +{ + struct device_node *np; + + gpr_v2 = true; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-src"); + if (!np) + return; + + src_base = of_iomap(np, 0); + if (!src_base) + return; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-gpc"); + if (!np) + return; + + gpc_base = of_iomap(np, 0); + if (!gpc_base) + return; +} diff --git a/arch/arm/mach-imx/suspend-imx53.S b/arch/arm/mach-imx/suspend-imx53.S index 41b8aad65363..46570ec2fbcf 100644 --- a/arch/arm/mach-imx/suspend-imx53.S +++ b/arch/arm/mach-imx/suspend-imx53.S @@ -28,11 +28,11 @@ * ^ * ^ * imx53_suspend code - * PM_INFO structure(imx53_suspend_info) + * PM_INFO structure(imx5_cpu_suspend_info) * ======================== low address ======================= */ -/* Offsets of members of struct imx53_suspend_info */ +/* Offsets of members of struct imx5_cpu_suspend_info */ #define SUSPEND_INFO_MX53_M4IF_V_OFFSET 0x0 #define SUSPEND_INFO_MX53_IOMUXC_V_OFFSET 0x4 #define SUSPEND_INFO_MX53_IO_COUNT_OFFSET 0x8 diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index 165c184801e1..bf14d65120b9 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -7,7 +7,7 @@ comment "IXP4xx Platforms" config MACH_IXP4XX_OF bool - prompt "Devce Tree IXP4xx boards" + prompt "Device Tree IXP4xx boards" default y select ARM_APPENDED_DTB # Old Redboot bootloaders deployed select I2C @@ -20,7 +20,7 @@ config MACH_IXP4XX_OF config MACH_NSLU2 bool prompt "Linksys NSLU2" - select FORCE_PCI + depends on IXP4XX_PCI_LEGACY help Say 'Y' here if you want your kernel to support Linksys's NSLU2 NAS device. For more information on this platform, @@ -28,7 +28,7 @@ config MACH_NSLU2 config MACH_AVILA bool "Avila" - select FORCE_PCI + depends on IXP4XX_PCI_LEGACY help Say 'Y' here if you want your kernel to support the Gateworks Avila Network Platform. For more information on this platform, @@ -44,7 +44,7 @@ config MACH_LOFT config ARCH_ADI_COYOTE bool "Coyote" - select FORCE_PCI + depends on IXP4XX_PCI_LEGACY help Say 'Y' here if you want your kernel to support the ADI Engineering Coyote Gateway Reference Platform. For more @@ -52,7 +52,7 @@ config ARCH_ADI_COYOTE config MACH_GATEWAY7001 bool "Gateway 7001" - select FORCE_PCI + depends on IXP4XX_PCI_LEGACY help Say 'Y' here if you want your kernel to support Gateway's 7001 Access Point. For more information on this platform, @@ -60,7 +60,7 @@ config MACH_GATEWAY7001 config MACH_WG302V2 bool "Netgear WG302 v2 / WAG302 v2" - select FORCE_PCI + depends on IXP4XX_PCI_LEGACY help Say 'Y' here if you want your kernel to support Netgear's WG302 v2 or WAG302 v2 Access Points. For more information @@ -68,6 +68,7 @@ config MACH_WG302V2 config ARCH_IXDP425 bool "IXDP425" + depends on IXP4XX_PCI_LEGACY help Say 'Y' here if you want your kernel to support Intel's IXDP425 Development Platform (Also known as Richfield). @@ -75,6 +76,7 @@ config ARCH_IXDP425 config MACH_IXDPG425 bool "IXDPG425" + depends on IXP4XX_PCI_LEGACY help Say 'Y' here if you want your kernel to support Intel's IXDPG425 Development Platform (Also known as Montajade). @@ -120,7 +122,7 @@ config ARCH_PRPMC1100 config MACH_NAS100D bool prompt "NAS100D" - select FORCE_PCI + depends on IXP4XX_PCI_LEGACY help Say 'Y' here if you want your kernel to support Iomega's NAS 100d device. For more information on this platform, @@ -129,7 +131,7 @@ config MACH_NAS100D config MACH_DSMG600 bool prompt "D-Link DSM-G600 RevA" - select FORCE_PCI + depends on IXP4XX_PCI_LEGACY help Say 'Y' here if you want your kernel to support D-Link's DSM-G600 RevA device. For more information on this platform, @@ -143,7 +145,7 @@ config ARCH_IXDP4XX config MACH_FSG bool prompt "Freecom FSG-3" - select FORCE_PCI + depends on IXP4XX_PCI_LEGACY help Say 'Y' here if you want your kernel to support Freecom's FSG-3 device. For more information on this platform, @@ -152,7 +154,7 @@ config MACH_FSG config MACH_ARCOM_VULCAN bool prompt "Arcom/Eurotech Vulcan" - select FORCE_PCI + depends on IXP4XX_PCI_LEGACY help Say 'Y' here if you want your kernel to support Arcom's Vulcan board. @@ -173,7 +175,7 @@ config CPU_IXP43X config MACH_GTWX5715 bool "Gemtek WX5715 (Linksys WRV54G)" depends on ARCH_IXP4XX - select FORCE_PCI + depends on IXP4XX_PCI_LEGACY help This board is currently inside the Linksys WRV54G Gateways. @@ -196,7 +198,7 @@ config MACH_DEVIXP config MACH_MICCPT bool "Omicron MICCPT" - select FORCE_PCI + depends on IXP4XX_PCI_LEGACY help Say 'Y' here if you want your kernel to support the MICCPT board from OMICRON electronics GmbH. @@ -209,9 +211,16 @@ config MACH_MIC256 comment "IXP4xx Options" +config IXP4XX_PCI_LEGACY + bool "IXP4xx legacy PCI driver support" + depends on PCI + help + Selects legacy PCI driver. + Not recommended for new development. + config IXP4XX_INDIRECT_PCI bool "Use indirect PCI memory access" - depends on PCI + depends on IXP4XX_PCI_LEGACY help IXP4xx provides two methods of accessing PCI memory space: diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c index 1981b33109cb..ec1d3029f80c 100644 --- a/arch/arm/mach-ixp4xx/avila-setup.c +++ b/arch/arm/mach-ixp4xx/avila-setup.c @@ -19,6 +19,7 @@ #include <linux/tty.h> #include <linux/serial_8250.h> #include <linux/gpio/machine.h> +#include <linux/platform_data/pata_ixp4xx_cf.h> #include <asm/types.h> #include <asm/setup.h> #include <asm/memory.h> diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 007a44412e24..b5eadd70d903 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -27,12 +27,12 @@ #include <linux/cpu.h> #include <linux/pci.h> #include <linux/sched_clock.h> +#include <linux/soc/ixp4xx/cpu.h> #include <linux/irqchip/irq-ixp4xx.h> #include <linux/platform_data/timer-ixp4xx.h> #include <linux/dma-map-ops.h> #include <mach/udc.h> #include <mach/hardware.h> -#include <mach/io.h> #include <linux/uaccess.h> #include <asm/page.h> #include <asm/exception.h> @@ -44,6 +44,27 @@ #include "irqs.h" +u32 ixp4xx_read_feature_bits(void) +{ + u32 val = ~__raw_readl(IXP4XX_EXP_CFG2); + + if (cpu_is_ixp42x_rev_a0()) + return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP | + IXP4XX_FEATURE_AES); + if (cpu_is_ixp42x()) + return val & IXP42X_FEATURE_MASK; + if (cpu_is_ixp43x()) + return val & IXP43X_FEATURE_MASK; + return val & IXP46X_FEATURE_MASK; +} +EXPORT_SYMBOL(ixp4xx_read_feature_bits); + +void ixp4xx_write_feature_bits(u32 value) +{ + __raw_writel(~value, IXP4XX_EXP_CFG2); +} +EXPORT_SYMBOL(ixp4xx_write_feature_bits); + #define IXP4XX_TIMER_FREQ 66666000 /************************************************************************* @@ -215,6 +236,27 @@ static struct resource ixp46x_i2c_resources[] = { } }; +/* A single 32-bit register on IXP46x */ +#define IXP4XX_HWRANDOM_BASE_PHYS 0x70002100 + +static struct resource ixp46x_hwrandom_resource[] = { + { + .start = IXP4XX_HWRANDOM_BASE_PHYS, + .end = IXP4XX_HWRANDOM_BASE_PHYS + 0x3, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ixp46x_hwrandom_device = { + .name = "ixp4xx-hwrandom", + .id = -1, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = ixp46x_hwrandom_resource, + .num_resources = ARRAY_SIZE(ixp46x_hwrandom_resource), +}; + /* * I2C controller. The IXP46x uses the same block as the IOP3xx, so * we just use the same device name. @@ -227,7 +269,8 @@ static struct platform_device ixp46x_i2c_controller = { }; static struct platform_device *ixp46x_devices[] __initdata = { - &ixp46x_i2c_controller + &ixp46x_hwrandom_device, + &ixp46x_i2c_controller, }; unsigned long ixp4xx_exp_bus_size; diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c index 507ee3878769..844329c5610d 100644 --- a/arch/arm/mach-ixp4xx/fsg-setup.c +++ b/arch/arm/mach-ixp4xx/fsg-setup.c @@ -28,6 +28,7 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> +#include <mach/hardware.h> #include "irqs.h" diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h deleted file mode 100644 index b872a5354ddd..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/cpu.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ixp4xx/include/mach/cpu.h - * - * IXP4XX cpu type detection - * - * Copyright (C) 2007 MontaVista Software, Inc. - */ - -#ifndef __ASM_ARCH_CPU_H__ -#define __ASM_ARCH_CPU_H__ - -#include <linux/io.h> -#include <asm/cputype.h> - -/* Processor id value in CP15 Register 0 */ -#define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */ -#define IXP42X_PROCESSOR_ID_MASK 0xffffffc0 - -#define IXP43X_PROCESSOR_ID_VALUE 0x69054040 -#define IXP43X_PROCESSOR_ID_MASK 0xfffffff0 - -#define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */ -#define IXP46X_PROCESSOR_ID_MASK 0xfffffff0 - -#define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \ - IXP42X_PROCESSOR_ID_VALUE) -#define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \ - IXP42X_PROCESSOR_ID_VALUE) -#define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \ - IXP43X_PROCESSOR_ID_VALUE) -#define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \ - IXP46X_PROCESSOR_ID_VALUE) - -static inline u32 ixp4xx_read_feature_bits(void) -{ - u32 val = ~__raw_readl(IXP4XX_EXP_CFG2); - - if (cpu_is_ixp42x_rev_a0()) - return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP | - IXP4XX_FEATURE_AES); - if (cpu_is_ixp42x()) - return val & IXP42X_FEATURE_MASK; - if (cpu_is_ixp43x()) - return val & IXP43X_FEATURE_MASK; - return val & IXP46X_FEATURE_MASK; -} - -static inline void ixp4xx_write_feature_bits(u32 value) -{ - __raw_writel(~value, IXP4XX_EXP_CFG2); -} - -#endif /* _ASM_ARCH_CPU_H */ diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h index b884eedcd0fc..b2b7301ce503 100644 --- a/arch/arm/mach-ixp4xx/include/mach/hardware.h +++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h @@ -23,7 +23,7 @@ #include "ixp4xx-regs.h" #ifndef __ASSEMBLER__ -#include <mach/cpu.h> +#include <linux/soc/ixp4xx/cpu.h> #endif /* Platform helper functions and definitions */ diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h index 708d085ce39f..abb07f105515 100644 --- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h +++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h @@ -45,21 +45,21 @@ * it can be used with the low-level debug code. */ #define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000 -#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000) +#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEC00000) #define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000 /* * PCI Config registers */ #define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000 -#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000) +#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEC13000) #define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000 /* * Expansion BUS Configuration registers */ #define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000 -#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000 +#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEC14000 #define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000 #define IXP4XX_EXP_CS0_OFFSET 0x00 @@ -120,6 +120,7 @@ #define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000) +/* The UART is explicitly put in the beginning of fixmap */ #define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000) #define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000) #define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000) @@ -299,58 +300,4 @@ #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ -/* "fuse" bits of IXP_EXP_CFG2 */ -/* All IXP4xx CPUs */ -#define IXP4XX_FEATURE_RCOMP (1 << 0) -#define IXP4XX_FEATURE_USB_DEVICE (1 << 1) -#define IXP4XX_FEATURE_HASH (1 << 2) -#define IXP4XX_FEATURE_AES (1 << 3) -#define IXP4XX_FEATURE_DES (1 << 4) -#define IXP4XX_FEATURE_HDLC (1 << 5) -#define IXP4XX_FEATURE_AAL (1 << 6) -#define IXP4XX_FEATURE_HSS (1 << 7) -#define IXP4XX_FEATURE_UTOPIA (1 << 8) -#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9) -#define IXP4XX_FEATURE_NPEC_ETH (1 << 10) -#define IXP4XX_FEATURE_RESET_NPEA (1 << 11) -#define IXP4XX_FEATURE_RESET_NPEB (1 << 12) -#define IXP4XX_FEATURE_RESET_NPEC (1 << 13) -#define IXP4XX_FEATURE_PCI (1 << 14) -#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) -#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) -#define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP | \ - IXP4XX_FEATURE_USB_DEVICE | \ - IXP4XX_FEATURE_HASH | \ - IXP4XX_FEATURE_AES | \ - IXP4XX_FEATURE_DES | \ - IXP4XX_FEATURE_HDLC | \ - IXP4XX_FEATURE_AAL | \ - IXP4XX_FEATURE_HSS | \ - IXP4XX_FEATURE_UTOPIA | \ - IXP4XX_FEATURE_NPEB_ETH0 | \ - IXP4XX_FEATURE_NPEC_ETH | \ - IXP4XX_FEATURE_RESET_NPEA | \ - IXP4XX_FEATURE_RESET_NPEB | \ - IXP4XX_FEATURE_RESET_NPEC | \ - IXP4XX_FEATURE_PCI | \ - IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \ - IXP4XX_FEATURE_XSCALE_MAX_FREQ) - - -/* IXP43x/46x CPUs */ -#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) -#define IXP4XX_FEATURE_USB_HOST (1 << 18) -#define IXP4XX_FEATURE_NPEA_ETH (1 << 19) -#define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK | \ - IXP4XX_FEATURE_ECC_TIMESYNC | \ - IXP4XX_FEATURE_USB_HOST | \ - IXP4XX_FEATURE_NPEA_ETH) - -/* IXP46x CPU (including IXP455) only */ -#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) -#define IXP4XX_FEATURE_RSA (1 << 21) -#define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK | \ - IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ - IXP4XX_FEATURE_RSA) - #endif diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h index 6d403fe0bf52..d8b4df96db08 100644 --- a/arch/arm/mach-ixp4xx/include/mach/platform.h +++ b/arch/arm/mach-ixp4xx/include/mach/platform.h @@ -80,20 +80,6 @@ extern unsigned long ixp4xx_exp_bus_size; #define IXP4XX_UART_XTAL 14745600 /* - * This structure provide a means for the board setup code - * to give information to th pata_ixp4xx driver. It is - * passed as platform_data. - */ -struct ixp4xx_pata_data { - volatile u32 *cs0_cfg; - volatile u32 *cs1_cfg; - unsigned long cs0_bits; - unsigned long cs1_bits; - void __iomem *cs0; - void __iomem *cs1; -}; - -/* * Frequency of clock used for primary clocksource */ extern unsigned long ixp4xx_timer_freq; diff --git a/arch/arm/mach-ixp4xx/ixp4xx-of.c b/arch/arm/mach-ixp4xx/ixp4xx-of.c index 7449b8319c8a..f9904716ec7f 100644 --- a/arch/arm/mach-ixp4xx/ixp4xx-of.c +++ b/arch/arm/mach-ixp4xx/ixp4xx-of.c @@ -9,8 +9,12 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/hardware.h> -#include <mach/ixp4xx-regs.h> +/* + * These are the only fixed phys to virt mappings we ever need + * we put it right after the UART mapping at 0xffc80000-0xffc81fff + */ +#define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000 +#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEC14000 static struct map_desc ixp4xx_of_io_desc[] __initdata = { /* diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c index 6959ad2e3aec..6133cf01cbe4 100644 --- a/arch/arm/mach-ixp4xx/nas100d-setup.c +++ b/arch/arm/mach-ixp4xx/nas100d-setup.c @@ -33,6 +33,7 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> +#include <mach/hardware.h> #include "irqs.h" diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c index a428bb918703..8526a70e401b 100644 --- a/arch/arm/mach-ixp4xx/nslu2-setup.c +++ b/arch/arm/mach-ixp4xx/nslu2-setup.c @@ -31,6 +31,7 @@ #include <asm/mach/arch.h> #include <asm/mach/flash.h> #include <asm/mach/time.h> +#include <mach/hardware.h> #include "irqs.h" diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 9536b8f3c07d..208c700c2455 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -65,14 +65,14 @@ config MACH_OMAP_INNOVATOR config MACH_OMAP_H2 bool "TI H2 Support" depends on ARCH_OMAP16XX - help + help TI OMAP 1610/1611B H2 board support. Say Y here if you have such a board. config MACH_OMAP_H3 bool "TI H3 Support" depends on ARCH_OMAP16XX - help + help TI OMAP 1710 H3 board support. Say Y here if you have such a board. @@ -85,14 +85,14 @@ config MACH_HERALD config MACH_OMAP_OSK bool "TI OSK Support" depends on ARCH_OMAP16XX - help + help TI OMAP 5912 OSK (OMAP Starter Kit) board support. Say Y here if you have such a board. config OMAP_OSK_MISTRAL bool "Mistral QVGA board Support" depends on MACH_OMAP_OSK - help + help The OSK supports an optional add-on board with a Quarter-VGA touchscreen, PDA-ish buttons, a resume button, bicolor LED, and camera connector. Say Y here if you have this board. @@ -100,14 +100,14 @@ config OMAP_OSK_MISTRAL config MACH_OMAP_PERSEUS2 bool "TI Perseus2" depends on ARCH_OMAP730 - help + help Support for TI OMAP 730 Perseus2 board. Say Y here if you have such a board. config MACH_OMAP_FSAMPLE bool "TI F-Sample" depends on ARCH_OMAP730 - help + help Support for TI OMAP 850 F-Sample board. Say Y here if you have such a board. diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index d02fe63dab59..14beb59e5f7b 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -26,7 +26,6 @@ extern struct omap_domain_base cm_base; extern struct omap_domain_base cm2_base; -extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2); # endif /* diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c index b7ea609386d5..e2d069fe67f1 100644 --- a/arch/arm/mach-omap2/cm_common.c +++ b/arch/arm/mach-omap2/cm_common.c @@ -38,19 +38,6 @@ struct omap_domain_base cm2_base; #define CM_SINGLE_INSTANCE 0x2 /** - * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use) - * @cm: CM base virtual address - * @cm2: CM2 base virtual address (if present on the booted SoC) - * - * XXX Will be replaced when the PRM/CM drivers are completed. - */ -void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2) -{ - cm_base.va = cm; - cm2_base.va = cm2; -} - -/** * cm_split_idlest_reg - split CM_IDLEST reg addr into its components * @idlest_reg: CM_IDLEST* virtual address * @prcm_inst: pointer to an s16 to return the PRCM instance offset diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index db446f271f5d..32f58f58515e 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -130,7 +130,6 @@ void am33xx_init_early(void); void am35xx_init_early(void); void ti814x_init_early(void); void ti816x_init_early(void); -void am33xx_init_early(void); void am43xx_init_early(void); void am43xx_init_late(void); void omap4430_init_early(void); diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 73338cf80d76..062d431fc33a 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -136,11 +136,6 @@ struct omap3_control_regs { static struct omap3_control_regs control_context; #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ -void __init omap2_set_globals_control(void __iomem *ctrl) -{ - omap2_ctrl_base = ctrl; -} - u8 omap_ctrl_readb(u16 offset) { u32 val; diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index eceb4b09adb2..c4ca30ba1790 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -528,7 +528,6 @@ extern int omap3_ctrl_save_padconf(void); void omap3_ctrl_init(void); int omap2_control_base_init(void); int omap_control_init(void); -void omap2_set_globals_control(void __iomem *ctrl); void __init omap3_control_legacy_iomap_init(void); #else #define omap_ctrl_readb(x) 0 diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c index 56f2c0bcae5a..bf0d25fd2cea 100644 --- a/arch/arm/mach-omap2/pm33xx-core.c +++ b/arch/arm/mach-omap2/pm33xx-core.c @@ -8,6 +8,7 @@ #include <linux/cpuidle.h> #include <linux/platform_data/pm33xx.h> +#include <linux/suspend.h> #include <asm/cpuidle.h> #include <asm/smp_scu.h> #include <asm/suspend.h> @@ -324,6 +325,44 @@ static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void) return NULL; } +#ifdef CONFIG_SUSPEND +/* + * Block system suspend initially. Later on pm33xx sets up it's own + * platform_suspend_ops after probe. That depends also on loaded + * wkup_m3_ipc and booted am335x-pm-firmware.elf. + */ +static int amx3_suspend_block(suspend_state_t state) +{ + pr_warn("PM not initialized for pm33xx, wkup_m3_ipc, or am335x-pm-firmware.elf\n"); + + return -EINVAL; +} + +static int amx3_pm_valid(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + return 1; + default: + return 0; + } +} + +static const struct platform_suspend_ops amx3_blocked_pm_ops = { + .begin = amx3_suspend_block, + .valid = amx3_pm_valid, +}; + +static void __init amx3_block_suspend(void) +{ + suspend_set_ops(&amx3_blocked_pm_ops); +} +#else +static inline void amx3_block_suspend(void) +{ +} +#endif /* CONFIG_SUSPEND */ + int __init amx3_common_pm_init(void) { struct am33xx_pm_platform_data *pdata; @@ -337,6 +376,7 @@ int __init amx3_common_pm_init(void) devinfo.size_data = sizeof(*pdata); devinfo.id = -1; platform_device_register_full(&devinfo); + amx3_block_suspend(); return 0; } diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c index d23970bd638d..f70fb9c4b0cb 100644 --- a/arch/arm/mach-rpc/riscpc.c +++ b/arch/arm/mach-rpc/riscpc.c @@ -49,6 +49,7 @@ static int __init parse_tag_acorn(const struct tag *tag) fallthrough; /* ??? */ case 256: vram_size += PAGE_SIZE * 256; + break; default: break; } diff --git a/arch/arm/mach-s3c/mach-rx1950.c b/arch/arm/mach-s3c/mach-rx1950.c index a3f46aa61c45..313e080e179e 100644 --- a/arch/arm/mach-s3c/mach-rx1950.c +++ b/arch/arm/mach-s3c/mach-rx1950.c @@ -271,7 +271,6 @@ static int rx1950_led_blink_set(struct gpio_desc *desc, int state, break; default: return -EINVAL; - break; } if (delay_on && delay_off && !*delay_on && !*delay_off) diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index 000e8210000b..80fb5a4a5c05 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -27,6 +27,7 @@ #include <linux/vmalloc.h> #include <linux/io.h> #include <linux/sizes.h> +#include <linux/memblock.h> #include <asm/cp15.h> #include <asm/cputype.h> @@ -284,7 +285,8 @@ static void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn, * Don't allow RAM to be mapped with mismatched attributes - this * causes problems with ARMv6+ */ - if (WARN_ON(pfn_valid(pfn) && mtype != MT_MEMORY_RW)) + if (WARN_ON(memblock_is_map_memory(PFN_PHYS(pfn)) && + mtype != MT_MEMORY_RW)) return NULL; area = get_vm_area_caller(size, VM_IOREMAP, caller); diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index e07e7de9ac49..b5b13a932561 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1605,7 +1605,8 @@ config ARM64_BTI_KERNEL depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 depends on !CC_IS_GCC || GCC_VERSION >= 100100 - depends on !(CC_IS_CLANG && GCOV_KERNEL) + # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 + depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) help Build the kernel with Branch Target Identification annotations diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 7336c1fd0dda..b0ce18d4cc98 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -16,6 +16,7 @@ config ARCH_SUNXI select IRQ_FASTEOI_HIERARCHY_HANDLERS select PINCTRL select RESET_CONTROLLER + select SUN4I_TIMER help This enables support for Allwinner sunxi based SoCs like the A64. diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile index 3b5b1c480449..7bc37d0a1b68 100644 --- a/arch/arm64/Makefile +++ b/arch/arm64/Makefile @@ -149,7 +149,6 @@ KBUILD_CFLAGS += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) KBUILD_CPPFLAGS += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) KBUILD_AFLAGS += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) -core-y += arch/arm64/ libs-y := arch/arm64/lib/ $(libs-y) libs-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 41ce680e5f8d..a96d9d2d8dd8 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-it.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 79adea3f8cc1..5b44a979f250 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -25,6 +25,11 @@ /* Backlight configuration differs per PinePhone revision. */ }; + bt_sco_codec: bt-sco-codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -91,6 +96,8 @@ }; &codec { + pinctrl-names = "default"; + pinctrl-0 = <&aif3_pins>; status = "okay"; }; @@ -426,6 +433,7 @@ &sound { status = "okay"; + simple-audio-card,name = "PinePhone"; simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; simple-audio-card,widgets = "Microphone", "Headset Microphone", "Microphone", "Internal Microphone", @@ -447,6 +455,23 @@ "MIC1", "Internal Microphone", "Headset Microphone", "HBIAS", "MIC2", "Headset Microphone"; + + simple-audio-card,dai-link@2 { + format = "dsp_a"; + frame-master = <&link2_codec>; + bitclock-master = <&link2_codec>; + bitclock-inversion; + + link2_cpu: cpu { + sound-dai = <&bt_sco_codec 0>; + }; + + link2_codec: codec { + sound-dai = <&codec 2>; + dai-tdm-slot-num = <1>; + dai-tdm-slot-width = <32>; + }; + }; }; &uart0 { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index e22b94c83647..5e66ce1a334f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -79,7 +79,7 @@ &emac { pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii-txid"; phy-handle = <&ext_rgmii_phy>; phy-supply = <®_dc1sw>; status = "okay"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 5b30e6c1fa05..6ddb717f2f98 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -131,12 +131,10 @@ }; sound: sound { + #address-cells = <1>; + #size-cells = <0>; compatible = "simple-audio-card"; simple-audio-card,name = "sun50i-a64-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&cpudai>; - simple-audio-card,bitclock-master = <&cpudai>; - simple-audio-card,mclk-fs = <128>; simple-audio-card,aux-devs = <&codec_analog>; simple-audio-card,routing = "Left DAC", "DACL", @@ -145,12 +143,19 @@ "ADCR", "Right ADC"; status = "disabled"; - cpudai: simple-audio-card,cpu { - sound-dai = <&dai>; - }; + simple-audio-card,dai-link@0 { + format = "i2s"; + frame-master = <&link0_cpu>; + bitclock-master = <&link0_cpu>; + mclk-fs = <128>; + + link0_cpu: cpu { + sound-dai = <&dai>; + }; - link_codec: simple-audio-card,codec { - sound-dai = <&codec>; + link0_codec: codec { + sound-dai = <&codec 0>; + }; }; }; @@ -659,6 +664,18 @@ interrupt-controller; #interrupt-cells = <3>; + /omit-if-no-ref/ + aif2_pins: aif2-pins { + pins = "PB4", "PB5", "PB6", "PB7"; + function = "aif2"; + }; + + /omit-if-no-ref/ + aif3_pins: aif3-pins { + pins = "PG10", "PG11", "PG12", "PG13"; + function = "aif3"; + }; + csi_pins: csi-pins { pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11"; @@ -799,6 +816,23 @@ }; }; + timer@1c20c00 { + compatible = "allwinner,sun50i-a64-timer", + "allwinner,sun8i-a23-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; + }; + + wdt0: watchdog@1c20ca0 { + compatible = "allwinner,sun50i-a64-wdt", + "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; + }; + spdif: spdif@1c21000 { #sound-dai-cells = <0>; compatible = "allwinner,sun50i-a64-spdif", @@ -880,7 +914,7 @@ }; codec: codec@1c22e00 { - #sound-dai-cells = <0>; + #sound-dai-cells = <1>; compatible = "allwinner,sun50i-a64-codec", "allwinner,sun8i-a33-codec"; reg = <0x01c22e00 0x600>; @@ -1325,13 +1359,5 @@ #address-cells = <1>; #size-cells = <0>; }; - - wdt0: watchdog@1c20ca0 { - compatible = "allwinner,sun50i-a64-wdt", - "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc24M>; - }; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts new file mode 100644 index 000000000000..55bcdf8d1a07 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Chukun Pan <amadeus@jmu.edu.cn> + * + * Based on sun50i-h5-nanopi-neo-plus2.dts, which is: + * Copyright (C) 2017 Antony Antony <antony@phenome.org> + * Copyright (C) 2016 ARM Ltd. + */ + +/dts-v1/; +#include "sun50i-h5.dtsi" +#include "sun50i-h5-cpu-opp.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "FriendlyARM NanoPi R1S H5"; + compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5"; + + aliases { + ethernet0 = &emac; + ethernet1 = &rtl8189etv; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_LAN; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + function = LED_FUNCTION_WAN; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; + }; + }; + + r-gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb0_vbus: usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; + }; + + vdd_cpux: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <1100000 0x0>, <1300000 0x1>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + post-power-on-delay-ms = <200>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpux>; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "microchip,24c02"; + reg = <0x51>; + pagesize = <16>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8189etv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pa_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + /* USB Type-A port's VBUS is always on */ + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 50815867ce7b..30d396e8c762 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -271,6 +271,15 @@ }; }; + timer@3009000 { + compatible = "allwinner,sun50i-h6-timer", + "allwinner,sun8i-a23-timer"; + reg = <0x03009000 0xa0>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; + }; + watchdog: watchdog@30090a0 { compatible = "allwinner,sun50i-h6-wdt", "allwinner,sun6i-a31-wdt"; diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index a58ccecfcb55..faa0a79a34f5 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m5.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 895c43c7af9f..3f5254eeb47b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1871,6 +1871,7 @@ status = "disabled"; clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; clock-names = "xtal", "pclk", "baud"; + fifo-size = <128>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 793d48f72390..00c6f53290d4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -2317,6 +2317,7 @@ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; clock-names = "xtal", "pclk", "baud"; status = "disabled"; + fifo-size = <128>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 3d00404aae0f..6b457b2c30a4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -301,6 +301,7 @@ reg = <0x0 0x84c0 0x0 0x18>; interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; status = "disabled"; + fifo-size = <128>; }; uart_B: serial@84dc { diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi index 66d67524b031..3cf4ecb6d52e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi @@ -171,11 +171,16 @@ sound { compatible = "amlogic,axg-sound-card"; model = "KHADAS-VIM3"; - audio-aux-devs = <&tdmout_a>; + audio-aux-devs = <&tdmin_a>, <&tdmout_a>; audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", "TDMOUT_A IN 1", "FRDDR_B OUT 0", "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT"; + "TDM_A Playback", "TDMOUT_A OUT", + "TDMIN_A IN 0", "TDM_A Capture", + "TDMIN_A IN 3", "TDM_A Loopback", + "TODDR_A IN 0", "TDMIN_A OUT", + "TODDR_B IN 0", "TDMIN_A OUT", + "TODDR_C IN 0", "TDMIN_A OUT"; assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, @@ -198,8 +203,20 @@ sound-dai = <&frddr_c>; }; - /* 8ch hdmi interface */ dai-link-3 { + sound-dai = <&toddr_a>; + }; + + dai-link-4 { + sound-dai = <&toddr_b>; + }; + + dai-link-5 { + sound-dai = <&toddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-6 { sound-dai = <&tdmif_a>; dai-format = "i2s"; dai-tdm-slot-tx-mask-0 = <1 1>; @@ -214,7 +231,7 @@ }; /* hdmi glue */ - dai-link-4 { + dai-link-7 { sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; codec { @@ -454,10 +471,26 @@ status = "okay"; }; +&tdmin_a { + status = "okay"; +}; + &tdmout_a { status = "okay"; }; +&toddr_a { + status = "okay"; +}; + +&toddr_b { + status = "okay"; +}; + +&toddr_c { + status = "okay"; +}; + &tohdmitx { status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts new file mode 100644 index 000000000000..effaa138b5f9 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts @@ -0,0 +1,646 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 BayLibre SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/dts-v1/; + +#include "meson-sm1.dtsi" +#include <dt-bindings/leds/common.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/gpio/meson-g12a-gpio.h> +#include <dt-bindings/sound/meson-g12a-toacodec.h> +#include <dt-bindings/sound/meson-g12a-tohdmitx.h> + +/ { + compatible = "bananapi,bpi-m5", "amlogic,sm1"; + model = "Banana Pi BPI-M5"; + + adc_keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + key { + label = "SW3"; + linux,code = <BTN_3>; + press-threshold-microvolt = <1700000>; + }; + }; + + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* TOFIX: handle CVBS_DET on SARADC channel 0 */ + cvbs-connector { + compatible = "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key { + label = "SW1"; + linux,code = <BTN_1>; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio_intc>; + interrupts = <3 IRQ_TYPE_EDGE_BOTH>; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + green { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; + }; + + blue { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + emmc_1v8: regulator-emmc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "EMMC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + dc_in: regulator-dc_in { + compatible = "regulator-fixed"; + regulator-name = "DC_IN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vddio_c: regulator-vddio_c { + compatible = "regulator-gpio"; + regulator-name = "VDDIO_C"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + + gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>; + gpios-states = <1>; + + states = <1800000 0>, + <3300000 1>; + }; + + tflash_vdd: regulator-tflash_vdd { + compatible = "regulator-fixed"; + regulator-name = "TFLASH_VDD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_in>; + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-high; + regulator-always-on; + }; + + vddao_1v8: regulator-vddao_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + vddcpu: regulator-vddcpu { + /* + * SY8120B1ABC DC/DC Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <690000>; + regulator-max-microvolt = <1050000>; + + vin-supply = <&dc_in>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + /* USB Hub Power Enable */ + vl_pwr_en: regulator-vl_pwr_en { + compatible = "regulator-fixed"; + regulator-name = "VL_PWR_EN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_in>; + + gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "BPI-M5"; + audio-widgets = "Line", "Lineout"; + audio-aux-devs = <&tdmout_b>, <&tdmout_c>, + <&tdmin_a>, <&tdmin_b>, <&tdmin_c>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT", + "TDMOUT_C IN 0", "FRDDR_A OUT 2", + "TDMOUT_C IN 1", "FRDDR_B OUT 2", + "TDMOUT_C IN 2", "FRDDR_C OUT 2", + "TDM_C Playback", "TDMOUT_C OUT", + "TDMIN_A IN 4", "TDM_B Loopback", + "TDMIN_B IN 4", "TDM_B Loopback", + "TDMIN_C IN 4", "TDM_B Loopback", + "TDMIN_A IN 5", "TDM_C Loopback", + "TDMIN_B IN 5", "TDM_C Loopback", + "TDMIN_C IN 5", "TDM_C Loopback", + "TODDR_A IN 0", "TDMIN_A OUT", + "TODDR_B IN 0", "TDMIN_A OUT", + "TODDR_C IN 0", "TDMIN_A OUT", + "TODDR_A IN 1", "TDMIN_B OUT", + "TODDR_B IN 1", "TDMIN_B OUT", + "TODDR_C IN 1", "TDMIN_B OUT", + "TODDR_A IN 2", "TDMIN_C OUT", + "TODDR_B IN 2", "TDMIN_C OUT", + "TODDR_C IN 2", "TDMIN_C OUT", + "Lineout", "ACODEC LOLP", + "Lineout", "ACODEC LORP"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + dai-link-3 { + sound-dai = <&toddr_a>; + }; + + dai-link-4 { + sound-dai = <&toddr_b>; + }; + + dai-link-5 { + sound-dai = <&toddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-6 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + + codec-1 { + sound-dai = <&toacodec TOACODEC_IN_B>; + }; + }; + + /* i2s jack output interface */ + dai-link-7 { + sound-dai = <&tdmif_c>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>; + }; + + codec-1 { + sound-dai = <&toacodec TOACODEC_IN_C>; + }; + }; + + /* hdmi glue */ + dai-link-8 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + + /* acodec glue */ + dai-link-9 { + sound-dai = <&toacodec TOACODEC_OUT>; + + codec { + sound-dai = <&acodec>; + }; + }; + }; +}; + +&acodec { + AVDD-supply = <&vddao_1v8>; + status = "okay"; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU1_CLK>; + clock-latency = <50000>; +}; + +&cpu2 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU2_CLK>; + clock-latency = <50000>; +}; + +&cpu3 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU3_CLK>; + clock-latency = <50000>; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +ðmac { + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii-txid"; + phy-handle = <&external_phy>; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&gpio { + gpio-line-names = + /* GPIOZ */ + "ETH_MDIO", /* GPIOZ_0 */ + "ETH_MDC", /* GPIOZ_1 */ + "ETH_RXCLK", /* GPIOZ_2 */ + "ETH_RX_DV", /* GPIOZ_3 */ + "ETH_RXD0", /* GPIOZ_4 */ + "ETH_RXD1", /* GPIOZ_5 */ + "ETH_RXD2", /* GPIOZ_6 */ + "ETH_RXD3", /* GPIOZ_7 */ + "ETH_TXCLK", /* GPIOZ_8 */ + "ETH_TXEN", /* GPIOZ_9 */ + "ETH_TXD0", /* GPIOZ_10 */ + "ETH_TXD1", /* GPIOZ_11 */ + "ETH_TXD2", /* GPIOZ_12 */ + "ETH_TXD3", /* GPIOZ_13 */ + "ETH_INTR", /* GPIOZ_14 */ + "ETH_NRST", /* GPIOZ_15 */ + /* GPIOH */ + "HDMI_SDA", /* GPIOH_0 */ + "HDMI_SCL", /* GPIOH_1 */ + "HDMI_HPD", /* GPIOH_2 */ + "HDMI_CEC", /* GPIOH_3 */ + "VL-RST_N", /* GPIOH_4 */ + "CON1-P36", /* GPIOH_5 */ + "VL-PWREN", /* GPIOH_6 */ + "WiFi_3V3_1V8", /* GPIOH_7 */ + "TFLASH_VDD_EN", /* GPIOH_8 */ + /* BOOT */ + "eMMC_D0", /* BOOT_0 */ + "eMMC_D1", /* BOOT_1 */ + "eMMC_D2", /* BOOT_2 */ + "eMMC_D3", /* BOOT_3 */ + "eMMC_D4", /* BOOT_4 */ + "eMMC_D5", /* BOOT_5 */ + "eMMC_D6", /* BOOT_6 */ + "eMMC_D7", /* BOOT_7 */ + "eMMC_CLK", /* BOOT_8 */ + "", + "eMMC_CMD", /* BOOT_10 */ + "", + "eMMC_RST#", /* BOOT_12 */ + "eMMC_DS", /* BOOT_13 */ + /* GPIOC */ + "SD_D0_B", /* GPIOC_0 */ + "SD_D1_B", /* GPIOC_1 */ + "SD_D2_B", /* GPIOC_2 */ + "SD_D3_B", /* GPIOC_3 */ + "SD_CLK_B", /* GPIOC_4 */ + "SD_CMD_B", /* GPIOC_5 */ + "CARD_EN_DET", /* GPIOC_6 */ + "", + /* GPIOA */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", + "CON1-P27", /* GPIOA_14 */ + "CON1-P28", /* GPIOA_15 */ + /* GPIOX */ + "CON1-P16", /* GPIOX_0 */ + "CON1-P18", /* GPIOX_1 */ + "CON1-P22", /* GPIOX_2 */ + "CON1-P11", /* GPIOX_3 */ + "CON1-P13", /* GPIOX_4 */ + "CON1-P07", /* GPIOX_5 */ + "CON1-P33", /* GPIOX_6 */ + "CON1-P15", /* GPIOX_7 */ + "CON1-P19", /* GPIOX_8 */ + "CON1-P21", /* GPIOX_9 */ + "CON1-P24", /* GPIOX_10 */ + "CON1-P23", /* GPIOX_11 */ + "CON1-P08", /* GPIOX_12 */ + "CON1-P10", /* GPIOX_13 */ + "CON1-P29", /* GPIOX_14 */ + "CON1-P31", /* GPIOX_15 */ + "CON1-P26", /* GPIOX_16 */ + "CON1-P03", /* GPIOX_17 */ + "CON1-P05", /* GPIOX_18 */ + "CON1-P32"; /* GPIOX_19 */ + + /* + * WARNING: The USB Hub on the BPI-M5 needs a reset signal + * to be turned high in order to be detected by the USB Controller + * This signal should be handled by a USB specific power sequence + * in order to reset the Hub when USB bus is powered down. + */ + usb-hub { + gpio-hog; + gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&gpio_ao { + gpio-line-names = + /* GPIOAO */ + "DEBUG TX", /* GPIOAO_0 */ + "DEBUG RX", /* GPIOAO_1 */ + "SYS_LED2", /* GPIOAO_2 */ + "UPDATE_KEY", /* GPIOAO_3 */ + "CON1-P40", /* GPIOAO_4 */ + "IR_IN", /* GPIOAO_5 */ + "TF_3V3N_1V8_EN", /* GPIOAO_6 */ + "CON1-P35", /* GPIOAO_7 */ + "CON1-P12", /* GPIOAO_8 */ + "CON1-P37", /* GPIOAO_9 */ + "CON1-P38", /* GPIOAO_10 */ + "SYS_LED", /* GPIOAO_11 */ + /* GPIOE */ + "VDDEE_PWM", /* GPIOE_0 */ + "VDDCPU_PWM", /* GPIOE_1 */ + "TF_PWR_EN"; /* GPIOE_2 */ +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; + hdmi-supply = <&dc_in>; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddao_1v8>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + /* TOFIX: SD card is barely usable in SDR modes */ + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&tflash_vdd>; + vqmmc-supply = <&vddio_c>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&emmc_1v8>; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmif_c { + status = "okay"; +}; + +&tdmin_a { + status = "okay"; +}; + +&tdmin_b { + status = "okay"; +}; + +&tdmin_c { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tdmout_c { + status = "okay"; +}; + +&toacodec { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + +&toddr_a { + status = "okay"; +}; + +&toddr_b { + status = "okay"; +}; + +&toddr_c { + status = "okay"; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; +}; + +&usb2_phy0 { + phy-supply = <&dc_in>; +}; + +&usb2_phy1 { + /* Enable the hub which is connected to this port */ + phy-supply = <&vl_pwr_en>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts index 06de0b1ce726..f2c098143594 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts @@ -32,6 +32,19 @@ regulator-boot-on; regulator-always-on; }; + + sound { + model = "G12B-KHADAS-VIM3L"; + audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", + "TDMOUT_A IN 1", "FRDDR_B OUT 0", + "TDMOUT_A IN 2", "FRDDR_C OUT 0", + "TDM_A Playback", "TDMOUT_A OUT", + "TDMIN_A IN 0", "TDM_A Capture", + "TDMIN_A IN 13", "TDM_A Loopback", + "TODDR_A IN 0", "TDMIN_A OUT", + "TODDR_B IN 0", "TDMIN_A OUT", + "TODDR_C IN 0", "TDMIN_A OUT"; + }; }; &cpu0 { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts index 8c327c03d845..8c30ce63686e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts @@ -23,18 +23,6 @@ }; }; - hub_5v: regulator-hub_5v { - compatible = "regulator-fixed"; - regulator-name = "HUB_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the Hub CHIPENABLE, LOW sets low power state */ - gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - sound { model = "ODROID-C4"; }; @@ -58,8 +46,3 @@ &ir { linux,rc-map-name = "rc-odroid"; }; - -&usb2_phy1 { - /* Enable the hub which is connected to this port */ - phy-supply = <&hub_5v>; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts index bf15700c4b15..f3f953225bf5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts @@ -44,6 +44,32 @@ }; }; + /* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */ + p12v_0: regulator-p12v_0 { + compatible = "regulator-fixed"; + regulator-name = "P12V_0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&main_12v>; + + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-high; + regulator-always-on; + }; + + /* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */ + p12v_1: regulator-p12v_1 { + compatible = "regulator-fixed"; + regulator-name = "P12V_1"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&main_12v>; + + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-high; + regulator-always-on; + }; + sound { model = "ODROID-HC4"; }; @@ -90,7 +116,25 @@ status = "disabled"; }; +&spifc { + status = "okay"; + pinctrl-0 = <&nor_pins>; + pinctrl-names = "default"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + }; +}; + &usb { - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; + phys = <&usb2_phy1>; + phy-names = "usb2-phy1"; +}; + +&usb2_phy0 { + status = "disabled"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi index d14716b3d0f1..fd0ad85c165b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi @@ -46,8 +46,13 @@ regulator-name = "TF_IO"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5v>; - gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>; + enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + + gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>; gpios-states = <0>; states = <3300000 0>, @@ -78,6 +83,8 @@ regulator-max-microvolt = <5000000>; regulator-always-on; vin-supply = <&main_12v>; + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-high; }; vcc_1v8: regulator-vcc_1v8 { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index c309517abae3..3d8b1f4f2001 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -401,6 +401,16 @@ status = "disabled"; }; + toacodec: audio-controller@740 { + compatible = "amlogic,sm1-toacodec", + "amlogic,g12a-toacodec"; + reg = <0x0 0x740 0x0 0x4>; + #sound-dai-cells = <1>; + sound-name-prefix = "TOACODEC"; + resets = <&clkc_audio AUD_RESET_TOACODEC>; + status = "disabled"; + }; + tohdmitx: audio-controller@744 { compatible = "amlogic,sm1-tohdmitx", "amlogic,g12a-tohdmitx"; diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 1cc7fdcec51b..8e7a66943b01 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -568,13 +568,13 @@ clocks { compatible = "arm,scpi-clocks"; - scpi_dvfs: scpi-dvfs { + scpi_dvfs: clocks-0 { compatible = "arm,scpi-dvfs-clocks"; #clock-cells = <1>; clock-indices = <0>, <1>, <2>; clock-output-names = "atlclk", "aplclk","gpuclk"; }; - scpi_clk: scpi-clk { + scpi_clk: clocks-1 { compatible = "arm,scpi-variable-clocks"; #clock-cells = <1>; clock-indices = <3>; @@ -582,7 +582,7 @@ }; }; - scpi_devpd: scpi-power-domains { + scpi_devpd: power-controller { compatible = "arm,scpi-power-domains"; num-domains = <2>; #power-domain-cells = <1>; diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index 998e240aa698..11eae3e3a944 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb \ +dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \ + bcm2711-rpi-4-b.dtb \ bcm2837-rpi-3-a-plus.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts new file mode 100644 index 000000000000..b9000f58beb5 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "arm/bcm2711-rpi-400.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi index 8060178b365d..a5a64d17d9ea 100644 --- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi @@ -306,7 +306,7 @@ interrupt-names = "nand"; status = "okay"; - nandcs: nandcs@0 { + nandcs: nand@0 { compatible = "brcm,nandcs"; reg = <0>; }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 2ffb2c92182a..7b04dfe67bef 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -470,7 +470,7 @@ status = "disabled"; }; - uart0: uart@100000 { + uart0: serial@100000 { device_type = "serial"; compatible = "snps,dw-apb-uart"; reg = <0x00100000 0x1000>; @@ -481,7 +481,7 @@ status = "disabled"; }; - uart1: uart@110000 { + uart1: serial@110000 { device_type = "serial"; compatible = "snps,dw-apb-uart"; reg = <0x00110000 0x1000>; @@ -492,7 +492,7 @@ status = "disabled"; }; - uart2: uart@120000 { + uart2: serial@120000 { device_type = "serial"; compatible = "snps,dw-apb-uart"; reg = <0x00120000 0x1000>; @@ -503,7 +503,7 @@ status = "disabled"; }; - uart3: uart@130000 { + uart3: serial@130000 { device_type = "serial"; compatible = "snps,dw-apb-uart"; reg = <0x00130000 0x1000>; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 773d9abe3a44..cbcc01a66aab 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -391,6 +391,7 @@ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; reg = <0x66>; samsung,s2mps11-wrstbi-ground; + wakeup-source; s2mps13_osc: clocks { compatible = "samsung,s2mps13-clk"; diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 44890d56c194..25806c4924cb 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts index 6290e2f9de6a..e8562585d4ac 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts @@ -24,6 +24,10 @@ status = "okay"; }; +&pcie1 { + status = "okay"; +}; + &qspi { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 9058cfa4980f..50a72cda4727 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -238,35 +238,35 @@ "fsl,sec-v4.0-rtic"; #address-cells = <1>; #size-cells = <1>; - reg = <0x60000 0x100 0x60e00 0x18>; + reg = <0x60000 0x100>, <0x60e00 0x18>; ranges = <0x0 0x60100 0x500>; rtic_a: rtic-a@0 { compatible = "fsl,sec-v5.4-rtic-memory", "fsl,sec-v5.0-rtic-memory", "fsl,sec-v4.0-rtic-memory"; - reg = <0x00 0x20 0x100 0x100>; + reg = <0x00 0x20>, <0x100 0x100>; }; rtic_b: rtic-b@20 { compatible = "fsl,sec-v5.4-rtic-memory", "fsl,sec-v5.0-rtic-memory", "fsl,sec-v4.0-rtic-memory"; - reg = <0x20 0x20 0x200 0x100>; + reg = <0x20 0x20>, <0x200 0x100>; }; rtic_c: rtic-c@40 { compatible = "fsl,sec-v5.4-rtic-memory", "fsl,sec-v5.0-rtic-memory", "fsl,sec-v4.0-rtic-memory"; - reg = <0x40 0x20 0x300 0x100>; + reg = <0x40 0x20>, <0x300 0x100>; }; rtic_d: rtic-d@60 { compatible = "fsl,sec-v5.4-rtic-memory", "fsl,sec-v5.0-rtic-memory", "fsl,sec-v4.0-rtic-memory"; - reg = <0x60 0x20 0x400 0x100>; + reg = <0x60 0x20>, <0x400 0x100>; }; }; }; @@ -522,8 +522,8 @@ pcie1: pcie@3400000 { compatible = "fsl,ls1012a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 118 0x4>, /* controller interrupt */ <0 117 0x4>; /* PME interrupt */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 9322c6ad8e4a..d7b527272500 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -275,6 +275,10 @@ status = "okay"; }; +&optee { + status = "okay"; +}; + &sai4 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index a30249ebffa8..b2e3e5d2a108 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -88,7 +88,7 @@ }; firmware { - optee { + optee: optee { compatible = "linaro,optee-tz"; method = "smc"; status = "disabled"; @@ -617,8 +617,8 @@ pcie1: pcie@3400000 { compatible = "fsl,ls1028a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ @@ -644,8 +644,8 @@ pcie2: pcie@3500000 { compatible = "fsl,ls1028a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; @@ -990,19 +990,19 @@ msi-map = <0 &its 0x17 0xe>; iommu-map = <0 &smmu 0x17 0xe>; /* PF0-6 BAR0 - non-prefetchable memory */ - ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 + ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 /* PF0-6 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 + 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ - 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 + 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 /* PF0: VF0-1 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 + 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ - 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 + 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 /* PF1: VF0-1 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000 + 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 /* BAR4 (PF5) - non-prefetchable memory */ - 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>; + 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; enetc_port0: ethernet@0,0 { compatible = "fsl,enetc"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 28c51e521cb2..01b01e320411 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -869,8 +869,8 @@ pcie1: pcie@3400000 { compatible = "fsl,ls1043a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 118 0x4>, /* controller interrupt */ <0 117 0x4>; /* PME interrupt */ @@ -895,8 +895,8 @@ pcie2: pcie@3500000 { compatible = "fsl,ls1043a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 128 0x4>, <0 127 0x4>; @@ -921,8 +921,8 @@ pcie3: pcie@3600000 { compatible = "fsl,ls1043a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 162 0x4>, <0 161 0x4>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 39458305e333..687fea6d8afa 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -773,8 +773,8 @@ pcie1: pcie@3400000 { compatible = "fsl,ls1046a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ @@ -799,8 +799,8 @@ pcie_ep1: pcie_ep@3400000 { compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; - reg = <0x00 0x03400000 0x0 0x00100000 - 0x40 0x00000000 0x8 0x00000000>; + reg = <0x00 0x03400000 0x0 0x00100000>, + <0x40 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; num-ib-windows = <6>; num-ob-windows = <8>; @@ -809,8 +809,8 @@ pcie2: pcie@3500000 { compatible = "fsl,ls1046a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ @@ -835,8 +835,8 @@ pcie_ep2: pcie_ep@3500000 { compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; - reg = <0x00 0x03500000 0x0 0x00100000 - 0x48 0x00000000 0x8 0x00000000>; + reg = <0x00 0x03500000 0x0 0x00100000>, + <0x48 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; num-ib-windows = <6>; num-ob-windows = <8>; @@ -845,8 +845,8 @@ pcie3: pcie@3600000 { compatible = "fsl,ls1046a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ @@ -871,8 +871,8 @@ pcie_ep3: pcie_ep@3600000 { compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"; - reg = <0x00 0x03600000 0x0 0x00100000 - 0x50 0x00000000 0x8 0x00000000>; + reg = <0x00 0x03600000 0x0 0x00100000>, + <0x50 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; num-ib-windows = <6>; num-ob-windows = <8>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 8ffbc9fde041..2fa6cfbef01f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -536,8 +536,8 @@ pcie1: pcie@3400000 { compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ interrupt-names = "aer"; @@ -562,8 +562,8 @@ pcie_ep1: pcie-ep@3400000 { compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; - reg = <0x00 0x03400000 0x0 0x00100000 - 0x20 0x00000000 0x8 0x00000000>; + reg = <0x00 0x03400000 0x0 0x00100000>, + <0x20 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; num-ib-windows = <24>; num-ob-windows = <256>; @@ -573,8 +573,8 @@ pcie2: pcie@3500000 { compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ interrupt-names = "aer"; @@ -599,8 +599,8 @@ pcie_ep2: pcie-ep@3500000 { compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; - reg = <0x00 0x03500000 0x0 0x00100000 - 0x28 0x00000000 0x8 0x00000000>; + reg = <0x00 0x03500000 0x0 0x00100000>, + <0x28 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; num-ib-windows = <6>; num-ob-windows = <6>; @@ -609,8 +609,8 @@ pcie3: pcie@3600000 { compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ interrupt-names = "aer"; @@ -635,8 +635,8 @@ pcie_ep3: pcie-ep@3600000 { compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; - reg = <0x00 0x03600000 0x0 0x00100000 - 0x30 0x00000000 0x8 0x00000000>; + reg = <0x00 0x03600000 0x0 0x00100000>, + <0x30 0x00000000 0x8 0x00000000>; reg-names = "regs", "addr_space"; num-ib-windows = <6>; num-ob-windows = <6>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 76ab68d2de0b..6f6667b70028 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -120,32 +120,32 @@ }; &pcie1 { - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x10 0x00000000 0x0 0x00002000>; /* configuration space */ ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; &pcie2 { - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x12 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x12 0x00000000 0x0 0x00002000>; /* configuration space */ ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; &pcie3 { - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x14 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x14 0x00000000 0x0 0x00002000>; /* configuration space */ ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; &pcie4 { - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ - 0x16 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ + <0x16 0x00000000 0x0 0x00002000>; /* configuration space */ ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index da24dc127698..c3dc38188c17 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -121,8 +121,8 @@ &pcie1 { compatible = "fsl,ls2088a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; @@ -130,8 +130,8 @@ &pcie2 { compatible = "fsl,ls2088a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; @@ -139,8 +139,8 @@ &pcie3 { compatible = "fsl,ls2088a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; @@ -148,8 +148,8 @@ &pcie4 { compatible = "fsl,ls2088a-pcie"; - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ - 0x38 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ + <0x38 0x00000000 0x0 0x00002000>; /* configuration space */ ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 135ac8210871..801ba9612d36 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -929,7 +929,6 @@ QORIQ_CLK_PLL_DIV(4)>; clock-names = "dspi"; spi-num-chipselects = <5>; - bus-num = <0>; }; esdhc: esdhc@2140000 { diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 0551f6f4c313..c4b1a59ba424 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1089,8 +1089,8 @@ pcie1: pcie@3400000 { compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "csr_axi_slave", "config_axi_slave"; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ @@ -1117,8 +1117,8 @@ pcie2: pcie@3500000 { compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "csr_axi_slave", "config_axi_slave"; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ @@ -1145,8 +1145,8 @@ pcie3: pcie@3600000 { compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x90 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "csr_axi_slave", "config_axi_slave"; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ @@ -1173,8 +1173,8 @@ pcie4: pcie@3700000 { compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ - 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ + <0x98 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "csr_axi_slave", "config_axi_slave"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ @@ -1201,8 +1201,8 @@ pcie5: pcie@3800000 { compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ - 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */ + <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "csr_axi_slave", "config_axi_slave"; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ @@ -1229,8 +1229,8 @@ pcie6: pcie@3900000 { compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ - 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */ + <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "csr_axi_slave", "config_axi_slave"; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index e1e81ca0ca69..a79f42a9618e 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -77,9 +77,12 @@ conn_subsys: bus@5b000000 { <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; clocks = <&enet0_lpcg IMX_LPCG_CLK_4>, <&enet0_lpcg IMX_LPCG_CLK_2>, - <&enet0_lpcg IMX_LPCG_CLK_1>, + <&enet0_lpcg IMX_LPCG_CLK_3>, <&enet0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; + assigned-clock-rates = <250000000>, <125000000>; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; power-domains = <&pd IMX_SC_R_ENET_0>; @@ -94,9 +97,12 @@ conn_subsys: bus@5b000000 { <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; clocks = <&enet1_lpcg IMX_LPCG_CLK_4>, <&enet1_lpcg IMX_LPCG_CLK_2>, - <&enet1_lpcg IMX_LPCG_CLK_1>, + <&enet1_lpcg IMX_LPCG_CLK_3>, <&enet1_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; + assigned-clock-rates = <250000000>, <125000000>; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; power-domains = <&pd IMX_SC_R_ENET_1>; @@ -152,15 +158,19 @@ conn_subsys: bus@5b000000 { #clock-cells = <1>; clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, - <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, - <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>, - <IMX_LPCG_CLK_5>; - clock-output-names = "enet0_ipg_root_clk", - "enet0_tx_clk", - "enet0_ahb_clk", - "enet0_ipg_clk", - "enet0_ipg_s_clk"; + <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>, + <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; + clock-output-names = "enet0_lpcg_timer_clk", + "enet0_lpcg_txc_sampling_clk", + "enet0_lpcg_ahb_clk", + "enet0_lpcg_rgmii_txc_clk", + "enet0_lpcg_ipg_clk", + "enet0_lpcg_ipg_s_clk"; power-domains = <&pd IMX_SC_R_ENET_0>; }; @@ -170,15 +180,19 @@ conn_subsys: bus@5b000000 { #clock-cells = <1>; clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, - <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, - <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>, - <IMX_LPCG_CLK_5>; - clock-output-names = "enet1_ipg_root_clk", - "enet1_tx_clk", - "enet1_ahb_clk", - "enet1_ipg_clk", - "enet1_ipg_s_clk"; + <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>, + <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; + clock-output-names = "enet1_lpcg_timer_clk", + "enet1_lpcg_txc_sampling_clk", + "enet1_lpcg_ahb_clk", + "enet1_lpcg_rgmii_txc_clk", + "enet1_lpcg_ipg_clk", + "enet1_lpcg_ipg_s_clk"; power-domains = <&pd IMX_SC_R_ENET_1>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 6518f088b2c2..e033d0257b5a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -314,6 +314,7 @@ srp-disable; adp-disable; usb-role-switch; + disable-over-current; samsung,picophy-pre-emp-curr-control = <3>; samsung,picophy-dc-vol-level-adjust = <7>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts new file mode 100644 index 000000000000..5a1e9df39bec --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -0,0 +1,1019 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 Gateworks Corporation + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/leds/common.h> + +#include "imx8mm.dtsi" + +/ { + model = "Gateworks Venice GW7901 i.MX8MM board"; + compatible = "gw,imx8mm-gw7901", "fsl,imx8mm"; + + aliases { + ethernet0 = &fec1; + ethernet1 = &lan1; + ethernet2 = &lan2; + ethernet3 = &lan3; + ethernet4 = &lan4; + usb0 = &usbotg1; + usb1 = &usbotg2; + }; + + chosen { + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = <BTN_1>; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key_erased"; + linux,code = <BTN_2>; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = <BTN_3>; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + tamper { + label = "tamper"; + linux,code = <BTN_4>; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = <BTN_5>; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + led-controller { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + label = "led01_red"; + gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + label = "led01_grn"; + gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-2 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + label = "led02_red"; + gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-3 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + label = "led02_grn"; + gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-4 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + label = "led03_red"; + gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-5 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + label = "led03_grn"; + gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-6 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + label = "led04_red"; + gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-7 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + label = "led04_grn"; + gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-8 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + label = "led05_red"; + gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-9 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + label = "led05_grn"; + gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-a { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + label = "led06_red"; + gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-b { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + label = "led06_grn"; + gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator-ioexp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_ioexp>; + compatible = "regulator-fixed"; + regulator-name = "ioexp"; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + regulator-isouart { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_isouart>; + compatible = "regulator-fixed"; + regulator-name = "iso_uart"; + gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; + startup-delay-us = <100>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb2_vbus: regulator-usb2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2>; + compatible = "regulator-fixed"; + regulator-name = "usb_usb2_vbus"; + gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_wifi: regulator-wifi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wl>; + compatible = "regulator-fixed"; + regulator-name = "wifi"; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + status = "okay"; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + local-mac-address = [00 00 00 00 00 00]; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + pinctrl-0 = <&pinctrl_gsc>; + interrupt-parent = <&gpio4>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vin_aux1"; + gw,voltage-divider-ohms = <22100 1000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vin_aux2"; + gw,voltage-divider-ohms = <22100 1000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_2p5"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@8e { + gw,mode = <2>; + reg = <0x8e>; + label = "vdd_0p95"; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_soc"; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_arm"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_1p8"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_1p2"; + }; + + channel@9c { + gw,mode = <2>; + reg = <0x9c>; + label = "vdd_dram"; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + }; + + gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + + regulators { + /* vdd_soc: 0.805-0.900V (typ=0.8V) */ + BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + /* vdd_arm: 0.805-1.0V (typ=0.9V) */ + BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ + BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_3p3 */ + BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_1p8 */ + BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_dram */ + BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + /* nvcc_snvs_1p8 */ + LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_snvs_0p8 */ + LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdda_1p8 */ + LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + leds_gpio: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + switch: switch@5f { + compatible = "microchip,ksz9897"; + reg = <0x5f>; + pinctrl-0 = <&pinctrl_ksz>; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + phy-mode = "rgmii-id"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + lan1: port@0 { + reg = <0>; + label = "lan1"; + local-mac-address = [00 00 00 00 00 00]; + }; + + lan2: port@1 { + reg = <1>; + label = "lan2"; + local-mac-address = [00 00 00 00 00 00]; + }; + + lan3: port@2 { + reg = <2>; + label = "lan3"; + local-mac-address = [00 00 00 00 00 00]; + }; + + lan4: port@3 { + reg = <3>; + label = "lan4"; + local-mac-address = [00 00 00 00 00 00]; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&fec1>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + crypto@60 { + compatible = "atmel,atecc508a"; + reg = <0x60>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; + rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; + cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>; + cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +/* SDIO WiFi */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wifi>; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */ + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */ + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */ + MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */ + MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */ + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */ + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */ + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */ + >; + }; + + pinctrl_gsc: gscgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_ksz: kszgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41 + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */ + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 + >; + }; + + pinctrl_reg_isouart: regisouartgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 + >; + }; + + pinctrl_reg_ioexp: regioexpgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 + >; + }; + + pinctrl_reg_wl: regwlgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041 + >; + }; + + pinctrl_reg_usb2: regusb1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x41 + MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x41 + >; + }; + + pinctrl_spi1: spi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140 + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140 + >; + }; + + pinctrl_uart1_gpio: uart1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */ + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140 + MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 + >; + }; + + pinctrl_uart3_gpio: uart3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000041 /* RS232# */ + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* RS422# */ + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000041 /* RS485# */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140 + MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140 + >; + }; + + pinctrl_uart4_gpio: uart4gpiogrp { + fsl,pins = < + + MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */ + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */ + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; + +&cpu_alert0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; +}; + +&cpu_crit0 { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index a27e02bee6b4..e7648c3b8390 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -261,6 +261,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; nvmem-cells = <&imx8mm_uid>; nvmem-cell-names = "soc_unique_id"; @@ -271,117 +272,125 @@ #size-cells = <1>; ranges = <0x30000000 0x30000000 0x400000>; - sai1: sai@30010000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30010000 0x10000>; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_SAI1_IPG>, - <&clk IMX8MM_CLK_SAI1_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + spba2: spba-bus@30000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x100000>; + ranges; + + sai1: sai@30010000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30010000 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, + <&clk IMX8MM_CLK_SAI1_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - sai2: sai@30020000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30020000 0x10000>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_SAI2_IPG>, - <&clk IMX8MM_CLK_SAI2_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + sai2: sai@30020000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30020000 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SAI2_IPG>, + <&clk IMX8MM_CLK_SAI2_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - sai3: sai@30030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30030000 0x10000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_SAI3_IPG>, - <&clk IMX8MM_CLK_SAI3_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + sai3: sai@30030000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30030000 0x10000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, + <&clk IMX8MM_CLK_SAI3_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - sai5: sai@30050000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30050000 0x10000>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_SAI5_IPG>, - <&clk IMX8MM_CLK_SAI5_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + sai5: sai@30050000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30050000 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, + <&clk IMX8MM_CLK_SAI5_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - sai6: sai@30060000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30060000 0x10000>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_SAI6_IPG>, - <&clk IMX8MM_CLK_SAI6_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + sai6: sai@30060000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30060000 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SAI6_IPG>, + <&clk IMX8MM_CLK_SAI6_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - micfil: audio-controller@30080000 { - compatible = "fsl,imx8mm-micfil"; - reg = <0x30080000 0x10000>; - interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_PDM_IPG>, - <&clk IMX8MM_CLK_PDM_ROOT>, - <&clk IMX8MM_AUDIO_PLL1_OUT>, - <&clk IMX8MM_AUDIO_PLL2_OUT>, - <&clk IMX8MM_CLK_EXT3>; - clock-names = "ipg_clk", "ipg_clk_app", - "pll8k", "pll11k", "clkext3"; - dmas = <&sdma2 24 25 0x80000000>; - dma-names = "rx"; - status = "disabled"; - }; + micfil: audio-controller@30080000 { + compatible = "fsl,imx8mm-micfil"; + reg = <0x30080000 0x10000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_PDM_IPG>, + <&clk IMX8MM_CLK_PDM_ROOT>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>, + <&clk IMX8MM_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + status = "disabled"; + }; - spdif1: spdif@30090000 { - compatible = "fsl,imx35-spdif"; - reg = <0x30090000 0x10000>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ - <&clk IMX8MM_CLK_24M>, /* rxtx0 */ - <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ - <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ - <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ - <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ - <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ - <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ - <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ - <&clk IMX8MM_CLK_DUMMY>; /* spba */ - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "spba"; - dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; - dma-names = "rx", "tx"; - status = "disabled"; + spdif1: spdif@30090000 { + compatible = "fsl,imx35-spdif"; + reg = <0x30090000 0x10000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ + <&clk IMX8MM_CLK_24M>, /* rxtx0 */ + <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MM_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; }; gpio1: gpio@30200000 { @@ -670,80 +679,88 @@ ranges = <0x30800000 0x30800000 0x400000>, <0x8000000 0x8000000 0x10000000>; - ecspi1: spi@30820000 { - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + spba1: spba-bus@30800000 { + compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - reg = <0x30820000 0x10000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, - <&clk IMX8MM_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + #size-cells = <1>; + reg = <0x30800000 0x100000>; + ranges; + + ecspi1: spi@30820000 { + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30820000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, + <&clk IMX8MM_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - ecspi2: spi@30830000 { - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30830000 0x10000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, - <&clk IMX8MM_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi2: spi@30830000 { + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30830000 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, + <&clk IMX8MM_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - ecspi3: spi@30840000 { - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30840000 0x10000>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, - <&clk IMX8MM_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi3: spi@30840000 { + compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30840000 0x10000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, + <&clk IMX8MM_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart1: serial@30860000 { - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_UART1_ROOT>, - <&clk IMX8MM_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + uart1: serial@30860000 { + compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_UART1_ROOT>, + <&clk IMX8MM_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart3: serial@30880000 { - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_UART3_ROOT>, - <&clk IMX8MM_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + uart3: serial@30880000 { + compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_UART3_ROOT>, + <&clk IMX8MM_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart2: serial@30890000 { - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MM_CLK_UART2_ROOT>, - <&clk IMX8MM_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; + uart2: serial@30890000 { + compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_UART2_ROOT>, + <&clk IMX8MM_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; }; crypto: crypto@30900000 { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index c35eeaff958f..54eaf3d6055b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -120,6 +120,9 @@ interrupt-parent = <&gpio1>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; regulators { buck1_reg: BUCK1 { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index a0dddba2e561..85e65f8719ea 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -193,6 +193,7 @@ srp-disable; adp-disable; usb-role-switch; + disable-over-current; samsung,picophy-pre-emp-curr-control = <3>; samsung,picophy-dc-vol-level-adjust = <7>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 4dac4da38f4c..d4231e061403 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -245,6 +245,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; nvmem-cells = <&imx8mn_uid>; nvmem-cell-names = "soc_unique_id"; @@ -255,7 +256,7 @@ #size-cells = <1>; ranges; - spba: spba-bus@30000000 { + spba2: spba-bus@30000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -681,80 +682,88 @@ #size-cells = <1>; ranges; - ecspi1: spi@30820000 { - compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; + spba1: spba-bus@30800000 { + compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - reg = <0x30820000 0x10000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, - <&clk IMX8MN_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + #size-cells = <1>; + reg = <0x30800000 0x100000>; + ranges; - ecspi2: spi@30830000 { - compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30830000 0x10000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, - <&clk IMX8MN_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi1: spi@30820000 { + compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30820000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, + <&clk IMX8MN_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - ecspi3: spi@30840000 { - compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30840000 0x10000>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, - <&clk IMX8MN_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi2: spi@30830000 { + compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30830000 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, + <&clk IMX8MN_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart1: serial@30860000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MN_CLK_UART1_ROOT>, - <&clk IMX8MN_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi3: spi@30840000 { + compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30840000 0x10000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, + <&clk IMX8MN_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart3: serial@30880000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MN_CLK_UART3_ROOT>, - <&clk IMX8MN_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + uart1: serial@30860000 { + compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_UART1_ROOT>, + <&clk IMX8MN_CLK_UART1_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart2: serial@30890000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MN_CLK_UART2_ROOT>, - <&clk IMX8MN_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; + uart3: serial@30880000 { + compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_UART3_ROOT>, + <&clk IMX8MN_CLK_UART3_ROOT>; + clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_UART2_ROOT>, + <&clk IMX8MN_CLK_UART2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; }; crypto: crypto@30900000 { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 2c28e589677e..7b99fad6e4d6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -81,6 +81,26 @@ status = "disabled";/* can2 pin conflict with pdm */ }; +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; @@ -104,6 +124,92 @@ }; }; +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1025000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1045000>; + regulator-max-microvolt = <1155000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + &i2c3 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -177,6 +283,26 @@ }; &iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 @@ -229,6 +355,13 @@ >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 @@ -236,6 +369,12 @@ >; }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index f3965ec5b31d..aa78e0d8c72b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -65,6 +65,20 @@ }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + som_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -217,6 +231,17 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index c2d51a46cb3c..ca38d0d6c3c4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -37,6 +37,7 @@ serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; + spi0 = &flexspi; }; cpus { @@ -407,7 +408,6 @@ <&clk IMX8MP_CLK_GIC>, <&clk IMX8MP_CLK_AUDIO_AHB>, <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, - <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, @@ -423,7 +423,6 @@ <500000000>, <400000000>, <800000000>, - <400000000>, <393216000>, <361267200>; }; @@ -761,6 +760,21 @@ status = "disabled"; }; + flexspi: spi@30bb0000 { + compatible = "nxp,imx8mp-fspi"; + reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, + <&clk IMX8MP_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_QSPI>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sdma1: dma-controller@30bd0000 { compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; reg = <0x30bd0000 0x10000>; @@ -807,9 +821,9 @@ eqos: ethernet@30bf0000 { compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; reg = <0x30bf0000 0x10000>; - interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "eth_wake_irq", "macirq"; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, <&clk IMX8MP_CLK_QOS_ENET_ROOT>, <&clk IMX8MP_CLK_ENET_QOS_TIMER>, diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 85b045253a0e..4d2035e3dd7c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -318,6 +318,7 @@ <&clk IMX8MQ_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + vph-supply = <&vgen5_reg>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts index 81d269296610..f70fb32b96b0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts @@ -34,6 +34,30 @@ }; }; + hdmi-connector { + compatible = "hdmi-connector"; + ddc-i2c-bus = <&ddc_i2c_bus>; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <<8912_out>; + }; + }; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_vref_0v9: regulator-vref-0v9 { compatible = "regulator-fixed"; regulator-name = "vref-0v9"; @@ -70,6 +94,9 @@ }; }; +&dphy { + status = "okay"; +}; &fec1 { pinctrl-names = "default"; @@ -91,6 +118,15 @@ }; }; +/* Release reset of the USB Host HUB */ +&gpio1 { + usb-host-reset-hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -174,6 +210,98 @@ }; }; +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + pca9546: i2cmux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c4@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + + hdmi-bridge@48 { + compatible = "lontium,lt8912b"; + reg = <0x48> ; + reset-gpios = <&max7323 0 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_out_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + lt8912_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + }; + + ddc_i2c_bus: i2c4@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + }; + + i2c4@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + + max7323: gpio-expander@68 { + compatible = "maxim,max7323"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max7323>; + gpio-controller; + reg = <0x68>; + #gpio-cells = <2>; + }; + }; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + remote-endpoint = <&hdmi_out_in>; + }; + }; + }; +}; + &uart1 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -190,6 +318,29 @@ status = "okay"; }; +&usb_dwc3_0 { + dr_mode = "otg"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3_0>; + status = "okay"; +}; + +&usb3_phy0 { + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb3_phy1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3_1>; + status = "okay"; +}; + &usdhc1 { assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; assigned-clock-rates = <400000000>; @@ -321,6 +472,19 @@ >; }; + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f + MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f + >; + }; + + pinctrl_max7323: max7323grp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 + >; + }; + pinctrl_reg_arm_dram: reg-arm-dramgrp { fsl,pins = < MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16 @@ -339,6 +503,12 @@ >; }; + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x16 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45 @@ -353,6 +523,18 @@ >; }; + pinctrl_usb3_0: usb3-0grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16 + >; + }; + + pinctrl_usb3_1: usb3-1grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 17c449e12c2e..91df9c5350ae 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1383,6 +1383,14 @@ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; reset-names = "pciephy", "apps", "turnoff"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_AUX>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <250000000>, <100000000>, + <10000000>; status = "disabled"; }; @@ -1413,6 +1421,14 @@ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; reset-names = "pciephy", "apps", "turnoff"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <250000000>, <100000000>, + <10000000>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi index d607f2f6698c..79a55a0fa2f1 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi @@ -3,7 +3,7 @@ /* * dtsi for Hisilicon Hi3660 Coresight * - * Copyright (C) 2016-2018 Hisilicon Ltd. + * Copyright (C) 2016-2018 HiSilicon Ltd. * * Author: Wanglai Shi <shiwanglai@hisilicon.com> * diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 963300eede17..f68580dc87d8 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -2,7 +2,7 @@ /* * dts file for Hisilicon HiKey960 Development Board * - * Copyright (C) 2016, Hisilicon Ltd. + * Copyright (C) 2016, HiSilicon Ltd. * */ diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index cab89dc6f596..f1ec87c05842 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -2,7 +2,7 @@ /* * dts file for Hisilicon Hi3660 SoC * - * Copyright (C) 2016, Hisilicon Ltd. + * Copyright (C) 2016, HiSilicon Ltd. */ #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts index 7f9f9886c349..d8abf442ee7e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts @@ -2,7 +2,7 @@ /* * dts file for Hisilicon HiKey970 Development Board * - * Copyright (C) 2016, Hisilicon Ltd. + * Copyright (C) 2016, HiSilicon Ltd. * Copyright (C) 2018, Linaro Ltd. * */ diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 8830795c8efc..20698cfd0637 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -2,7 +2,7 @@ /* * dts file for Hisilicon Hi3670 SoC * - * Copyright (C) 2016, Hisilicon Ltd. + * Copyright (C) 2016, HiSilicon Ltd. * Copyright (C) 2018, Linaro Ltd. */ diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi index 7b3010f448c5..3f387f4cf5e0 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi @@ -2,7 +2,7 @@ /* * dtsi file for Hisilicon Hi6220 coresight * - * Copyright (C) 2017 Hisilicon Ltd. + * Copyright (C) 2017 HiSilicon Ltd. * * Author: Pengcheng Li <lipengcheng8@huawei.com> * Leo Yan <leo.yan@linaro.org> diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 91d08673c02e..3df2afb2f637 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -2,7 +2,7 @@ /* * dts file for Hisilicon HiKey Development Board * - * Copyright (C) 2015, Hisilicon Ltd. + * Copyright (C) 2015, HiSilicon Ltd. * */ diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index d426c6c8722b..dde9371dc545 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -2,7 +2,7 @@ /* * dts file for Hisilicon Hi6220 SoC * - * Copyright (C) 2015, Hisilicon Ltd. + * Copyright (C) 2015, HiSilicon Ltd. */ #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts index 369b69b17b91..40f3e00ac832 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts @@ -2,7 +2,7 @@ /** * dts file for Hisilicon D02 Development Board * - * Copyright (C) 2014,2015 Hisilicon Ltd. + * Copyright (C) 2014,2015 HiSilicon Ltd. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 4aed8d440b3a..7b2abd10d3d6 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -2,7 +2,7 @@ /** * dts file for Hisilicon D02 Development Board * - * Copyright (C) 2014,2015 Hisilicon Ltd. + * Copyright (C) 2014,2015 HiSilicon Ltd. */ #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts index 9f4a930e734d..35af5d3821e8 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts +++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts @@ -2,7 +2,7 @@ /** * dts file for Hisilicon D03 Development Board * - * Copyright (C) 2016 Hisilicon Ltd. + * Copyright (C) 2016 HiSilicon Ltd. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 7deca5f763d5..70d7732dd348 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -2,7 +2,7 @@ /** * dts file for Hisilicon D03 Development Board * - * Copyright (C) 2016 Hisilicon Ltd. + * Copyright (C) 2016 HiSilicon Ltd. */ #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts index 81a2312c8a26..c3df67845f03 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts +++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts @@ -2,7 +2,7 @@ /** * dts file for Hisilicon D05 Development Board * - * Copyright (C) 2016 Hisilicon Ltd. + * Copyright (C) 2016 HiSilicon Ltd. */ /dts-v1/; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 2172d8071181..6baf6a686450 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -2,7 +2,7 @@ /** * dts file for Hisilicon D05 Development Board * - * Copyright (C) 2016 Hisilicon Ltd. + * Copyright (C) 2016 HiSilicon Ltd. */ #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index 53e817c5f6f3..ce2bcddf396f 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -109,10 +109,8 @@ }; firmware { - turris-mox-rwtm { - compatible = "cznic,turris-mox-rwtm"; - mboxes = <&rwtm 0>; - status = "okay"; + armada-3700-rwtm { + compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm"; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 6ffbb099fcac..5db81a416cd6 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -504,4 +504,12 @@ }; }; }; + + firmware { + armada-3700-rwtm { + compatible = "marvell,armada-3700-rwtm-firmware"; + mboxes = <&rwtm 0>; + status = "okay"; + }; + }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap807.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi index d9bbbfa4b4eb..4a23f65d475f 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap807.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi @@ -29,6 +29,7 @@ }; &ap_sdhci0 { - compatible = "marvell,armada-ap807-sdhci"; + compatible = "marvell,armada-ap807-sdhci", + "marvell,armada-ap806-sdhci"; /* Backward compatibility */ }; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts b/arch/arm64/boot/dts/marvell/cn9130-db.dts index 2c2af001619b..9758609541c7 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dts +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts @@ -260,7 +260,7 @@ }; partition@200000 { label = "Linux"; - reg = <0x200000 0xd00000>; + reg = <0x200000 0xe00000>; }; partition@1000000 { label = "Filesystem"; diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index a1c50adc98fa..4f68ebed2e31 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -13,8 +13,16 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 1c5639ead622..9029051624a6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/clock/mt8167-clk.h> #include <dt-bindings/memory/mt8167-larb-port.h> +#include <dt-bindings/power/mt8167-power.h> #include "mt8167-pinfunc.h" @@ -34,6 +35,73 @@ #clock-cells = <1>; }; + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + spm: power-controller { + compatible = "mediatek,mt8167-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domains of the SoC */ + power-domain@MT8167_POWER_DOMAIN_MM { + reg = <MT8167_POWER_DOMAIN_MM>; + clocks = <&topckgen CLK_TOP_SMI_MM>; + clock-names = "mm"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8167_POWER_DOMAIN_VDEC { + reg = <MT8167_POWER_DOMAIN_VDEC>; + clocks = <&topckgen CLK_TOP_SMI_MM>, + <&topckgen CLK_TOP_RG_VDEC>; + clock-names = "mm", "vdec"; + #power-domain-cells = <0>; + }; + + power-domain@MT8167_POWER_DOMAIN_ISP { + reg = <MT8167_POWER_DOMAIN_ISP>; + clocks = <&topckgen CLK_TOP_SMI_MM>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + + power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC { + reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>; + clocks = <&topckgen CLK_TOP_RG_AXI_MFG>, + <&topckgen CLK_TOP_RG_SLOW_MFG>; + clock-names = "axi_mfg", "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + mediatek,infracfg = <&infracfg>; + + power-domain@MT8167_POWER_DOMAIN_MFG_2D { + reg = <MT8167_POWER_DOMAIN_MFG_2D>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8167_POWER_DOMAIN_MFG { + reg = <MT8167_POWER_DOMAIN_MFG>; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + + power-domain@MT8167_POWER_DOMAIN_CONN { + reg = <MT8167_POWER_DOMAIN_CONN>; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + imgsys: syscon@15000000 { compatible = "mediatek,mt8167-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; @@ -57,5 +125,58 @@ #interrupt-cells = <2>; interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; }; + + mmsys: mmsys@14000000 { + compatible = "mediatek,mt8167-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + smi_common: smi@14017000 { + compatible = "mediatek,mt8167-smi-common"; + reg = <0 0x14017000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + }; + + larb0: larb@14016000 { + compatible = "mediatek,mt8167-smi-larb"; + reg = <0 0x14016000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + }; + + larb1: larb@15001000 { + compatible = "mediatek,mt8167-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB1_SMI>, + <&imgsys CLK_IMG_LARB1_SMI>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_ISP>; + }; + + larb2: larb@16010000 { + compatible = "mediatek,mt8167-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_CKEN>, + <&vdecsys CLK_VDEC_LARB1_CKEN>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>; + }; + + iommu: m4u@10203000 { + compatible = "mediatek,mt8167-m4u"; + reg = <0 0x10203000 0 0x1000>; + mediatek,larbs = <&larb0 &larb1 &larb2>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>; + #iommu-cells = <1>; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 003a5653c505..22f271b1f5b0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1459,14 +1459,11 @@ clock-names = "apb", "smi"; }; - vcodec_enc: vcodec@18002000 { + vcodec_enc_avc: vcodec@18002000 { compatible = "mediatek,mt8173-vcodec-enc"; - reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ - <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; - mediatek,larb = <&larb3>, - <&larb5>; + reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */ + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; + mediatek,larb = <&larb3>; iommus = <&iommu M4U_PORT_VENC_RCPU>, <&iommu M4U_PORT_VENC_REC>, <&iommu M4U_PORT_VENC_BSDMA>, @@ -1477,29 +1474,12 @@ <&iommu M4U_PORT_VENC_REF_LUMA>, <&iommu M4U_PORT_VENC_REF_CHROMA>, <&iommu M4U_PORT_VENC_NBM_RDMA>, - <&iommu M4U_PORT_VENC_NBM_WDMA>, - <&iommu M4U_PORT_VENC_RCPU_SET2>, - <&iommu M4U_PORT_VENC_REC_FRM_SET2>, - <&iommu M4U_PORT_VENC_BSDMA_SET2>, - <&iommu M4U_PORT_VENC_SV_COMA_SET2>, - <&iommu M4U_PORT_VENC_RD_COMA_SET2>, - <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, - <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, - <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, - <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; + <&iommu M4U_PORT_VENC_NBM_WDMA>; mediatek,vpu = <&vpu>; - clocks = <&topckgen CLK_TOP_VENCPLL_D2>, - <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_UNIVPLL1_D2>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - clock-names = "venc_sel_src", - "venc_sel", - "venc_lt_sel_src", - "venc_lt_sel"; - assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>, - <&topckgen CLK_TOP_VCODECPLL_370P5>; + clocks = <&topckgen CLK_TOP_VENC_SEL>; + clock-names = "venc_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; }; jpegdec: jpegdec@18004000 { @@ -1531,5 +1511,27 @@ <&vencltsys CLK_VENCLT_CKE0>; clock-names = "apb", "smi"; }; + + vcodec_enc_vp8: vcodec@19002000 { + compatible = "mediatek,mt8173-vcodec-enc-vp8"; + reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, + <&iommu M4U_PORT_VENC_REC_FRM_SET2>, + <&iommu M4U_PORT_VENC_BSDMA_SET2>, + <&iommu M4U_PORT_VENC_SV_COMA_SET2>, + <&iommu M4U_PORT_VENC_RD_COMA_SET2>, + <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, + <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, + <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, + <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; + mediatek,larb = <&larb5>; + mediatek,vpu = <&vpu>; + clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; + clock-names = "venc_lt_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; + assigned-clock-parents = + <&topckgen CLK_TOP_VCODECPLL_370P5>; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index edff1e03e6fe..7bc0a6a7fadf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -42,6 +42,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&mt6358_vgpu_reg>; + sram-supply = <&mt6358_vsram_gpu_reg>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c_pins_0>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts new file mode 100644 index 000000000000..a8d6f32ade8d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" + +/ { + model = "Google burnet board"; + compatible = "google,burnet", "mediatek,mt8183"; +}; + +&mt6358codec { + mediatek,dmic-mode = <1>; /* one-wire */ +}; + +&i2c0 { + touchscreen@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <200>; + hid-descr-addr = <0x0020>; + }; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts new file mode 100644 index 000000000000..ef6257c9a2d2 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-fennel.dtsi" + +/ { + model = "Google fennel sku1 board"; + compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183"; + + pwmleds { + compatible = "pwm-leds"; + keyboard_backlight: keyboard-backlight { + label = "cros_ec::kbd_backlight"; + pwms = <&cros_ec_pwm 0>; + max-brightness = <1023>; + }; + }; +}; + +&cros_ec_pwm { + status = "okay"; +}; + +&touchscreen { + status = "okay"; + + compatible = "hid-over-i2c"; + reg = <0x10>; + interrupt-parent = <&pio>; + interrupts = <155 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_FENNEL"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts new file mode 100644 index 000000000000..899c2e42385c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-fennel.dtsi" + +/ { + model = "Google fennel sku6 board"; + compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183"; +}; + +&touchscreen { + status = "okay"; + + compatible = "hid-over-i2c"; + reg = <0x10>; + interrupt-parent = <&pio>; + interrupts = <155 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; +}; + + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_FENNEL"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi new file mode 100644 index 000000000000..bbe6c338f465 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" + +&mt6358codec { + mediatek,dmic-mode = <1>; /* one-wire */ +}; + +&i2c2 { + trackpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + + interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + }; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts new file mode 100644 index 000000000000..e8c41f6b4b0d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-fennel.dtsi" + +/ { + model = "Google fennel14 sku0 board"; + compatible = "google,fennel-sku0", "google,fennel", "mediatek,mt8183"; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_FENNEL14"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts new file mode 100644 index 000000000000..b3f46c16e5d7 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" + +/ { + model = "Google kappa board"; + compatible = "google,kappa", "mediatek,mt8183"; +}; + +&mt6358codec { + mediatek,dmic-mode = <1>; /* one-wire */ +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts new file mode 100644 index 000000000000..6f1aa692753a --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-juniper.dtsi" + +/ { + model = "Google kenzo sku17 board"; + compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts new file mode 100644 index 000000000000..281265f082db --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-willow.dtsi" + +/ { + model = "Google willow board sku0"; + compatible = "google,willow-sku0", "google,willow", "mediatek,mt8183"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts new file mode 100644 index 000000000000..22e56bdc1ee3 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-willow.dtsi" + +/ { + model = "Google willow board sku1"; + compatible = "google,willow-sku1", "google,willow", "mediatek,mt8183"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi new file mode 100644 index 000000000000..76d33540166f --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" + +&i2c2 { + trackpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + + interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + }; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_JUNIPER"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 4049dff8464b..d8826c82bcda 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -92,6 +92,14 @@ }; }; +&cros_ec { + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + status = "disabled"; + }; +}; + &dsi0 { status = "okay"; /delete-node/panel@0; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi index b442e38a3156..28966a65391b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi @@ -88,11 +88,13 @@ pinctrl-0 = <&i2c2_pins>; status = "okay"; clock-frequency = <400000>; + vbus-supply = <&mt6358_vcamio_reg>; eeprom@58 { compatible = "atmel,24c32"; reg = <0x58>; pagesize = <32>; + vcc-supply = <&mt6358_vcama2_reg>; }; }; @@ -101,11 +103,13 @@ pinctrl-0 = <&i2c4_pins>; status = "okay"; clock-frequency = <400000>; + vbus-supply = <&mt6358_vcn18_reg>; eeprom@54 { compatible = "atmel,24c32"; reg = <0x54>; pagesize = <32>; + vcc-supply = <&mt6358_vcn18_reg>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi index 2f5234a16ead..3aa79403c0c2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi @@ -62,11 +62,13 @@ pinctrl-0 = <&i2c2_pins>; status = "okay"; clock-frequency = <400000>; + vbus-supply = <&mt6358_vcamio_reg>; eeprom@58 { compatible = "atmel,24c64"; reg = <0x58>; pagesize = <32>; + vcc-supply = <&mt6358_vcamio_reg>; }; }; @@ -75,11 +77,13 @@ pinctrl-0 = <&i2c4_pins>; status = "okay"; clock-frequency = <400000>; + vbus-supply = <&mt6358_vcn18_reg>; eeprom@54 { compatible = "atmel,24c64"; reg = <0x54>; pagesize = <32>; + vcc-supply = <&mt6358_vcn18_reg>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi index fbc471ccf805..30c183c96a54 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi @@ -71,11 +71,13 @@ pinctrl-0 = <&i2c2_pins>; status = "okay"; clock-frequency = <400000>; + vbus-supply = <&mt6358_vcamio_reg>; eeprom@58 { compatible = "atmel,24c32"; reg = <0x58>; pagesize = <32>; + vcc-supply = <&mt6358_vcama2_reg>; }; }; @@ -84,11 +86,13 @@ pinctrl-0 = <&i2c4_pins>; status = "okay"; clock-frequency = <400000>; + vbus-supply = <&mt6358_vcn18_reg>; eeprom@54 { compatible = "atmel,24c32"; reg = <0x54>; pagesize = <32>; + vcc-supply = <&mt6358_vcn18_reg>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index ff56bcfa3370..ae549d55a94f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -279,6 +279,11 @@ }; }; +&gpu { + mali-supply = <&mt6358_vgpu_reg>; + sram-supply = <&mt6358_vsram_gpu_reg>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -816,6 +821,10 @@ compatible = "google,extcon-usbc-cros-ec"; google,usb-port-id = <0>; }; + + cbas { + compatible = "google,cros-cbas"; + }; }; }; @@ -847,6 +856,20 @@ status = "okay"; }; +&thermal_zones { + tboard1 { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&tboard_thermistor1>; + }; + + tboard2 { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&tboard_thermistor2>; + }; +}; + &u3phy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index 0aff5eb52e88..ee912825cfc6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -68,6 +68,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&mt6358_vgpu_reg>; + sram-supply = <&mt6358_vsram_gpu_reg>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c_pins_0>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index c5e822b6b77a..f90df6439c08 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -197,6 +197,91 @@ }; }; + gpu_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <625000>, <850000>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + opp-microvolt = <631250>, <850000>; + }; + + opp-340000000 { + opp-hz = /bits/ 64 <340000000>; + opp-microvolt = <637500>, <850000>; + }; + + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + opp-microvolt = <643750>, <850000>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + opp-microvolt = <650000>, <850000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <656250>, <850000>; + }; + + opp-420000000 { + opp-hz = /bits/ 64 <420000000>; + opp-microvolt = <662500>, <850000>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + opp-microvolt = <675000>, <850000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <687500>, <850000>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + opp-microvolt = <700000>, <850000>; + }; + + opp-580000000 { + opp-hz = /bits/ 64 <580000000>; + opp-microvolt = <712500>, <850000>; + }; + + opp-620000000 { + opp-hz = /bits/ 64 <620000000>; + opp-microvolt = <725000>, <850000>; + }; + + opp-653000000 { + opp-hz = /bits/ 64 <653000000>; + opp-microvolt = <743750>, <850000>; + }; + + opp-698000000 { + opp-hz = /bits/ 64 <698000000>; + opp-microvolt = <768750>, <868750>; + }; + + opp-743000000 { + opp-hz = /bits/ 64 <743000000>; + opp-microvolt = <793750>, <893750>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <825000>, <925000>; + }; + }; + pmu-a53 { compatible = "arm,cortex-a53-pmu"; interrupt-parent = <&gic>; @@ -673,7 +758,7 @@ nvmem-cell-names = "calibration-data"; }; - thermal-zones { + thermal_zones: thermal-zones { cpu_thermal: cpu_thermal { polling-delay-passive = <100>; polling-delay = <500>; @@ -1118,6 +1203,26 @@ #clock-cells = <1>; }; + gpu: gpu@13040000 { + compatible = "mediatek,mt8183-mali", "arm,mali-bifrost"; + reg = <0 0x13040000 0 0x4000>; + interrupts = + <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "job", "mmu", "gpu"; + + clocks = <&topckgen CLK_TOP_MFGPLL_CK>; + + power-domains = + <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, + <&spm MT8183_POWER_DOMAIN_MFG_CORE1>, + <&spm MT8183_POWER_DOMAIN_MFG_2D>; + power-domain-names = "core0", "core1", "core2"; + + operating-points-v2 = <&gpu_opp_table>; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt8183-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; @@ -1263,13 +1368,14 @@ }; smi_common: smi@14019000 { - compatible = "mediatek,mt8183-smi-common", "syscon"; + compatible = "mediatek,mt8183-smi-common"; reg = <0 0x14019000 0 0x1000>; clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_GALS_COMM0>, <&mmsys CLK_MM_GALS_COMM1>; clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; }; imgsys: syscon@15020000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 683743f81849..74c1a5df3fdb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -817,7 +817,7 @@ }; hda@3510000 { - nvidia,model = "jetson-tx2-hda"; + nvidia,model = "NVIDIA Jetson TX2 HDA"; status = "okay"; }; @@ -1109,6 +1109,6 @@ <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>, <&dspk1_port>, <&dspk2_port>; - label = "jetson-tx2-ape"; + label = "NVIDIA Jetson TX2 APE"; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 9f75bbf00cf7..d02f6bf3e2ca 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1082,7 +1082,7 @@ }; smmu: iommu@12000000 { - compatible = "arm,mmu-500"; + compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; reg = <0 0x12000000 0 0x800000>; interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, @@ -1152,6 +1152,8 @@ stream-match-mask = <0x7f80>; #global-interrupts = <1>; #iommu-cells = <1>; + + nvidia,memory-controller = <&mc>; }; host1x@13e00000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index d618f197a1d3..96bd01cadb18 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -554,7 +554,7 @@ }; hda@3510000 { - nvidia,model = "jetson-xavier-hda"; + nvidia,model = "NVIDIA Jetson AGX Xavier HDA"; status = "okay"; }; @@ -831,7 +831,7 @@ <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>, <&dmic3_port>; - label = "jetson-xavier-ape"; + label = "NVIDIA Jetson AGX Xavier APE"; widgets = "Microphone", "CVB-RT MIC Jack", diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index d1d77220154f..836a7e0a4267 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -15,6 +15,577 @@ interrupt-controller@2a40000 { status = "okay"; }; + + ahub@2900800 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + xbar_admaif0_ep: endpoint { + remote-endpoint = <&admaif0_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + xbar_admaif1_ep: endpoint { + remote-endpoint = <&admaif1_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + xbar_admaif2_ep: endpoint { + remote-endpoint = <&admaif2_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + xbar_admaif3_ep: endpoint { + remote-endpoint = <&admaif3_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + xbar_admaif4_ep: endpoint { + remote-endpoint = <&admaif4_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + xbar_admaif5_ep: endpoint { + remote-endpoint = <&admaif5_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + xbar_admaif6_ep: endpoint { + remote-endpoint = <&admaif6_ep>; + }; + }; + + port@7 { + reg = <0x7>; + + xbar_admaif7_ep: endpoint { + remote-endpoint = <&admaif7_ep>; + }; + }; + + port@8 { + reg = <0x8>; + + xbar_admaif8_ep: endpoint { + remote-endpoint = <&admaif8_ep>; + }; + }; + + port@9 { + reg = <0x9>; + + xbar_admaif9_ep: endpoint { + remote-endpoint = <&admaif9_ep>; + }; + }; + + port@a { + reg = <0xa>; + + xbar_admaif10_ep: endpoint { + remote-endpoint = <&admaif10_ep>; + }; + }; + + port@b { + reg = <0xb>; + + xbar_admaif11_ep: endpoint { + remote-endpoint = <&admaif11_ep>; + }; + }; + + port@c { + reg = <0xc>; + + xbar_admaif12_ep: endpoint { + remote-endpoint = <&admaif12_ep>; + }; + }; + + port@d { + reg = <0xd>; + + xbar_admaif13_ep: endpoint { + remote-endpoint = <&admaif13_ep>; + }; + }; + + port@e { + reg = <0xe>; + + xbar_admaif14_ep: endpoint { + remote-endpoint = <&admaif14_ep>; + }; + }; + + port@f { + reg = <0xf>; + + xbar_admaif15_ep: endpoint { + remote-endpoint = <&admaif15_ep>; + }; + }; + + port@10 { + reg = <0x10>; + + xbar_admaif16_ep: endpoint { + remote-endpoint = <&admaif16_ep>; + }; + }; + + port@11 { + reg = <0x11>; + + xbar_admaif17_ep: endpoint { + remote-endpoint = <&admaif17_ep>; + }; + }; + + port@12 { + reg = <0x12>; + + xbar_admaif18_ep: endpoint { + remote-endpoint = <&admaif18_ep>; + }; + }; + + port@13 { + reg = <0x13>; + + xbar_admaif19_ep: endpoint { + remote-endpoint = <&admaif19_ep>; + }; + }; + + xbar_i2s3_port: port@16 { + reg = <0x16>; + + xbar_i2s3_ep: endpoint { + remote-endpoint = <&i2s3_cif_ep>; + }; + }; + + xbar_i2s5_port: port@18 { + reg = <0x18>; + + xbar_i2s5_ep: endpoint { + remote-endpoint = <&i2s5_cif_ep>; + }; + }; + + xbar_dmic1_port: port@1a { + reg = <0x1a>; + + xbar_dmic1_ep: endpoint { + remote-endpoint = <&dmic1_cif_ep>; + }; + }; + + xbar_dmic2_port: port@1b { + reg = <0x1b>; + + xbar_dmic2_ep: endpoint { + remote-endpoint = <&dmic2_cif_ep>; + }; + }; + + xbar_dmic4_port: port@1d { + reg = <0x1d>; + + xbar_dmic4_ep: endpoint { + remote-endpoint = <&dmic4_cif_ep>; + }; + }; + + xbar_dspk1_port: port@1e { + reg = <0x1e>; + + xbar_dspk1_ep: endpoint { + remote-endpoint = <&dspk1_cif_ep>; + }; + }; + + xbar_dspk2_port: port@1f { + reg = <0x1f>; + + xbar_dspk2_ep: endpoint { + remote-endpoint = <&dspk2_cif_ep>; + }; + }; + }; + + admaif@290f000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0_ep: endpoint { + remote-endpoint = <&xbar_admaif0_ep>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1_ep: endpoint { + remote-endpoint = <&xbar_admaif1_ep>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2_ep: endpoint { + remote-endpoint = <&xbar_admaif2_ep>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3_ep: endpoint { + remote-endpoint = <&xbar_admaif3_ep>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4_ep: endpoint { + remote-endpoint = <&xbar_admaif4_ep>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5_ep: endpoint { + remote-endpoint = <&xbar_admaif5_ep>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6_ep: endpoint { + remote-endpoint = <&xbar_admaif6_ep>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7_ep: endpoint { + remote-endpoint = <&xbar_admaif7_ep>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8_ep: endpoint { + remote-endpoint = <&xbar_admaif8_ep>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9_ep: endpoint { + remote-endpoint = <&xbar_admaif9_ep>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10_ep: endpoint { + remote-endpoint = <&xbar_admaif10_ep>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11_ep: endpoint { + remote-endpoint = <&xbar_admaif11_ep>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12_ep: endpoint { + remote-endpoint = <&xbar_admaif12_ep>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13_ep: endpoint { + remote-endpoint = <&xbar_admaif13_ep>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14_ep: endpoint { + remote-endpoint = <&xbar_admaif14_ep>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15_ep: endpoint { + remote-endpoint = <&xbar_admaif15_ep>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16_ep: endpoint { + remote-endpoint = <&xbar_admaif16_ep>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17_ep: endpoint { + remote-endpoint = <&xbar_admaif17_ep>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18_ep: endpoint { + remote-endpoint = <&xbar_admaif18_ep>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19_ep: endpoint { + remote-endpoint = <&xbar_admaif19_ep>; + }; + }; + }; + }; + + i2s@2901200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s3_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s3_ep>; + }; + }; + + i2s3_port: port@1 { + reg = <1>; + + i2s3_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + i2s@2901400 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s5_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s5_ep>; + }; + }; + + i2s5_port: port@1 { + reg = <1>; + + i2s5_dap_ep: endpoint@0 { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + + dmic1_port: port@1 { + reg = <1>; + + dmic1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + + dmic2_port: port@1 { + reg = <1>; + + dmic2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic4_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic4_ep>; + }; + }; + + dmic4_port: port@1 { + reg = <1>; + + dmic4_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dspk@2905000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk1_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk1_ep>; + }; + }; + + dspk1_port: port@1 { + reg = <1>; + + dspk1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dspk@2905100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk2_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk2_ep>; + }; + }; + + dspk2_port: port@1 { + reg = <1>; + + dspk2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + }; }; ddc: i2c@3190000 { @@ -36,7 +607,7 @@ }; hda@3510000 { - nvidia,model = "jetson-xavier-nx-hda"; + nvidia,model = "NVIDIA Jetson Xavier NX HDA"; status = "okay"; }; @@ -265,6 +836,28 @@ regulator-boot-on; }; + sound { + compatible = "nvidia,tegra186-audio-graph-card"; + status = "okay"; + + dais = /* ADMAIF (FE) Ports */ + <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, + <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, + <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, + <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, + /* XBAR Ports */ + <&xbar_i2s3_port>, <&xbar_i2s5_port>, + <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic4_port>, + <&xbar_dspk1_port>, <&xbar_dspk2_port>, + /* BE I/O Ports */ + <&i2s3_port>, <&i2s5_port>, + <&dmic1_port>, <&dmic2_port>, <&dmic4_port>, + <&dspk1_port>, <&dspk2_port>; + + label = "NVIDIA Jetson Xavier NX APE"; + }; + thermal-zones { cpu { polling-delay = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 9449156fae39..076d5efc4c3d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -62,6 +62,7 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_EQOS>; status = "disabled"; snps,write-requests = <1>; @@ -733,6 +734,7 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_SDMMC1>; nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; nvidia,pad-autocal-pull-down-offset-3v3-timeout = @@ -759,6 +761,7 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_SDMMC3>; nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; @@ -790,6 +793,7 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_SDMMC4>; nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; @@ -821,6 +825,7 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_HDA>; status = "disabled"; }; @@ -943,6 +948,10 @@ <&bpmp TEGRA194_CLK_XUSB_SS>, <&bpmp TEGRA194_CLK_XUSB_FS>; clock-names = "dev", "ss", "ss_src", "fs_src"; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_XUSB_DEV>; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; power-domain-names = "dev", "ss"; @@ -972,6 +981,10 @@ "xusb_ss", "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_XUSB_HOST>; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; @@ -1300,6 +1313,84 @@ interrupt-controller; }; + smmu: iommu@12000000 { + compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; + reg = <0x12000000 0x800000>, + <0x11000000 0x800000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + stream-match-mask = <0x7f80>; + #global-interrupts = <2>; + #iommu-cells = <1>; + + nvidia,memory-controller = <&mc>; + status = "okay"; + }; + host1x@13e00000 { compatible = "nvidia,tegra194-host1x"; reg = <0x13e00000 0x10000>, @@ -1319,6 +1410,7 @@ ranges = <0x15000000 0x15000000 0x01000000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; interconnect-names = "dma-mem"; + iommus = <&smmu TEGRA194_SID_HOST1X>; display-hub@15200000 { compatible = "nvidia,tegra194-display"; @@ -1430,6 +1522,7 @@ interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_VIC>; }; dpaux0: dpaux@155c0000 { @@ -2136,6 +2229,7 @@ <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; interconnect-names = "read", "write", "dma-mem", "dma-write"; + iommus = <&smmu TEGRA194_SID_BPMP>; bpmp_i2c: i2c { compatible = "nvidia,tegra186-bpmp-i2c"; @@ -2345,6 +2439,20 @@ }; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 + &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; + }; + psci { compatible = "arm,psci-1.0"; status = "okay"; @@ -2369,6 +2477,11 @@ * for 8x and 11.025x sample rate streams. */ assigned-clock-rates = <258000000>; + + interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_APE>; }; tcu: tcu { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 497635af7fab..7d3e3634743e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -424,6 +424,6 @@ <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>, <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>; - label = "jetson-tx1-ape"; + label = "NVIDIA Jetson TX1 APE"; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index a9caaf7c0d67..d8409c1b4380 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1345,7 +1345,7 @@ }; hda@70030000 { - nvidia,model = "jetson-tx1-hda"; + nvidia,model = "NVIDIA Jetson TX1 HDA"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 14c128a5e248..7dbb13f20de7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -441,7 +441,7 @@ }; hda@70030000 { - nvidia,model = "jetson-nano-hda"; + nvidia,model = "NVIDIA Jetson Nano HDA"; status = "okay"; }; @@ -1043,6 +1043,6 @@ <&i2s3_port>, <&i2s4_port>, <&dmic1_port>, <&dmic2_port>; - label = "jetson-nano-ape"; + label = "NVIDIA Jetson Nano APE"; }; }; diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 456502aeee49..4f0597091976 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -5,8 +5,11 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb @@ -32,11 +35,12 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-dumpling.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb +dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r2-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb @@ -51,6 +55,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb @@ -70,8 +76,13 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-bahamut.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-griffin.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index defcbd15edf9..51e17094d7b1 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -41,14 +41,14 @@ / { aliases { - serial0 = &blsp2_uart1; - serial1 = &blsp2_uart2; - serial2 = &blsp1_uart1; - i2c0 = &blsp1_i2c2; + serial0 = &blsp2_uart2; + serial1 = &blsp2_uart3; + serial2 = &blsp1_uart2; + i2c0 = &blsp1_i2c3; i2c1 = &blsp2_i2c1; - i2c2 = &blsp2_i2c0; - spi0 = &blsp1_spi0; - spi1 = &blsp2_spi5; + i2c2 = &blsp2_i2c1; + spi0 = &blsp1_spi1; + spi1 = &blsp2_spi6; }; chosen { @@ -133,24 +133,24 @@ }; }; -&blsp1_i2c2 { +&blsp1_i2c3 { /* On Low speed expansion */ label = "LS-I2C0"; status = "okay"; }; -&blsp1_spi0 { +&blsp1_spi1 { /* On Low speed expansion */ label = "LS-SPI0"; status = "okay"; }; -&blsp1_uart1 { +&blsp1_uart2 { label = "BT-UART"; status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart1_default>; - pinctrl-1 = <&blsp1_uart1_sleep>; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; bluetooth { compatible = "qcom,qca6174-bt"; @@ -162,7 +162,11 @@ }; }; -&blsp2_i2c0 { +&adsp_pil { + status = "okay"; +}; + +&blsp2_i2c1 { /* On High speed expansion */ label = "HS-I2C2"; status = "okay"; @@ -174,32 +178,36 @@ status = "okay"; }; -&blsp2_spi5 { +&blsp2_spi6 { /* On High speed expansion */ label = "HS-SPI1"; status = "okay"; }; -&blsp2_uart1 { +&blsp2_uart2 { label = "LS-UART1"; status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart1_2pins_default>; - pinctrl-1 = <&blsp2_uart1_2pins_sleep>; + pinctrl-0 = <&blsp2_uart2_2pins_default>; + pinctrl-1 = <&blsp2_uart2_2pins_sleep>; }; -&blsp2_uart2 { +&blsp2_uart3 { label = "LS-UART0"; status = "disabled"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart2_4pins_default>; - pinctrl-1 = <&blsp2_uart2_4pins_sleep>; + pinctrl-0 = <&blsp2_uart3_4pins_default>; + pinctrl-1 = <&blsp2_uart3_4pins_sleep>; }; &camss { vdda-supply = <&vreg_l2a_1p25>; }; +&gpu { + status = "okay"; +}; + &hdmi { status = "okay"; @@ -245,7 +253,12 @@ vdd-gfx-supply = <&vdd_gfx>; }; -&msmgpio { +&pm8994_resin { + status = "okay"; + linux,code = <KEY_VOLUMEDOWN>; +}; + +&tlmm { gpio-line-names = "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */ "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */ @@ -424,7 +437,7 @@ }; }; - blsp1_uart1_default: blsp1_uart1_default { + blsp1_uart2_default: blsp1_uart2_default { mux { pins = "gpio41", "gpio42", "gpio43", "gpio44"; function = "blsp_uart2"; @@ -437,7 +450,7 @@ }; }; - blsp1_uart1_sleep: blsp1_uart1_sleep { + blsp1_uart2_sleep: blsp1_uart2_sleep { mux { pins = "gpio41", "gpio42", "gpio43", "gpio44"; function = "gpio"; @@ -505,20 +518,20 @@ &pcie0 { status = "okay"; - perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>; + perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&vreg_l28a_0p925>; }; &pcie1 { status = "okay"; - perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>; + perst-gpio = <&tlmm 130 GPIO_ACTIVE_LOW>; vdda-supply = <&vreg_l28a_0p925>; }; &pcie2 { status = "okay"; - perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>; + perst-gpio = <&tlmm 114 GPIO_ACTIVE_LOW>; vdda-supply = <&vreg_l28a_0p925>; }; @@ -929,9 +942,9 @@ &sdhc2 { /* External SD card */ pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - cd-gpios = <&msmgpio 38 0x1>; + pinctrl-0 = <&sdc2_state_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_state_off &sdc2_cd_off>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; vmmc-supply = <&vreg_l21a_2p95>; vqmmc-supply = <&vreg_l13a_2p95>; status = "okay"; @@ -1026,20 +1039,6 @@ }; }; -&spmi_bus { - pmic@0 { - pon@800 { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEDOWN>; - }; - }; - }; -}; - &ufsphy { status = "okay"; @@ -1089,6 +1088,10 @@ }; +&venus { + status = "okay"; +}; + &wcd9335 { clock-names = "mclk", "slimbus"; clocks = <&div1_mclk>, diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts index f6ddf17ada81..8c7a27e972b7 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts @@ -17,7 +17,7 @@ qcom,board-id = <0x00010018 0>; aliases { - serial0 = &blsp2_uart1; + serial0 = &blsp2_uart2; }; chosen { @@ -81,14 +81,22 @@ }; }; -&blsp2_uart1 { +&blsp2_uart2 { status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart1_2pins_default>; - pinctrl-1 = <&blsp2_uart1_2pins_sleep>; + pinctrl-0 = <&blsp2_uart2_2pins_default>; + pinctrl-1 = <&blsp2_uart2_2pins_sleep>; }; -&msmgpio { +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&tlmm { sdc2_pins_default: sdc2-pins-default { clk { pins = "sdc2_clk"; @@ -352,7 +360,7 @@ bus-width = <4>; - cd-gpios = <&msmgpio 38 0x1>; + cd-gpios = <&tlmm 38 0x1>; vmmc-supply = <&vreg_l21a_2p95>; vqmmc-supply = <&vreg_l13a_2p95>; @@ -383,3 +391,7 @@ vdda-phy-max-microamp = <18380>; vdda-pll-max-microamp = <9440>; }; + +&venus { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts new file mode 100644 index 000000000000..2bfcf42aeabc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2020 The Linux Foundation. All rights reserved. + */ +/dts-v1/; + +#include "ipq8074-hk10.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C1"; + compatible = "qcom,ipq8074-hk10-c1", "qcom,ipq8074"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts new file mode 100644 index 000000000000..7da39f1d979b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; +/* Copyright (c) 2020 The Linux Foundation. All rights reserved. + */ +#include "ipq8074-hk10.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C2"; + compatible = "qcom,ipq8074-hk10-c2", "qcom,ipq8074"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi new file mode 100644 index 000000000000..07e670829676 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ +/dts-v1/; + +#include "ipq8074.dtsi" + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + + interrupt-parent = <&intc>; + + aliases { + serial0 = &blsp1_uart5; + }; + + chosen { + stdout-path = "serial0"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x20000000>; + }; +}; + +&blsp1_spi1 { + status = "ok"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&blsp1_uart5 { + status = "ok"; +}; + +&pcie0 { + status = "ok"; + perst-gpio = <&tlmm 58 0x1>; +}; + +&pcie1 { + status = "ok"; + perst-gpio = <&tlmm 61 0x1>; +}; + +&pcie_phy0 { + status = "ok"; +}; + +&pcie_phy1 { + status = "ok"; +}; + +&qpic_bam { + status = "ok"; +}; + +&qpic_nand { + status = "ok"; + + nand@0 { + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index a32e5e79ab0b..f39bc10cc5bd 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -165,6 +165,7 @@ clock-names = "cfg_ahb", "ref"; resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + status = "disabled"; }; pcie_phy0: phy@86000 { @@ -372,6 +373,21 @@ status = "disabled"; }; + blsp1_i2c6: i2c@78ba000 { + compatible = "qcom,i2c-qup-v2.2.1"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x078ba000 0x600>; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <100000>; + dmas = <&blsp_dma 23>, <&blsp_dma 22>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + qpic_bam: dma-controller@7984000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07984000 0x1a000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index 540b1fa4b260..670bd1bebd73 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -45,6 +45,24 @@ status = "okay"; }; +&blsp_i2c4 { + status = "okay"; + + touchscreen@26 { + compatible = "mstar,msg2638"; + reg = <0x26>; + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&msmgpio 100 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_reset_default>; + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l5>; + touchscreen-size-x = <2048>; + touchscreen-size-y = <2048>; + }; +}; + &blsp_i2c5 { status = "okay"; @@ -281,6 +299,14 @@ bias-pull-up; }; + ts_int_reset_default: ts-int-reset-default { + pins = "gpio13", "gpio100"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + usb_id_default: usb-id-default { pins = "gpio69"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts new file mode 100644 index 000000000000..e0075b574190 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -0,0 +1,454 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2021 Stephan Gerhold + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> + +/* + * Note: The original firmware from Huawei can only boot 32-bit kernels. + * To boot arm64 kernels it is necessary to flash 64-bit TZ/HYP firmware + * with EDL, e.g. taken from the DragonBoard 410c. This works because Huawei + * forgot to set up (firmware) secure boot for some reason. + * + * Also note that Huawei no longer provides bootloader unlock codes. + * This can be bypassed by patching the bootloader from a custom HYP firmware, + * making it think the bootloader is unlocked. + * + * See: https://wiki.postmarketos.org/wiki/Huawei_Ascend_G7_(huawei-g7) + */ + +/ { + model = "Huawei Ascend G7"; + compatible = "huawei,g7", "qcom,msm8916"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + label = "GPIO Buttons"; + + volume-up { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_leds_default>; + + led-0 { + gpios = <&msmgpio 8 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + }; + + led-1 { + gpios = <&msmgpio 9 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + }; + + led-2 { + gpios = <&msmgpio 10 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_BLUE>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + }; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&msmgpio 117 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_default>; + }; +}; + +&blsp_i2c2 { + status = "okay"; + + magnetometer@c { + compatible = "asahi-kasei,ak09911"; + reg = <0x0c>; + + vdd-supply = <&pm8916_l17>; + vid-supply = <&pm8916_l6>; + + reset-gpios = <&msmgpio 36 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&mag_reset_default>; + }; + + accelerometer@1e { + compatible = "kionix,kx023-1025"; + reg = <0x1e>; + + interrupt-parent = <&msmgpio>; + interrupts = <115 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + + pinctrl-names = "default"; + pinctrl-0 = <&accel_irq_default>; + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "1"; + }; + + proximity@39 { + compatible = "avago,apds9930"; + reg = <0x39>; + + interrupt-parent = <&msmgpio>; + interrupts = <113 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + + led-max-microamp = <100000>; + amstaos,proximity-diodes = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&prox_irq_default>; + }; + + regulator@3e { + compatible = "ti,tps65132"; + reg = <0x3e>; + + pinctrl-names = "default"; + pinctrl-0 = <®_lcd_en_default>; + + reg_lcd_pos: outp { + regulator-name = "outp"; + regulator-min-microvolt = <5400000>; + regulator-max-microvolt = <5400000>; + enable-gpios = <&msmgpio 97 GPIO_ACTIVE_HIGH>; + regulator-active-discharge = <1>; + }; + + reg_lcd_neg: outn { + regulator-name = "outn"; + regulator-min-microvolt = <5400000>; + regulator-max-microvolt = <5400000>; + enable-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + regulator-active-discharge = <1>; + }; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + rmi4@70 { + compatible = "syna,rmi4-i2c"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&pm8916_l17>; + vio-supply = <&pm8916_l16>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_irq_default>; + + syna,startup-delay-ms = <100>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; /* Allow sleeping */ + }; + + rmi4-f11@11 { + reg = <0x11>; + syna,sensor-type = <1>; /* Touchscreen */ + }; + }; +}; + +&blsp_i2c6 { + status = "okay"; + + nfc@28 { + compatible = "nxp,pn547", "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupt-parent = <&msmgpio>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&msmgpio 2 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&nfc_default>; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8916_resin { + status = "okay"; + linux,code = <KEY_VOLUMEDOWN>; +}; + +&pm8916_vib { + status = "okay"; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdhc2_cd_default>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdhc2_cd_default>; + + /* + * The Huawei device tree sets cd-gpios = <&msmgpio 38 GPIO_ACTIVE_HIGH>. + * However, gpio38 does not change its state when inserting/removing the + * SD card, it's just low all the time. The Huawei kernel seems to use + * polling for SD card detection instead. + * + * However, looking closer at the GPIO debug output it turns out that + * gpio56 switches its state when inserting/removing the SD card. + * It behaves just like gpio38 normally does. Usually GPIO56 is used as + * "UIM2_PRESENT", i.e. to check if a second SIM card is inserted. + * Maybe Huawei decided to replace the second SIM card slot with the + * SD card slot and forgot to re-route to gpio38. + */ + cd-gpios = <&msmgpio 56 GPIO_ACTIVE_LOW>; +}; + +&usb { + status = "okay"; + extcon = <&usb_id>, <&usb_id>; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + accel_irq_default: accel-irq-default { + pins = "gpio115"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default { + pins = "gpio107"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + + gpio_leds_default: gpio-leds-default { + pins = "gpio8", "gpio9", "gpio10"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + nfc_default: nfc-default { + pins = "gpio2", "gpio20", "gpio21"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + mag_reset_default: mag-reset-default { + pins = "gpio36"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + prox_irq_default: prox-irq-default { + pins = "gpio113"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + reg_lcd_en_default: reg-lcd-en-default { + pins = "gpio32", "gpio97"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + sdhc2_cd_default: sdhc2-cd-default { + pins = "gpio56"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + ts_irq_default: ts-irq-default { + pins = "gpio13"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + usb_id_default: usb-id-default { + pins = "gpio117"; + function = "gpio"; + + drive-strength = <8>; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 230ba3ce3277..9b4b7de7cec2 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -4,6 +4,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> / { aliases { @@ -95,6 +96,63 @@ pinctrl-0 = <&muic_int_default>; }; }; + + i2c-tkey { + compatible = "i2c-gpio"; + sda-gpios = <&msmgpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&msmgpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_i2c_default>; + + #address-cells = <1>; + #size-cells = <0>; + + touchkey: touchkey@20 { + /* Note: Actually an ABOV MCU that implements same interface */ + compatible = "coreriver,tc360-touchkey"; + reg = <0x20>; + + interrupt-parent = <&msmgpio>; + interrupts = <98 IRQ_TYPE_EDGE_FALLING>; + + /* vcc/vdd-supply are board-specific */ + vddio-supply = <&pm8916_l6>; + + linux,keycodes = <KEY_APPSELECT KEY_BACK>; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_default>; + }; + }; + + i2c-nfc { + compatible = "i2c-gpio"; + sda-gpios = <&msmgpio 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&msmgpio 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&nfc_i2c_default>; + + #address-cells = <1>; + #size-cells = <0>; + + nfc@27 { + compatible = "samsung,s3fwrn5-i2c"; + reg = <0x27>; + + interrupt-parent = <&msmgpio>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + + en-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; + wake-gpios = <&msmgpio 49 GPIO_ACTIVE_HIGH>; + + clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>; + + pinctrl-names = "default"; + pinctrl-0 = <&nfc_default &nfc_clk_req>; + }; + }; }; &blsp_i2c2 { @@ -122,6 +180,20 @@ }; }; +&blsp_i2c4 { + status = "okay"; + + battery@35 { + compatible = "richtek,rt5033-battery"; + reg = <0x35>; + interrupt-parent = <&msmgpio>; + interrupts = <121 IRQ_TYPE_EDGE_BOTH>; + + pinctrl-names = "default"; + pinctrl-0 = <&fg_alert_default>; + }; +}; + &blsp1_uart2 { status = "okay"; }; @@ -284,6 +356,14 @@ bias-disable; }; + fg_alert_default: fg-alert-default { + pins = "gpio121"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + gpio_keys_default: gpio-keys-default { pins = "gpio107", "gpio109"; function = "gpio"; @@ -333,6 +413,46 @@ bias-disable; }; + nfc_default: nfc-default { + pins = "gpio20", "gpio49"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + + irq { + pins = "gpio21"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-down; + }; + }; + + nfc_i2c_default: nfc-i2c-default { + pins = "gpio0", "gpio1"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + tkey_default: tkey-default { + pins = "gpio98"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + tkey_i2c_default: tkey-i2c-default { + pins = "gpio16", "gpio17"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + tsp_en_default: tsp-en-default { pins = "gpio73"; function = "gpio"; @@ -341,3 +461,14 @@ bias-disable; }; }; + +&pm8916_gpios { + nfc_clk_req: nfc-clk-req { + pins = "gpio2"; + function = "func1"; + + input-enable; + bias-disable; + power-source = <PM8916_GPIO_L2>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts index 661f41ad978b..6cc2eaeb1d33 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts @@ -20,6 +20,37 @@ pinctrl-names = "default"; pinctrl-0 = <&panel_vdd3_default>; }; + + reg_touch_key: regulator-touch-key { + compatible = "regulator-fixed"; + regulator-name = "touch_key"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + gpio = <&msmgpio 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_en_default>; + }; + + reg_key_led: regulator-key-led { + compatible = "regulator-fixed"; + regulator-name = "key_led"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 60 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_led_en_default>; + }; +}; + +&touchkey { + vcc-supply = <®_touch_key>; + vdd-supply = <®_key_led>; }; &accelerometer { @@ -81,6 +112,22 @@ bias-disable; }; + tkey_en_default: tkey-en-default { + pins = "gpio86"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + tkey_led_en_default: tkey-led-en-default { + pins = "gpio60"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + ts_int_default: ts-int-default { pins = "gpio13"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts index dd35c3344358..c2eff5aebf85 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts @@ -7,6 +7,19 @@ / { model = "Samsung Galaxy A5U (EUR)"; compatible = "samsung,a5u-eur", "qcom,msm8916"; + + reg_touch_key: regulator-touch-key { + compatible = "regulator-fixed"; + regulator-name = "touch_key"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 97 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tkey_en_default>; + }; }; &accelerometer { @@ -42,7 +55,20 @@ }; }; +&touchkey { + vcc-supply = <®_touch_key>; + vdd-supply = <®_touch_key>; +}; + &msmgpio { + tkey_en_default: tkey-en-default { + pins = "gpio97"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + ts_int_default: ts-int-default { pins = "gpio13"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts index baa55643b40f..ffe1a9bd8f70 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts @@ -32,3 +32,7 @@ }; }; }; + +&tlmm { + gpio-reserved-ranges = <85 4>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi index 5f46a1427f1f..1e1514e9158c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi @@ -7,7 +7,7 @@ / { aliases { - serial0 = &blsp2_uart1; + serial0 = &blsp2_uart2; }; chosen { diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi deleted file mode 100644 index ac1ede579361..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ /dev/null @@ -1,653 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. - */ - -&msmgpio { - - wcd9xxx_intr { - wcd_intr_default: wcd_intr_default{ - mux { - pins = "gpio54"; - function = "gpio"; - }; - - config { - pins = "gpio54"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* pull down */ - input-enable; - }; - }; - }; - - cdc_reset_ctrl { - cdc_reset_sleep: cdc_reset_sleep { - mux { - pins = "gpio64"; - function = "gpio"; - }; - config { - pins = "gpio64"; - drive-strength = <16>; - bias-disable; - output-low; - }; - }; - cdc_reset_active:cdc_reset_active { - mux { - pins = "gpio64"; - function = "gpio"; - }; - config { - pins = "gpio64"; - drive-strength = <16>; - bias-pull-down; - output-high; - }; - }; - }; - - blsp1_spi0_default: blsp1_spi0_default { - pinmux { - function = "blsp_spi1"; - pins = "gpio0", "gpio1", "gpio3"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio2"; - }; - pinconf { - pins = "gpio0", "gpio1", "gpio3"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio2"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp1_spi0_sleep: blsp1_spi0_sleep { - pinmux { - function = "gpio"; - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - }; - pinconf { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - blsp1_i2c2_default: blsp1_i2c2_default { - pinmux { - function = "blsp_i2c3"; - pins = "gpio47", "gpio48"; - }; - pinconf { - pins = "gpio47", "gpio48"; - drive-strength = <16>; - bias-disable = <0>; - }; - }; - - blsp1_i2c2_sleep: blsp1_i2c2_sleep { - pinmux { - function = "gpio"; - pins = "gpio47", "gpio48"; - }; - pinconf { - pins = "gpio47", "gpio48"; - drive-strength = <2>; - bias-disable = <0>; - }; - }; - - blsp2_i2c0_default: blsp2_i2c0 { - pinmux { - function = "blsp_i2c7"; - pins = "gpio55", "gpio56"; - }; - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_i2c0_sleep: blsp2_i2c0_sleep { - pinmux { - function = "gpio"; - pins = "gpio55", "gpio56"; - }; - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart1_2pins_default: blsp2_uart1_2pins { - pinmux { - function = "blsp_uart8"; - pins = "gpio4", "gpio5"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_uart1_2pins_sleep: blsp2_uart1_2pins_sleep { - pinmux { - function = "gpio"; - pins = "gpio4", "gpio5"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart1_4pins_default: blsp2_uart1_4pins { - pinmux { - function = "blsp_uart8"; - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - }; - - pinconf { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_uart1_4pins_sleep: blsp2_uart1_4pins_sleep { - pinmux { - function = "gpio"; - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - }; - - pinconf { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_i2c1_default: blsp2_i2c1 { - pinmux { - function = "blsp_i2c8"; - pins = "gpio6", "gpio7"; - }; - pinconf { - pins = "gpio6", "gpio7"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_i2c1_sleep: blsp2_i2c1_sleep { - pinmux { - function = "gpio"; - pins = "gpio6", "gpio7"; - }; - pinconf { - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart2_2pins_default: blsp2_uart2_2pins { - pinmux { - function = "blsp_uart9"; - pins = "gpio49", "gpio50"; - }; - pinconf { - pins = "gpio49", "gpio50"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_uart2_2pins_sleep: blsp2_uart2_2pins_sleep { - pinmux { - function = "gpio"; - pins = "gpio49", "gpio50"; - }; - pinconf { - pins = "gpio49", "gpio50"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart2_4pins_default: blsp2_uart2_4pins { - pinmux { - function = "blsp_uart9"; - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - }; - - pinconf { - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_uart2_4pins_sleep: blsp2_uart2_4pins_sleep { - pinmux { - function = "gpio"; - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - }; - - pinconf { - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_spi5_default: blsp2_spi5_default { - pinmux { - function = "blsp_spi12"; - pins = "gpio85", "gpio86", "gpio88"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio87"; - }; - pinconf { - pins = "gpio85", "gpio86", "gpio88"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio87"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp2_spi5_sleep: blsp2_spi5_sleep { - pinmux { - function = "gpio"; - pins = "gpio85", "gpio86", "gpio87", "gpio88"; - }; - pinconf { - pins = "gpio85", "gpio86", "gpio87", "gpio88"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - sdc2_clk_on: sdc2_clk_on { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_clk_off: sdc2_clk_off { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_cmd_on: sdc2_cmd_on { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 MA */ - }; - }; - - sdc2_cmd_off: sdc2_cmd_off { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_data_on: sdc2_data_on { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 MA */ - }; - }; - - sdc2_data_off: sdc2_data_off { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - pcie0_clkreq_default: pcie0_clkreq_default { - mux { - pins = "gpio36"; - function = "pci_e0"; - }; - - config { - pins = "gpio36"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie0_perst_default: pcie0_perst_default { - mux { - pins = "gpio35"; - function = "gpio"; - }; - - config { - pins = "gpio35"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie0_wake_default: pcie0_wake_default { - mux { - pins = "gpio37"; - function = "gpio"; - }; - - config { - pins = "gpio37"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie0_clkreq_sleep: pcie0_clkreq_sleep { - mux { - pins = "gpio36"; - function = "gpio"; - }; - - config { - pins = "gpio36"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie0_wake_sleep: pcie0_wake_sleep { - mux { - pins = "gpio37"; - function = "gpio"; - }; - - config { - pins = "gpio37"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie1_clkreq_default: pcie1_clkreq_default { - mux { - pins = "gpio131"; - function = "pci_e1"; - }; - - config { - pins = "gpio131"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie1_perst_default: pcie1_perst_default { - mux { - pins = "gpio130"; - function = "gpio"; - }; - - config { - pins = "gpio130"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie1_wake_default: pcie1_wake_default { - mux { - pins = "gpio132"; - function = "gpio"; - }; - - config { - pins = "gpio132"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie1_clkreq_sleep: pcie1_clkreq_sleep { - mux { - pins = "gpio131"; - function = "gpio"; - }; - - config { - pins = "gpio131"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie1_wake_sleep: pcie1_wake_sleep { - mux { - pins = "gpio132"; - function = "gpio"; - }; - - config { - pins = "gpio132"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie2_clkreq_default: pcie2_clkreq_default { - mux { - pins = "gpio115"; - function = "pci_e2"; - }; - - config { - pins = "gpio115"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie2_perst_default: pcie2_perst_default { - mux { - pins = "gpio114"; - function = "gpio"; - }; - - config { - pins = "gpio114"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie2_wake_default: pcie2_wake_default { - mux { - pins = "gpio116"; - function = "gpio"; - }; - - config { - pins = "gpio116"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie2_clkreq_sleep: pcie2_clkreq_sleep { - mux { - pins = "gpio115"; - function = "gpio"; - }; - - config { - pins = "gpio115"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie2_wake_sleep: pcie2_wake_sleep { - mux { - pins = "gpio116"; - function = "gpio"; - }; - - config { - pins = "gpio116"; - drive-strength = <2>; - bias-disable; - }; - }; - - cci0_default: cci0_default { - pinmux { - function = "cci_i2c"; - pins = "gpio17", "gpio18"; - }; - pinconf { - pins = "gpio17", "gpio18"; - drive-strength = <16>; - bias-disable; - }; - }; - - cci1_default: cci1_default { - pinmux { - function = "cci_i2c"; - pins = "gpio19", "gpio20"; - }; - pinconf { - pins = "gpio19", "gpio20"; - drive-strength = <16>; - bias-disable; - }; - }; - - camera_board_default: camera_board_default { - mux_pwdn { - function = "gpio"; - pins = "gpio98"; - }; - config_pwdn { - pins = "gpio98"; - drive-strength = <16>; - bias-disable; - }; - - mux_rst { - function = "gpio"; - pins = "gpio104"; - }; - config_rst { - pins = "gpio104"; - drive-strength = <16>; - bias-disable; - }; - - mux_mclk1 { - function = "cam_mclk"; - pins = "gpio14"; - }; - config_mclk1 { - pins = "gpio14"; - drive-strength = <16>; - bias-disable; - }; - }; - - camera_front_default: camera_front_default { - mux_pwdn { - function = "gpio"; - pins = "gpio133"; - }; - config_pwdn { - pins = "gpio133"; - drive-strength = <16>; - bias-disable; - }; - - mux_rst { - function = "gpio"; - pins = "gpio23"; - }; - config_rst { - pins = "gpio23"; - drive-strength = <16>; - bias-disable; - }; - - mux_mclk2 { - function = "cam_mclk"; - pins = "gpio15"; - }; - config_mclk2 { - pins = "gpio15"; - drive-strength = <16>; - bias-disable; - }; - }; - - camera_rear_default: camera_rear_default { - mux_pwdn { - function = "gpio"; - pins = "gpio26"; - }; - config_pwdn { - pins = "gpio26"; - drive-strength = <16>; - bias-disable; - }; - - mux_rst { - function = "gpio"; - pins = "gpio25"; - }; - config_rst { - pins = "gpio25"; - drive-strength = <16>; - bias-disable; - }; - - mux_mclk0 { - function = "cam_mclk"; - pins = "gpio13"; - }; - config_mclk0 { - pins = "gpio13"; - drive-strength = <16>; - bias-disable; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 5d06216c5c1c..78c55ca10ba9 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -6,7 +6,9 @@ #include <dt-bindings/clock/qcom,gcc-msm8996.h> #include <dt-bindings/clock/qcom,mmcc-msm8996.h> #include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,apr.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&intc>; @@ -43,6 +45,9 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; + clocks = <&kryocc 0>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; @@ -57,6 +62,9 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; + clocks = <&kryocc 0>; + operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; next-level-cache = <&L2_0>; }; @@ -67,6 +75,9 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; + clocks = <&kryocc 1>; + operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "cache"; @@ -81,6 +92,9 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; + clocks = <&kryocc 1>; + operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; next-level-cache = <&L2_1>; }; @@ -120,6 +134,227 @@ }; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + /* Nominal fmax for now */ + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-422400000 { + opp-hz = /bits/ 64 <422400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-556800000 { + opp-hz = /bits/ 64 <556800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + /* Nominal fmax for now */ + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-556800000 { + opp-hz = /bits/ 64 <556800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + opp-2150400000 { + opp-hz = /bits/ 64 <2150400000>; + opp-supported-hw = <0x77>; + clock-latency-ns = <200000>; + }; + }; + firmware { scm { compatible = "qcom,scm-msm8996"; @@ -424,7 +659,7 @@ bits = <1 4>; }; - gpu_speed_bin: gpu_speed_bin@133 { + speedbin_efuse: speedbin@133 { reg = <0x133 0x1>; bits = <5 3>; }; @@ -472,7 +707,7 @@ tcsr_mutex_regs: syscon@740000 { compatible = "syscon"; - reg = <0x00740000 0x20000>; + reg = <0x00740000 0x40000>; }; tcsr: syscon@7a0000 { @@ -521,6 +756,8 @@ #size-cells = <1>; ranges; + status = "disabled"; + mdp: mdp@901000 { compatible = "qcom,mdp5"; reg = <0x00901000 0x90000>; @@ -542,6 +779,11 @@ iommus = <&mdp_smmu 0>; + assigned-clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + assigned-clock-rates = <300000000>, + <19200000>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -552,9 +794,82 @@ remote-endpoint = <&hdmi_in>; }; }; + + port@1 { + reg = <1>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; }; }; + dsi0: dsi@994000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x00994000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "byte", + "iface", + "bus", + "core_mmss", + "pixel", + "core"; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@994400 { + compatible = "qcom,dsi-phy-14nm"; + reg = <0x00994400 0x100>, + <0x00994500 0x300>, + <0x00994800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; + clock-names = "iface", "ref"; + status = "disabled"; + }; + hdmi: hdmi-tx@9a0000 { compatible = "qcom,hdmi-tx-8996"; reg = <0x009a0000 0x50c>, @@ -618,7 +933,8 @@ "ref"; }; }; - gpu@b00000 { + + gpu: gpu@b00000 { compatible = "qcom,adreno-530.2", "qcom,adreno"; #stream-id-cells = <16>; @@ -642,7 +958,7 @@ power-domains = <&mmcc GPU_GX_GDSC>; iommus = <&adreno_smmu 0>; - nvmem-cells = <&gpu_speed_bin>; + nvmem-cells = <&speedbin_efuse>; nvmem-cell-names = "speed_bin"; qcom,gpu-quirk-two-pass-use-wfi; @@ -650,6 +966,8 @@ operating-points-v2 = <&gpu_opp_table>; + status = "disabled"; + gpu_opp_table: opp-table { compatible ="operating-points-v2"; @@ -693,15 +1011,482 @@ }; }; - msmgpio: pinctrl@1010000 { + tlmm: pinctrl@1010000 { compatible = "qcom,msm8996-pinctrl"; reg = <0x01010000 0x300000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; - gpio-ranges = <&msmgpio 0 0 150>; + gpio-ranges = <&tlmm 0 0 150>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + + blsp1_spi1_default: blsp1-spi1-default { + spi { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + drive-strength = <12>; + bias-disable; + }; + + cs { + pins = "gpio2"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp1_spi1_sleep: blsp1-spi1-sleep { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp2_uart2_2pins_default: blsp2-uart1-2pins { + pins = "gpio4", "gpio5"; + function = "blsp_uart8"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep { + pins = "gpio4", "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c2_default: blsp2-i2c2 { + pins = "gpio6", "gpio7"; + function = "blsp_i2c8"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_i2c2_sleep: blsp2-i2c2-sleep { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cci0_default: cci0-default { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + drive-strength = <16>; + bias-disable; + }; + + camera0_state_on: + camera_rear_default: camera-rear-default { + mclk0 { + pins = "gpio13"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + + rst { + pins = "gpio25"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + pwdn { + pins = "gpio26"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + }; + + cci1_default: cci1-default { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + drive-strength = <16>; + bias-disable; + }; + + camera1_state_on: + camera_board_default: camera-board-default { + mclk1 { + pins = "gpio14"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + + pwdn { + pins = "gpio98"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + rst { + pins = "gpio104"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + }; + + camera2_state_on: + camera_front_default: camera-front-default { + mclk2 { + pins = "gpio15"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + + rst { + pins = "gpio23"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + pwdn { + pins = "gpio133"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + }; + + pcie0_state_on: pcie0-state-on { + perst { + pins = "gpio35"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio36"; + function = "pci_e0"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio37"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_state_off: pcie0-state-off { + perst { + pins = "gpio35"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio36"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake { + pins = "gpio37"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_i2c3_default: blsp1-i2c2-default { + pins = "gpio47", "gpio48"; + function = "blsp_i2c3"; + drive-strength = <16>; + bias-disable = <0>; + }; + + blsp1_i2c3_sleep: blsp1-i2c2-sleep { + pins = "gpio47", "gpio48"; + function = "gpio"; + drive-strength = <2>; + bias-disable = <0>; + }; + + blsp2_uart3_4pins_default: blsp2-uart2-4pins { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "blsp_uart9"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "blsp_uart9"; + drive-strength = <2>; + bias-disable; + }; + + wcd_intr_default: wcd-intr-default{ + pins = "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + blsp2_i2c1_default: blsp2-i2c1 { + pins = "gpio55", "gpio56"; + function = "blsp_i2c7"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_i2c1_sleep: blsp2-i2c0-sleep { + pins = "gpio55", "gpio56"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c5_default: blsp2-i2c5 { + pins = "gpio60", "gpio61"; + function = "blsp_i2c11"; + drive-strength = <2>; + bias-disable; + }; + + /* Sleep state for BLSP2_I2C5 is missing.. */ + + cdc_reset_active: cdc-reset-active { + pins = "gpio64"; + function = "gpio"; + drive-strength = <16>; + bias-pull-down; + output-high; + }; + + cdc_reset_sleep: cdc-reset-sleep { + pins = "gpio64"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + blsp2_spi6_default: blsp2-spi5-default { + spi { + pins = "gpio85", "gpio86", "gpio88"; + function = "blsp_spi12"; + drive-strength = <12>; + bias-disable; + }; + + cs { + pins = "gpio87"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp2_spi6_sleep: blsp2-spi5-sleep { + pins = "gpio85", "gpio86", "gpio87", "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp2_i2c6_default: blsp2-i2c6 { + pins = "gpio87", "gpio88"; + function = "blsp_i2c12"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_i2c6_sleep: blsp2-i2c6-sleep { + pins = "gpio87", "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie1_state_on: pcie1-state-on { + perst { + pins = "gpio130"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio131"; + function = "pci_e1"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio132"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie1_state_off: pcie1-state-off { + /* Perst is missing? */ + clkreq { + pins = "gpio131"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake { + pins = "gpio132"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie2_state_on: pcie2-state-on { + perst { + pins = "gpio114"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio115"; + function = "pci_e2"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio116"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie2_state_off: pcie2-state-off { + /* Perst is missing? */ + clkreq { + pins = "gpio115"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake { + pins = "gpio116"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + sdc1_state_on: sdc1-state-on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-state-off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_state_on: sdc2-clk-on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc2_state_off: sdc2-clk-off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; }; spmi_bus: qcom,spmi@400f000 { @@ -762,8 +1547,8 @@ <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; - pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>; + pinctrl-0 = <&pcie0_state_on>; + pinctrl-1 = <&pcie0_state_off>; linux,pci-domain = <0>; @@ -816,8 +1601,8 @@ <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>; - pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>; + pinctrl-0 = <&pcie1_state_on>; + pinctrl-1 = <&pcie1_state_off>; linux,pci-domain = <1>; @@ -867,8 +1652,8 @@ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>; - pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >; + pinctrl-0 = <&pcie2_state_on>; + pinctrl-1 = <&pcie2_state_off>; linux,pci-domain = <2>; clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, @@ -1152,7 +1937,7 @@ power-domains = <&mmcc GPU_GDSC>; }; - video-codec@c00000 { + venus: video-codec@c00000 { compatible = "qcom,msm8996-venus"; reg = <0x00c00000 0xff000>; interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; @@ -1183,7 +1968,7 @@ <&venus_smmu 0x2d>, <&venus_smmu 0x31>; memory-region = <&venus_region>; - status = "okay"; + status = "disabled"; video-decoder { compatible = "venus-decoder"; @@ -1745,9 +2530,14 @@ }; }; }; + kryocc: clock-controller@6400000 { - compatible = "qcom,apcc-msm8996"; + compatible = "qcom,msm8996-apcc"; reg = <0x06400000 0x90000>; + + clock-names = "xo"; + clocks = <&xo_board>; + #clock-cells = <1>; }; @@ -1758,6 +2548,10 @@ #size-cells = <1>; ranges; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "ss_phy_irq"; + clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, <&gcc GCC_USB30_MASTER_CLK>, <&gcc GCC_AGGRE2_USB3_AXI_CLK>, @@ -1841,34 +2635,75 @@ status = "disabled"; }; + sdhc1: sdhci@7464900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x07464900 0x11c>, <0x07464000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clock-names = "iface", "core", "xo"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + + bus-width = <8>; + non-removable; + status = "disabled"; + }; + sdhc2: sdhci@74a4900 { - status = "disabled"; - compatible = "qcom,sdhci-msm-v4"; - reg = <0x074a4900 0x314>, <0x074a4000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, - <0 221 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - - clock-names = "iface", "core", "xo"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; - bus-width = <4>; + compatible = "qcom,sdhci-msm-v4"; + reg = <0x074a4900 0x314>, <0x074a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clock-names = "iface", "core", "xo"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_state_on>; + pinctrl-1 = <&sdc2_state_off>; + + bus-width = <4>; + status = "disabled"; }; - blsp1_uart1: serial@7570000 { + blsp1_dma: dma@7544000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07544000 0x2b000>; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + qcom,controlled-remotely; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp1_uart2: serial@7570000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x07570000 0x1000>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; - blsp1_spi0: spi@7575000 { + blsp1_spi1: spi@7575000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x07575000 0x600>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; @@ -1876,14 +2711,16 @@ <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_spi0_default>; - pinctrl-1 = <&blsp1_spi0_sleep>; + pinctrl-0 = <&blsp1_spi1_default>; + pinctrl-1 = <&blsp1_spi1_sleep>; + dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; - blsp1_i2c2: i2c@7577000 { + blsp1_i2c3: i2c@7577000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x07577000 0x1000>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; @@ -1891,14 +2728,27 @@ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_i2c2_default>; - pinctrl-1 = <&blsp1_i2c2_sleep>; + pinctrl-0 = <&blsp1_i2c3_default>; + pinctrl-1 = <&blsp1_i2c3_sleep>; + dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; - blsp2_uart1: serial@75b0000 { + blsp2_dma: dma@7584000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07584000 0x2b000>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + qcom,controlled-remotely; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + blsp2_uart2: serial@75b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x075b0000 0x1000>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; @@ -1908,7 +2758,7 @@ status = "disabled"; }; - blsp2_uart2: serial@75b1000 { + blsp2_uart3: serial@75b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x075b1000 0x1000>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; @@ -1918,7 +2768,7 @@ status = "disabled"; }; - blsp2_i2c0: i2c@75b5000 { + blsp2_i2c1: i2c@75b5000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x075b5000 0x1000>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; @@ -1926,14 +2776,16 @@ <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_i2c0_default>; - pinctrl-1 = <&blsp2_i2c0_sleep>; + pinctrl-0 = <&blsp2_i2c1_default>; + pinctrl-1 = <&blsp2_i2c1_sleep>; + dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; - blsp2_i2c1: i2c@75b6000 { + blsp2_i2c2: i2c@75b6000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x075b6000 0x1000>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; @@ -1941,14 +2793,49 @@ <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_i2c1_default>; - pinctrl-1 = <&blsp2_i2c1_sleep>; + pinctrl-0 = <&blsp2_i2c2_default>; + pinctrl-1 = <&blsp2_i2c2_sleep>; + dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; - blsp2_spi5: spi@75ba000{ + blsp2_i2c5: i2c@75b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x75b9000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp2_i2c5_default>; + dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_i2c6: i2c@75ba000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x75ba000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c6_default>; + pinctrl-1 = <&blsp2_i2c6_sleep>; + dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_spi6: spi@75ba000{ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x075ba000 0x600>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; @@ -1956,8 +2843,10 @@ <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_spi5_default>; - pinctrl-1 = <&blsp2_spi5_sleep>; + pinctrl-0 = <&blsp2_spi6_default>; + pinctrl-1 = <&blsp2_spi6_sleep>; + dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1981,6 +2870,7 @@ assigned-clock-rates = <19200000>, <60000000>; power-domains = <&gcc USB30_GDSC>; + qcom,select-utmi-as-pipe-clk; status = "disabled"; dwc3@7600000 { @@ -1989,6 +2879,7 @@ interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; phys = <&hsusb_phy2>; phy-names = "usb2-phy"; + maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; }; @@ -2032,13 +2923,13 @@ compatible = "slim217,1a0"; reg = <1 0>; - interrupt-parent = <&msmgpio>; + interrupt-parent = <&tlmm>; interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, <53 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "intr1", "intr2"; interrupt-controller; #interrupt-cells = <1>; - reset-gpios = <&msmgpio 64 0>; + reset-gpios = <&tlmm 64 0>; slim-ifc-dev = <&tasha_ifd>; @@ -2067,6 +2958,11 @@ qcom,smem-states = <&smp2p_adsp_out 0>; qcom,smem-state-names = "stop"; + power-domains = <&rpmpd MSM8996_VDDCX>; + power-domain-names = "cx"; + + status = "disabled"; + smd-edge { interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; @@ -2458,4 +3354,3 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; }; -#include "msm8996-pins.dtsi" diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 8ab4f1f78bbf..8a4972e6a24c 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -7,6 +7,30 @@ #include <dt-bindings/spmi/spmi.h> #include <dt-bindings/thermal/thermal.h> +/ { + thermal-zones { + pm6150_thermal: pm6150-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm6150_temp>; + + trips { + pm6150_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm6150_crit: crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pm6150_lsid0: pmic@0 { compatible = "qcom,pm6150", "qcom,spmi-pmic"; diff --git a/arch/arm64/boot/dts/qcom/pm7325.dtsi b/arch/arm64/boot/dts/qcom/pm7325.dtsi new file mode 100644 index 000000000000..e7f64a9ddc9c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm7325.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2021, The Linux Foundation. All rights reserved. + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +&spmi_bus { + pm7325: pmic@1 { + compatible = "qcom,pm7325", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm7325_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm7325_gpios: gpios@8800 { + compatible = "qcom,pm7325-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm7325_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&thermal_zones { + pm7325_thermal: pm7325-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm7325_temp_alarm>; + + trips { + pm7325_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm7325_crit: pm7325-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index fa4ea7ded0ab..c566a64b1373 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -50,7 +50,8 @@ pon: power-on@800 { compatible = "qcom,pm8916-pon"; reg = <0x0800>; - pwrkey { + + pon_pwrkey: pwrkey { compatible = "qcom,pm8941-pwrkey"; interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>; debounce = <15625>; @@ -59,6 +60,15 @@ status = "disabled"; }; + + pon_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + + status = "disabled"; + }; }; pm8150_temp: temp-alarm@2400 { diff --git a/arch/arm64/boot/dts/qcom/pm8350c.dtsi b/arch/arm64/boot/dts/qcom/pm8350c.dtsi index 2b9b75ecec60..e1b75ae0a823 100644 --- a/arch/arm64/boot/dts/qcom/pm8350c.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350c.dtsi @@ -13,13 +13,43 @@ #address-cells = <1>; #size-cells = <0>; + pm8350c_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pm8350c_gpios: gpio@8800 { - compatible = "qcom,pm8350c-gpio"; + compatible = "qcom,pm8350c-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; + gpio-ranges = <&pm8350c_gpios 0 0 9>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; }; + +&thermal_zones { + pm8350c_thermal: pm8350c-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8350c_temp_alarm>; + + trips { + pm8350c_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8350c_crit: pm8350c-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index c3876c82c874..ad19016df047 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -45,7 +45,6 @@ pm8994_pon: pon@800 { compatible = "qcom,pm8916-pon"; - reg = <0x800>; mode-bootloader = <0x2>; mode-recovery = <0x1>; @@ -58,6 +57,13 @@ linux,code = <KEY_POWER>; }; + pm8994_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; }; pm8994_temp: temp-alarm@2400 { diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi index e5ed28ab9b2d..b4ac900ab115 100644 --- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi @@ -32,5 +32,18 @@ #address-cells = <1>; #size-cells = <1>; }; + + pmi8994_wled: wled@d800 { + compatible = "qcom,pmi8994-wled"; + reg = <0xd800 0xd900>; + interrupts = <3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "short"; + qcom,num-strings = <3>; + /* Yes, all four strings *have to* be defined or things won't work. */ + qcom,enabled-strings = <0 1 2 3>; + qcom,cabc; + qcom,eternal-pfet; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index 1530b8ff270f..04fc2632a0b2 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -3,6 +3,8 @@ * Copyright (c) 2021, Linaro Limited */ +#include <dt-bindings/input/input.h> +#include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/spmi/spmi.h> @@ -13,10 +15,57 @@ #address-cells = <1>; #size-cells = <0>; + pmk8350_pon: pon@1300 { + compatible = "qcom,pm8998-pon"; + reg = <0x1300>; + + pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = <KEY_POWER>; + }; + + resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; + + pmk8350_vadc: adc@3100 { + compatible = "qcom,spmi-adc7"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + }; + + pmk8350_adc_tm: adc-tm@3400 { + compatible = "qcom,adc-tm7"; + reg = <0x3400>; + interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "threshold"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + pmk8350_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + }; + pmk8350_gpios: gpio@b000 { - compatible = "qcom,pmk8350-gpio"; + compatible = "qcom,pmk8350-gpio", "qcom,spmi-gpio"; reg = <0xb000>; gpio-controller; + gpio-ranges = <&pmk8350_gpios 0 0 4>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi new file mode 100644 index 000000000000..7072e5a2e73f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Limited + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/iio/qcom,spmi-vadc.h> + +/ { + thermal-zones { + pmm8155au-1-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmm8155au_1_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmic@0 { + compatible = "qcom,pmm8155au", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pon: power-on@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x0800>; + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = <KEY_POWER>; + + status = "disabled"; + }; + }; + + pmm8155au_1_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmm8155au_1_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pmm8155au_1_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = <ADC5_REF_GND>; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = <ADC5_1P25VREF>; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + die-temp@6 { + reg = <ADC5_DIE_TEMP>; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + }; + + pmm8155au_1_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pmm8155au_1_rtc: rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + + status = "disabled"; + }; + + pmm8155au_1_gpios: gpio@c000 { + compatible = "qcom,pmm8155au-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmm8155au_1_gpios 0 0 10>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@1 { + compatible = "qcom,pmm8155au", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi new file mode 100644 index 000000000000..72075964fbb9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Limited + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pmm8155au-2-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmm8155au_2_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmic@4 { + compatible = "qcom,pmm8155au", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + power-on@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x0800>; + + status = "disabled"; + }; + + pmm8155au_2_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmm8155au_2_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pmm8155au_2_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = <ADC5_REF_GND>; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = <ADC5_1P25VREF>; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + die-temp@6 { + reg = <ADC5_DIE_TEMP>; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + }; + + pmm8155au_2_gpios: gpio@c000 { + compatible = "qcom,pmm8155au-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmm8155au_2_gpios 0 0 10>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@5 { + compatible = "qcom,pmm8155au", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmr735a.dtsi b/arch/arm64/boot/dts/qcom/pmr735a.dtsi index 1c675af13cbf..b4b6ba24f845 100644 --- a/arch/arm64/boot/dts/qcom/pmr735a.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735a.dtsi @@ -13,13 +13,43 @@ #address-cells = <1>; #size-cells = <0>; + pmr735a_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pmr735a_gpios: gpio@8800 { - compatible = "qcom,pmr735a-gpio"; + compatible = "qcom,pmr735a-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; + gpio-ranges = <&pmr735a_gpios 0 0 4>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; }; + +&thermal_zones { + pmr735a_thermal: pmr735a-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmr735a_temp_alarm>; + + trips { + pmr735a_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pmr735a_crit: pmr735a-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 5f41de20aa22..8ac96f8e79d4 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -5,7 +5,6 @@ /dts-v1/; -#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> @@ -552,7 +551,13 @@ vdds-supply = <&vreg_l5a_0p88>; }; +&gmu { + status = "okay"; +}; + &gpu { + status = "okay"; + zap-shader { memory-region = <&gpu_mem>; firmware-name = "qcom/sm8250/a650_zap.mbn"; @@ -664,10 +669,6 @@ &pcie0 { status = "okay"; - perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; - wake-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_default_state>; }; &pcie0_phy { @@ -678,10 +679,6 @@ &pcie1 { status = "okay"; - perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>; - wake-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_default_state>; }; &pcie1_phy { @@ -692,10 +689,6 @@ &pcie2 { status = "okay"; - perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>; - wake-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_default_state>; }; &pcie2_phy { @@ -1173,81 +1166,6 @@ bias-disable; }; - pcie0_default_state: pcie0-default { - clkreq { - pins = "gpio80"; - function = "pci_e0"; - bias-pull-up; - }; - - reset-n { - pins = "gpio79"; - function = "gpio"; - - drive-strength = <2>; - output-low; - bias-pull-down; - }; - - wake-n { - pins = "gpio81"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie1_default_state: pcie1-default { - clkreq { - pins = "gpio83"; - function = "pci_e1"; - bias-pull-up; - }; - - reset-n { - pins = "gpio82"; - function = "gpio"; - - drive-strength = <2>; - output-low; - bias-pull-down; - }; - - wake-n { - pins = "gpio84"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie2_default_state: pcie2-default { - clkreq { - pins = "gpio86"; - function = "pci_e2"; - bias-pull-up; - }; - - reset-n { - pins = "gpio85"; - function = "gpio"; - - drive-strength = <2>; - output-low; - bias-pull-down; - }; - - wake-n { - pins = "gpio87"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - }; - sdc2_default_state: sdc2-default { clk { pins = "sdc2_clk"; @@ -1352,6 +1270,10 @@ qcom,dmic-sample-rate = <600000>; }; +&venus { + status = "okay"; +}; + /* PINCTRL - additions to nodes defined in sm8250.dtsi */ &qup_spi0_cs_gpio { drive-strength = <6>; diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts new file mode 100644 index 000000000000..0da7a3b8d1bf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/gpio/gpio.h> +#include "sm8150.dtsi" +#include "pmm8155au_1.dtsi" +#include "pmm8155au_2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155P ADP"; + compatible = "qcom,sa8155p-adp", "qcom,sa8155p"; + + aliases { + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vreg_3p3: vreg_3p3_regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + /* + * S4A is always on and not controllable through RPMh. + * So model it as a fixed regulator. + */ + vreg_s4a_1p8: smps4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + + vin-supply = <&vreg_3p3>; + }; +}; + +&apps_rsc { + pmm8155au-1-rpmh-regulators { + compatible = "qcom,pmm8155au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vreg_3p3>; + vdd-s2-supply = <&vreg_3p3>; + vdd-s3-supply = <&vreg_3p3>; + vdd-s4-supply = <&vreg_3p3>; + vdd-s5-supply = <&vreg_3p3>; + vdd-s6-supply = <&vreg_3p3>; + vdd-s7-supply = <&vreg_3p3>; + vdd-s8-supply = <&vreg_3p3>; + vdd-s9-supply = <&vreg_3p3>; + vdd-s10-supply = <&vreg_3p3>; + + vdd-l1-l8-l11-supply = <&vreg_s6a_0p92>; + vdd-l2-l10-supply = <&vreg_3p3>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p92>; + vdd-l6-l9-supply = <&vreg_s6a_0p92>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + vdd-l13-l16-l17-supply = <&vreg_3p3>; + + vreg_s5a_2p04: smps5 { + regulator-name = "vreg_s5a_2p04"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_s6a_0p92: smps6 { + regulator-name = "vreg_s6a_0p92"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_l1a_0p752: ldo1 { + regulator-name = "vreg_l1a_0p752"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdda_usb_hs_3p1: + vreg_l2a_3p072: ldo2 { + regulator-name = "vreg_l2a_3p072"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3a_0p8: ldo3 { + regulator-name = "vreg_l3a_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdd_usb_hs_core: + vdda_usb_ss_dp_core_1: + vreg_l5a_0p88: ldo5 { + regulator-name = "vreg_l5a_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l7a_1p8: ldo7 { + regulator-name = "vreg_l7a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10a_2p96: ldo10 { + regulator-name = "vreg_l10a_2p96"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l11a_0p8: ldo11 { + regulator-name = "vreg_l11a_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdda_usb_hs_1p8: + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13a_2p7: ldo13 { + regulator-name = "vreg_l13a_2p7"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15a_1p7: ldo15 { + regulator-name = "vreg_l15a_1p7"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1704000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16a_2p7: ldo16 { + regulator-name = "vreg_l16a_2p7"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17a_2p96: ldo17 { + regulator-name = "vreg_l17a_2p96"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + pmm8155au-2-rpmh-regulators { + compatible = "qcom,pmm8155au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vreg_3p3>; + vdd-s2-supply = <&vreg_3p3>; + vdd-s3-supply = <&vreg_3p3>; + vdd-s4-supply = <&vreg_3p3>; + vdd-s5-supply = <&vreg_3p3>; + vdd-s6-supply = <&vreg_3p3>; + vdd-s7-supply = <&vreg_3p3>; + vdd-s8-supply = <&vreg_3p3>; + vdd-s9-supply = <&vreg_3p3>; + vdd-s10-supply = <&vreg_3p3>; + + vdd-l1-l8-l11-supply = <&vreg_s4c_1p352>; + vdd-l2-l10-supply = <&vreg_3p3>; + vdd-l3-l4-l5-l18-supply = <&vreg_s4c_1p352>; + vdd-l6-l9-supply = <&vreg_s6c_1p128>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5c_2p04>; + vdd-l13-l16-l17-supply = <&vreg_3p3>; + + vreg_s4c_1p352: smps4 { + regulator-name = "vreg_s4c_1p352"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5c_2p04: smps5 { + regulator-name = "vreg_s5c_2p04"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_s6c_1p128: smps6 { + regulator-name = "vreg_s6c_1p128"; + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_l1c_1p304: ldo1 { + regulator-name = "vreg_l1c_1p304"; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c_1p808: ldo2 { + regulator-name = "vreg_l2c_1p808"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5c_1p2: ldo5 { + regulator-name = "vreg_l5c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l7c_1p8: ldo7 { + regulator-name = "vreg_l7c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8c_1p2: ldo8 { + regulator-name = "vreg_l8c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l10c_3p3: ldo10 { + regulator-name = "vreg_l10c_3p3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11c_0p8: ldo11 { + regulator-name = "vreg_l11c_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12c_1p808: ldo12 { + regulator-name = "vreg_l12c_1p808"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13c_2p96: ldo13 { + regulator-name = "vreg_l13c_2p96"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15c_1p9: ldo15 { + regulator-name = "vreg_l15c_1p9"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16c_3p008: ldo16 { + regulator-name = "vreg_l16c_3p008"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18c_0p88: ldo18 { + regulator-name = "vreg_l18c_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>; +}; + +&uart2 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l10a_2p96>; + vcc-max-microamp = <750000>; + vccq-supply = <&vreg_l5c_1p2>; + vccq-max-microamp = <700000>; + vccq2-supply = <&vreg_s4a_1p8>; + vccq2-max-microamp = <750000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l8c_1p2>; + vdda-max-microamp = <87100>; + vdda-pll-supply = <&vreg_l5a_0p88>; + vdda-pll-max-microamp = <18300>; +}; + + +&usb_1_hsphy { + status = "okay"; + vdda-pll-supply = <&vdd_usb_hs_core>; + vdda33-supply = <&vdda_usb_hs_3p1>; + vdda18-supply = <&vdda_usb_hs_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l8c_1p2>; + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index e77a7926034a..acdb36f4479f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -9,6 +9,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include "sc7180.dtsi" #include "pm6150.dtsi" #include "pm6150l.dtsi" @@ -45,7 +46,7 @@ /* Increase the size from 2MB to 8MB */ &rmtfs_mem { - reg = <0x0 0x84400000 0x0 0x800000>; + reg = <0x0 0x94600000 0x0 0x800000>; }; / { @@ -288,6 +289,57 @@ }; }; +&dsi0 { + status = "okay"; + + vdda-supply = <&vreg_l3c_1p2>; + + panel@0 { + compatible = "visionox,rm69299-1080p-display"; + reg = <0>; + + vdda-supply = <&vreg_l8c_1p8>; + vdd3p3-supply = <&vreg_l18a_2p8>; + + pinctrl-names = "default"; + pinctrl-0 = <&disp_pins>; + + reset-gpios = <&pm6150l_gpio 3 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dsi_phy { + status = "okay"; +}; + +&mdp { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + &qfprom { vcc-supply = <&vreg_l11a_1p8>; }; @@ -414,6 +466,19 @@ /* PINCTRL - additions to nodes defined in sc7180.dtsi */ +&pm6150l_gpio { + disp_pins: disp-pins { + pinconf { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_FUNC1; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_MED>; + power-source = <0>; + bias-disable; + output-low; + }; + }; +}; + &qspi_clk { pinconf { pins = "gpio63"; @@ -598,4 +663,106 @@ bias-pull-up; }; }; + + sdc1_on: sdc1-on { + pinconf-clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + pinconf-cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + pinconf-data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + pinconf-rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1-off { + pinconf-clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + pinconf-cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf-data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf-rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2-on { + pinconf-clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + pinconf-cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + pinconf-data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + pinconf-sd-cd { + pins = "gpio69"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2-off { + pinconf-clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + pinconf-cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf-data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf-sd-cd { + pins = "gpio69"; + bias-pull-up; + drive-strength = <2>; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts index 533c048903ea..82dc00cc7fb9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts @@ -9,8 +9,8 @@ #include "sc7180-trogdor-lte-sku.dtsi" / { - model = "Google CoachZ (rev1) with LTE"; - compatible = "google,coachz-rev1-sku0", "qcom,sc7180"; + model = "Google CoachZ (rev1 - 2) with LTE"; + compatible = "google,coachz-rev1-sku0", "google,coachz-rev2-sku0", "qcom,sc7180"; }; &cros_ec_proximity { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts index 1b1dbdb2a82f..21b516e0694a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts @@ -10,8 +10,26 @@ #include "sc7180-trogdor-coachz.dtsi" / { - model = "Google CoachZ (rev1)"; - compatible = "google,coachz-rev1", "qcom,sc7180"; + model = "Google CoachZ (rev1 - 2)"; + compatible = "google,coachz-rev1", "google,coachz-rev2", "qcom,sc7180"; +}; + +/* + * CoachZ rev1 is stuffed with a 47k NTC as charger thermistor which currently + * is not supported by the PM6150 ADC driver. Disable the charger thermal zone + * to avoid using bogus temperature values. + */ +&charger_thermal { + status = "disabled"; +}; + +/* + * CoachZ rev1 is stuffed with a 47k NTC as thermistor for skin temperature, + * which currently is not supported by the PM6150 ADC driver. Disable the + * skin temperature thermal zone to avoid using bogus temperature values. + */ +&skin_temp_thermal { + status = "disabled"; }; &tlmm { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3-lte.dts index 6e7745801fae..d23409034e8c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3-lte.dts @@ -2,14 +2,14 @@ /* * Google CoachZ board device tree source * - * Copyright 2020 Google LLC. + * Copyright 2021 Google LLC. */ -#include "sc7180-trogdor-coachz-r2.dts" +#include "sc7180-trogdor-coachz-r3.dts" #include "sc7180-trogdor-lte-sku.dtsi" / { - model = "Google CoachZ (rev2+) with LTE"; + model = "Google CoachZ (rev3+) with LTE"; compatible = "google,coachz-sku0", "qcom,sc7180"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3.dts index 4f69b6ba299f..a02d2d57c78c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3.dts @@ -2,7 +2,7 @@ /* * Google CoachZ board device tree source * - * Copyright 2020 Google LLC. + * Copyright 2021 Google LLC. */ /dts-v1/; @@ -10,6 +10,6 @@ #include "sc7180-trogdor-coachz.dtsi" / { - model = "Google CoachZ (rev2+)"; + model = "Google CoachZ (rev3+)"; compatible = "google,coachz", "qcom,sc7180"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 4c6e433c8226..6f9c07147551 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -23,8 +23,53 @@ ap_h1_spi: &spi0 {}; adau7002: audio-codec-1 { compatible = "adi,adau7002"; IOVDD-supply = <&pp1800_l15a>; + wakeup-delay-ms = <15>; #sound-dai-cells = <0>; }; + + thermal-zones { + skin_temp_thermal: skin-temp-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&pm6150_adc_tm 1>; + sustainable-power = <814>; + + trips { + skin_temp_alert0: trip-point0 { + temperature = <42000>; + hysteresis = <1000>; + type = "passive"; + }; + + skin_temp_alert1: trip-point1 { + temperature = <45000>; + hysteresis = <1000>; + type = "passive"; + }; + + skin-temp-crit { + temperature = <60000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&skin_temp_alert0>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&skin_temp_alert1>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; }; &ap_spi_fp { @@ -77,6 +122,25 @@ ap_ts_pen_1v8: &i2c4 { compatible = "boe,nv110wtm-n61"; }; +&pm6150_adc { + skin-temp-thermistor@4e { + reg = <ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm6150_adc_tm { + status = "okay"; + + skin-temp-thermistor@1 { + reg = <1>; + io-channels = <&pm6150_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + &pp3300_dx_edp { gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts index 5c997cd90069..30e3e769d2b4 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts @@ -14,15 +14,6 @@ compatible = "google,lazor-rev0", "qcom,sc7180"; }; -/* - * Lazor is stuffed with a 47k NTC as charger thermistor which currently is - * not supported by the PM6150 ADC driver. Disable the charger thermal zone - * to avoid using bogus temperature values. - */ -&charger_thermal { - status = "disabled"; -}; - &pp3300_hub { /* pp3300_l7c is used to power the USB hub */ /delete-property/regulator-always-on; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts index d9fbcc7bc5bd..c2ef06367baf 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts @@ -14,15 +14,6 @@ compatible = "google,lazor-rev1", "google,lazor-rev2", "qcom,sc7180"; }; -/* - * Lazor is stuffed with a 47k NTC as charger thermistor which currently is - * not supported by the PM6150 ADC driver. Disable the charger thermal zone - * to avoid using bogus temperature values. - */ -&charger_thermal { - status = "disabled"; -}; - &pp3300_hub { /* pp3300_l7c is used to power the USB hub */ /delete-property/regulator-always-on; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts index ea8c2ee09741..b474df47cd70 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts @@ -14,12 +14,3 @@ model = "Google Lazor (rev3+)"; compatible = "google,lazor", "qcom,sc7180"; }; - -/* - * Lazor is stuffed with a 47k NTC as charger thermistor which currently is - * not supported by the PM6150 ADC driver. Disable the charger thermal zone - * to avoid using bogus temperature values. - */ -&charger_thermal { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 6b10b96173e8..00535aaa43c9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -21,6 +21,15 @@ ap_h1_spi: &spi0 {}; semtech,avg-pos-strength = <64>; }; +/* + * Lazor is stuffed with a 47k NTC as charger thermistor which currently is + * not supported by the PM6150 ADC driver. Disable the charger thermal zone + * to avoid using bogus temperature values. + */ +&charger_thermal { + status = "disabled"; +}; + ap_ts_pen_1v8: &i2c4 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts index e720e7bd0d70..e122a6b481ff 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts @@ -9,11 +9,23 @@ #include "sc7180-trogdor-pompom.dtsi" +/delete-node/ &keyboard_controller; +#include <arm/cros-ec-keyboard.dtsi> + / { model = "Google Pompom (rev1)"; compatible = "google,pompom-rev1", "qcom,sc7180"; }; +/* + * Pompom rev1 is stuffed with a 47k NTC as charger thermistor which currently + * is not supported by the PM6150 ADC driver. Disable the charger thermal zone + * to avoid using bogus temperature values. + */ +&charger_thermal { + status = "disabled"; +}; + &pp3300_hub { /* pp3300_l7c is used to power the USB hub */ /delete-property/regulator-always-on; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dts index 791d496ad046..00e187c08eb9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dts @@ -9,6 +9,6 @@ #include "sc7180-trogdor-lte-sku.dtsi" / { - model = "Google Pompom (rev2+) with LTE"; - compatible = "google,pompom-sku0", "qcom,sc7180"; + model = "Google Pompom (rev2) with LTE"; + compatible = "google,pompom-rev2-sku0", "qcom,sc7180"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts index 984d7337da78..4f32e6733f4c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts @@ -10,35 +10,15 @@ #include "sc7180-trogdor-pompom.dtsi" / { - model = "Google Pompom (rev2+)"; - compatible = "google,pompom", "qcom,sc7180"; + model = "Google Pompom (rev2)"; + compatible = "google,pompom-rev2", "qcom,sc7180"; }; -&keyboard_controller { - function-row-physmap = < - MATRIX_KEY(0x00, 0x02, 0) /* T1 */ - MATRIX_KEY(0x03, 0x02, 0) /* T2 */ - MATRIX_KEY(0x02, 0x02, 0) /* T3 */ - MATRIX_KEY(0x01, 0x02, 0) /* T4 */ - MATRIX_KEY(0x03, 0x04, 0) /* T5 */ - MATRIX_KEY(0x02, 0x04, 0) /* T6 */ - MATRIX_KEY(0x01, 0x04, 0) /* T7 */ - MATRIX_KEY(0x02, 0x09, 0) /* T8 */ - MATRIX_KEY(0x01, 0x09, 0) /* T9 */ - MATRIX_KEY(0x00, 0x04, 0) /* T10 */ - >; - linux,keymap = < - MATRIX_KEY(0x00, 0x02, KEY_BACK) - MATRIX_KEY(0x03, 0x02, KEY_REFRESH) - MATRIX_KEY(0x02, 0x02, KEY_ZOOM) - MATRIX_KEY(0x01, 0x02, KEY_SCALE) - MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) - MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) - MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) - MATRIX_KEY(0x02, 0x09, KEY_MUTE) - MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) - MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) - - CROS_STD_MAIN_KEYMAP - >; +/* + * Pompom rev2 is stuffed with a 47k NTC as charger thermistor which currently + * is not supported by the PM6150 ADC driver. Disable the charger thermal zone + * to avoid using bogus temperature values. + */ +&charger_thermal { + status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dts new file mode 100644 index 000000000000..e90b73c353bb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pompom board device tree source + * + * Copyright 2021 Google LLC. + */ + +#include "sc7180-trogdor-pompom-r3.dts" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Pompom (rev3+) with LTE"; + compatible = "google,pompom-sku0", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dts new file mode 100644 index 000000000000..f8aac63a53ef --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Pompom board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor-pompom.dtsi" + +/ { + model = "Google Pompom (rev3+)"; + compatible = "google,pompom", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index 622b5f1b88a2..a246dbd74cc1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -107,6 +107,35 @@ ap_ts_pen_1v8: &i2c4 { }; }; +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; + &panel { compatible = "kingdisplay,kd116n21-30nv-a010"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 24d293ef56d7..77ae7561d436 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -64,11 +64,6 @@ no-map; }; - camera_mem: memory@8ec00000 { - reg = <0x0 0x8ec00000 0x0 0x500000>; - no-map; - }; - venus_mem: memory@8f600000 { reg = <0 0x8f600000 0 0x500000>; no-map; @@ -335,8 +330,7 @@ compatible = "jedec,spi-nor"; reg = <0>; - /* TODO: Increase frequency after testing */ - spi-max-frequency = <25000000>; + spi-max-frequency = <37500000>; spi-tx-bus-width = <2>; spi-rx-bus-width = <2>; }; @@ -564,10 +558,6 @@ #size-cells = <0>; }; - pdupdate { - compatible = "google,cros-ec-pd-update"; - }; - typec { compatible = "google,cros-ec-typec"; #address-cells = <1>; @@ -655,6 +645,8 @@ edp_brij_i2c: &i2c2 { clocks = <&rpmhcc RPMH_LN_BB_CLK3>; clock-names = "refclk"; + no-hpd; + ports { #address-cells = <1>; #size-cells = <0>; @@ -772,7 +764,7 @@ hp_i2c: &i2c9 { qcom,capture-sd-lines = <0>; }; - mi2s@1 { + secondary_mi2s: mi2s@1 { reg = <MI2S_SECONDARY>; qcom,playback-sd-lines = <0>; }; @@ -805,7 +797,7 @@ hp_i2c: &i2c9 { }; }; -&pm6150_pwrkey { +&pm6150_pon { status = "disabled"; }; @@ -981,6 +973,7 @@ ap_spi_fp: &spi10 { &qspi_clk { pinconf { pins = "gpio63"; + drive-strength = <8>; bias-disable; }; }; @@ -1494,4 +1487,106 @@ ap_spi_fp: &spi10 { drive-strength = <2>; }; }; + + sdc1_on: sdc1-on { + pinconf-clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + pinconf-cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + pinconf-data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + pinconf-rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1-off { + pinconf-clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + pinconf-cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf-data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf-rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2-on { + pinconf-clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + pinconf-cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + pinconf-data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + pinconf-sd-cd { + pins = "gpio69"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2-off { + pinconf-clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + pinconf-cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf-data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + pinconf-sd-cd { + pins = "gpio69"; + bias-pull-up; + drive-strength = <2>; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 6228ba2d8513..a9a052f8c63c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -701,8 +701,9 @@ interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; + <&gcc GCC_SDCC1_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; @@ -726,15 +727,15 @@ opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <100000 100000>; - opp-avg-kBps = <100000 50000>; + opp-peak-kBps = <1800000 600000>; + opp-avg-kBps = <100000 0>; }; opp-384000000 { opp-hz = /bits/ 64 <384000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - opp-peak-kBps = <600000 900000>; - opp-avg-kBps = <261438 300000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5400000 1600000>; + opp-avg-kBps = <390000 0>; }; }; }; @@ -768,8 +769,6 @@ #size-cells = <2>; ranges; iommus = <&apps_smmu 0x43 0x0>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>; - interconnect-names = "qup-core"; status = "disabled"; i2c0: i2c@880000 { @@ -1059,8 +1058,6 @@ #size-cells = <2>; ranges; iommus = <&apps_smmu 0x4c3 0x0>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>; - interconnect-names = "qup-core"; status = "disabled"; i2c6: i2c@a80000 { @@ -1871,108 +1868,6 @@ function = "lpass_ext"; }; }; - - sdc1_on: sdc1-on { - pinconf-clk { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <16>; - }; - - pinconf-cmd { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - pinconf-data { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <10>; - }; - - pinconf-rclk { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - - sdc1_off: sdc1-off { - pinconf-clk { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; - - pinconf-cmd { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - pinconf-data { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - - pinconf-rclk { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - - sdc2_on: sdc2-on { - pinconf-clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; - - pinconf-cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - pinconf-data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - - pinconf-sd-cd { - pins = "gpio69"; - bias-pull-up; - drive-strength = <2>; - }; - }; - - sdc2_off: sdc2-off { - pinconf-clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <2>; - }; - - pinconf-cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - pinconf-data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <2>; - }; - - pinconf-sd-cd { - pins = "gpio69"; - bias-disable; - drive-strength = <2>; - }; - }; }; remoteproc_mpss: remoteproc@4080000 { @@ -2670,8 +2565,9 @@ interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>; - clock-names = "core", "iface"; + <&gcc GCC_SDCC2_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; @@ -2689,15 +2585,15 @@ opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <160000 100000>; - opp-avg-kBps = <80000 50000>; + opp-peak-kBps = <1800000 600000>; + opp-avg-kBps = <100000 0>; }; opp-202000000 { opp-hz = /bits/ 64 <202000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - opp-peak-kBps = <200000 120000>; - opp-avg-kBps = <100000 60000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5400000 1600000>; + opp-avg-kBps = <200000 0>; }; }; }; @@ -2754,8 +2650,8 @@ usb_1_qmpphy: phy-wrapper@88e9000 { compatible = "qcom,sc7180-qmp-usb3-dp-phy"; reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x38>, - <0 0x088ea000 0 0x40>; + <0 0x088e8000 0 0x3c>, + <0 0x088ea000 0 0x18c>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 54d2cb365b71..3900cfc09562 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -7,11 +7,19 @@ /dts-v1/; +#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h> +#include <dt-bindings/iio/qcom,spmi-adc7-pmr735b.h> +#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h> +#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> #include "sc7280.dtsi" +#include "pm7325.dtsi" +#include "pmr735a.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" / { model = "Qualcomm Technologies, Inc. sc7280 IDP platform"; - compatible = "qcom,sc7280-idp", "qcom,sc7280"; + compatible = "qcom,sc7280-idp", "google,senor", "qcom,sc7280"; aliases { serial0 = &uart5; @@ -234,6 +242,32 @@ }; }; +&pmk8350_vadc { + pm8350_die_temp { + reg = <PM8350_ADC7_DIE_TEMP>; + label = "pm8350_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pmk8350_die_temp { + reg = <PMK8350_ADC7_DIE_TEMP>; + label = "pmk8350_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pmr735a_die_temp { + reg = <PMR735A_ADC7_DIE_TEMP>; + label = "pmr735a_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pmr735b_die_temp { + reg = <PMR735B_ADC7_DIE_TEMP>; + label = "pmr735b_die_temp"; + qcom,pre-scaling = <1 1>; + }; +}; + &qupv3_id_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 2cc478553935..a8c274ad74c4 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -11,7 +11,10 @@ #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/power/qcom-aoss-qmp.h> #include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/reset/qcom,sdm845-aoss.h> +#include <dt-bindings/reset/qcom,sdm845-pdc.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&intc>; @@ -51,6 +54,11 @@ no-map; }; + smem_mem: memory@80900000 { + reg = <0x0 0x80900000 0x0 0x200000>; + no-map; + }; + cpucp_mem: memory@80b00000 { no-map; reg = <0x0 0x80b00000 0x0 0x100000>; @@ -70,6 +78,8 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -88,6 +98,8 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -103,6 +115,8 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -118,6 +132,8 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -133,6 +149,8 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -148,6 +166,8 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -163,6 +183,8 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -178,6 +200,8 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -251,6 +275,125 @@ }; }; + clk_virt: interconnect { + compatible = "qcom,sc7280-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-wpss { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <13>; + + wpss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wpss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; @@ -316,6 +459,93 @@ }; }; + cnoc2: interconnect@1500000 { + reg = <0 0x01500000 0 0x1000>; + compatible = "qcom,sc7280-cnoc2"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + cnoc3: interconnect@1502000 { + reg = <0 0x01502000 0 0x1000>; + compatible = "qcom,sc7280-cnoc3"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@1580000 { + reg = <0 0x01580000 0 0x4>; + compatible = "qcom,sc7280-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + reg = <0 0x01680000 0 0x15480>; + compatible = "qcom,sc7280-system-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sc7280-aggre1-noc"; + reg = <0 0x016e0000 0 0x1c080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + reg = <0 0x01700000 0 0x2b080>; + compatible = "qcom,sc7280-aggre2-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + reg = <0 0x01740000 0 0x1e080>; + compatible = "qcom,sc7280-mmss-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex", "syscon"; + reg = <0 0x01f40000 0 0x40000>; + #hwlock-cells = <1>; + }; + + lpasscc: lpasscc@3000000 { + compatible = "qcom,sc7280-lpasscc"; + reg = <0 0x03000000 0 0x40>, + <0 0x03c04000 0 0x4>, + <0 0x03389000 0 0x24>; + reg-names = "qdsp6ss", "top_cc", "cc"; + clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; + clock-names = "iface"; + #clock-cells = <1>; + }; + + lpass_ag_noc: interconnect@3c40000 { + reg = <0 0x03c40000 0 0xf080>; + compatible = "qcom,sc7280-lpass-ag-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sc7280-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, @@ -805,6 +1035,20 @@ }; }; + dc_noc: interconnect@90e0000 { + reg = <0 0x090e0000 0 0x5080>; + compatible = "qcom,sc7280-dc-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9100000 { + reg = <0 0x9100000 0 0xe2200>; + compatible = "qcom,sc7280-gem-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + system-cache-controller@9200000 { compatible = "qcom,sc7280-llcc"; reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; @@ -812,6 +1056,42 @@ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; + nsp_noc: interconnect@a0c0000 { + reg = <0 0x0a0c0000 0 0x10000>; + compatible = "qcom,sc7280-nsp-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + videocc: clock-controller@aaf0000 { + compatible = "qcom,sc7280-videocc"; + reg = <0 0xaaf0000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>; + clock-names = "bi_tcxo", "bi_tcxo_ao"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sc7280-dispcc"; + reg = <0 0xaf00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <0>, <0>, <0>, <0>, <0>, <0>; + clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk", + "edp_phy_pll_link_clk", + "edp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; @@ -825,6 +1105,40 @@ interrupt-controller; }; + pdc_reset: reset-controller@b5e0000 { + compatible = "qcom,sc7280-pdc-global"; + reg = <0 0x0b5e0000 0 0x20000>; + #reset-cells = <1>; + }; + + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x1ff>; /* SROT */ + #qcom,sensors = <15>; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow","critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x1ff>; /* SROT */ + #qcom,sensors = <12>; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow","critical"; + #thermal-sensor-cells = <1>; + }; + + aoss_reset: reset-controller@c2a0000 { + compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; + reg = <0 0x0c2a0000 0 0x31000>; + #reset-cells = <1>; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,sc7280-aoss-qmp"; reg = <0 0x0c300000 0 0x100000>; @@ -1063,6 +1377,10 @@ <WAKE_TCS 3>, <CONTROL_TCS 1>; + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + rpmhpd: power-controller { compatible = "qcom,sc7280-rpmhpd"; #power-domain-cells = <1>; @@ -1116,6 +1434,859 @@ #clock-cells = <1>; }; }; + + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,cpufreq-epss"; + reg = <0 0x18591000 0 0x1000>, + <0 0x18592000 0 0x1000>, + <0 0x18593000 0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #freq-domain-cells = <1>; + }; + }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu0_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu1_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu2_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu3_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 7>; + + trips { + cpu4_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu4_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu4_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpu5_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu5_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu5_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 9>; + + trips { + cpu6_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu6_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu6_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu7_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu7_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu7_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu8-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 11>; + + trips { + cpu8_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu8_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu8_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu8_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu8_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu9-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 12>; + + trips { + cpu9_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu9_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu9_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu9_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu9_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu10-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 13>; + + trips { + cpu10_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu10_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu10_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu10_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu10_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu11-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 14>; + + trips { + cpu11_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu11_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu11_crit: cpu-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu11_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu11_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + aoss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 0>; + + trips { + aoss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0_crit: aoss0-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 0>; + + trips { + aoss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss1_crit: aoss1-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 5>; + + trips { + cpuss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + cpuss0_crit: cluster0-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 6>; + + trips { + cpuss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + cpuss1_crit: cluster0-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 1>; + + trips { + gpuss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpuss0_crit: gpuss0-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 2>; + + trips { + gpuss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpuss1_crit: gpuss1-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nspss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 3>; + + trips { + nspss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nspss0_crit: nspss0-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nspss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 4>; + + trips { + nspss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nspss1_crit: nspss1-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 5>; + + trips { + video_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + video_crit: video-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 6>; + + trips { + ddr_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + ddr_crit: ddr-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 7>; + + trips { + mdmss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + mdmss0_crit: mdmss0-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 8>; + + trips { + mdmss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + mdmss1_crit: mdmss1-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 9>; + + trips { + mdmss2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + mdmss2_crit: mdmss2-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 10>; + + trips { + mdmss3_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + mdmss3_crit: mdmss3-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 11>; + + trips { + camera0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + camera0_crit: camera0-crit { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; }; timer { diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 216a74f0057c..dfd1b42c07fd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -714,10 +714,6 @@ ap_ts_i2c: &i2c14 { #address-cells = <1>; #size-cells = <0>; }; - - pdupdate { - compatible = "google,cros-ec-pd-update"; - }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 1372fe8601f5..91ede9296aff 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -448,6 +448,11 @@ clock-frequency = <400000>; }; +&ipa { + status = "okay"; + memory-region = <&ipa_fw_mem>; +}; + &mdss { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 8f617f7b6d34..4d052e39b348 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -46,6 +46,14 @@ }; reserved-memory { + /* The rmtfs_mem needs to be guarded due to "XPU limitations" + * it is otherwise possible for an allocation adjacent to the + * rmtfs_mem region to trigger an XPU violation, causing a crash. + */ + rmtfs_lower_guard: memory@f5b00000 { + no-map; + reg = <0 0xf5b00000 0 0x1000>; + }; /* * The rmtfs memory region in downstream is 'dynamically allocated' * but given the same address every time. Hard code it as this address is @@ -59,6 +67,10 @@ qcom,client-id = <1>; qcom,vmid = <15>; }; + rmtfs_upper_guard: memory@f5d01000 { + no-map; + reg = <0 0xf5d01000 0 0x2000>; + }; /* * It seems like reserving the old rmtfs_mem region is also needed to prevent @@ -387,6 +399,12 @@ }; }; +&ipa { + status = "okay"; + + memory-region = <&ipa_fw_mem>; +}; + &mdss { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 7d029425336e..c60c8c640e17 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -5,6 +5,8 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/sound/qcom,q6afe.h> +#include <dt-bindings/sound/qcom,q6asm.h> #include "sdm845.dtsi" #include "pm8998.dtsi" #include "pmi8998.dtsi" @@ -311,6 +313,28 @@ }; }; +/* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */ +&q6afedai { + qi2s@22 { + reg = <22>; + qcom,sd-lines = <0>; + }; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; +}; + &qupv3_id_0 { status = "okay"; }; @@ -328,6 +352,70 @@ cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>; }; +&sound { + compatible = "qcom,db845c-sndcard"; + pinctrl-0 = <&quat_mi2s_active + &quat_mi2s_sd0_active>; + pinctrl-names = "default"; + model = "Xiaomi Poco F1"; + audio-routing = + "RX_BIAS", "MCLK", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS3"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 0>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 1>; + }; + }; +}; + &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; @@ -356,6 +444,15 @@ function = "gpio"; bias-pull-up; }; + + wcd_intr_default: wcd_intr_default { + pins = <54>; + function = "gpio"; + + input-enable; + bias-pull-down; + drive-strength = <2>; + }; }; &uart6 { @@ -416,6 +513,23 @@ vdda-pll-supply = <&vreg_l1a_0p875>; }; +&wcd9340{ + pinctrl-0 = <&wcd_intr_default>; + pinctrl-names = "default"; + clock-names = "extclk"; + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; + reset-gpios = <&tlmm 64 0>; + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + qcom,micbias1-microvolt = <2700000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <2700000>; + qcom,micbias4-microvolt = <2700000>; +}; + &wifi { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 140db2d5ba31..c2a709a384e9 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -376,6 +376,8 @@ clocks = <&sn65dsi86_refclk>; clock-names = "refclk"; + no-hpd; + ports { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index fb2cf3d987a1..335aa0753fc0 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -354,22 +354,26 @@ }; }; -&qupv3_id_1 { +&gmu { status = "okay"; }; -&pon { - pwrkey { - status = "okay"; - }; +&gpu { + status = "okay"; +}; - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + + linux,code = <KEY_VOLUMEDOWN>; +}; + +&qupv3_id_1 { + status = "okay"; }; &remoteproc_adsp { diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts new file mode 100644 index 000000000000..736da9af44e0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts @@ -0,0 +1,543 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (C) 2021, Microsoft Corporation + */ + +/dts-v1/; + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/gpio/gpio.h> +#include "sm8150.dtsi" +#include "pm8150.dtsi" +#include "pm8150b.dtsi" +#include "pm8150l.dtsi" + +/ { + model = "Microsoft Surface Duo"; + compatible = "microsoft,surface-duo", "qcom,sm8150"; + + aliases { + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + /* + * Apparently RPMh does not provide support for PM8150 S4 because it + * is always-on; model it as a fixed regulator. + */ + vreg_s4a_1p8: pm8150-s4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + vol_up { + label = "Volume Up"; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; +}; + +&apps_rsc { + pm8150-rpmh-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>; + vdd-l6-l9-supply = <&vreg_s8c_1p3>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_s6a_0p9: smps6 { + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + }; + + vdda_wcss_pll: + vreg_l1a_0p75: ldo1 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdd_pdphy: + vdda_usb_hs_3p1: + vreg_l2a_3p1: ldo2 { + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3a_0p8: ldo3 { + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <932000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdd_usb_hs_core: + vdda_csi_0_0p9: + vdda_csi_1_0p9: + vdda_csi_2_0p9: + vdda_csi_3_0p9: + vdda_dsi_0_0p9: + vdda_dsi_1_0p9: + vdda_dsi_0_pll_0p9: + vdda_dsi_1_pll_0p9: + vdda_pcie_1ln_core: + vdda_pcie_2ln_core: + vdda_pll_hv_cc_ebi01: + vdda_pll_hv_cc_ebi23: + vdda_qrefs_0p875_5: + vdda_sp_sensor: + vdda_ufs_2ln_core_1: + vdda_ufs_2ln_core_2: + vdda_usb_ss_dp_core_1: + vdda_usb_ss_dp_core_2: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vreg_l5a_0p875: ldo5 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6a_1p2: ldo6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vddpx_10: + vreg_l9a_1p2: ldo9 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10a_2p5: ldo10 { + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11a_0p8: ldo11 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdd_qfprom: + vdd_qfprom_sp: + vdda_apc_cs_1p8: + vdda_gfx_cs_1p8: + vdda_usb_hs_1p8: + vdda_qrefs_vref_1p8: + vddpx_10_a: + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13a_2p7: ldo13 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15a_1p7: ldo15 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1704000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17a_3p0: ldo17 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + pm8150l-rpmh-regulators { + compatible = "qcom,pm8150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + + vdd-l1-l8-supply = <&vreg_s4a_1p8>; + vdd-l2-l3-supply = <&vreg_s8c_1p3>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + + vdd-bob-supply = <&vph_pwr>; + vdd-flash-supply = <&vreg_bob>; + vdd-rgb-supply = <&vreg_bob>; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <4000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-bypass; + }; + + vreg_s8c_1p3: smps8 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdda_wcss_adcdac_1: + vdda_wcss_adcdac_22: + vreg_l2c_1p3: ldo2 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vdda_hv_ebi0: + vdda_hv_ebi1: + vdda_hv_ebi2: + vdda_hv_ebi3: + vdda_hv_refgen0: + vdda_qlink_hv_ck: + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vddpx_5: + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vddpx_6: + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vddpx_2: + vreg_l6c_2p9: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9c_2p9: ldo9 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + pm8009-rpmh-regulators { + compatible = "qcom,pm8009-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vreg_bob>; + + vdd-l2-supply = <&vreg_s8c_1p3>; + vdd-l5-l6-supply = <&vreg_bob>; + + vreg_l2f_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5f_2p85: ldo5 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6f_2p85: ldo6 { + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <2856000>; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + bq27742@55 { + compatible = "ti,bq27742"; + reg = <0x55>; + }; + + da7280@4a { + compatible = "dlg,da7280"; + reg = <0x4a>; + interrupts-extended = <&tlmm 42 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "da7280_default"; + pinctrl-0 = <&da7280_intr_default>; + + dlg,actuator-type = "LRA"; + dlg,dlg,const-op-mode = <1>; + dlg,dlg,periodic-op-mode = <1>; + dlg,nom-microvolt = <2000000>; + dlg,abs-max-microvolt = <2000000>; + dlg,imax-microamp = <129000>; + dlg,resonant-freq-hz = <180>; + dlg,impd-micro-ohms = <14300000>; + dlg,freq-track-enable; + dlg,bemf-sens-enable; + dlg,mem-array = < + 0x06 0x08 0x10 0x11 0x12 0x13 0x14 0x15 0x1c 0x2a + 0x33 0x3c 0x42 0x4b 0x4c 0x4e 0x17 0x19 0x27 0x29 + 0x17 0x19 0x03 0x84 0x5e 0x04 0x08 0x84 0x5d 0x01 + 0x84 0x5e 0x02 0x00 0xa4 0x5d 0x03 0x84 0x5e 0x06 + 0x08 0x84 0x5d 0x05 0x84 0x5d 0x06 0x84 0x5e 0x08 + 0x84 0x5e 0x05 0x8c 0x5e 0x24 0x84 0x5f 0x10 0x84 + 0x5e 0x05 0x84 0x5e 0x08 0x84 0x5f 0x01 0x8c 0x5e + 0x04 0x84 0x5e 0x08 0x84 0x5f 0x11 0x19 0x88 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + >; + }; + + /* SMB1381 @ 0x44 */ + /* MAX34417 @ 0x1c */ +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + /* SMB1355 @ 0x0c */ + /* SMB1390 @ 0x10 */ +}; + +&i2c17 { + status = "okay"; + clock-frequency = <400000>; + + bq27742@55 { + compatible = "ti,bq27742"; + reg = <0x55>; + }; +}; + +&i2c19 { + status = "okay"; + clock-frequency = <400000>; + + /* MAX34417 @ 0x12 */ + /* MAX34417 @ 0x1a */ + /* MAX34417 @ 0x1e */ +}; + +&pon { + pwrkey { + status = "okay"; + }; + + resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = <KEY_VOLUMEDOWN>; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&remoteproc_adsp { + status = "okay"; + firmware-name = "qcom/sm8150/microsoft/adsp.mdt"; +}; + +&remoteproc_cdsp { + status = "okay"; + firmware-name = "qcom/sm8150/microsoft/cdsp.mdt"; +}; + +&remoteproc_mpss { + status = "okay"; + firmware-name = "qcom/sm8150/microsoft/modem.mdt"; +}; + +&remoteproc_slpi { + status = "okay"; + firmware-name = "qcom/sm8150/microsoft/slpi.mdt"; +}; + +&tlmm { + gpio-reserved-ranges = <126 4>; + + da7280_intr_default: da7280-intr-default { + pins = "gpio42"; + function = "gpio"; + bias-pull-up; + input-enable; + }; +}; + +&uart2 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l10a_2p5>; + vcc-max-microamp = <750000>; + vccq-supply = <&vreg_l9a_1p2>; + vccq-max-microamp = <700000>; + vccq2-supply = <&vreg_s4a_1p8>; + vccq2-max-microamp = <750000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vdda_ufs_2ln_core_1>; + vdda-max-microamp = <90200>; + vdda-pll-supply = <&vreg_l3c_1p2>; + vdda-pll-max-microamp = <19000>; +}; + +&usb_1_hsphy { + status = "okay"; + vdda-pll-supply = <&vdd_usb_hs_core>; + vdda33-supply = <&vdda_usb_hs_3p1>; + vdda18-supply = <&vdda_usb_hs_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vdda_wcss_pll>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vdda_wcss_adcdac_1>; + vdd-3.3-ch0-supply = <&vreg_l11c_3p3>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 3774f8e63416..53edf7541169 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -349,22 +349,26 @@ }; }; -&qupv3_id_1 { +&gmu { status = "okay"; }; -&pon { - pwrkey { - status = "okay"; - }; +&gpu { + status = "okay"; +}; - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + + linux,code = <KEY_VOLUMEDOWN>; +}; + +&qupv3_id_1 { + status = "okay"; }; &remoteproc_adsp { diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-bahamut.dts b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-bahamut.dts new file mode 100644 index 000000000000..3b55fdda767a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-bahamut.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +/dts-v1/; + +#include "sm8150-sony-xperia-kumano.dtsi" + +/ { + model = "Sony Xperia 5"; + compatible = "sony,bahamut-generic", "qcom,sm8150"; +}; + +&framebuffer { + width = <1080>; + height = <2520>; + stride = <(1080 * 4)>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-griffin.dts b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-griffin.dts new file mode 100644 index 000000000000..6f490ec284bd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano-griffin.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +/dts-v1/; + +#include "sm8150-sony-xperia-kumano.dtsi" + +/ { + model = "Sony Xperia 1"; + compatible = "sony,griffin-generic", "qcom,sm8150"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi new file mode 100644 index 000000000000..014fe3a31548 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -0,0 +1,452 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sm8150.dtsi" +#include "pm8150.dtsi" +#include "pm8150b.dtsi" +#include "pm8150l.dtsi" + +/delete-node/ &cdsp_mem; +/delete-node/ &gpu_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &mpss_mem; +/delete-node/ &slpi_mem; +/delete-node/ &spss_mem; +/delete-node/ &venus_mem; + +/ { + qcom,msm-id = <339 0x20000>; /* SM8150 v2 */ + qcom,board-id = <8 0>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@9c000000 { + compatible = "simple-framebuffer"; + reg = <0 0x9c000000 0 0x2300000>; + width = <1644>; + height = <3840>; + stride = <(1644 * 4)>; + format = "a8r8g8b8"; + /* + * That's (going to be) a lot of clocks, but it's necessary due + * to unused clk cleanup & no panel driver yet (& no dispcc either).. + */ + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + /* + * Apparently RPMh does not provide support for PM8150 S4 because it + * is always-on; model it as a fixed regulator. + */ + vreg_s4a_1p8: pm8150-s4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + reserved-memory { + mpss_mem: memory@8dc00000 { + reg = <0x0 0x8dc00000 0x0 0x9600000>; + no-map; + }; + + venus_mem: memory@97200000 { + reg = <0x0 0x97200000 0x0 0x500000>; + no-map; + }; + + slpi_mem: memory@97700000 { + reg = <0x0 0x97700000 0x0 0x1400000>; + no-map; + }; + + ipa_fw_mem: memory@98b00000 { + reg = <0x0 0x98b00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: memory@98b10000 { + reg = <0x0 0x98b10000 0x0 0x5000>; + no-map; + }; + + gpu_mem: memory@98b15000 { + reg = <0x0 0x98b15000 0x0 0x2000>; + no-map; + }; + + spss_mem: memory@98c00000 { + reg = <0x0 0x98c00000 0x0 0x100000>; + no-map; + }; + + cdsp_mem: memory@98d00000 { + reg = <0x0 0x98d00000 0x0 0x1400000>; + no-map; + }; + + cont_splash_mem: memory@9c000000 { + reg = <0x0 0x9c000000 0x0 0x2400000>; + no-map; + }; + + cdsp_sec_mem: memory@a4c00000 { + reg = <0x0 0xa4c00000 0x0 0x3c00000>; + no-map; + }; + + ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0x0 0xffc00000 0x0 0x100000>; + record-size = <0x1000>; + console-size = <0x40000>; + msg-size = <0x20000 0x20000>; + ecc-size = <16>; + no-map; + }; + }; +}; + +&adsp_mem { + reg = <0x0 0x8be00000 0x0 0x1e00000>; +}; + +&apps_rsc { + pm8150-rpmh-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>; + vdd-l6-l9-supply = <&vreg_s8c_1p3>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + vreg_s2a_0p6: smps2 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5a_1p9: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s6a_0p9: smps6 { + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1a_0p75: ldo1 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2a_3p1: ldo2 { + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3a_0p8: ldo3 { + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <932000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5a_0p875: ldo5 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6a_1p2: ldo6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9a_1p2: ldo9 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10a_2p5: ldo10 { + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11a_0p8: ldo11 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L13 is unused. */ + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15a_1p7: ldo15 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1704000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17a_3p0: ldo17 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18a_0p8: ldo18 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + pm8150l-rpmh-regulators { + compatible = "qcom,pm8150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + + vdd-l1-l8-supply = <&vreg_s4a_1p8>; + vdd-l2-l3-supply = <&vreg_s8c_1p3>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + + vdd-bob-supply = <&vph_pwr>; + vdd-flash-supply = <&vreg_bob>; + vdd-rgb-supply = <&vreg_bob>; + + vreg_bob: bob { + regulator-min-microvolt = <3350000>; + regulator-max-microvolt = <4000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + regulator-allow-bypass; + }; + + vreg_s1c_1p1: smps1 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s8c_1p3: smps8 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c_1p3: ldo2 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6c_2p9: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9c_2p9: ldo9 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* PM8009 is not present on these boards, even if downstream sources suggest so. */ +}; + +&i2c4 { + status = "okay"; + + /* Qcom SMB1355 @ c */ + /* Qcom SMB1390 @ 10 */ + /* NXP PN553 NFC @ 28 */ + /* Qcom FSA4480 USB-C audio switch @ 43 */ +}; + +&i2c7 { + status = "okay"; + + /* AMS TCS3490 RGB+IR color sensor @ 72 */ +}; + +&i2c10 { + status = "okay"; + + /* Samsung touchscreen @ 48 */ +}; + +&pon_pwrkey { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <126 4>; +}; + +&uart2 { + status = "okay"; +}; + +/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */ +&ufs_mem_hc { status = "disabled"; }; +&ufs_mem_phy { status = "disabled"; }; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + vdda-pll-supply = <&vreg_l5a_0p875>; + vdda33-supply = <&vreg_l2a_3p1>; + vdda18-supply = <&vreg_l12a_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l18a_0p8>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 51235a9521c2..eef9d79157e9 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -4,6 +4,7 @@ * Copyright (c) 2019, Linaro Limited */ +#include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-aoss-qmp.h> #include <dt-bindings/power/qcom-rpmpd.h> @@ -577,6 +578,29 @@ <&sleep_clk>; }; + gpi_dma0: dma-controller@800000 { + compatible = "qcom,sm8150-gpi-dma"; + reg = <0 0x800000 0 0x60000>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + iommus = <&apps_smmu 0x00d6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -695,6 +719,29 @@ }; + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm8150-gpi-dma"; + reg = <0 0xa00000 0 0x60000>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + iommus = <&apps_smmu 0x0616 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x6000>; @@ -795,6 +842,29 @@ }; }; + gpi_dma2: dma-controller@c00000 { + compatible = "qcom,sm8150-gpi-dma"; + reg = <0 0xc00000 0 0x60000>; + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + iommus = <&apps_smmu 0x07b6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_2: geniqup@cc0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00cc0000 0x0 0x6000>; @@ -1082,6 +1152,8 @@ qcom,gmu = <&gmu>; + status = "disabled"; + zap-shader { memory-region = <&gpu_mem>; }; @@ -1149,6 +1221,8 @@ operating-points-v2 = <&gmu_opp_table>; + status = "disabled"; + gmu_opp_table: opp-table { compatible = "operating-points-v2"; @@ -1496,6 +1570,8 @@ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; + status = "disabled"; + glink-edge { interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; label = "modem"; diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index c3a2c5aa6fe9..47742816ac2f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -6,7 +6,6 @@ /dts-v1/; #include <dt-bindings/regulator/qcom,rpmh-regulator.h> -#include <dt-bindings/gpio/gpio.h> #include "sm8250.dtsi" #include "pm8150.dtsi" #include "pm8150b.dtsi" @@ -365,22 +364,26 @@ }; }; -&qupv3_id_1 { +&gmu { status = "okay"; }; -&pon { - pwrkey { - status = "okay"; - }; +&gpu { + status = "okay"; +}; - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + + linux,code = <KEY_VOLUMEDOWN>; +}; + +&qupv3_id_1 { + status = "okay"; }; &tlmm { @@ -452,3 +455,7 @@ &usb_2_dwc3 { dr_mode = "host"; }; + +&venus { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index cfc4d1febe0f..062b944be91d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -465,7 +465,13 @@ firmware-name = "qcom/sm8250/cdsp.mbn"; }; +&gmu { + status = "okay"; +}; + &gpu { + status = "okay"; + zap-shader { memory-region = <&gpu_mem>; firmware-name = "qcom/sm8250/a650_zap.mbn"; @@ -691,3 +697,7 @@ vdda-phy-supply = <&vreg_l9a_1p2>; vdda-pll-supply = <&vreg_l18a_0p9>; }; + +&venus { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts new file mode 100644 index 000000000000..79afeb07f4a2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +/dts-v1/; + +#include "sm8250-sony-xperia-edo.dtsi" + +/ { + model = "Sony Xperia 1 II"; + compatible = "sony,pdx203-generic", "qcom,sm8250"; +}; + +/delete-node/ &vreg_l7f_1p8; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts new file mode 100644 index 000000000000..16c96e838534 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +/dts-v1/; + +#include "sm8250-sony-xperia-edo.dtsi" + +/ { + model = "Sony Xperia 5 II"; + compatible = "sony,pdx206-generic", "qcom,sm8250"; +}; + +&framebuffer { + width = <1080>; + height = <2520>; + stride = <(1080 * 4)>; +}; + +&gpio_keys { + g-assist-key { + label = "Google Assistant Key"; + linux,code = <KEY_LEFTMETA>; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; +}; + +&vreg_l2f_1p3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi new file mode 100644 index 000000000000..d63f7a9bc4e9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -0,0 +1,636 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sm8250.dtsi" +#include "pm8150.dtsi" +#include "pm8150b.dtsi" +#include "pm8150l.dtsi" +#include "pm8009.dtsi" + +/delete-node/ &adsp_mem; +/delete-node/ &spss_mem; +/delete-node/ &cdsp_secure_heap; + +/ { + qcom,msm-id = <356 0x20001>; /* SM8250 v2.1 */ + qcom,board-id = <0x10008 0>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@9c000000 { + compatible = "simple-framebuffer"; + reg = <0 0x9c000000 0 0x2300000>; + width = <1644>; + height = <3840>; + stride = <(1644 * 4)>; + format = "a8r8g8b8"; + /* + * That's a lot of clocks, but it's necessary due + * to unused clk cleanup & no panel driver yet.. + */ + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>; + power-domains = <&dispcc MDSS_GDSC>; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + /* + * Camera focus (light press) and camera snapshot (full press) + * seem not to work properly.. Adding the former one stalls the CPU + * and the latter kills the volume down key for whatever reason. In any + * case, they are both on &pm8150b_gpios: camera focus(2), camera snapshot(1). + */ + + vol-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + /* S6c is really ebi.lvl but it's there for supply map completeness sake. */ + vreg_s6c_0p88: smpc6-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s6c_0p88"; + + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-always-on; + vin-supply = <&vph_pwr>; + }; + + reserved-memory { + adsp_mem: memory@8a100000 { + reg = <0x0 0x8a100000 0x0 0x2500000>; + no-map; + }; + + spss_mem: memory@8c600000 { + reg = <0x0 0x8c600000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap: memory@8c700000 { + reg = <0x0 0x8c700000 0x0 0x4600000>; + no-map; + }; + + cont_splash_mem: memory@9c000000 { + reg = <0x0 0x9c000000 0x0 0x2300000>; + no-map; + }; + + ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0x0 0xffc00000 0x0 0x100000>; + record-size = <0x1000>; + console-size = <0x40000>; + msg-size = <0x20000 0x20000>; + ecc-size = <16>; + no-map; + }; + }; +}; + +&adsp { + status = "okay"; +}; + +&apps_rsc { + pm8150-rpmh-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p6>; + vdd-l6-l9-supply = <&vreg_s8c_1p2>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + /* (S1+S2+S3) - cx.lvl (ARC) */ + + vreg_s4a_1p8: smps4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5a_1p9: smps5 { + regulator-name = "vreg_s5a_1p9"; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s6a_0p6: smps6 { + regulator-name = "vreg_s6a_0p6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2a_3p1: ldo2 { + regulator-name = "vreg_l2a_3p1"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3a_0p9: ldo3 { + regulator-name = "vreg_l3a_0p9"; + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <932000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L4 - lmx.lvl (ARC) */ + + vreg_l5a_0p88: ldo5 { + regulator-name = "vreg_l5a_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6a_1p2: ldo6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L7 is unused. */ + + vreg_l9a_1p2: ldo9 { + regulator-name = "vreg_l9a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L10 is unused, L11 - lcx.lvl (ARC) */ + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L13 is unused. */ + + vreg_l14a_1p8: ldo14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L15 & L16 are unused. */ + + vreg_l17a_3p0: ldo17 { + regulator-name = "vreg_l17a_3p0"; + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18a_0p9: ldo18 { + regulator-name = "vreg_l18a_0p9"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* + * Remaining regulators that are not yet supported: + * OLEDB: 4925000-8100000 + * ab: 4600000-6100000 + * ibb: 800000-5400000 + */ + pm8150l-rpmh-regulators { + compatible = "qcom,pm8150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l8-supply = <&vreg_s4a_1p8>; + vdd-l2-l3-supply = <&vreg_s8c_1p2>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3350000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + }; + + /* + * S1-S6 are ARCs: + * (S1+S2) - gfx.lvl, + * S3 - mx.lvl, + * (S4+S5) - mmcx.lvl, + * S6 - ebi.lvl + */ + + vreg_s7c_0p35: smps7 { + regulator-name = "vreg_s7c_0p35"; + regulator-min-microvolt = <348000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s8c_1p2: smps8 { + regulator-name = "vreg_s8c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L2-4 are unused. */ + + vreg_l5c_1p8: ldo5 { + regulator-name = "vreg_l5c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6c_2p9: ldo6 { + regulator-name = "vreg_l6c_2p9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l7c_2p85: ldo7 { + regulator-name = "vreg_l7c_2p85"; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9c_2p9: ldo9 { + regulator-name = "vreg_l9c_2p9"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + }; + + vreg_l10c_3p3: ldo10 { + regulator-name = "vreg_l10c_3p3"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3296000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11c_3p0: ldo11 { + regulator-name = "vreg_l11c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + pm8009-rpmh-regulators { + compatible = "qcom,pm8009-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vreg_bob>; + vdd-l2-supply = <&vreg_s8c_1p2>; + vdd-l5-l6-supply = <&vreg_bob>; + vdd-l7-supply = <&vreg_s4a_1p8>; + + vreg_s1f_1p2: smps1 { + regulator-name = "vreg_s1f_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2f_0p5: smps2 { + regulator-name = "vreg_s2f_0p5"; + regulator-min-microvolt = <512000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L1 is unused. */ + + vreg_l2f_1p3: ldo2 { + regulator-name = "vreg_l2f_1p3"; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L3 & L4 are unused. */ + + vreg_l5f_2p8: ldo5 { + regulator-name = "vreg_l5f_2p85"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6f_2p8: ldo6 { + regulator-name = "vreg_l6f_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7f_1p8: ldo7 { + regulator-name = "vreg_l7f_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&cdsp { + status = "okay"; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + /* NXP PN553 NFC @ 28 */ +}; + +&i2c2 { + status = "okay"; + clock-frequency = <1000000>; + + /* Dual Cirrus Logic CS35L41 amps @ 40, 41 */ +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + /* Dialog SLG51000 CMIC @ 75 */ +}; + +&i2c9 { + status = "okay"; + clock-frequency = <400000>; + + /* AMS TCS3490 RGB+IR color sensor @ 72 */ +}; + +&i2c13 { + status = "okay"; + clock-frequency = <400000>; + + touchscreen@48 { + compatible = "samsung,s6sy761"; + reg = <0x48>; + interrupt-parent = <&tlmm>; + interrupts = <39 0x2008>; + /* It's "vddio" downstream but it works anyway! */ + vdd-supply = <&vreg_l1c_1p8>; + avdd-supply = <&vreg_l10c_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_default>; + }; +}; + +&i2c15 { + status = "okay"; + clock-frequency = <400000>; + + /* Qcom SMB1390 @ 10 */ + /* Silicon Labs SI4704 FM Radio Receiver @ 11 */ + /* Qcom SMB1390_slave @ 18 */ + /* HALO HL6111R Qi charger @ 25 */ + /* Richwave RTC6226 FM Radio Receiver @ 64 */ +}; + +&pcie0 { + status = "okay"; +}; + +&pcie0_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; +}; + +&pcie2 { + status = "okay"; + + pinctrl-0 = <&pcie2_default_state &mdm2ap_default &ap2mdm_default>; +}; + +&pcie2_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + + linux,code = <KEY_VOLUMEUP>; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&sdhc_2 { + status = "okay"; + + cd-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>; + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + bus-width = <4>; + no-sdio; + no-emmc; +}; + +&slpi { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <40 4>, <52 4>; + + sdc2_default_state: sdc2-default { + clk { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd { + pins = "sdc2_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + data { + pins = "sdc2_data"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + mdm2ap_default: mdm2ap-default { + pins = "gpio1", "gpio3"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + ts_int_default: ts-int-default { + pins = "gpio39"; + function = "gpio"; + drive-strength = <2>; + bias-disabled; + input-enable; + }; + + ap2mdm_default: ap2mdm-default { + pins = "gpio56", "gpio57"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + sdc2_card_det_n: sd-card-det-n { + pins = "gpio77"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; +}; + +&uart12 { + status = "okay"; +}; + +/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */ +&ufs_mem_hc { status = "disabled"; }; +&ufs_mem_phy { status = "disabled"; }; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l5a_0p88>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l2a_3p1>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l9a_1p2>; + vdda-pll-supply = <&vreg_l18a_0p9>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4c0de12aaba6..4798368b02ef 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -8,6 +8,8 @@ #include <dt-bindings/clock/qcom,gcc-sm8250.h> #include <dt-bindings/clock/qcom,gpucc-sm8250.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/dma/qcom-gpi.h> +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sm8250.h> #include <dt-bindings/mailbox/qcom-ipcc.h> @@ -519,6 +521,26 @@ }; }; + gpi_dma2: dma-controller@800000 { + compatible = "qcom,sm8250-gpi-dma"; + reg = <0 0x00800000 0 0x70000>; + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <10>; + dma-channel-mask = <0x3f>; + iommus = <&apps_smmu 0x76 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -714,6 +736,29 @@ }; }; + gpi_dma0: dma-controller@900000 { + compatible = "qcom,sm8250-gpi-dma"; + reg = <0 0x00900000 0 0x70000>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <15>; + dma-channel-mask = <0x7ff>; + iommus = <&apps_smmu 0x5b6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x009c0000 0x0 0x6000>; @@ -961,6 +1006,26 @@ }; }; + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm8250-gpi-dma"; + reg = <0 0x00a00000 0 0x70000>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <10>; + dma-channel-mask = <0x3f>; + iommus = <&apps_smmu 0x56 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x6000>; @@ -1249,6 +1314,12 @@ phys = <&pcie0_lane>; phy-names = "pciephy"; + perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; + enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + status = "disabled"; }; @@ -1347,6 +1418,12 @@ phys = <&pcie1_lane>; phy-names = "pciephy"; + perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>; + enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + status = "disabled"; }; @@ -1447,6 +1524,12 @@ phys = <&pcie2_lane>; phy-names = "pciephy"; + perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>; + enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_default_state>; + status = "disabled"; }; @@ -1470,7 +1553,7 @@ status = "disabled"; - pcie2_lane: lanes@1c0e200 { + pcie2_lane: lanes@1c16200 { reg = <0 0x1c16200 0 0x170>, /* tx0 */ <0 0x1c16400 0 0x200>, /* rx0 */ <0 0x1c16a00 0 0x1f0>, /* pcs */ @@ -1746,6 +1829,8 @@ qcom,gmu = <&gmu>; + status = "disabled"; + zap-shader { memory-region = <&gpu_mem>; }; @@ -1819,6 +1904,8 @@ operating-points-v2 = <&gmu_opp_table>; + status = "disabled"; + gmu_opp_table: opp-table { compatible = "operating-points-v2"; @@ -2323,6 +2410,8 @@ <&videocc VIDEO_CC_MVS0C_CLK_ARES>; reset-names = "bus", "core"; + status = "disabled"; + video-decoder { compatible = "venus-decoder"; }; @@ -2370,7 +2459,7 @@ }; mdss: mdss@ae00000 { - compatible = "qcom,sdm845-mdss"; + compatible = "qcom,sm8250-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; @@ -2402,7 +2491,7 @@ ranges; mdss_mdp: mdp@ae01000 { - compatible = "qcom,sdm845-dpu"; + compatible = "qcom,sm8250-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x2008>; reg-names = "mdp", "vbif"; @@ -2424,8 +2513,6 @@ interrupt-parent = <&mdss>; interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - ports { #address-cells = <1>; #size-cells = <0>; @@ -2499,6 +2586,9 @@ status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -2566,6 +2656,9 @@ status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -3395,6 +3488,95 @@ output-high; }; }; + + sdc2_sleep_state: sdc2-sleep { + clk { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_default_state: pcie0-default { + perst { + pins = "gpio79"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio80"; + function = "pci_e0"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio81"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default { + perst { + pins = "gpio82"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio83"; + function = "pci_e1"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio84"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie2_default_state: pcie2-default { + perst { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio86"; + function = "pci_e2"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio87"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; apps_smmu: iommu@15000000 { diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index 6ca638b4e321..93740444dd1e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -364,3 +364,9 @@ vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l5b_0p88>; }; + +&ipa { + status = "okay"; + + memory-region = <&pil_ipa_fw_mem>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index ed0b51bc03ea..0d16392bb976 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -6,11 +6,13 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-sm8350.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/interconnect/qcom,sm8350.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/power/qcom-aoss-qmp.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/interconnect/qcom,sm8350.h> / { interrupt-parent = <&intc>; @@ -391,6 +393,17 @@ interrupt-controller; #interrupt-cells = <2>; }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; smp2p-slpi { @@ -629,6 +642,45 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + ipa: ipa@1e40000 { + compatible = "qcom,sm8350-ipa"; + + iommus = <&apps_smmu 0x5c0 0x0>, + <&apps_smmu 0x5c2 0x0>; + reg = <0 0x1e40000 0 0x8000>, + <0 0x1e50000 0 0x4b20>, + <0 0x1e04000 0 0x23000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; + interconnect-names = "ipa_to_llcc", + "llcc_to_ebi1", + "appss_to_ipa"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -656,7 +708,7 @@ <&rpmhpd 12>; power-domain-names = "load_state", "cx", "mss"; - interconnects = <&mc_virt 0 &mc_virt 1>; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; memory-region = <&pil_modem_mem>; @@ -689,7 +741,7 @@ interrupt-controller; }; - tsens0: thermal-sensor@c222000 { + tsens0: thermal-sensor@c263000 { compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x8>; /* SROT */ @@ -700,7 +752,7 @@ #thermal-sensor-cells = <1>; }; - tsens1: thermal-sensor@c223000 { + tsens1: thermal-sensor@c265000 { compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x8>; /* SROT */ @@ -1063,7 +1115,7 @@ <&rpmhpd 10>; power-domain-names = "load_state", "cx", "mxc"; - interconnects = <&compute_noc 1 &mc_virt 1>; + interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; memory-region = <&pil_cdsp_mem>; @@ -1176,7 +1228,7 @@ }; }; - dc_noc: interconnect@90e0000 { + dc_noc: interconnect@90c0000 { compatible = "qcom,sm8350-dc-noc"; reg = <0 0x090c0000 0 0x4200>; #interconnect-cells = <1>; @@ -1317,7 +1369,7 @@ }; }; - thermal-zones { + thermal_zones: thermal-zones { cpu0-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index f2de2fa0c8b8..68e30e26564b 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -62,3 +62,5 @@ dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb + +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index d8046fedf9c1..e3c8b2fe143e 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -271,12 +271,12 @@ &ehci0 { dr_mode = "otg"; status = "okay"; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>; }; &ehci1 { status = "okay"; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>; }; &hdmi0 { diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 8d3a4d6ee885..090dc9c4f57b 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -53,6 +53,8 @@ phy-handle = <&phy0>; rx-internal-delay-ps = <1800>; tx-internal-delay-ps = <2000>; + clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>; + clock-names = "fck", "refclk"; status = "okay"; phy0: ethernet-phy@0 { @@ -319,8 +321,10 @@ status = "okay"; }; -&usb_extal_clk { - clock-frequency = <50000000>; +&usb2_clksel { + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, + <&versaclock5 3>, <&usb3s0_clk>; + status = "okay"; }; &usb3s0_clk { diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 46f8dbf68904..78c121a89f11 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -76,6 +76,7 @@ opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <820000>; clock-latency-ns = <300000>; + opp-suspend; }; }; @@ -1127,6 +1128,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index d16a4be5ef77..28c612ce49c0 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1001,6 +1001,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 1aef34447abd..a5d4dce8476d 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -957,6 +957,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 1f51237ab0a6..379a1300272b 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1230,6 +1230,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 85d66d15465a..2e4c18b8eee4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -1312,6 +1312,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 12476e354d74..2bd8169735d3 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -63,18 +63,19 @@ opp-500000000 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; }; opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; + opp-suspend; }; opp-1600000000 { opp-hz = /bits/ 64 <1600000000>; @@ -1188,6 +1189,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index d9804768425a..91b501e0121e 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -52,18 +52,19 @@ opp-500000000 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; }; opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <820000>; + opp-microvolt = <830000>; clock-latency-ns = <300000>; + opp-suspend; }; opp-1600000000 { opp-hz = /bits/ 64 <1600000000>; @@ -559,10 +560,19 @@ }; intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a77961", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; - /* placeholder */ + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; tmu0: timer@e61e0000 { @@ -1144,6 +1154,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index dcb9df861d74..ad69da362a72 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1050,6 +1050,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index 874a7fc2730b..5c84681703ed 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -73,6 +73,12 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + x1_clk: x1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; }; &avb { @@ -104,6 +110,8 @@ }; &du { + clocks = <&cpg CPG_MOD 724>, <&x1_clk>; + clock-names = "du.0", "dclkin.0"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index 7417cf5fea0f..2426e533128c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -59,7 +59,7 @@ memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; + reg = <0x0 0x48000000 0x0 0x78000000>; }; osc5_clk: osc5-clock { diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index e8f6352c3665..517892cf6294 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -612,6 +612,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts index 04d47c0c9bb9..7bde0a549c09 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -210,7 +210,7 @@ &mmc0 { pinctrl-0 = <&mmc_pins>; - pinctrl-1 = <&mmc_pins_uhs>; + pinctrl-1 = <&mmc_pins>; pinctrl-names = "default", "state_uhs"; vmmc-supply = <&d3_3v>; @@ -255,12 +255,6 @@ mmc_pins: mmc { groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; function = "mmc"; - power-source = <3300>; - }; - - mmc_pins_uhs: mmc_uhs { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; power-source = <1800>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 7b51d464de0e..6347d15e66b6 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -664,6 +664,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 0eaea58f4210..4d0304bc9745 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1000,6 +1000,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 2319271c881b..84dba3719381 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -760,6 +760,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi index 14d3db5d6c16..f791c76f1bcf 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi @@ -6,6 +6,27 @@ */ &i2c0 { + pca9654_a: gpio@21 { + compatible = "onnn,pca9654"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9654_b: gpio@22 { + compatible = "onnn,pca9654"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9654_c: gpio@23 { + compatible = "onnn,pca9654"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + eeprom@52 { compatible = "rohm,br24g01", "atmel,24c01"; label = "csi-dsi-sub-board-id"; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 70b3604e56cd..78ca75f619f6 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -618,6 +618,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 211>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 211>; phy-mode = "rgmii"; @@ -665,6 +666,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 212>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 212>; phy-mode = "rgmii"; @@ -712,6 +714,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 213>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 213>; phy-mode = "rgmii"; @@ -759,6 +762,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 214>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 214>; phy-mode = "rgmii"; @@ -806,6 +810,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 215>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 215>; phy-mode = "rgmii"; @@ -853,6 +858,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 216>; phy-mode = "rgmii"; @@ -1096,7 +1102,6 @@ <0x0 0xf1060000 0 0x110000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; }; fcpvd0: fcp@fea10000 { diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi new file mode 100644 index 000000000000..01482d227506 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r9a07g044-cpg.h> + +/ { + compatible = "renesas,r9a07g044"; + #address-cells = <2>; + #size-cells = <2>; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g044-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g044-sysc"; + reg = <0 0x11020000 0 0x10000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + status = "disabled"; + }; + + gic: interrupt-controller@11900000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x11900000 0 0x40000>, + <0x0 0x11940000 0 0x60000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi new file mode 100644 index 000000000000..9d89d4590358 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L R9A07G044L1 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044.dtsi" + +/ { + compatible = "renesas,r9a07g044l1", "renesas,r9a07g044"; + + cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + }; + + timer { + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts new file mode 100644 index 000000000000..d3f72ec62f03 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L SMARC EVK board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044l2.dtsi" +#include "rzg2l-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g044l2"; + compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi new file mode 100644 index 000000000000..91dc10b2cdbb --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L R9A07G044L2 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044.dtsi" + +/ { + compatible = "renesas,r9a07g044l2", "renesas,r9a07g044"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi new file mode 100644 index 000000000000..adcd4f50519e --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L SMARC EVK common parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + serial0 = &scif0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; + +&scif0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index c3e00c0e2db7..7fdb41de01ec 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -51,3 +51,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 09baa8a167ce..248ebb61aa79 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -244,28 +244,31 @@ #size-cells = <0>; /* These power domains are grouped by VD_LOGIC */ - pd_usb@PX30_PD_USB { + power-domain@PX30_PD_USB { reg = <PX30_PD_USB>; clocks = <&cru HCLK_HOST>, <&cru HCLK_OTG>, <&cru SCLK_OTG_ADP>; pm_qos = <&qos_usb_host>, <&qos_usb_otg>; + #power-domain-cells = <0>; }; - pd_sdcard@PX30_PD_SDCARD { + power-domain@PX30_PD_SDCARD { reg = <PX30_PD_SDCARD>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; pm_qos = <&qos_sdmmc>; + #power-domain-cells = <0>; }; - pd_gmac@PX30_PD_GMAC { + power-domain@PX30_PD_GMAC { reg = <PX30_PD_GMAC>; clocks = <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, <&cru SCLK_MAC_REF>, <&cru SCLK_GMAC_RX_TX>; pm_qos = <&qos_gmac>; + #power-domain-cells = <0>; }; - pd_mmc_nand@PX30_PD_MMC_NAND { + power-domain@PX30_PD_MMC_NAND { reg = <PX30_PD_MMC_NAND>; clocks = <&cru HCLK_NANDC>, <&cru HCLK_EMMC>, @@ -277,15 +280,17 @@ <&cru SCLK_SFC>; pm_qos = <&qos_emmc>, <&qos_nand>, <&qos_sdio>, <&qos_sfc>; + #power-domain-cells = <0>; }; - pd_vpu@PX30_PD_VPU { + power-domain@PX30_PD_VPU { reg = <PX30_PD_VPU>; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; pm_qos = <&qos_vpu>, <&qos_vpu_r128>; + #power-domain-cells = <0>; }; - pd_vo@PX30_PD_VO { + power-domain@PX30_PD_VO { reg = <PX30_PD_VO>; clocks = <&cru ACLK_RGA>, <&cru ACLK_VOPB>, @@ -300,8 +305,9 @@ <&cru SCLK_VOPB_PWM>; pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, <&qos_vop_m0>, <&qos_vop_m1>; + #power-domain-cells = <0>; }; - pd_vi@PX30_PD_VI { + power-domain@PX30_PD_VI { reg = <PX30_PD_VI>; clocks = <&cru ACLK_CIF>, <&cru ACLK_ISP>, @@ -311,11 +317,13 @@ pm_qos = <&qos_isp_128>, <&qos_isp_rd>, <&qos_isp_wr>, <&qos_isp_m1>, <&qos_vip>; + #power-domain-cells = <0>; }; - pd_gpu@PX30_PD_GPU { + power-domain@PX30_PD_GPU { reg = <PX30_PD_GPU>; clocks = <&cru SCLK_GPU>; pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; }; }; }; @@ -814,7 +822,7 @@ #address-cells = <1>; #size-cells = <1>; - u2phy: usb2-phy@100 { + u2phy: usb2phy@100 { compatible = "rockchip,px30-usb2phy"; reg = <0x100 0x20>; clocks = <&pmucru SCLK_USBPHY_REF>; @@ -1087,7 +1095,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff460f00 0x0 0x100>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vopb_mmu"; clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; clock-names = "aclk", "iface"; power-domains = <&power PX30_PD_VO>; @@ -1128,7 +1135,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff470f00 0x0 0x100>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vopl_mmu"; clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; clock-names = "aclk", "iface"; power-domains = <&power PX30_PD_VO>; diff --git a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts index 3dddd4742c3a..665b2e69455d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts @@ -84,8 +84,8 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0 - 3300000 0x1>; + states = <1800000 0x0>, + <3300000 0x1>; vin-supply = <&vcc5v0_sys>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index b815ce73e5c6..a185901aba9a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -164,7 +164,7 @@ grf: grf@ff000000 { compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff000000 0x0 0x10000>; + reg = <0x0 0xff000000 0x0 0x08000>; reboot-mode { compatible = "syscon-reboot-mode"; @@ -177,6 +177,42 @@ }; }; + usb2phy_grf: syscon@ff008000 { + compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff008000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy: usb2phy@100 { + compatible = "rockchip,rk3308-usb2phy"; + reg = <0x100 0x10>; + assigned-clocks = <&cru USB480M>; + assigned-clock-parents = <&u2phy>; + clocks = <&cru SCLK_USBPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy"; + #clock-cells = <0>; + status = "disabled"; + + u2phy_otg: otg-port { + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy_host: host-port { + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + detect_grf: syscon@ff00b000 { compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; reg = <0x0 0xff00b000 0x0 0x1000>; @@ -579,6 +615,42 @@ status = "disabled"; }; + usb20_otg: usb@ff400000 { + compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff400000 0x0 0x40000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host_ehci: usb@ff440000 { + compatible = "generic-ehci"; + reg = <0x0 0xff440000 0x0 0x10000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host_ohci: usb@ff450000 { + compatible = "generic-ohci"; + reg = <0x0 0xff450000 0x0 0x10000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + sdmmc: mmc@ff480000 { compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff480000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts index 49c97f76df77..7fc674a99a6c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts @@ -165,6 +165,31 @@ }; }; + rk817-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Analog"; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Speaker"; + simple-audio-card,routing = + "MICL", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Speaker", "SPKO"; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s1_2ch>; + }; + }; + vccsys: vccsys { compatible = "regulator-fixed"; regulator-name = "vcc3v8_sys"; @@ -239,6 +264,7 @@ backlight = <&backlight>; iovcc-supply = <&vcc_lcd>; reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + rotation = <270>; vdd-supply = <&vcc_lcd>; port { @@ -269,11 +295,14 @@ reg = <0x20>; interrupt-parent = <&gpio0>; interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>; + clock-output-names = "rk808-clkout1", "xin32k"; + clock-names = "mclk"; + clocks = <&cru SCLK_I2S1_OUT>; pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; + pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>; wakeup-source; #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "xin32k"; + #sound-dai-cells = <0>; vcc1-supply = <&vccsys>; vcc2-supply = <&vccsys>; @@ -432,6 +461,10 @@ }; }; }; + + rk817_codec: codec { + rockchip,mic-in-differential; + }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts index f807bc066ccb..3857d487ab84 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts @@ -14,6 +14,7 @@ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; aliases { + ethernet1 = &rtl8153; mmc0 = &sdmmc; }; @@ -76,8 +77,8 @@ regulator-settling-time-us = <5000>; regulator-type = "voltage"; startup-delay-us = <2000>; - states = <1800000 0x1 - 3300000 0x0>; + states = <1800000 0x1>, + <3300000 0x0>; vin-supply = <&vcc_io_33>; }; @@ -101,6 +102,18 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + vdd_5v_lan: vdd-5v-lan { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&lan_vdd_pin>; + pinctrl-names = "default"; + regulator-name = "vdd_5v_lan"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; }; &cpu0 { @@ -309,6 +322,12 @@ }; }; + lan { + lan_vdd_pin: lan-vdd-pin { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; @@ -368,6 +387,19 @@ dr_mode = "host"; }; +&usbdrd3 { + dr_mode = "host"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + /* Second port is for USB 3.0 */ + rtl8153: device@2 { + compatible = "usbbda,8153"; + reg = <2>; + }; +}; + &usb_host0_ehci { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts index a05732b59f38..aa22a0c22265 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -50,8 +50,8 @@ vcc_sdio: sdmmcio-regulator { compatible = "regulator-gpio"; gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 - 3300000 0x0>; + states = <1800000 0x1>, + <3300000 0x0>; regulator-name = "vcc_sdio"; regulator-type = "voltage"; regulator-min-microvolt = <1800000>; @@ -363,6 +363,11 @@ status = "okay"; }; +&usbdrd3 { + dr_mode = "host"; + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts index c7e31efdd2e1..018a3a5075c7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts @@ -177,8 +177,6 @@ }; &gmac2phy { - pinctrl-names = "default"; - pinctrl-0 = <&fephyled_linkm1>, <&fephyled_rxm1>; status = "okay"; }; @@ -382,6 +380,11 @@ status = "okay"; }; +&usbdrd3 { + dr_mode = "host"; + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts index 3bef1f39bc6e..1b0f7e4551ea 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts @@ -381,6 +381,11 @@ status = "okay"; }; +&usbdrd3 { + dr_mode = "host"; + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 3ed69ecbcf3c..8c821acb21ff 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -288,7 +288,7 @@ status = "disabled"; }; - grf_gpio: grf-gpio { + grf_gpio: gpio { compatible = "rockchip,rk3328-grf-gpio"; gpio-controller; #gpio-cells = <2>; @@ -300,15 +300,18 @@ #address-cells = <1>; #size-cells = <0>; - pd_hevc@RK3328_PD_HEVC { + power-domain@RK3328_PD_HEVC { reg = <RK3328_PD_HEVC>; + #power-domain-cells = <0>; }; - pd_video@RK3328_PD_VIDEO { + power-domain@RK3328_PD_VIDEO { reg = <RK3328_PD_VIDEO>; + #power-domain-cells = <0>; }; - pd_vpu@RK3328_PD_VPU { + power-domain@RK3328_PD_VPU { reg = <RK3328_PD_VPU>; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + #power-domain-cells = <0>; }; }; @@ -816,7 +819,7 @@ #address-cells = <1>; #size-cells = <1>; - u2phy: usb2-phy@100 { + u2phy: usb2phy@100 { compatible = "rockchip,rk3328-usb2phy"; reg = <0x100 0x10>; clocks = <&xin24m>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index dfc6376171d0..4c64fbefb483 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -664,6 +664,8 @@ compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; reg = <0x0 0xff810000 0x0 0x20>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; + clock-names = "pclk", "timer"; }; spdif: spdif@ff880000 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts index 45254be1350d..c4dd2a6b4836 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts @@ -6,6 +6,7 @@ /dts-v1/; #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/usb/pd.h> #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -94,6 +95,13 @@ }; }; + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int>; + pinctrl-names = "default"; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -151,6 +159,23 @@ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; }; + sound-dit { + compatible = "audio-graph-card"; + label = "SPDIF"; + dais = <&spdif_p0>; + }; + + spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port { + dit_p0_0: endpoint { + remote-endpoint = <&spdif_p0_0>; + }; + }; + }; + /* switched by pmic_sleep */ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { compatible = "regulator-fixed"; @@ -196,6 +221,17 @@ vin-supply = <&vcc_sys>; }; + vcc5v0_typec: vcc5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vcc5v0_typec"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + vcc_sys: vcc-sys { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -521,6 +557,53 @@ i2c-scl-falling-time-ns = <20>; status = "okay"; + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc5v0_typec>; + status = "okay"; + + connector { + compatible = "usb-c-connector"; + data-role = "host"; + label = "USB-C"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + sink-pdos = + <PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>; + source-pdos = + <PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc_hs: endpoint { + remote-endpoint = + <&u2phy0_typec_hs>; + }; + }; + + port@1 { + reg = <1>; + + usbc_ss: endpoint { + remote-endpoint = + <&tcphy0_typec_ss>; + }; + }; + }; + }; + }; + accelerometer@68 { compatible = "invensense,mpu6500"; reg = <0x68>; @@ -578,12 +661,34 @@ }; }; + fusb302x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + ir { + ir_int: ir-int { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + lcd-panel { lcd_panel_reset: lcd-panel-reset { rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + leds { + work_led_pin: work-led-pin { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_pin: diy-led-pin { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie { pcie_pwr_en: pcie-pwr-en { rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; @@ -595,6 +700,10 @@ }; pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vsel1_pin: vsel1-pin { rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; }; @@ -604,21 +713,21 @@ }; }; - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - rt5640 { rt5640_hpcon: rt5640-hpcon { rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0_typec_en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; }; }; @@ -633,16 +742,6 @@ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - - leds { - work_led_pin: work-led-pin { - rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - diy_led_pin: diy-led-pin { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; }; &pwm0 { @@ -710,10 +809,29 @@ status = "okay"; }; +&spdif { + pinctrl-0 = <&spdif_bus_1>; + status = "okay"; + + spdif_p0: port { + spdif_p0_0: endpoint { + remote-endpoint = <&dit_p0_0>; + }; + }; +}; + &tcphy0 { status = "okay"; }; +&tcphy0_usb3 { + port { + tcphy0_typec_ss: endpoint { + remote-endpoint = <&usbc_ss>; + }; + }; +}; + &tcphy1 { status = "okay"; }; @@ -737,6 +855,12 @@ phy-supply = <&vcc5v0_host>; status = "okay"; }; + + port { + u2phy0_typec_hs: endpoint { + remote-endpoint = <&usbc_hs>; + }; + }; }; &u2phy1 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi index beee5fbb3443..5d7a9d96d163 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -245,7 +245,7 @@ pp1800_pcie: &pp1800_s0 { }; &ppvar_sd_card_io { - states = <1800000 0x0 3300000 0x1>; + states = <1800000 0x0>, <3300000 0x1>; regulator-max-microvolt = <3300000>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 4002742fed4c..c1bcc8ca3769 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -252,8 +252,8 @@ enable-active-high; enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 - 3000000 0x0>; + states = <1800000 0x1>, + <3000000 0x0>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts index 19485b552bc4..738cfd21df3e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts @@ -23,6 +23,16 @@ mmc1 = &sdhci; }; + avdd_0v9_s0: avdd-0v9-s0 { + compatible = "regulator-fixed"; + regulator-name = "avdd_0v9_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc1v8_sys_s3>; + }; + avdd_1v8_s0: avdd-1v8-s0 { compatible = "regulator-fixed"; regulator-name = "avdd_1v8_s0"; @@ -40,6 +50,20 @@ #clock-cells = <0>; }; + fan1 { + /* fan connected to P7 */ + compatible = "pwm-fan"; + pwms = <&pwm0 0 40000 0>; + cooling-levels = <0 80 170 255>; + }; + + fan2 { + /* fan connected to P6 */ + compatible = "pwm-fan"; + pwms = <&pwm1 0 40000 0>; + cooling-levels = <0 80 170 255>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -58,6 +82,18 @@ }; }; + pcie_power: pcie-power { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie_pwr>; + pinctrl-names = "default"; + regulator-boot-on; + regulator-name = "pcie_power"; + startup-delay-us = <10000>; + vin-supply = <&vcc5v0_perdev>; + }; + vcc1v8_sys_s0: vcc1v8-sys-s0 { compatible = "regulator-fixed"; regulator-name = "vcc1v8_sys_s0"; @@ -95,6 +131,16 @@ }; }; + vcc5v0_perdev: vcc5v0-perdev { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_perdev"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin_bkup>; + }; + vcc5v0_sys: vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -109,6 +155,20 @@ }; }; + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_en>; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_perdev>; + }; + vcc12v_dcin: vcc12v-dcin { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -317,6 +377,20 @@ status = "okay"; }; +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + num-lanes = <2>; + status = "okay"; + + vpcie12v-supply = <&vcc12v_dcin>; + vpcie3v3-supply = <&pcie_power>; + vpcie1v8-supply = <&avdd_1v8_s0>; + vpcie0v9-supply = <&avdd_0v9_s0>; +}; + &pinctrl { gmac { gphy_reset: gphy-reset { @@ -334,12 +408,25 @@ }; }; + pcie { + pcie_pwr: pcie-pwr { + rockchip,pins = + <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + power { + vcc5v0_usb_en: vcc5v0-usb-en { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + vcc3v0-sd { sdmmc0_pwr_h: sdmmc0-pwr-h { rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; @@ -352,6 +439,16 @@ status = "okay"; }; +&pwm0 { + /* pwm-fan on P7 */ + status = "okay"; +}; + +&pwm1 { + /* pwm-fan on P6 */ + status = "okay"; +}; + &sdhci { bus-width = <8>; mmc-hs200-1_8v; @@ -372,6 +469,30 @@ status = "okay"; }; +&tcphy1 { + /* phy for &usbdrd_dwc3_1 */ + status = "okay"; +}; + +&u2phy1 { + status = "okay"; + + otg-port { + /* phy for &usbdrd_dwc3_1 */ + phy-supply = <&vcc5v0_usb>; + status = "okay"; + }; +}; + &uart2 { status = "okay"; }; + +&usbdrd3_1 { + status = "okay"; + + usb@fe900000 { + dr_mode = "host"; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts index fa5809887643..cef4d18b599d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts @@ -33,7 +33,7 @@ sys_led: led-sys { gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - label = "red:sys"; + label = "red:power"; default-state = "on"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi index 16fd58c4a80f..8c0ff6c96e03 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -510,7 +510,6 @@ }; &pcie0 { - max-link-speed = <2>; num-lanes = <2>; vpcie0v9-supply = <&vcca0v9_s3>; vpcie1v8-supply = <&vcca1v8_s3>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi index c172f5a803e7..d1aaf8e83391 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi @@ -63,6 +63,13 @@ }; }; + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -389,6 +396,7 @@ vcc_sdio: LDO_REG4 { regulator-name = "vcc_sdio"; + regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; @@ -493,6 +501,8 @@ regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; vin-supply = <&vcc3v3_sys>; regulator-state-mem { @@ -601,6 +611,12 @@ }; }; + ir { + ir_int: ir-int { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + lcd-panel { lcd_panel_reset: lcd-panel-reset { rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 7d0a7c697703..b28888ea9262 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -474,7 +474,6 @@ &pcie0 { ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; - max-link-speed = <2>; num-lanes = <4>; pinctrl-0 = <&pcie_clkreqnb_cpm>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 634a91af8e83..3871c7fd83b0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -227,7 +227,7 @@ <&pcie_phy 2>, <&pcie_phy 3>; phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3"; - ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>, + ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>, <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, @@ -968,126 +968,146 @@ #size-cells = <0>; /* These power domains are grouped by VD_CENTER */ - pd_iep@RK3399_PD_IEP { + power-domain@RK3399_PD_IEP { reg = <RK3399_PD_IEP>; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; pm_qos = <&qos_iep>; + #power-domain-cells = <0>; }; - pd_rga@RK3399_PD_RGA { + power-domain@RK3399_PD_RGA { reg = <RK3399_PD_RGA>; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; pm_qos = <&qos_rga_r>, <&qos_rga_w>; + #power-domain-cells = <0>; }; - pd_vcodec@RK3399_PD_VCODEC { + power-domain@RK3399_PD_VCODEC { reg = <RK3399_PD_VCODEC>; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; pm_qos = <&qos_video_m0>; + #power-domain-cells = <0>; }; - pd_vdu@RK3399_PD_VDU { + power-domain@RK3399_PD_VDU { reg = <RK3399_PD_VDU>; clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; pm_qos = <&qos_video_m1_r>, <&qos_video_m1_w>; + #power-domain-cells = <0>; }; /* These power domains are grouped by VD_GPU */ - pd_gpu@RK3399_PD_GPU { + power-domain@RK3399_PD_GPU { reg = <RK3399_PD_GPU>; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; }; /* These power domains are grouped by VD_LOGIC */ - pd_edp@RK3399_PD_EDP { + power-domain@RK3399_PD_EDP { reg = <RK3399_PD_EDP>; clocks = <&cru PCLK_EDP_CTRL>; + #power-domain-cells = <0>; }; - pd_emmc@RK3399_PD_EMMC { + power-domain@RK3399_PD_EMMC { reg = <RK3399_PD_EMMC>; clocks = <&cru ACLK_EMMC>; pm_qos = <&qos_emmc>; + #power-domain-cells = <0>; }; - pd_gmac@RK3399_PD_GMAC { + power-domain@RK3399_PD_GMAC { reg = <RK3399_PD_GMAC>; clocks = <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; pm_qos = <&qos_gmac>; + #power-domain-cells = <0>; }; - pd_sd@RK3399_PD_SD { + power-domain@RK3399_PD_SD { reg = <RK3399_PD_SD>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; pm_qos = <&qos_sd>; + #power-domain-cells = <0>; }; - pd_sdioaudio@RK3399_PD_SDIOAUDIO { + power-domain@RK3399_PD_SDIOAUDIO { reg = <RK3399_PD_SDIOAUDIO>; clocks = <&cru HCLK_SDIO>; pm_qos = <&qos_sdioaudio>; + #power-domain-cells = <0>; }; - pd_tcpc0@RK3399_PD_TCPD0 { + power-domain@RK3399_PD_TCPD0 { reg = <RK3399_PD_TCPD0>; clocks = <&cru SCLK_UPHY0_TCPDCORE>, <&cru SCLK_UPHY0_TCPDPHY_REF>; + #power-domain-cells = <0>; }; - pd_tcpc1@RK3399_PD_TCPD1 { + power-domain@RK3399_PD_TCPD1 { reg = <RK3399_PD_TCPD1>; clocks = <&cru SCLK_UPHY1_TCPDCORE>, <&cru SCLK_UPHY1_TCPDPHY_REF>; + #power-domain-cells = <0>; }; - pd_usb3@RK3399_PD_USB3 { + power-domain@RK3399_PD_USB3 { reg = <RK3399_PD_USB3>; clocks = <&cru ACLK_USB3>; pm_qos = <&qos_usb_otg0>, <&qos_usb_otg1>; + #power-domain-cells = <0>; }; - pd_vio@RK3399_PD_VIO { + power-domain@RK3399_PD_VIO { reg = <RK3399_PD_VIO>; + #power-domain-cells = <1>; #address-cells = <1>; #size-cells = <0>; - pd_hdcp@RK3399_PD_HDCP { + power-domain@RK3399_PD_HDCP { reg = <RK3399_PD_HDCP>; clocks = <&cru ACLK_HDCP>, <&cru HCLK_HDCP>, <&cru PCLK_HDCP>; pm_qos = <&qos_hdcp>; + #power-domain-cells = <0>; }; - pd_isp0@RK3399_PD_ISP0 { + power-domain@RK3399_PD_ISP0 { reg = <RK3399_PD_ISP0>; clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>; pm_qos = <&qos_isp0_m0>, <&qos_isp0_m1>; + #power-domain-cells = <0>; }; - pd_isp1@RK3399_PD_ISP1 { + power-domain@RK3399_PD_ISP1 { reg = <RK3399_PD_ISP1>; clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; pm_qos = <&qos_isp1_m0>, <&qos_isp1_m1>; + #power-domain-cells = <0>; }; - pd_vo@RK3399_PD_VO { + power-domain@RK3399_PD_VO { reg = <RK3399_PD_VO>; + #power-domain-cells = <1>; #address-cells = <1>; #size-cells = <0>; - pd_vopb@RK3399_PD_VOPB { + power-domain@RK3399_PD_VOPB { reg = <RK3399_PD_VOPB>; clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; pm_qos = <&qos_vop_big_r>, <&qos_vop_big_w>; + #power-domain-cells = <0>; }; - pd_vopl@RK3399_PD_VOPL { + power-domain@RK3399_PD_VOPL { reg = <RK3399_PD_VOPL>; clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; pm_qos = <&qos_vop_little>; + #power-domain-cells = <0>; }; }; }; @@ -1398,7 +1418,7 @@ status = "disabled"; }; - u2phy0: usb2-phy@e450 { + u2phy0: usb2phy@e450 { compatible = "rockchip,rk3399-usb2phy"; reg = <0xe450 0x10>; clocks = <&cru SCLK_USB2PHY0_REF>; @@ -1425,7 +1445,7 @@ }; }; - u2phy1: usb2-phy@e460 { + u2phy1: usb2phy@e460 { compatible = "rockchip,rk3399-usb2phy"; reg = <0xe460 0x10>; clocks = <&cru SCLK_USB2PHY1_REF>; @@ -2354,7 +2374,7 @@ }; }; - sleep { + suspend { ap_pwroff: ap-pwroff { rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi index c0074b3ed4af..01d1a75c8b4d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi @@ -329,7 +329,6 @@ &pcie0 { ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - max-link-speed = <2>; num-lanes = <4>; pinctrl-0 = <&pcie_clkreqnb_cpm>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts new file mode 100644 index 000000000000..69786557093d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3568.dtsi" + +/ { + model = "Rockchip RK3568 EVB1 DDR4 V10 Board"; + compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568"; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd1_n: vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi new file mode 100644 index 000000000000..a588ca95ace2 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi @@ -0,0 +1,3111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/pinctrl/rockchip.h> +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + acodec { + /omit-if-no-ref/ + acodec_pins: acodec-pins { + rockchip,pins = + /* acodec_adc_sync */ + <1 RK_PB1 5 &pcfg_pull_none>, + /* acodec_adcclk */ + <1 RK_PA1 5 &pcfg_pull_none>, + /* acodec_adcdata */ + <1 RK_PA0 5 &pcfg_pull_none>, + /* acodec_dac_datal */ + <1 RK_PA7 5 &pcfg_pull_none>, + /* acodec_dac_datar */ + <1 RK_PB0 5 &pcfg_pull_none>, + /* acodec_dacclk */ + <1 RK_PA3 5 &pcfg_pull_none>, + /* acodec_dacsync */ + <1 RK_PA5 5 &pcfg_pull_none>; + }; + }; + + audiopwm { + /omit-if-no-ref/ + audiopwm_lout: audiopwm-lout { + rockchip,pins = + /* audiopwm_lout */ + <1 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_loutn: audiopwm-loutn { + rockchip,pins = + /* audiopwm_loutn */ + <1 RK_PA1 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_loutp: audiopwm-loutp { + rockchip,pins = + /* audiopwm_loutp */ + <1 RK_PA0 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_rout: audiopwm-rout { + rockchip,pins = + /* audiopwm_rout */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_routn: audiopwm-routn { + rockchip,pins = + /* audiopwm_routn */ + <1 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_routp: audiopwm-routp { + rockchip,pins = + /* audiopwm_routp */ + <1 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + bt656 { + /omit-if-no-ref/ + bt656m0_pins: bt656m0-pins { + rockchip,pins = + /* bt656_clkm0 */ + <3 RK_PA0 2 &pcfg_pull_none>, + /* bt656_d0m0 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* bt656_d1m0 */ + <2 RK_PD1 2 &pcfg_pull_none>, + /* bt656_d2m0 */ + <2 RK_PD2 2 &pcfg_pull_none>, + /* bt656_d3m0 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* bt656_d4m0 */ + <2 RK_PD4 2 &pcfg_pull_none>, + /* bt656_d5m0 */ + <2 RK_PD5 2 &pcfg_pull_none>, + /* bt656_d6m0 */ + <2 RK_PD6 2 &pcfg_pull_none>, + /* bt656_d7m0 */ + <2 RK_PD7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + bt656m1_pins: bt656m1-pins { + rockchip,pins = + /* bt656_clkm1 */ + <4 RK_PB4 5 &pcfg_pull_none>, + /* bt656_d0m1 */ + <3 RK_PC6 5 &pcfg_pull_none>, + /* bt656_d1m1 */ + <3 RK_PC7 5 &pcfg_pull_none>, + /* bt656_d2m1 */ + <3 RK_PD0 5 &pcfg_pull_none>, + /* bt656_d3m1 */ + <3 RK_PD1 5 &pcfg_pull_none>, + /* bt656_d4m1 */ + <3 RK_PD2 5 &pcfg_pull_none>, + /* bt656_d5m1 */ + <3 RK_PD3 5 &pcfg_pull_none>, + /* bt656_d6m1 */ + <3 RK_PD4 5 &pcfg_pull_none>, + /* bt656_d7m1 */ + <3 RK_PD5 5 &pcfg_pull_none>; + }; + }; + + bt1120 { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins = + /* bt1120_clk */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* bt1120_d0 */ + <3 RK_PA1 2 &pcfg_pull_none>, + /* bt1120_d1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* bt1120_d2 */ + <3 RK_PA3 2 &pcfg_pull_none>, + /* bt1120_d3 */ + <3 RK_PA4 2 &pcfg_pull_none>, + /* bt1120_d4 */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* bt1120_d5 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* bt1120_d6 */ + <3 RK_PB0 2 &pcfg_pull_none>, + /* bt1120_d7 */ + <3 RK_PB1 2 &pcfg_pull_none>, + /* bt1120_d8 */ + <3 RK_PB2 2 &pcfg_pull_none>, + /* bt1120_d9 */ + <3 RK_PB3 2 &pcfg_pull_none>, + /* bt1120_d10 */ + <3 RK_PB4 2 &pcfg_pull_none>, + /* bt1120_d11 */ + <3 RK_PB5 2 &pcfg_pull_none>, + /* bt1120_d12 */ + <3 RK_PB6 2 &pcfg_pull_none>, + /* bt1120_d13 */ + <3 RK_PC1 2 &pcfg_pull_none>, + /* bt1120_d14 */ + <3 RK_PC2 2 &pcfg_pull_none>, + /* bt1120_d15 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + cam { + /omit-if-no-ref/ + cam_clkout0: cam-clkout0 { + rockchip,pins = + /* cam_clkout0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cam_clkout1: cam-clkout1 { + rockchip,pins = + /* cam_clkout1 */ + <4 RK_PB0 1 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins = + /* can0_rxm0 */ + <0 RK_PB4 2 &pcfg_pull_none>, + /* can0_txm0 */ + <0 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins = + /* can0_rxm1 */ + <2 RK_PA2 4 &pcfg_pull_none>, + /* can0_txm1 */ + <2 RK_PA1 4 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins = + /* can1_rxm0 */ + <1 RK_PA0 3 &pcfg_pull_none>, + /* can1_txm0 */ + <1 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins = + /* can1_rxm1 */ + <4 RK_PC2 3 &pcfg_pull_none>, + /* can1_txm1 */ + <4 RK_PC3 3 &pcfg_pull_none>; + }; + }; + + can2 { + /omit-if-no-ref/ + can2m0_pins: can2m0-pins { + rockchip,pins = + /* can2_rxm0 */ + <4 RK_PB4 3 &pcfg_pull_none>, + /* can2_txm0 */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can2m1_pins: can2m1-pins { + rockchip,pins = + /* can2_rxm1 */ + <2 RK_PB1 4 &pcfg_pull_none>, + /* can2_txm1 */ + <2 RK_PB2 4 &pcfg_pull_none>; + }; + }; + + cif { + /omit-if-no-ref/ + cif_clk: cif-clk { + rockchip,pins = + /* cif_clkout */ + <4 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_clk: cif-dvp-clk { + rockchip,pins = + /* cif_clkin */ + <4 RK_PC1 1 &pcfg_pull_none>, + /* cif_href */ + <4 RK_PB6 1 &pcfg_pull_none>, + /* cif_vsync */ + <4 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus16: cif-dvp-bus16 { + rockchip,pins = + /* cif_d8 */ + <3 RK_PD6 1 &pcfg_pull_none>, + /* cif_d9 */ + <3 RK_PD7 1 &pcfg_pull_none>, + /* cif_d10 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* cif_d11 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* cif_d12 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* cif_d13 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* cif_d14 */ + <4 RK_PA4 1 &pcfg_pull_none>, + /* cif_d15 */ + <4 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus8: cif-dvp-bus8 { + rockchip,pins = + /* cif_d0 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* cif_d1 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* cif_d2 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* cif_d3 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* cif_d4 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* cif_d5 */ + <3 RK_PD3 1 &pcfg_pull_none>, + /* cif_d6 */ + <3 RK_PD4 1 &pcfg_pull_none>, + /* cif_d7 */ + <3 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + clk32k { + /omit-if-no-ref/ + clk32k_in: clk32k-in { + rockchip,pins = + /* clk32k_in */ + <0 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out0: clk32k-out0 { + rockchip,pins = + /* clk32k_out0 */ + <0 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out1: clk32k-out1 { + rockchip,pins = + /* clk32k_out1 */ + <2 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins = + /* cpu_avs */ + <0 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + ebc { + /omit-if-no-ref/ + ebc_extern: ebc-extern { + rockchip,pins = + /* ebc_sdce1 */ + <4 RK_PA7 2 &pcfg_pull_none>, + /* ebc_sdce2 */ + <4 RK_PB0 2 &pcfg_pull_none>, + /* ebc_sdce3 */ + <4 RK_PB1 2 &pcfg_pull_none>, + /* ebc_sdshr */ + <4 RK_PB5 2 &pcfg_pull_none>, + /* ebc_vcom */ + <4 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + ebc_pins: ebc-pins { + rockchip,pins = + /* ebc_gdclk */ + <4 RK_PC0 2 &pcfg_pull_none>, + /* ebc_gdoe */ + <4 RK_PB3 2 &pcfg_pull_none>, + /* ebc_gdsp */ + <4 RK_PB4 2 &pcfg_pull_none>, + /* ebc_sdce0 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* ebc_sdclk */ + <4 RK_PC1 2 &pcfg_pull_none>, + /* ebc_sddo0 */ + <3 RK_PC6 2 &pcfg_pull_none>, + /* ebc_sddo1 */ + <3 RK_PC7 2 &pcfg_pull_none>, + /* ebc_sddo2 */ + <3 RK_PD0 2 &pcfg_pull_none>, + /* ebc_sddo3 */ + <3 RK_PD1 2 &pcfg_pull_none>, + /* ebc_sddo4 */ + <3 RK_PD2 2 &pcfg_pull_none>, + /* ebc_sddo5 */ + <3 RK_PD3 2 &pcfg_pull_none>, + /* ebc_sddo6 */ + <3 RK_PD4 2 &pcfg_pull_none>, + /* ebc_sddo7 */ + <3 RK_PD5 2 &pcfg_pull_none>, + /* ebc_sddo8 */ + <3 RK_PD6 2 &pcfg_pull_none>, + /* ebc_sddo9 */ + <3 RK_PD7 2 &pcfg_pull_none>, + /* ebc_sddo10 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* ebc_sddo11 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* ebc_sddo12 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* ebc_sddo13 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* ebc_sddo14 */ + <4 RK_PA4 2 &pcfg_pull_none>, + /* ebc_sddo15 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* ebc_sdle */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* ebc_sdoe */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + edpdp { + /omit-if-no-ref/ + edpdpm0_pins: edpdpm0-pins { + rockchip,pins = + /* edpdp_hpdinm0 */ + <4 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + edpdpm1_pins: edpdpm1-pins { + rockchip,pins = + /* edpdp_hpdinm1 */ + <0 RK_PC2 2 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clkout */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_datastrobe: emmc-datastrobe { + rockchip,pins = + /* emmc_datastrobe */ + <1 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + eth0 { + /omit-if-no-ref/ + eth0_pins: eth0-pins { + rockchip,pins = + /* eth0_refclko25m */ + <2 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + eth1 { + /omit-if-no-ref/ + eth1m0_pins: eth1m0-pins { + rockchip,pins = + /* eth1_refclko25mm0 */ + <3 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + eth1m1_pins: eth1m1-pins { + rockchip,pins = + /* eth1_refclko25mm1 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + flash { + /omit-if-no-ref/ + flash_pins: flash-pins { + rockchip,pins = + /* flash_ale */ + <1 RK_PD0 2 &pcfg_pull_none>, + /* flash_cle */ + <1 RK_PC6 3 &pcfg_pull_none>, + /* flash_cs0n */ + <1 RK_PD3 2 &pcfg_pull_none>, + /* flash_cs1n */ + <1 RK_PD4 2 &pcfg_pull_none>, + /* flash_d0 */ + <1 RK_PB4 2 &pcfg_pull_none>, + /* flash_d1 */ + <1 RK_PB5 2 &pcfg_pull_none>, + /* flash_d2 */ + <1 RK_PB6 2 &pcfg_pull_none>, + /* flash_d3 */ + <1 RK_PB7 2 &pcfg_pull_none>, + /* flash_d4 */ + <1 RK_PC0 2 &pcfg_pull_none>, + /* flash_d5 */ + <1 RK_PC1 2 &pcfg_pull_none>, + /* flash_d6 */ + <1 RK_PC2 2 &pcfg_pull_none>, + /* flash_d7 */ + <1 RK_PC3 2 &pcfg_pull_none>, + /* flash_dqs */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* flash_rdn */ + <1 RK_PD2 2 &pcfg_pull_none>, + /* flash_rdy */ + <1 RK_PD1 2 &pcfg_pull_none>, + /* flash_volsel */ + <0 RK_PA7 1 &pcfg_pull_none>, + /* flash_wpn */ + <1 RK_PC7 3 &pcfg_pull_none>, + /* flash_wrn */ + <1 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PC7 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PD4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_cs1: fspi-cs1 { + rockchip,pins = + /* fspi_cs1n */ + <1 RK_PC6 2 &pcfg_pull_up>; + }; + }; + + gmac0 { + /omit-if-no-ref/ + gmac0_miim: gmac0-miim { + rockchip,pins = + /* gmac0_mdc */ + <2 RK_PC3 2 &pcfg_pull_none>, + /* gmac0_mdio */ + <2 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_clkinout: gmac0-clkinout { + rockchip,pins = + /* gmac0_mclkinout */ + <2 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_er: gmac0-rx-er { + rockchip,pins = + /* gmac0_rxer */ + <2 RK_PC5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_bus2: gmac0-rx-bus2 { + rockchip,pins = + /* gmac0_rxd0 */ + <2 RK_PB6 1 &pcfg_pull_none>, + /* gmac0_rxd1 */ + <2 RK_PB7 2 &pcfg_pull_none>, + /* gmac0_rxdvcrs */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_tx_bus2: gmac0-tx-bus2 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>, + /* gmac0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>, + /* gmac0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_clk: gmac0-rgmii-clk { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB0 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus: gmac0-rgmii-bus { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PA6 2 &pcfg_pull_none_drv_level_2>, + /* gmac0_txd3 */ + <2 RK_PA7 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + gmac1 { + /omit-if-no-ref/ + gmac1m0_miim: gmac1m0-miim { + rockchip,pins = + /* gmac1_mdcm0 */ + <3 RK_PC4 3 &pcfg_pull_none>, + /* gmac1_mdiom0 */ + <3 RK_PC5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_clkinout: gmac1m0-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm0 */ + <3 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rx_er: gmac1m0-rx-er { + rockchip,pins = + /* gmac1_rxerm0 */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rx_bus2: gmac1m0-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m0 */ + <3 RK_PB1 3 &pcfg_pull_none>, + /* gmac1_rxd1m0 */ + <3 RK_PB2 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm0 */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_tx_bus2: gmac1m0-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_clk: gmac1m0-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_bus: gmac1m0-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m1_miim: gmac1m1-miim { + rockchip,pins = + /* gmac1_mdcm1 */ + <4 RK_PB6 3 &pcfg_pull_none>, + /* gmac1_mdiom1 */ + <4 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_clkinout: gmac1m1-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm1 */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rx_er: gmac1m1-rx-er { + rockchip,pins = + /* gmac1_rxerm1 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rx_bus2: gmac1m1-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m1 */ + <4 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_rxd1m1 */ + <4 RK_PB0 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm1 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_tx_bus2: gmac1m1-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_clk: gmac1m1-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm1 */ + <4 RK_PA3 3 &pcfg_pull_none>, + /* gmac1_txclkm1 */ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_bus: gmac1m1-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m1 */ + <4 RK_PA1 3 &pcfg_pull_none>, + /* gmac1_rxd3m1 */ + <4 RK_PA2 3 &pcfg_pull_none>, + /* gmac1_txd2m1 */ + <3 RK_PD6 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd3m1 */ + <3 RK_PD7 3 &pcfg_pull_none_drv_level_2>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <0 RK_PC0 2 &pcfg_pull_none>, + /* gpu_pwren */ + <0 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + hdmitx { + /omit-if-no-ref/ + hdmitxm0_cec: hdmitxm0-cec { + rockchip,pins = + /* hdmitxm0_cec */ + <4 RK_PD1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitxm1_cec: hdmitxm1-cec { + rockchip,pins = + /* hdmitxm1_cec */ + <0 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitx_scl: hdmitx-scl { + rockchip,pins = + /* hdmitx_scl */ + <4 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitx_sda: hdmitx-sda { + rockchip,pins = + /* hdmitx_sda */ + <4 RK_PD0 1 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB1 1 &pcfg_pull_none_smt>, + /* i2c0_sda */ + <0 RK_PB2 1 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1_xfer: i2c1-xfer { + rockchip,pins = + /* i2c1_scl */ + <0 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c1_sda */ + <0 RK_PB4 1 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_sclm0 */ + <0 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sdam0 */ + <0 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_sclm1 */ + <4 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sdam1 */ + <4 RK_PB4 1 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_sclm0 */ + <1 RK_PA1 1 &pcfg_pull_none_smt>, + /* i2c3_sdam0 */ + <1 RK_PA0 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_sclm1 */ + <3 RK_PB5 4 &pcfg_pull_none_smt>, + /* i2c3_sdam1 */ + <3 RK_PB6 4 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_sclm0 */ + <4 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c4_sdam0 */ + <4 RK_PB2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_sclm1 */ + <2 RK_PB2 2 &pcfg_pull_none_smt>, + /* i2c4_sdam1 */ + <2 RK_PB1 2 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_sclm0 */ + <3 RK_PB3 4 &pcfg_pull_none_smt>, + /* i2c5_sdam0 */ + <3 RK_PB4 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_sclm1 */ + <4 RK_PC7 2 &pcfg_pull_none_smt>, + /* i2c5_sdam1 */ + <4 RK_PD0 2 &pcfg_pull_none_smt>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrckrx: i2s1m0-lrckrx { + rockchip,pins = + /* i2s1m0_lrckrx */ + <1 RK_PA6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_lrcktx: i2s1m0-lrcktx { + rockchip,pins = + /* i2s1m0_lrcktx */ + <1 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1m0_mclk */ + <1 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sclkrx: i2s1m0-sclkrx { + rockchip,pins = + /* i2s1m0_sclkrx */ + <1 RK_PA4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sclktx: i2s1m0-sclktx { + rockchip,pins = + /* i2s1m0_sclktx */ + <1 RK_PA3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1m0_sdi0 */ + <1 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1m0_sdi1 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1m0_sdi2 */ + <1 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1m0_sdi3 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1m0_sdo0 */ + <1 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins = + /* i2s1m0_sdo1 */ + <1 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins = + /* i2s1m0_sdo2 */ + <1 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins = + /* i2s1m0_sdo3 */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrckrx: i2s1m1-lrckrx { + rockchip,pins = + /* i2s1m1_lrckrx */ + <4 RK_PA7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrcktx: i2s1m1-lrcktx { + rockchip,pins = + /* i2s1m1_lrcktx */ + <3 RK_PD0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins = + /* i2s1m1_mclk */ + <3 RK_PC6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sclkrx: i2s1m1-sclkrx { + rockchip,pins = + /* i2s1m1_sclkrx */ + <4 RK_PA6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sclktx: i2s1m1-sclktx { + rockchip,pins = + /* i2s1m1_sclktx */ + <3 RK_PC7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins = + /* i2s1m1_sdi0 */ + <3 RK_PD2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins = + /* i2s1m1_sdi1 */ + <3 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins = + /* i2s1m1_sdi2 */ + <3 RK_PD4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins = + /* i2s1m1_sdi3 */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins = + /* i2s1m1_sdo0 */ + <3 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins = + /* i2s1m1_sdo1 */ + <4 RK_PB0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins = + /* i2s1m1_sdo2 */ + <4 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins = + /* i2s1m1_sdo3 */ + <4 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_lrckrx: i2s1m2-lrckrx { + rockchip,pins = + /* i2s1m2_lrckrx */ + <3 RK_PC5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_lrcktx: i2s1m2-lrcktx { + rockchip,pins = + /* i2s1m2_lrcktx */ + <2 RK_PD2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_mclk: i2s1m2-mclk { + rockchip,pins = + /* i2s1m2_mclk */ + <2 RK_PD0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sclkrx: i2s1m2-sclkrx { + rockchip,pins = + /* i2s1m2_sclkrx */ + <3 RK_PC3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sclktx: i2s1m2-sclktx { + rockchip,pins = + /* i2s1m2_sclktx */ + <2 RK_PD1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi0: i2s1m2-sdi0 { + rockchip,pins = + /* i2s1m2_sdi0 */ + <2 RK_PD3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi1: i2s1m2-sdi1 { + rockchip,pins = + /* i2s1m2_sdi1 */ + <2 RK_PD4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi2: i2s1m2-sdi2 { + rockchip,pins = + /* i2s1m2_sdi2 */ + <2 RK_PD5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi3: i2s1m2-sdi3 { + rockchip,pins = + /* i2s1m2_sdi3 */ + <2 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo0: i2s1m2-sdo0 { + rockchip,pins = + /* i2s1m2_sdo0 */ + <2 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo1: i2s1m2-sdo1 { + rockchip,pins = + /* i2s1m2_sdo1 */ + <3 RK_PA0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo2: i2s1m2-sdo2 { + rockchip,pins = + /* i2s1m2_sdo2 */ + <3 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo3: i2s1m2-sdo3 { + rockchip,pins = + /* i2s1m2_sdo3 */ + <3 RK_PC2 5 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_lrckrx: i2s2m0-lrckrx { + rockchip,pins = + /* i2s2m0_lrckrx */ + <2 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_lrcktx: i2s2m0-lrcktx { + rockchip,pins = + /* i2s2m0_lrcktx */ + <2 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2m0_mclk */ + <2 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclkrx: i2s2m0-sclkrx { + rockchip,pins = + /* i2s2m0_sclkrx */ + <2 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclktx: i2s2m0-sclktx { + rockchip,pins = + /* i2s2m0_sclktx */ + <2 RK_PC2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2m0_sdi */ + <2 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2m0_sdo */ + <2 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrckrx: i2s2m1-lrckrx { + rockchip,pins = + /* i2s2m1_lrckrx */ + <4 RK_PA5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrcktx: i2s2m1-lrcktx { + rockchip,pins = + /* i2s2m1_lrcktx */ + <4 RK_PA4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + /* i2s2m1_mclk */ + <4 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sclkrx: i2s2m1-sclkrx { + rockchip,pins = + /* i2s2m1_sclkrx */ + <4 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sclktx: i2s2m1-sclktx { + rockchip,pins = + /* i2s2m1_sclktx */ + <4 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + /* i2s2m1_sdi */ + <4 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + /* i2s2m1_sdo */ + <4 RK_PB3 5 &pcfg_pull_none>; + }; + }; + + i2s3 { + /omit-if-no-ref/ + i2s3m0_lrck: i2s3m0-lrck { + rockchip,pins = + /* i2s3m0_lrck */ + <3 RK_PA4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_mclk: i2s3m0-mclk { + rockchip,pins = + /* i2s3m0_mclk */ + <3 RK_PA2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sclk: i2s3m0-sclk { + rockchip,pins = + /* i2s3m0_sclk */ + <3 RK_PA3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sdi: i2s3m0-sdi { + rockchip,pins = + /* i2s3m0_sdi */ + <3 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sdo: i2s3m0-sdo { + rockchip,pins = + /* i2s3m0_sdo */ + <3 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_lrck: i2s3m1-lrck { + rockchip,pins = + /* i2s3m1_lrck */ + <4 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_mclk: i2s3m1-mclk { + rockchip,pins = + /* i2s3m1_mclk */ + <4 RK_PC2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sclk: i2s3m1-sclk { + rockchip,pins = + /* i2s3m1_sclk */ + <4 RK_PC3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sdi: i2s3m1-sdi { + rockchip,pins = + /* i2s3m1_sdi */ + <4 RK_PC6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sdo: i2s3m1-sdo { + rockchip,pins = + /* i2s3m1_sdo */ + <4 RK_PC5 5 &pcfg_pull_none>; + }; + }; + + isp { + /omit-if-no-ref/ + isp_pins: isp-pins { + rockchip,pins = + /* isp_flashtrigin */ + <4 RK_PB4 4 &pcfg_pull_none>, + /* isp_flashtrigout */ + <4 RK_PA6 1 &pcfg_pull_none>, + /* isp_prelighttrig */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtag_pins: jtag-pins { + rockchip,pins = + /* jtag_tck */ + <1 RK_PD7 2 &pcfg_pull_none>, + /* jtag_tms */ + <2 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + lcdc { + /omit-if-no-ref/ + lcdc_ctl: lcdc-ctl { + rockchip,pins = + /* lcdc_clk */ + <3 RK_PA0 1 &pcfg_pull_none>, + /* lcdc_d0 */ + <2 RK_PD0 1 &pcfg_pull_none>, + /* lcdc_d1 */ + <2 RK_PD1 1 &pcfg_pull_none>, + /* lcdc_d2 */ + <2 RK_PD2 1 &pcfg_pull_none>, + /* lcdc_d3 */ + <2 RK_PD3 1 &pcfg_pull_none>, + /* lcdc_d4 */ + <2 RK_PD4 1 &pcfg_pull_none>, + /* lcdc_d5 */ + <2 RK_PD5 1 &pcfg_pull_none>, + /* lcdc_d6 */ + <2 RK_PD6 1 &pcfg_pull_none>, + /* lcdc_d7 */ + <2 RK_PD7 1 &pcfg_pull_none>, + /* lcdc_d8 */ + <3 RK_PA1 1 &pcfg_pull_none>, + /* lcdc_d9 */ + <3 RK_PA2 1 &pcfg_pull_none>, + /* lcdc_d10 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* lcdc_d11 */ + <3 RK_PA4 1 &pcfg_pull_none>, + /* lcdc_d12 */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* lcdc_d13 */ + <3 RK_PA6 1 &pcfg_pull_none>, + /* lcdc_d14 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* lcdc_d15 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* lcdc_d16 */ + <3 RK_PB1 1 &pcfg_pull_none>, + /* lcdc_d17 */ + <3 RK_PB2 1 &pcfg_pull_none>, + /* lcdc_d18 */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* lcdc_d19 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* lcdc_d20 */ + <3 RK_PB5 1 &pcfg_pull_none>, + /* lcdc_d21 */ + <3 RK_PB6 1 &pcfg_pull_none>, + /* lcdc_d22 */ + <3 RK_PB7 1 &pcfg_pull_none>, + /* lcdc_d23 */ + <3 RK_PC0 1 &pcfg_pull_none>, + /* lcdc_den */ + <3 RK_PC3 1 &pcfg_pull_none>, + /* lcdc_hsync */ + <3 RK_PC1 1 &pcfg_pull_none>, + /* lcdc_vsync */ + <3 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + mcu { + /omit-if-no-ref/ + mcu_pins: mcu-pins { + rockchip,pins = + /* mcu_jtagtck */ + <0 RK_PB4 4 &pcfg_pull_none>, + /* mcu_jtagtdi */ + <0 RK_PC1 4 &pcfg_pull_none>, + /* mcu_jtagtdo */ + <0 RK_PB3 4 &pcfg_pull_none>, + /* mcu_jtagtms */ + <0 RK_PC2 4 &pcfg_pull_none>, + /* mcu_jtagtrstn */ + <0 RK_PC3 4 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins = + /* npu_avs */ + <0 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + pcie20 { + /omit-if-no-ref/ + pcie20m0_pins: pcie20m0-pins { + rockchip,pins = + /* pcie20_clkreqnm0 */ + <0 RK_PA5 3 &pcfg_pull_none>, + /* pcie20_perstnm0 */ + <0 RK_PB6 3 &pcfg_pull_none>, + /* pcie20_wakenm0 */ + <0 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m1_pins: pcie20m1-pins { + rockchip,pins = + /* pcie20_clkreqnm1 */ + <2 RK_PD0 4 &pcfg_pull_none>, + /* pcie20_perstnm1 */ + <3 RK_PC1 4 &pcfg_pull_none>, + /* pcie20_wakenm1 */ + <2 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m2_pins: pcie20m2-pins { + rockchip,pins = + /* pcie20_clkreqnm2 */ + <1 RK_PB0 4 &pcfg_pull_none>, + /* pcie20_perstnm2 */ + <1 RK_PB2 4 &pcfg_pull_none>, + /* pcie20_wakenm2 */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20_buttonrstn: pcie20-buttonrstn { + rockchip,pins = + /* pcie20_buttonrstn */ + <0 RK_PB4 3 &pcfg_pull_none>; + }; + }; + + pcie30x1 { + /omit-if-no-ref/ + pcie30x1m0_pins: pcie30x1m0-pins { + rockchip,pins = + /* pcie30x1_clkreqnm0 */ + <0 RK_PA4 3 &pcfg_pull_none>, + /* pcie30x1_perstnm0 */ + <0 RK_PC3 3 &pcfg_pull_none>, + /* pcie30x1_wakenm0 */ + <0 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_pins: pcie30x1m1-pins { + rockchip,pins = + /* pcie30x1_clkreqnm1 */ + <2 RK_PD2 4 &pcfg_pull_none>, + /* pcie30x1_perstnm1 */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* pcie30x1_wakenm1 */ + <2 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_pins: pcie30x1m2-pins { + rockchip,pins = + /* pcie30x1_clkreqnm2 */ + <1 RK_PA5 4 &pcfg_pull_none>, + /* pcie30x1_perstnm2 */ + <1 RK_PA2 4 &pcfg_pull_none>, + /* pcie30x1_wakenm2 */ + <1 RK_PA3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_buttonrstn: pcie30x1-buttonrstn { + rockchip,pins = + /* pcie30x1_buttonrstn */ + <0 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + pcie30x2 { + /omit-if-no-ref/ + pcie30x2m0_pins: pcie30x2m0-pins { + rockchip,pins = + /* pcie30x2_clkreqnm0 */ + <0 RK_PA6 2 &pcfg_pull_none>, + /* pcie30x2_perstnm0 */ + <0 RK_PC6 3 &pcfg_pull_none>, + /* pcie30x2_wakenm0 */ + <0 RK_PC5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_pins: pcie30x2m1-pins { + rockchip,pins = + /* pcie30x2_clkreqnm1 */ + <2 RK_PD4 4 &pcfg_pull_none>, + /* pcie30x2_perstnm1 */ + <2 RK_PD6 4 &pcfg_pull_none>, + /* pcie30x2_wakenm1 */ + <2 RK_PD5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_pins: pcie30x2m2-pins { + rockchip,pins = + /* pcie30x2_clkreqnm2 */ + <4 RK_PC2 4 &pcfg_pull_none>, + /* pcie30x2_perstnm2 */ + <4 RK_PC4 4 &pcfg_pull_none>, + /* pcie30x2_wakenm2 */ + <4 RK_PC3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2_buttonrstn: pcie30x2-buttonrstn { + rockchip,pins = + /* pcie30x2_buttonrstn */ + <0 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdmm0_clk: pdmm0-clk { + rockchip,pins = + /* pdm_clk0m0 */ + <1 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_clk1: pdmm0-clk1 { + rockchip,pins = + /* pdmm0_clk1 */ + <1 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi0: pdmm0-sdi0 { + rockchip,pins = + /* pdmm0_sdi0 */ + <1 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi1: pdmm0-sdi1 { + rockchip,pins = + /* pdmm0_sdi1 */ + <1 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi2: pdmm0-sdi2 { + rockchip,pins = + /* pdmm0_sdi2 */ + <1 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi3: pdmm0-sdi3 { + rockchip,pins = + /* pdmm0_sdi3 */ + <1 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk: pdmm1-clk { + rockchip,pins = + /* pdm_clk0m1 */ + <3 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk1: pdmm1-clk1 { + rockchip,pins = + /* pdmm1_clk1 */ + <4 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi0: pdmm1-sdi0 { + rockchip,pins = + /* pdmm1_sdi0 */ + <3 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi1: pdmm1-sdi1 { + rockchip,pins = + /* pdmm1_sdi1 */ + <4 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi2: pdmm1-sdi2 { + rockchip,pins = + /* pdmm1_sdi2 */ + <4 RK_PA2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi3: pdmm1-sdi3 { + rockchip,pins = + /* pdmm1_sdi3 */ + <4 RK_PA3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_clk1: pdmm2-clk1 { + rockchip,pins = + /* pdmm2_clk1 */ + <3 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi0: pdmm2-sdi0 { + rockchip,pins = + /* pdmm2_sdi0 */ + <3 RK_PB3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi1: pdmm2-sdi1 { + rockchip,pins = + /* pdmm2_sdi1 */ + <3 RK_PB4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi2: pdmm2-sdi2 { + rockchip,pins = + /* pdmm2_sdi2 */ + <3 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi3: pdmm2-sdi3 { + rockchip,pins = + /* pdmm2_sdi3 */ + <3 RK_PC0 5 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_pins: pmic-pins { + rockchip,pins = + /* pmic_sleep */ + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug0 */ + <0 RK_PA5 4 &pcfg_pull_none>, + /* pmu_debug1 */ + <0 RK_PA6 3 &pcfg_pull_none>, + /* pmu_debug2 */ + <0 RK_PC4 4 &pcfg_pull_none>, + /* pmu_debug3 */ + <0 RK_PC5 4 &pcfg_pull_none>, + /* pmu_debug4 */ + <0 RK_PC6 4 &pcfg_pull_none>, + /* pmu_debug5 */ + <0 RK_PC7 4 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <0 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <0 RK_PC7 2 &pcfg_pull_none>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <0 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <0 RK_PB5 4 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <0 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <0 RK_PB6 4 &pcfg_pull_none>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3_pins: pwm3-pins { + rockchip,pins = + /* pwm3_ir */ + <0 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4_pins: pwm4-pins { + rockchip,pins = + /* pwm4 */ + <0 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5_pins: pwm5-pins { + rockchip,pins = + /* pwm5 */ + <0 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6_pins: pwm6-pins { + rockchip,pins = + /* pwm6 */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7_pins: pwm7-pins { + rockchip,pins = + /* pwm7_ir */ + <0 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + /* pwm8_m0 */ + <3 RK_PB1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + /* pwm8_m1 */ + <1 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + /* pwm9_m0 */ + <3 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + /* pwm9_m1 */ + <1 RK_PD6 4 &pcfg_pull_none>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + /* pwm10_m0 */ + <3 RK_PB5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + /* pwm10_m1 */ + <2 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_irm0 */ + <3 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + /* pwm11_irm1 */ + <4 RK_PC0 3 &pcfg_pull_none>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins = + /* pwm12_m0 */ + <3 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins = + /* pwm12_m1 */ + <4 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins = + /* pwm13_m0 */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins = + /* pwm13_m1 */ + <4 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins = + /* pwm14_m0 */ + <3 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins = + /* pwm14_m1 */ + <4 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins = + /* pwm15_irm0 */ + <3 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins = + /* pwm15_irm1 */ + <4 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + refclk { + /omit-if-no-ref/ + refclk_pins: refclk-pins { + rockchip,pins = + /* refclk_ou */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + sata { + /omit-if-no-ref/ + sata_pins: sata-pins { + rockchip,pins = + /* sata_cpdet */ + <0 RK_PA4 2 &pcfg_pull_none>, + /* sata_cppod */ + <0 RK_PA6 1 &pcfg_pull_none>, + /* sata_mpswitch */ + <0 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + sata0 { + /omit-if-no-ref/ + sata0_pins: sata0-pins { + rockchip,pins = + /* sata0_actled */ + <4 RK_PC6 3 &pcfg_pull_none>; + }; + }; + + sata1 { + /omit-if-no-ref/ + sata1_pins: sata1-pins { + rockchip,pins = + /* sata1_actled */ + <4 RK_PC5 3 &pcfg_pull_none>; + }; + }; + + sata2 { + /omit-if-no-ref/ + sata2_pins: sata2-pins { + rockchip,pins = + /* sata2_actled */ + <4 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + scr { + /omit-if-no-ref/ + scr_pins: scr-pins { + rockchip,pins = + /* scr_clk */ + <1 RK_PA2 3 &pcfg_pull_none>, + /* scr_det */ + <1 RK_PA7 3 &pcfg_pull_up>, + /* scr_io */ + <1 RK_PA3 3 &pcfg_pull_up>, + /* scr_rst */ + <1 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + /* sdmmc0_det */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins = + /* sdmmc0_pwren */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + /* sdmmc1_det */ + <2 RK_PB2 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins = + /* sdmmc1_pwren */ + <2 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + sdmmc2 { + /omit-if-no-ref/ + sdmmc2m0_bus4: sdmmc2m0-bus4 { + rockchip,pins = + /* sdmmc2_d0m0 */ + <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d1m0 */ + <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d2m0 */ + <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d3m0 */ + <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_clk: sdmmc2m0-clk { + rockchip,pins = + /* sdmmc2_clkm0 */ + <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_cmd: sdmmc2m0-cmd { + rockchip,pins = + /* sdmmc2_cmdm0 */ + <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_det: sdmmc2m0-det { + rockchip,pins = + /* sdmmc2_detm0 */ + <3 RK_PD4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc2m0_pwren: sdmmc2m0-pwren { + rockchip,pins = + /* sdmmc2m0_pwren */ + <3 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sdmmc2m1_bus4: sdmmc2m1-bus4 { + rockchip,pins = + /* sdmmc2_d0m1 */ + <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d1m1 */ + <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d2m1 */ + <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d3m1 */ + <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_clk: sdmmc2m1-clk { + rockchip,pins = + /* sdmmc2_clkm1 */ + <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_cmd: sdmmc2m1-cmd { + rockchip,pins = + /* sdmmc2_cmdm1 */ + <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_det: sdmmc2m1-det { + rockchip,pins = + /* sdmmc2_detm1 */ + <3 RK_PA7 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc2m1_pwren: sdmmc2m1-pwren { + rockchip,pins = + /* sdmmc2m1_pwren */ + <3 RK_PB0 4 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_tx: spdifm0-tx { + rockchip,pins = + /* spdifm0_tx */ + <1 RK_PA4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_tx: spdifm1-tx { + rockchip,pins = + /* spdifm1_tx */ + <3 RK_PC5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_tx: spdifm2-tx { + rockchip,pins = + /* spdifm2_tx */ + <4 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins = + /* spi0_clkm0 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* spi0_misom0 */ + <0 RK_PC5 2 &pcfg_pull_none>, + /* spi0_mosim0 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0m0 */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1m0 */ + <0 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins = + /* spi0_clkm1 */ + <2 RK_PD3 3 &pcfg_pull_none>, + /* spi0_misom1 */ + <2 RK_PD0 3 &pcfg_pull_none>, + /* spi0_mosim1 */ + <2 RK_PD1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0m1 */ + <2 RK_PD2 3 &pcfg_pull_none>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins = + /* spi1_clkm0 */ + <2 RK_PB5 3 &pcfg_pull_none>, + /* spi1_misom0 */ + <2 RK_PB6 3 &pcfg_pull_none>, + /* spi1_mosim0 */ + <2 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m0_cs0: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0m0 */ + <2 RK_PC0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m0_cs1: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1m0 */ + <2 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins = + /* spi1_clkm1 */ + <3 RK_PC3 3 &pcfg_pull_none>, + /* spi1_misom1 */ + <3 RK_PC2 3 &pcfg_pull_none>, + /* spi1_mosim1 */ + <3 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m1_cs0: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0m1 */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins = + /* spi2_clkm0 */ + <2 RK_PC1 4 &pcfg_pull_none>, + /* spi2_misom0 */ + <2 RK_PC2 4 &pcfg_pull_none>, + /* spi2_mosim0 */ + <2 RK_PC3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m0_cs0: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0m0 */ + <2 RK_PC4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m0_cs1: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1m0 */ + <2 RK_PC5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins = + /* spi2_clkm1 */ + <3 RK_PA0 3 &pcfg_pull_none>, + /* spi2_misom1 */ + <2 RK_PD7 3 &pcfg_pull_none>, + /* spi2_mosim1 */ + <2 RK_PD6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_cs0: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0m1 */ + <2 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_cs1: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1m1 */ + <2 RK_PD4 3 &pcfg_pull_none>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m0_pins: spi3m0-pins { + rockchip,pins = + /* spi3_clkm0 */ + <4 RK_PB3 4 &pcfg_pull_none>, + /* spi3_misom0 */ + <4 RK_PB0 4 &pcfg_pull_none>, + /* spi3_mosim0 */ + <4 RK_PB2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m0_cs0: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0m0 */ + <4 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m0_cs1: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1m0 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_pins: spi3m1-pins { + rockchip,pins = + /* spi3_clkm1 */ + <4 RK_PC2 2 &pcfg_pull_none>, + /* spi3_misom1 */ + <4 RK_PC5 2 &pcfg_pull_none>, + /* spi3_mosim1 */ + <4 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_cs0: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0m1 */ + <4 RK_PC6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_cs1: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1m1 */ + <4 RK_PD1 2 &pcfg_pull_none>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm0_shut: tsadcm0-shut { + rockchip,pins = + /* tsadcm0_shut */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadcm1_shut: tsadcm1-shut { + rockchip,pins = + /* tsadcm1_shut */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shutorg: tsadc-shutorg { + rockchip,pins = + /* tsadc_shutorg */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <0 RK_PC0 3 &pcfg_pull_up>, + /* uart0_tx */ + <0 RK_PC1 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + /* uart0_ctsn */ + <0 RK_PC7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + /* uart0_rtsn */ + <0 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rxm0 */ + <2 RK_PB3 2 &pcfg_pull_up>, + /* uart1_txm0 */ + <2 RK_PB4 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + /* uart1m0_ctsn */ + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + /* uart1m0_rtsn */ + <2 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rxm1 */ + <3 RK_PD7 4 &pcfg_pull_up>, + /* uart1_txm1 */ + <3 RK_PD6 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + /* uart1m1_ctsn */ + <4 RK_PC1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + /* uart1m1_rtsn */ + <4 RK_PB6 4 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rxm0 */ + <0 RK_PD0 1 &pcfg_pull_up>, + /* uart2_txm0 */ + <0 RK_PD1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rxm1 */ + <1 RK_PD6 2 &pcfg_pull_up>, + /* uart2_txm1 */ + <1 RK_PD5 2 &pcfg_pull_up>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rxm0 */ + <1 RK_PA0 2 &pcfg_pull_up>, + /* uart3_txm0 */ + <1 RK_PA1 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m0_ctsn: uart3m0-ctsn { + rockchip,pins = + /* uart3m0_ctsn */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m0_rtsn: uart3m0-rtsn { + rockchip,pins = + /* uart3m0_rtsn */ + <1 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rxm1 */ + <3 RK_PC0 4 &pcfg_pull_up>, + /* uart3_txm1 */ + <3 RK_PB7 4 &pcfg_pull_up>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rxm0 */ + <1 RK_PA4 2 &pcfg_pull_up>, + /* uart4_txm0 */ + <1 RK_PA6 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m0_ctsn: uart4m0-ctsn { + rockchip,pins = + /* uart4m0_ctsn */ + <1 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m0_rtsn: uart4m0-rtsn { + rockchip,pins = + /* uart4m0_rtsn */ + <1 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + /* uart4_rxm1 */ + <3 RK_PB1 4 &pcfg_pull_up>, + /* uart4_txm1 */ + <3 RK_PB2 4 &pcfg_pull_up>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rxm0 */ + <2 RK_PA1 3 &pcfg_pull_up>, + /* uart5_txm0 */ + <2 RK_PA2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <1 RK_PD7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rxm1 */ + <3 RK_PC3 4 &pcfg_pull_up>, + /* uart5_txm1 */ + <3 RK_PC2 4 &pcfg_pull_up>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rxm0 */ + <2 RK_PA3 3 &pcfg_pull_up>, + /* uart6_txm0 */ + <2 RK_PA4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins = + /* uart6m0_ctsn */ + <2 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins = + /* uart6m0_rtsn */ + <2 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rxm1 */ + <1 RK_PD6 3 &pcfg_pull_up>, + /* uart6_txm1 */ + <1 RK_PD5 3 &pcfg_pull_up>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rxm0 */ + <2 RK_PA5 3 &pcfg_pull_up>, + /* uart7_txm0 */ + <2 RK_PA6 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <2 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <2 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rxm1 */ + <3 RK_PC5 4 &pcfg_pull_up>, + /* uart7_txm1 */ + <3 RK_PC4 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m2_xfer: uart7m2-xfer { + rockchip,pins = + /* uart7_rxm2 */ + <4 RK_PA3 4 &pcfg_pull_up>, + /* uart7_txm2 */ + <4 RK_PA2 4 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins = + /* uart8_rxm0 */ + <2 RK_PC6 2 &pcfg_pull_up>, + /* uart8_txm0 */ + <2 RK_PC5 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins = + /* uart8m0_ctsn */ + <2 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins = + /* uart8m0_rtsn */ + <2 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins = + /* uart8_rxm1 */ + <3 RK_PA0 4 &pcfg_pull_up>, + /* uart8_txm1 */ + <2 RK_PD7 4 &pcfg_pull_up>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rxm0 */ + <2 RK_PA7 3 &pcfg_pull_up>, + /* uart9_txm0 */ + <2 RK_PB0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins = + /* uart9m0_ctsn */ + <2 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins = + /* uart9m0_rtsn */ + <2 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rxm1 */ + <4 RK_PC6 4 &pcfg_pull_up>, + /* uart9_txm1 */ + <4 RK_PC5 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m2_xfer: uart9m2-xfer { + rockchip,pins = + /* uart9_rxm2 */ + <4 RK_PA5 4 &pcfg_pull_up>, + /* uart9_txm2 */ + <4 RK_PA4 4 &pcfg_pull_up>; + }; + }; + + vop { + /omit-if-no-ref/ + vopm0_pins: vopm0-pins { + rockchip,pins = + /* vop_pwmm0 */ + <0 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + vopm1_pins: vopm1-pins { + rockchip,pins = + /* vop_pwmm1 */ + <3 RK_PC4 2 &pcfg_pull_none>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + spi0-hs { + /omit-if-no-ref/ + spi0m0_pins_hs: spi0m0-pins { + rockchip,pins = + /* spi0_clkm0 */ + <0 RK_PB5 2 &pcfg_pull_up_drv_level_1>, + /* spi0_misom0 */ + <0 RK_PC5 2 &pcfg_pull_up_drv_level_1>, + /* spi0_mosim0 */ + <0 RK_PB6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs0_hs: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0m0 */ + <0 RK_PC6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs1_hs: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1m0 */ + <0 RK_PC4 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_pins_hs: spi0m1-pins { + rockchip,pins = + /* spi0_clkm1 */ + <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>, + /* spi0_misom1 */ + <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>, + /* spi0_mosim1 */ + <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_cs0_hs: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0m1 */ + <2 RK_PD2 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi1-hs { + /omit-if-no-ref/ + spi1m0_pins_hs: spi1m0-pins { + rockchip,pins = + /* spi1_clkm0 */ + <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>, + /* spi1_misom0 */ + <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>, + /* spi1_mosim0 */ + <2 RK_PB7 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs0_hs: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0m0 */ + <2 RK_PC0 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs1_hs: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1m0 */ + <2 RK_PC6 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_pins_hs: spi1m1-pins { + rockchip,pins = + /* spi1_clkm1 */ + <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>, + /* spi1_misom1 */ + <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>, + /* spi1_mosim1 */ + <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_cs0_hs: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0m1 */ + <3 RK_PA1 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi2-hs { + /omit-if-no-ref/ + spi2m0_pins_hs: spi2m0-pins { + rockchip,pins = + /* spi2_clkm0 */ + <2 RK_PC1 4 &pcfg_pull_up_drv_level_1>, + /* spi2_misom0 */ + <2 RK_PC2 4 &pcfg_pull_up_drv_level_1>, + /* spi2_mosim0 */ + <2 RK_PC3 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs0_hs: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0m0 */ + <2 RK_PC4 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs1_hs: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1m0 */ + <2 RK_PC5 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_pins_hs: spi2m1-pins { + rockchip,pins = + /* spi2_clkm1 */ + <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>, + /* spi2_misom1 */ + <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>, + /* spi2_mosim1 */ + <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs0_hs: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0m1 */ + <2 RK_PD5 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs1_hs: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1m1 */ + <2 RK_PD4 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3-hs { + /omit-if-no-ref/ + spi3m0_pins_hs: spi3m0-pins { + rockchip,pins = + /* spi3_clkm0 */ + <4 RK_PB3 4 &pcfg_pull_up_drv_level_1>, + /* spi3_misom0 */ + <4 RK_PB0 4 &pcfg_pull_up_drv_level_1>, + /* spi3_mosim0 */ + <4 RK_PB2 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs0_hs: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0m0 */ + <4 RK_PA6 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs1_hs: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1m0 */ + <4 RK_PA7 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_pins_hs: spi3m1-pins { + rockchip,pins = + /* spi3_clkm1 */ + <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>, + /* spi3_misom1 */ + <4 RK_PC5 2 &pcfg_pull_up_drv_level_1>, + /* spi3_mosim1 */ + <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs0_hs: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0m1 */ + <4 RK_PC6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs1_hs: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1m1 */ + <4 RK_PD1 2 &pcfg_pull_up_drv_level_1>; + }; + }; + + gmac-txd-level3 { + /omit-if-no-ref/ + gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none_drv_level_3>, + /* gmac0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* gmac0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PA6 2 &pcfg_pull_none_drv_level_3>, + /* gmac0_txd3 */ + <2 RK_PA7 2 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 { + rockchip,pins = + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 { + rockchip,pins = + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 { + rockchip,pins = + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 { + rockchip,pins = + /* gmac1_rxd2m1 */ + <4 RK_PA1 3 &pcfg_pull_none>, + /* gmac1_rxd3m1 */ + <4 RK_PA2 3 &pcfg_pull_none>, + /* gmac1_txd2m1 */ + <3 RK_PD6 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd3m1 */ + <3 RK_PD7 3 &pcfg_pull_none_drv_level_3>; + }; + }; + + gmac-txc-level2 { + /omit-if-no-ref/ + gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB0 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 { + rockchip,pins = + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 { + rockchip,pins = + /* gmac1_rxclkm1 */ + <4 RK_PA3 3 &pcfg_pull_none>, + /* gmac1_txclkm1 */ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi new file mode 100644 index 000000000000..d225e6a45d5c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/clock/rk3568-cru.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,boot-mode.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + compatible = "rockchip,rk3568"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + clocks = <&scmi_clk 0>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <900000 900000 1150000>; + clock-latency-ns = <40000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1150000>; + }; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <900000 900000 1150000>; + opp-suspend; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <900000 900000 1150000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <900000 900000 1150000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <975000 975000 1150000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1050000 1050000 1150000>; + }; + + opp-1992000000 { + opp-hz = /bits/ 64 <1992000000>; + opp-microvolt = <1150000 1150000 1150000>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; + arm,no-tick-in-suspend; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + pinctrl-0 = <&clk32k_out0>; + pinctrl-names = "default"; + #clock-cells = <0>; + }; + + sram@10f000 { + compatible = "mmio-sram"; + reg = <0x0 0x0010f000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x0010f000 0x100>; + + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + }; + + gic: interrupt-controller@fd400000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ + <0x0 0xfd460000 0 0x80000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + mbi-alias = <0x0 0xfd100000>; + mbi-ranges = <296 24>; + msi-controller; + }; + + pmugrf: syscon@fdc20000 { + compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc20000 0x0 0x10000>; + }; + + grf: syscon@fdc60000 { + compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc60000 0x0 0x10000>; + }; + + pmucru: clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x0 0xfdd00000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x0 0xfdd20000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + i2c0: i2c@fdd40000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfdd40000 0x0 0x1000>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@fdd50000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfdd50000 0x0 0x100>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 0>, <&dmac0 1>; + pinctrl-0 = <&uart0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + sdmmc2: mmc@fe000000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe000000 0x0 0x4000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, + <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC2>; + reset-names = "reset"; + status = "disabled"; + }; + + sdmmc0: mmc@fe2b0000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, + <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdmmc1: mmc@fe2c0000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, + <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC1>; + reset-names = "reset"; + status = "disabled"; + }; + + sdhci: mmc@fe310000 { + compatible = "rockchip,rk3568-dwcmshc"; + reg = <0x0 0xfe310000 0x0 0x10000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>; + clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + status = "disabled"; + }; + + dmac0: dmac@fe530000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe530000 0x0 0x4000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_BUS>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + dmac1: dmac@fe550000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe550000 0x0 0x4000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_BUS>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + i2c1: i2c@fe5a0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5a0000 0x0 0x1000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c1_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@fe5b0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5b0000 0x0 0x1000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c2m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@fe5c0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5c0000 0x0 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c3m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@fe5d0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5d0000 0x0 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c4m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@fe5e0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5e0000 0x0 0x1000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c5m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart1: serial@fe650000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe650000 0x0 0x100>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + pinctrl-0 = <&uart1m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@fe660000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe660000 0x0 0x100>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 4>, <&dmac0 5>; + pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@fe670000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe670000 0x0 0x100>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 6>, <&dmac0 7>; + pinctrl-0 = <&uart3m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@fe680000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe680000 0x0 0x100>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 8>, <&dmac0 9>; + pinctrl-0 = <&uart4m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart5: serial@fe690000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe690000 0x0 0x100>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 10>, <&dmac0 11>; + pinctrl-0 = <&uart5m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart6: serial@fe6a0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6a0000 0x0 0x100>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 12>, <&dmac0 13>; + pinctrl-0 = <&uart6m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart7: serial@fe6b0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6b0000 0x0 0x100>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 14>, <&dmac0 15>; + pinctrl-0 = <&uart7m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart8: serial@fe6c0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6c0000 0x0 0x100>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 16>, <&dmac0 17>; + pinctrl-0 = <&uart8m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart9: serial@fe6d0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6d0000 0x0 0x100>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 18>, <&dmac0 19>; + pinctrl-0 = <&uart9m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@fdd60000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfdd60000 0x0 0x100>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmucru PCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@fe740000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe740000 0x0 0x100>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@fe750000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe750000 0x0 0x100>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@fe760000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe760000 0x0 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@fe770000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe770000 0x0 0x100>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rk3568-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi b/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi new file mode 100644 index 000000000000..5c645437b507 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +&pinctrl { + /omit-if-no-ref/ + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 { + bias-disable; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 { + bias-disable; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 { + bias-disable; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 { + bias-disable; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 { + bias-disable; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 { + bias-disable; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 { + bias-disable; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 { + bias-disable; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 { + bias-disable; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 { + bias-disable; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 { + bias-disable; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 { + bias-disable; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 { + bias-disable; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 { + bias-disable; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 { + bias-pull-up; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 { + bias-pull-up; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 { + bias-pull-up; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 { + bias-pull-up; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 { + bias-pull-up; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 { + bias-pull-up; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 { + bias-pull-up; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 { + bias-pull-up; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 { + bias-pull-up; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 { + bias-pull-up; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 { + bias-pull-up; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 { + bias-pull-up; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 { + bias-pull-down; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 { + bias-pull-down; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 { + bias-pull-down; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 { + bias-pull-down; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 { + bias-pull-down; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 { + bias-pull-down; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 { + bias-pull-down; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 { + bias-pull-down; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 { + bias-pull-down; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 { + bias-pull-down; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 { + bias-pull-down; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 { + bias-pull-down; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 { + bias-pull-down; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 { + bias-pull-down; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 { + bias-pull-down; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 { + bias-pull-down; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_smt: pcfg-pull-up-smt { + bias-pull-up; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_down_smt: pcfg-pull-down-smt { + bias-pull-down; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt { + bias-disable; + drive-strength = <0>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_output_high: pcfg-output-high { + output-high; + }; + + /omit-if-no-ref/ + pcfg_output_low: pcfg-output-low { + output-low; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index ca59d1f711f8..02c3fdf9cc46 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -5,6 +5,17 @@ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include <dt-bindings/phy/phy-cadence.h> +#include <dt-bindings/phy/phy-ti.h> + +/ { + serdes_refclk: clock-cmnrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; + &cbass_main { oc_sram: sram@70000000 { compatible = "mmio-sram"; @@ -13,8 +24,30 @@ #size-cells = <1>; ranges = <0x0 0x00 0x70000000 0x200000>; - atf-sram@0 { - reg = <0x0 0x1a000>; + tfa-sram@1c0000 { + reg = <0x1c0000 0x20000>; + }; + + dmsc-sram@1e0000 { + reg = <0x1e0000 0x1c000>; + }; + + sproxy-sram@1fc000 { + reg = <0x1fc000 0x4000>; + }; + }; + + main_conf: syscon@43000000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x0 0x43000000 0x0 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x43000000 0x20000>; + + serdes_ln_ctrl: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ }; }; @@ -189,8 +222,6 @@ main_uart0: serial@2800000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -202,8 +233,6 @@ main_uart1: serial@2810000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -215,8 +244,6 @@ main_uart2: serial@2820000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -228,8 +255,6 @@ main_uart3: serial@2830000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -241,8 +266,6 @@ main_uart4: serial@2840000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -254,8 +277,6 @@ main_uart5: serial@2850000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -267,8 +288,6 @@ main_uart6: serial@2860000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -489,7 +508,8 @@ ti,mac-only; label = "port1"; phys = <&phy_gmii_sel 1>; - mac-address = [00 00 de ad be ef]; + mac-address = [00 00 00 00 00 00]; + ti,syscon-efuse = <&main_conf 0x200>; }; cpsw_port2: port@2 { @@ -497,7 +517,7 @@ ti,mac-only; label = "port2"; phys = <&phy_gmii_sel 2>; - mac-address = [00 01 de ad be ef]; + mac-address = [00 00 00 00 00 00]; }; }; @@ -673,4 +693,170 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; }; + + main_r5fss0: r5fss@78000000 { + compatible = "ti,am64-r5fss"; + ti,cluster-mode = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x78000000 0x00 0x78000000 0x10000>, + <0x78100000 0x00 0x78100000 0x10000>, + <0x78200000 0x00 0x78200000 0x08000>, + <0x78300000 0x00 0x78300000 0x08000>; + power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss0_core0: r5f@78000000 { + compatible = "ti,am64-r5f"; + reg = <0x78000000 0x00010000>, + <0x78100000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <121>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 121 1>; + firmware-name = "am64-main-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss0_core1: r5f@78200000 { + compatible = "ti,am64-r5f"; + reg = <0x78200000 0x00008000>, + <0x78300000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <122>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 122 1>; + firmware-name = "am64-main-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + main_r5fss1: r5fss@78400000 { + compatible = "ti,am64-r5fss"; + ti,cluster-mode = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x78400000 0x00 0x78400000 0x10000>, + <0x78500000 0x00 0x78500000 0x10000>, + <0x78600000 0x00 0x78600000 0x08000>, + <0x78700000 0x00 0x78700000 0x08000>; + power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss1_core0: r5f@78400000 { + compatible = "ti,am64-r5f"; + reg = <0x78400000 0x00010000>, + <0x78500000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <123>; + ti,sci-proc-ids = <0x06 0xff>; + resets = <&k3_reset 123 1>; + firmware-name = "am64-main-r5f1_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss1_core1: r5f@78600000 { + compatible = "ti,am64-r5f"; + reg = <0x78600000 0x00008000>, + <0x78700000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <124>; + ti,sci-proc-ids = <0x07 0xff>; + resets = <&k3_reset 124 1>; + firmware-name = "am64-main-r5f1_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + serdes_wiz0: wiz@f000000 { + compatible = "ti,am64-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <1>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; + + assigned-clocks = <&k3_clks 162 1>; + assigned-clock-parents = <&k3_clks 162 5>; + + serdes0: serdes@f000000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x0f000000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 162 1>, + <&k3_clks 162 1>, + <&k3_clks 162 1>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + }; + }; + + pcie0_rc: pcie@f102000 { + compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x0f102000 0x00 0x1000>, + <0x00 0x0f100000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x68000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&main_conf 0x4070>; + max-link-speed = <2>; + num-lanes = <1>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names = "fck", "pcie_refclk"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + cdns,no-bar-match-nbits = <64>; + vendor-id = <0x104c>; + device-id = <0xb010>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, + <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; + }; + + pcie0_ep: pcie-ep@f102000 { + compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; + reg = <0x00 0x0f102000 0x00 0x1000>, + <0x00 0x0f100000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x68000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names = "link_state"; + interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; + ti,syscon-pcie-ctrl = <&main_conf 0x4070>; + max-link-speed = <2>; + num-lanes = <1>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "fck"; + max-functions = /bits/ 8 <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index deb19ae5e168..59cc58f7d0c8 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -9,8 +9,6 @@ mcu_uart0: serial@4a00000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -22,8 +20,6 @@ mcu_uart1: serial@4a10000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a10000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -87,7 +83,7 @@ }; mcu_gpio0: gpio@4201000 { - compatible = "ti,am64-gpio", "keystone-gpio"; + compatible = "ti,am64-gpio", "ti,keystone-gpio"; reg = <0x0 0x4201000 0x0 0x100>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index dad0efa961ed..030712221188 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/mux/ti-serdes.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/net/ti-dp83867.h> @@ -36,6 +38,60 @@ alignment = <0x1000>; no-map; }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; }; evm_12v0: fixedregulator-evm12v0 { @@ -334,7 +390,7 @@ &main_spi0 { pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; eeprom@0 { compatible = "microchip,93lc46b"; reg = <0>; @@ -466,3 +522,55 @@ &mailbox0_cluster7 { status = "disabled"; }; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&serdes_ln_ctrl { + idle-states = <AM64_SERDES0_LANE0_PCIE0>; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz0 1>; + }; +}; + +&pcie0_rc { + reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + +&pcie0_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 8424cd071955..d3aa2901e6fd 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include <dt-bindings/mux/ti-serdes.h> +#include <dt-bindings/phy/phy.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/net/ti-dp83867.h> #include "k3-am642.dtsi" @@ -35,6 +37,60 @@ alignment = <0x1000>; no-map; }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; }; vusb_main: fixed-regulator-vusb-main5v0 { @@ -85,6 +141,12 @@ >; }; + main_usb0_pins_default: main-usb0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ @@ -235,6 +297,33 @@ disable-wp; }; +&serdes_ln_ctrl { + idle-states = <AM64_SERDES0_LANE0_USB>; +}; + +&serdes0 { + serdes0_usb_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_USB3>; + resets = <&serdes_wiz0 1>; + }; +}; + +&usbss0 { + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "host"; + maximum-speed = "super-speed"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb0_pins_default>; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + &cpsw3g { pinctrl-names = "default"; pinctrl-0 = <&mdio1_pins_default @@ -332,3 +421,35 @@ &mailbox0_cluster7 { status = "disabled"; }; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&pcie0_rc { + status = "disabled"; +}; + +&pcie0_ep { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index de763ca9251c..1008e9162ba2 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -555,6 +555,7 @@ pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; disable-wp; + no-1-8-v; }; &usb0 { @@ -575,7 +576,7 @@ #address-cells = <1>; #size-cells= <0>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; }; &tscadc0 { @@ -653,3 +654,63 @@ &pcie1_ep { status = "disabled"; }; + +&mailbox0_cluster0 { + status = "disabled"; +}; + +&mailbox0_cluster1 { + status = "disabled"; +}; + +&mailbox0_cluster2 { + status = "disabled"; +}; + +&mailbox0_cluster3 { + status = "disabled"; +}; + +&mailbox0_cluster4 { + status = "disabled"; +}; + +&mailbox0_cluster5 { + status = "disabled"; +}; + +&mailbox0_cluster6 { + status = "disabled"; +}; + +&mailbox0_cluster7 { + status = "disabled"; +}; + +&mailbox0_cluster8 { + status = "disabled"; +}; + +&mailbox0_cluster9 { + status = "disabled"; +}; + +&mailbox0_cluster10 { + status = "disabled"; +}; + +&mailbox0_cluster11 { + status = "disabled"; +}; + +&icssg0_mdio { + status = "disabled"; +}; + +&icssg1_mdio { + status = "disabled"; +}; + +&icssg2_mdio { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 6cd3131eb9ff..ba4e5d3e1ed7 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -84,8 +84,6 @@ main_uart0: serial@2800000 { compatible = "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -95,8 +93,6 @@ main_uart1: serial@2810000 { compatible = "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; @@ -105,8 +101,6 @@ main_uart2: serial@2820000 { compatible = "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; @@ -301,7 +295,6 @@ ti,otap-del-sel = <0x2>; ti,trm-icp = <0x8>; dma-coherent; - no-1-8-v; }; scm_conf: scm-conf@100000 { @@ -1053,6 +1046,16 @@ reg-names = "iram", "control", "debug"; firmware-name = "am65x-txpru0_1-fw"; }; + + icssg0_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 62 3>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + }; }; icssg1: icssg@b100000 { @@ -1184,6 +1187,16 @@ reg-names = "iram", "control", "debug"; firmware-name = "am65x-txpru1_1-fw"; }; + + icssg1_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 63 3>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + }; }; icssg2: icssg@b200000 { @@ -1315,5 +1328,15 @@ reg-names = "iram", "control", "debug"; firmware-name = "am65x-txpru2_1-fw"; }; + + icssg2_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 64 3>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index f5b8ef2f5f77..c93ff1520a0e 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -23,8 +23,6 @@ mcu_uart0: serial@40a00000 { compatible = "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <96000000>; current-speed = <115200>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index 7cb864b4d74a..9d21cdf6fce8 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -50,8 +50,6 @@ wkup_uart0: serial@42300000 { compatible = "ti,am654-uart"; reg = <0x42300000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts index 4f7e3f2a6265..94bb5dd39122 100644 --- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts +++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts @@ -59,3 +59,8 @@ pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; + +&mcu_r5fss0 { + /* lock-step mode not supported on this board */ + ti,cluster-mode = <0>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index eddb2ffb93ca..cfbcebfa37c1 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -85,6 +85,38 @@ gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>; }; }; + + evm_12v0: fixedregulator-evm12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "evm_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc3v3_io: fixedregulator-vcc3v3io { + /* Output of TPS54334 */ + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&evm_12v0>; + }; + + vdd_mmc1_sd: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc3v3_io>; + gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>; + }; }; &wkup_pmx0 { @@ -136,7 +168,7 @@ AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */ AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */ AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */ - AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */ + AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */ AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */ >; }; @@ -299,7 +331,7 @@ pinctrl-0 = <&main_spi0_pins_default>; #address-cells = <1>; #size-cells= <0>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; flash@0{ compatible = "jedec,spi-nor"; @@ -327,6 +359,7 @@ * disable sdhci1 */ &sdhci1 { + vmmc-supply = <&vdd_mmc1_sd>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; @@ -506,3 +539,15 @@ &dss { status = "disabled"; }; + +&icssg0_mdio { + status = "disabled"; +}; + +&icssg1_mdio { + status = "disabled"; +}; + +&icssg2_mdio { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index bedd01b7a32c..d14f3c18b65f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -90,7 +90,7 @@ J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 19fea8adbcff..e8a41d09b45f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -301,8 +301,6 @@ main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -314,8 +312,6 @@ main_uart1: serial@2810000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -327,8 +323,6 @@ main_uart2: serial@2820000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -340,8 +334,6 @@ main_uart3: serial@2830000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -353,8 +345,6 @@ main_uart4: serial@2840000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -366,8 +356,6 @@ main_uart5: serial@2850000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -379,8 +367,6 @@ main_uart6: serial@2860000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -392,8 +378,6 @@ main_uart7: serial@2870000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02870000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -405,8 +389,6 @@ main_uart8: serial@2880000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02880000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -418,8 +400,6 @@ main_uart9: serial@2890000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02890000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -683,6 +663,7 @@ "otg"; maximum-speed = "super-speed"; dr_mode = "otg"; + cdns,phyrst-a-enable; }; }; @@ -696,7 +677,6 @@ <149>; interrupt-controller; #interrupt-cells = <2>; - #address-cells = <0>; ti,ngpio = <69>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; @@ -714,7 +694,6 @@ <158>; interrupt-controller; #interrupt-cells = <2>; - #address-cells = <0>; ti,ngpio = <69>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; @@ -732,7 +711,6 @@ <167>; interrupt-controller; #interrupt-cells = <2>; - #address-cells = <0>; ti,ngpio = <69>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; @@ -750,7 +728,6 @@ <176>; interrupt-controller; #interrupt-cells = <2>; - #address-cells = <0>; ti,ngpio = <69>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 5663fe3ea466..1044ec6c4b0d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -73,8 +73,6 @@ wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -86,8 +84,6 @@ mcu_uart0: serial@40a00000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <96000000>; current-speed = <115200>; @@ -117,7 +113,6 @@ interrupts = <103>, <104>, <105>, <106>, <107>, <108>; interrupt-controller; #interrupt-cells = <2>; - #address-cells = <0>; ti,ngpio = <85>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; @@ -134,7 +129,6 @@ interrupts = <112>, <113>, <114>, <115>, <116>, <117>; interrupt-controller; #interrupt-cells = <2>; - #address-cells = <0>; ti,ngpio = <85>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 60764366e22b..8bd02d9e28ad 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -9,6 +9,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/phy/phy-cadence.h> / { chosen { @@ -237,7 +238,7 @@ J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ >; }; @@ -358,7 +359,7 @@ }; &serdes3 { - serdes3_usb_link: link@0 { + serdes3_usb_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -635,8 +636,45 @@ status = "disabled"; }; +&cmn_refclk1 { + clock-frequency = <100000000>; +}; + +&wiz0_pll1_refclk { + assigned-clocks = <&wiz0_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz0_refclk_dig { + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz1_pll1_refclk { + assigned-clocks = <&wiz1_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz1_refclk_dig { + assigned-clocks = <&wiz1_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz2_pll1_refclk { + assigned-clocks = <&wiz2_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz2_refclk_dig { + assigned-clocks = <&wiz2_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + &serdes0 { - serdes0_pcie_link: link@0 { + assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; + assigned-clock-parents = <&wiz0_pll1_refclk>; + + serdes0_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <1>; #phy-cells = <0>; @@ -646,7 +684,10 @@ }; &serdes1 { - serdes1_pcie_link: link@0 { + assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; + assigned-clock-parents = <&wiz1_pll1_refclk>; + + serdes1_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -656,7 +697,10 @@ }; &serdes2 { - serdes2_pcie_link: link@0 { + assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>; + assigned-clock-parents = <&wiz2_pll1_refclk>; + + serdes2_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; @@ -718,3 +762,11 @@ &dss { status = "disabled"; }; + +&icssg0_mdio { + status = "disabled"; +}; + +&icssg1_mdio { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 3bcafe4c1742..cf3482376c1e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -8,6 +8,20 @@ #include <dt-bindings/mux/mux.h> #include <dt-bindings/mux/ti-serdes.h> +/ { + cmn_refclk: clock-cmnrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + cmn_refclk1: clock-cmnrefclk1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -338,24 +352,12 @@ pinctrl-single,function-mask = <0xffffffff>; }; - dummy_cmn_refclk: dummy-cmn-refclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - - dummy_cmn_refclk1: dummy-cmn-refclk1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - serdes_wiz0: wiz@5000000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; @@ -364,21 +366,21 @@ ranges = <0x5000000 0x0 0x5000000 0x10000>; wiz0_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 292 11>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz0_pll0_refclk>; assigned-clock-parents = <&k3_clks 292 11>; }; wiz0_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 292 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz0_pll1_refclk>; assigned-clock-parents = <&k3_clks 292 0>; }; wiz0_refclk_dig: refclk-dig { - clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz0_refclk_dig>; assigned-clock-parents = <&k3_clks 292 11>; @@ -400,10 +402,13 @@ reg = <0x5000000 0x10000>; #address-cells = <1>; #size-cells = <0>; + #clock-cells = <1>; resets = <&serdes_wiz0 0>; reset-names = "sierra_reset"; - clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, + <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", + "pll0_refclk", "pll1_refclk"; }; }; @@ -412,7 +417,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; @@ -421,21 +426,21 @@ ranges = <0x5010000 0x0 0x5010000 0x10000>; wiz1_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 293 13>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz1_pll0_refclk>; assigned-clock-parents = <&k3_clks 293 13>; }; wiz1_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 293 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz1_pll1_refclk>; assigned-clock-parents = <&k3_clks 293 0>; }; wiz1_refclk_dig: refclk-dig { - clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz1_refclk_dig>; assigned-clock-parents = <&k3_clks 293 13>; @@ -457,10 +462,13 @@ reg = <0x5010000 0x10000>; #address-cells = <1>; #size-cells = <0>; + #clock-cells = <1>; resets = <&serdes_wiz1 0>; reset-names = "sierra_reset"; - clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, + <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", + "pll0_refclk", "pll1_refclk"; }; }; @@ -469,7 +477,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; @@ -478,21 +486,21 @@ ranges = <0x5020000 0x0 0x5020000 0x10000>; wiz2_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 294 11>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz2_pll0_refclk>; assigned-clock-parents = <&k3_clks 294 11>; }; wiz2_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 294 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz2_pll1_refclk>; assigned-clock-parents = <&k3_clks 294 0>; }; wiz2_refclk_dig: refclk-dig { - clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz2_refclk_dig>; assigned-clock-parents = <&k3_clks 294 11>; @@ -514,10 +522,13 @@ reg = <0x5020000 0x10000>; #address-cells = <1>; #size-cells = <0>; + #clock-cells = <1>; resets = <&serdes_wiz2 0>; reset-names = "sierra_reset"; - clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, + <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", + "pll0_refclk", "pll1_refclk"; }; }; @@ -526,7 +537,7 @@ #address-cells = <1>; #size-cells = <1>; power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; clock-names = "fck", "core_ref_clk", "ext_ref_clk"; assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; @@ -535,21 +546,21 @@ ranges = <0x5030000 0x0 0x5030000 0x10000>; wiz3_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>; + clocks = <&k3_clks 295 9>, <&cmn_refclk>; #clock-cells = <0>; assigned-clocks = <&wiz3_pll0_refclk>; assigned-clock-parents = <&k3_clks 295 9>; }; wiz3_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 295 0>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz3_pll1_refclk>; assigned-clock-parents = <&k3_clks 295 0>; }; wiz3_refclk_dig: refclk-dig { - clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; + clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz3_refclk_dig>; assigned-clock-parents = <&k3_clks 295 9>; @@ -571,10 +582,13 @@ reg = <0x5030000 0x10000>; #address-cells = <1>; #size-cells = <0>; + #clock-cells = <1>; resets = <&serdes_wiz3 0>; reset-names = "sierra_reset"; - clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, + <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", + "pll0_refclk", "pll1_refclk"; }; }; @@ -775,8 +789,6 @@ main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -788,8 +800,6 @@ main_uart1: serial@2810000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -801,8 +811,6 @@ main_uart2: serial@2820000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -814,8 +822,6 @@ main_uart3: serial@2830000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -827,8 +833,6 @@ main_uart4: serial@2840000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -840,8 +844,6 @@ main_uart5: serial@2850000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -853,8 +855,6 @@ main_uart6: serial@2860000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -866,8 +866,6 @@ main_uart7: serial@2870000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02870000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -879,8 +877,6 @@ main_uart8: serial@2880000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02880000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -892,8 +888,6 @@ main_uart9: serial@2890000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02890000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -1794,6 +1788,16 @@ reg-names = "iram", "control", "debug"; firmware-name = "j7-txpru0_1-fw"; }; + + icssg0_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 119 1>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + }; }; icssg1: icssg@b100000 { @@ -1925,5 +1929,15 @@ reg-names = "iram", "control", "debug"; firmware-name = "j7-txpru1_1-fw"; }; + + icssg1_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 120 4>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 5e825e4d0306..d2dceda72fe9 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -73,8 +73,6 @@ wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; current-speed = <115200>; @@ -86,8 +84,6 @@ mcu_uart0: serial@40a00000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <96000000>; current-speed = <115200>; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts index bf0620afe117..29a4d9fc1e47 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts @@ -68,3 +68,11 @@ &gpio { status = "okay"; }; + +&pwm_mux { + groups = "pwm0_gpio16_grp", "pwm1_gpio17_grp", "pwm2_gpio18_grp", "pwm3_gpio19_grp"; +}; + +&pwm { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 17934fd9a14c..4b4231ff43cf 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -432,6 +432,15 @@ reg = <0 0x28330000 0 0x1000>; status = "disabled"; }; + + pwm: pwm@241c0000 { + compatible = "toshiba,visconti-pwm"; + reg = <0 0x241c0000 0 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_mux>; + #pwm-cells = <2>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi index 34de00015a7f..a480c6ba5f5d 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi @@ -90,4 +90,9 @@ groups = "i2c8_grp"; bias-pull-up; }; + + pwm_mux: pwm_mux { + function = "pwm"; + }; + }; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 08c6f769df9a..f423d08b9a71 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -289,6 +289,7 @@ CONFIG_SCSI_UFSHCD=y CONFIG_SCSI_UFSHCD_PLATFORM=y CONFIG_SCSI_UFS_QCOM=m CONFIG_SCSI_UFS_HISI=y +CONFIG_SCSI_UFS_EXYNOS=y CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_AHCI_PLATFORM=y @@ -491,7 +492,6 @@ CONFIG_SPI_S3C64XX=y CONFIG_SPI_SH_MSIOF=m CONFIG_SPI_SUN6I=y CONFIG_SPI_SPIDEV=m -CONFIG_MTK_PMIC_WRAP=m CONFIG_SPMI=y CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_MAX77620=y @@ -530,6 +530,7 @@ CONFIG_GPIO_MXC=y CONFIG_GPIO_PL061=y CONFIG_GPIO_RCAR=y CONFIG_GPIO_UNIPHIER=y +CONFIG_GPIO_VISCONTI=y CONFIG_GPIO_WCD934X=m CONFIG_GPIO_XGENE=y CONFIG_GPIO_XGENE_SB=y @@ -662,6 +663,7 @@ CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m CONFIG_VIDEO_RENESAS_FDP1=m CONFIG_VIDEO_RENESAS_FCP=m CONFIG_VIDEO_RENESAS_VSP1=m +CONFIG_VIDEO_QCOM_VENUS=m CONFIG_SDR_PLATFORM_DRIVERS=y CONFIG_VIDEO_RCAR_DRIF=m CONFIG_VIDEO_IMX219=m @@ -701,6 +703,7 @@ CONFIG_DRM_PANEL_RAYDIUM_RM67191=m CONFIG_DRM_PANEL_SITRONIX_ST7703=m CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_LONTIUM_LT8912B=m CONFIG_DRM_NWL_MIPI_DSI=m CONFIG_DRM_LONTIUM_LT9611=m CONFIG_DRM_PARADE_PS8640=m @@ -774,6 +777,8 @@ CONFIG_SND_SOC_AK4613=m CONFIG_SND_SOC_ES7134=m CONFIG_SND_SOC_ES7241=m CONFIG_SND_SOC_GTM601=m +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m CONFIG_SND_SOC_PCM3168A_I2C=m CONFIG_SND_SOC_RT5659=m CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m @@ -795,6 +800,8 @@ CONFIG_USB_CONN_GPIO=m CONFIG_USB=y CONFIG_USB_OTG=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=m +CONFIG_USB_XHCI_PCI_RENESAS=m CONFIG_USB_XHCI_TEGRA=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_EXYNOS=y @@ -866,6 +873,7 @@ CONFIG_MMC_DW_K3=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SUNXI=y CONFIG_MMC_BCM2835=y +CONFIG_MMC_MTK=y CONFIG_MMC_SDHCI_XENON=y CONFIG_MMC_SDHCI_AM654=y CONFIG_MMC_OWL=y @@ -884,6 +892,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_PANIC=y CONFIG_EDAC=y CONFIG_EDAC_GHES=y +CONFIG_EDAC_LAYERSCAPE=m CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=m CONFIG_RTC_DRV_HYM8563=m @@ -987,6 +996,7 @@ CONFIG_SM_GPUCC_8250=y CONFIG_SM_DISPCC_8250=y CONFIG_QCOM_HFPLL=y CONFIG_CLK_GFM_LPASS_SM8250=m +CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_ARM_MHU=y @@ -1043,6 +1053,7 @@ CONFIG_ARCH_R8A77980=y CONFIG_ARCH_R8A77990=y CONFIG_ARCH_R8A77995=y CONFIG_ARCH_R8A779A0=y +CONFIG_ARCH_R9A07G044=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y @@ -1059,6 +1070,7 @@ CONFIG_RENESAS_RPCIF=m CONFIG_IIO=y CONFIG_EXYNOS_ADC=y CONFIG_MAX9611=m +CONFIG_QCOM_SPMI_VADC=m CONFIG_QCOM_SPMI_ADC5=m CONFIG_ROCKCHIP_SARADC=m CONFIG_IIO_CROS_EC_SENSORS_CORE=m @@ -1083,6 +1095,7 @@ CONFIG_PWM_SAMSUNG=y CONFIG_PWM_SL28CPLD=m CONFIG_PWM_SUN4I=m CONFIG_PWM_TEGRA=m +CONFIG_PWM_VISCONTI=m CONFIG_SL28CPLD_INTC=y CONFIG_QCOM_PDC=y CONFIG_RESET_IMX7=y @@ -1110,6 +1123,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m CONFIG_PHY_ROCKCHIP_PCIE=m CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PHY_SAMSUNG_UFS=y CONFIG_PHY_UNIPHIER_USB2=y CONFIG_PHY_UNIPHIER_USB3=y CONFIG_PHY_TEGRA_XUSB=y @@ -1148,6 +1162,7 @@ CONFIG_INTERCONNECT_QCOM_OSM_L3=m CONFIG_INTERCONNECT_QCOM_SDM845=y CONFIG_INTERCONNECT_QCOM_SM8150=m CONFIG_INTERCONNECT_QCOM_SM8250=m +CONFIG_INTERCONNECT_QCOM_SM8350=m CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS_POSIX_ACL=y diff --git a/arch/arm64/include/asm/Kbuild b/arch/arm64/include/asm/Kbuild index 26889dbfe904..64202010b700 100644 --- a/arch/arm64/include/asm/Kbuild +++ b/arch/arm64/include/asm/Kbuild @@ -3,7 +3,6 @@ generic-y += early_ioremap.h generic-y += mcs_spinlock.h generic-y += qrwlock.h generic-y += qspinlock.h -generic-y += set_memory.h generic-y += user.h generated-y += cpucaps.h diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index a9c0716e7440..a074459f8f2f 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -47,7 +47,7 @@ * cache before the transfer is done, causing old data to be seen by * the CPU. */ -#define ARCH_DMA_MINALIGN L1_CACHE_BYTES +#define ARCH_DMA_MINALIGN (128) #ifdef CONFIG_KASAN_SW_TAGS #define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT) diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h index 543c997eb3b7..5a228e203ef9 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -144,12 +144,6 @@ static __always_inline void icache_inval_all_pou(void) dsb(ish); } -int set_memory_valid(unsigned long addr, int numpages, int enable); - -int set_direct_map_invalid_noflush(struct page *page); -int set_direct_map_default_noflush(struct page *page); -bool kernel_page_present(struct page *page); - #include <asm-generic/cacheflush.h> #endif /* __ASM_CACHEFLUSH_H */ diff --git a/arch/arm64/include/asm/kfence.h b/arch/arm64/include/asm/kfence.h index d061176d57ea..aa855c6a0ae6 100644 --- a/arch/arm64/include/asm/kfence.h +++ b/arch/arm64/include/asm/kfence.h @@ -8,7 +8,7 @@ #ifndef __ASM_KFENCE_H #define __ASM_KFENCE_H -#include <asm/cacheflush.h> +#include <asm/set_memory.h> static inline bool arch_kfence_init_pool(void) { return true; } diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 508c7ffad515..f09bf5c02891 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -649,9 +649,9 @@ static inline phys_addr_t pud_page_paddr(pud_t pud) return __pud_to_phys(pud); } -static inline unsigned long pud_page_vaddr(pud_t pud) +static inline pmd_t *pud_pgtable(pud_t pud) { - return (unsigned long)__va(pud_page_paddr(pud)); + return (pmd_t *)__va(pud_page_paddr(pud)); } /* Find an entry in the second-level page table. */ @@ -710,9 +710,9 @@ static inline phys_addr_t p4d_page_paddr(p4d_t p4d) return __p4d_to_phys(p4d); } -static inline unsigned long p4d_page_vaddr(p4d_t p4d) +static inline pud_t *p4d_pgtable(p4d_t p4d) { - return (unsigned long)__va(p4d_page_paddr(p4d)); + return (pud_t *)__va(p4d_page_paddr(p4d)); } /* Find an entry in the frst-level page table. */ diff --git a/arch/arm64/include/asm/set_memory.h b/arch/arm64/include/asm/set_memory.h new file mode 100644 index 000000000000..0f740b781187 --- /dev/null +++ b/arch/arm64/include/asm/set_memory.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ASM_ARM64_SET_MEMORY_H +#define _ASM_ARM64_SET_MEMORY_H + +#include <asm-generic/set_memory.h> + +bool can_set_direct_map(void); +#define can_set_direct_map can_set_direct_map + +int set_memory_valid(unsigned long addr, int numpages, int enable); + +int set_direct_map_invalid_noflush(struct page *page); +int set_direct_map_default_noflush(struct page *page); +bool kernel_page_present(struct page *page); + +#endif /* _ASM_ARM64_SET_MEMORY_H */ diff --git a/arch/arm64/include/asm/smp_plat.h b/arch/arm64/include/asm/smp_plat.h index 99ad77df8f52..97ddc6c203b7 100644 --- a/arch/arm64/include/asm/smp_plat.h +++ b/arch/arm64/include/asm/smp_plat.h @@ -10,6 +10,7 @@ #include <linux/cpumask.h> +#include <asm/smp.h> #include <asm/types.h> struct mpidr_hash { diff --git a/arch/arm64/include/uapi/asm/unistd.h b/arch/arm64/include/uapi/asm/unistd.h index f83a70e07df8..ce2ee8f1e361 100644 --- a/arch/arm64/include/uapi/asm/unistd.h +++ b/arch/arm64/include/uapi/asm/unistd.h @@ -20,5 +20,6 @@ #define __ARCH_WANT_SET_GET_RLIMIT #define __ARCH_WANT_TIME32_SYSCALLS #define __ARCH_WANT_SYS_CLONE3 +#define __ARCH_WANT_MEMFD_SECRET #include <asm-generic/unistd.h> diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index cce308586fcc..3f1490bfb938 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -17,7 +17,7 @@ CFLAGS_syscall.o += -fno-stack-protector # It's not safe to invoke KCOV when portions of the kernel environment aren't # available or are out-of-sync with HW state. Since `noinstr` doesn't always # inhibit KCOV instrumentation, disable it for the entire compilation unit. -KCOV_INSTRUMENT_entry.o := n +KCOV_INSTRUMENT_entry-common.o := n KCOV_INSTRUMENT_idle.o := n # Object file lists. diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 125d5c9471ac..0ead8bfedf20 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -81,6 +81,7 @@ #include <asm/mmu_context.h> #include <asm/mte.h> #include <asm/processor.h> +#include <asm/smp.h> #include <asm/sysreg.h> #include <asm/traps.h> #include <asm/virt.h> diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c index 12ce14a98b7c..db8b2e2d02c2 100644 --- a/arch/arm64/kernel/entry-common.c +++ b/arch/arm64/kernel/entry-common.c @@ -604,7 +604,7 @@ asmlinkage void noinstr el0t_64_fiq_handler(struct pt_regs *regs) __el0_fiq_handler_common(regs); } -static void __el0_error_handler_common(struct pt_regs *regs) +static void noinstr __el0_error_handler_common(struct pt_regs *regs) { unsigned long esr = read_sysreg(esr_el1); diff --git a/arch/arm64/kernel/machine_kexec.c b/arch/arm64/kernel/machine_kexec.c index 03ceabe4d912..213d56c14f60 100644 --- a/arch/arm64/kernel/machine_kexec.c +++ b/arch/arm64/kernel/machine_kexec.c @@ -11,6 +11,7 @@ #include <linux/kernel.h> #include <linux/kexec.h> #include <linux/page-flags.h> +#include <linux/set_memory.h> #include <linux/smp.h> #include <asm/cacheflush.h> diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c index 69b3fde8759e..36f51b0e438a 100644 --- a/arch/arm64/kernel/mte.c +++ b/arch/arm64/kernel/mte.c @@ -193,18 +193,6 @@ void mte_check_tfsr_el1(void) } #endif -static void update_gcr_el1_excl(u64 excl) -{ - - /* - * Note that the mask controlled by the user via prctl() is an - * include while GCR_EL1 accepts an exclude mask. - * No need for ISB since this only affects EL0 currently, implicit - * with ERET. - */ - sysreg_clear_set_s(SYS_GCR_EL1, SYS_GCR_EL1_EXCL_MASK, excl); -} - static void set_gcr_el1_excl(u64 excl) { current->thread.gcr_user_excl = excl; @@ -265,7 +253,8 @@ void mte_suspend_exit(void) if (!system_supports_mte()) return; - update_gcr_el1_excl(gcr_kernel_excl); + sysreg_clear_set_s(SYS_GCR_EL1, SYS_GCR_EL1_EXCL_MASK, gcr_kernel_excl); + isb(); } long set_mte_ctrl(struct task_struct *task, unsigned long arg) diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index 880f40bae60e..be5f85b0a24d 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -293,10 +293,7 @@ u64 cpu_logical_map(unsigned int cpu) void __init __no_sanitize_address setup_arch(char **cmdline_p) { - init_mm.start_code = (unsigned long) _stext; - init_mm.end_code = (unsigned long) _etext; - init_mm.end_data = (unsigned long) _edata; - init_mm.brk = (unsigned long) _end; + setup_initial_init_mm(_stext, _etext, _edata, _end); *cmdline_p = boot_command_line; diff --git a/arch/arm64/kernel/smccc-call.S b/arch/arm64/kernel/smccc-call.S index d3d37f932b97..487381164ff6 100644 --- a/arch/arm64/kernel/smccc-call.S +++ b/arch/arm64/kernel/smccc-call.S @@ -32,20 +32,23 @@ SYM_FUNC_END(__arm_smccc_sve_check) EXPORT_SYMBOL(__arm_smccc_sve_check) .macro SMCCC instr + stp x29, x30, [sp, #-16]! + mov x29, sp alternative_if ARM64_SVE bl __arm_smccc_sve_check alternative_else_nop_endif \instr #0 - ldr x4, [sp] + ldr x4, [sp, #16] stp x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS] stp x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS] - ldr x4, [sp, #8] + ldr x4, [sp, #24] cbz x4, 1f /* no quirk structure */ ldr x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS] cmp x9, #ARM_SMCCC_QUIRK_QCOM_A6 b.ne 1f str x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS] -1: ret +1: ldp x29, x30, [sp], #16 + ret .endm /* diff --git a/arch/arm64/kernel/stacktrace.c b/arch/arm64/kernel/stacktrace.c index b189de5ca6cb..b83c8d911930 100644 --- a/arch/arm64/kernel/stacktrace.c +++ b/arch/arm64/kernel/stacktrace.c @@ -153,7 +153,7 @@ NOKPROBE_SYMBOL(walk_stackframe); static void dump_backtrace_entry(unsigned long where, const char *loglvl) { - printk("%s %pS\n", loglvl, (void *)where); + printk("%s %pSb\n", loglvl, (void *)where); } void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk, diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 3155c9e778f0..0625bf2353c2 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -947,7 +947,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, vma_shift = get_vma_page_shift(vma, hva); } - shared = (vma->vm_flags & VM_PFNMAP); + shared = (vma->vm_flags & VM_SHARED); switch (vma_shift) { #ifndef __PAGETABLE_PMD_FOLDED diff --git a/arch/arm64/lib/copy_from_user.S b/arch/arm64/lib/copy_from_user.S index 95cd62d67371..2cf999e41d30 100644 --- a/arch/arm64/lib/copy_from_user.S +++ b/arch/arm64/lib/copy_from_user.S @@ -29,7 +29,7 @@ .endm .macro ldrh1 reg, ptr, val - user_ldst 9998f, ldtrh, \reg, \ptr, \val + user_ldst 9997f, ldtrh, \reg, \ptr, \val .endm .macro strh1 reg, ptr, val @@ -37,7 +37,7 @@ .endm .macro ldr1 reg, ptr, val - user_ldst 9998f, ldtr, \reg, \ptr, \val + user_ldst 9997f, ldtr, \reg, \ptr, \val .endm .macro str1 reg, ptr, val @@ -45,7 +45,7 @@ .endm .macro ldp1 reg1, reg2, ptr, val - user_ldp 9998f, \reg1, \reg2, \ptr, \val + user_ldp 9997f, \reg1, \reg2, \ptr, \val .endm .macro stp1 reg1, reg2, ptr, val @@ -53,8 +53,10 @@ .endm end .req x5 +srcin .req x15 SYM_FUNC_START(__arch_copy_from_user) add end, x0, x2 + mov srcin, x1 #include "copy_template.S" mov x0, #0 // Nothing to copy ret @@ -63,6 +65,11 @@ EXPORT_SYMBOL(__arch_copy_from_user) .section .fixup,"ax" .align 2 +9997: cmp dst, dstin + b.ne 9998f + // Before being absolutely sure we couldn't copy anything, try harder +USER(9998f, ldtrb tmp1w, [srcin]) + strb tmp1w, [dst], #1 9998: sub x0, end, dst // bytes not copied ret .previous diff --git a/arch/arm64/lib/copy_in_user.S b/arch/arm64/lib/copy_in_user.S index 1f61cd0df062..dbea3799c3ef 100644 --- a/arch/arm64/lib/copy_in_user.S +++ b/arch/arm64/lib/copy_in_user.S @@ -30,33 +30,34 @@ .endm .macro ldrh1 reg, ptr, val - user_ldst 9998f, ldtrh, \reg, \ptr, \val + user_ldst 9997f, ldtrh, \reg, \ptr, \val .endm .macro strh1 reg, ptr, val - user_ldst 9998f, sttrh, \reg, \ptr, \val + user_ldst 9997f, sttrh, \reg, \ptr, \val .endm .macro ldr1 reg, ptr, val - user_ldst 9998f, ldtr, \reg, \ptr, \val + user_ldst 9997f, ldtr, \reg, \ptr, \val .endm .macro str1 reg, ptr, val - user_ldst 9998f, sttr, \reg, \ptr, \val + user_ldst 9997f, sttr, \reg, \ptr, \val .endm .macro ldp1 reg1, reg2, ptr, val - user_ldp 9998f, \reg1, \reg2, \ptr, \val + user_ldp 9997f, \reg1, \reg2, \ptr, \val .endm .macro stp1 reg1, reg2, ptr, val - user_stp 9998f, \reg1, \reg2, \ptr, \val + user_stp 9997f, \reg1, \reg2, \ptr, \val .endm end .req x5 - +srcin .req x15 SYM_FUNC_START(__arch_copy_in_user) add end, x0, x2 + mov srcin, x1 #include "copy_template.S" mov x0, #0 ret @@ -65,6 +66,12 @@ EXPORT_SYMBOL(__arch_copy_in_user) .section .fixup,"ax" .align 2 +9997: cmp dst, dstin + b.ne 9998f + // Before being absolutely sure we couldn't copy anything, try harder +USER(9998f, ldtrb tmp1w, [srcin]) +USER(9998f, sttrb tmp1w, [dst]) + add dst, dst, #1 9998: sub x0, end, dst // bytes not copied ret .previous diff --git a/arch/arm64/lib/copy_to_user.S b/arch/arm64/lib/copy_to_user.S index 043da90f5dd7..9f380eecf653 100644 --- a/arch/arm64/lib/copy_to_user.S +++ b/arch/arm64/lib/copy_to_user.S @@ -32,7 +32,7 @@ .endm .macro strh1 reg, ptr, val - user_ldst 9998f, sttrh, \reg, \ptr, \val + user_ldst 9997f, sttrh, \reg, \ptr, \val .endm .macro ldr1 reg, ptr, val @@ -40,7 +40,7 @@ .endm .macro str1 reg, ptr, val - user_ldst 9998f, sttr, \reg, \ptr, \val + user_ldst 9997f, sttr, \reg, \ptr, \val .endm .macro ldp1 reg1, reg2, ptr, val @@ -48,12 +48,14 @@ .endm .macro stp1 reg1, reg2, ptr, val - user_stp 9998f, \reg1, \reg2, \ptr, \val + user_stp 9997f, \reg1, \reg2, \ptr, \val .endm end .req x5 +srcin .req x15 SYM_FUNC_START(__arch_copy_to_user) add end, x0, x2 + mov srcin, x1 #include "copy_template.S" mov x0, #0 ret @@ -62,6 +64,12 @@ EXPORT_SYMBOL(__arch_copy_to_user) .section .fixup,"ax" .align 2 +9997: cmp dst, dstin + b.ne 9998f + // Before being absolutely sure we couldn't copy anything, try harder + ldrb tmp1w, [srcin] +USER(9998f, sttrb tmp1w, [dst]) + add dst, dst, #1 9998: sub x0, end, dst // bytes not copied ret .previous diff --git a/arch/arm64/lib/strlen.S b/arch/arm64/lib/strlen.S index 35fbdb7d6e1a..1648790e91b3 100644 --- a/arch/arm64/lib/strlen.S +++ b/arch/arm64/lib/strlen.S @@ -8,6 +8,7 @@ #include <linux/linkage.h> #include <asm/assembler.h> +#include <asm/mte-def.h> /* Assumptions: * @@ -42,7 +43,16 @@ #define REP8_7f 0x7f7f7f7f7f7f7f7f #define REP8_80 0x8080808080808080 +/* + * When KASAN_HW_TAGS is in use, memory is checked at MTE_GRANULE_SIZE + * (16-byte) granularity, and we must ensure that no access straddles this + * alignment boundary. + */ +#ifdef CONFIG_KASAN_HW_TAGS +#define MIN_PAGE_SIZE MTE_GRANULE_SIZE +#else #define MIN_PAGE_SIZE 4096 +#endif /* Since strings are short on average, we check the first 16 bytes of the string for a NUL character. In order to do an unaligned ldp diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 595fde9a47dd..9ff0de1b2b93 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -22,6 +22,7 @@ #include <linux/io.h> #include <linux/mm.h> #include <linux/vmalloc.h> +#include <linux/set_memory.h> #include <asm/barrier.h> #include <asm/cputype.h> @@ -515,8 +516,7 @@ static void __init map_mem(pgd_t *pgdp) */ BUILD_BUG_ON(pgd_index(direct_map_end - 1) == pgd_index(direct_map_end)); - if (rodata_full || crash_mem_map || debug_pagealloc_enabled() || - IS_ENABLED(CONFIG_KFENCE)) + if (can_set_direct_map() || crash_mem_map || IS_ENABLED(CONFIG_KFENCE)) flags |= NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; /* @@ -1339,7 +1339,6 @@ void *__init fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t prot) return dt_virt; } -#if CONFIG_PGTABLE_LEVELS > 3 int pud_set_huge(pud_t *pudp, phys_addr_t phys, pgprot_t prot) { pud_t new_pud = pfn_pud(__phys_to_pfn(phys), mk_pud_sect_prot(prot)); @@ -1354,16 +1353,6 @@ int pud_set_huge(pud_t *pudp, phys_addr_t phys, pgprot_t prot) return 1; } -int pud_clear_huge(pud_t *pudp) -{ - if (!pud_sect(READ_ONCE(*pudp))) - return 0; - pud_clear(pudp); - return 1; -} -#endif - -#if CONFIG_PGTABLE_LEVELS > 2 int pmd_set_huge(pmd_t *pmdp, phys_addr_t phys, pgprot_t prot) { pmd_t new_pmd = pfn_pmd(__phys_to_pfn(phys), mk_pmd_sect_prot(prot)); @@ -1378,6 +1367,14 @@ int pmd_set_huge(pmd_t *pmdp, phys_addr_t phys, pgprot_t prot) return 1; } +int pud_clear_huge(pud_t *pudp) +{ + if (!pud_sect(READ_ONCE(*pudp))) + return 0; + pud_clear(pudp); + return 1; +} + int pmd_clear_huge(pmd_t *pmdp) { if (!pmd_sect(READ_ONCE(*pmdp))) @@ -1385,7 +1382,6 @@ int pmd_clear_huge(pmd_t *pmdp) pmd_clear(pmdp); return 1; } -#endif int pmd_free_pte_page(pmd_t *pmdp, unsigned long addr) { @@ -1489,8 +1485,7 @@ int arch_add_memory(int nid, u64 start, u64 size, * KFENCE requires linear map to be mapped at page granularity, so that * it is possible to protect/unprotect single pages in the KFENCE pool. */ - if (rodata_full || debug_pagealloc_enabled() || - IS_ENABLED(CONFIG_KFENCE)) + if (can_set_direct_map() || IS_ENABLED(CONFIG_KFENCE)) flags |= NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; __create_pgd_mapping(swapper_pg_dir, start, __phys_to_virt(start), diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c index 92eccaf595c8..a3bacd79507a 100644 --- a/arch/arm64/mm/pageattr.c +++ b/arch/arm64/mm/pageattr.c @@ -19,6 +19,11 @@ struct page_change_data { bool rodata_full __ro_after_init = IS_ENABLED(CONFIG_RODATA_FULL_DEFAULT_ENABLED); +bool can_set_direct_map(void) +{ + return rodata_full || debug_pagealloc_enabled(); +} + static int change_page_range(pte_t *ptep, unsigned long addr, void *data) { struct page_change_data *cdata = data; @@ -155,7 +160,7 @@ int set_direct_map_invalid_noflush(struct page *page) .clear_mask = __pgprot(PTE_VALID), }; - if (!debug_pagealloc_enabled() && !rodata_full) + if (!can_set_direct_map()) return 0; return apply_to_page_range(&init_mm, @@ -170,7 +175,7 @@ int set_direct_map_default_noflush(struct page *page) .clear_mask = __pgprot(PTE_RDONLY), }; - if (!debug_pagealloc_enabled() && !rodata_full) + if (!can_set_direct_map()) return 0; return apply_to_page_range(&init_mm, @@ -181,7 +186,7 @@ int set_direct_map_default_noflush(struct page *page) #ifdef CONFIG_DEBUG_PAGEALLOC void __kernel_map_pages(struct page *page, int numpages, int enable) { - if (!debug_pagealloc_enabled() && !rodata_full) + if (!can_set_direct_map()) return; set_memory_valid((unsigned long)page_address(page), numpages, enable); @@ -206,7 +211,7 @@ bool kernel_page_present(struct page *page) pte_t *ptep; unsigned long addr = (unsigned long)page_address(page); - if (!debug_pagealloc_enabled() && !rodata_full) + if (!can_set_direct_map()) return true; pgdp = pgd_offset_k(addr); diff --git a/arch/csky/Kbuild b/arch/csky/Kbuild new file mode 100644 index 000000000000..a4e40e534e6a --- /dev/null +++ b/arch/csky/Kbuild @@ -0,0 +1 @@ +# SPDX-License-Identifier: GPL-2.0-only diff --git a/arch/csky/kernel/setup.c b/arch/csky/kernel/setup.c index e93bc6f74432..c64e7be2045b 100644 --- a/arch/csky/kernel/setup.c +++ b/arch/csky/kernel/setup.c @@ -78,10 +78,7 @@ void __init setup_arch(char **cmdline_p) pr_info("Phys. mem: %ldMB\n", (unsigned long) memblock_phys_mem_size()/1024/1024); - init_mm.start_code = (unsigned long) _stext; - init_mm.end_code = (unsigned long) _etext; - init_mm.end_data = (unsigned long) _edata; - init_mm.brk = (unsigned long) _end; + setup_initial_init_mm(_stext, _etext, _edata, _end); parse_early_param(); diff --git a/arch/h8300/Kbuild b/arch/h8300/Kbuild new file mode 100644 index 000000000000..b2583e7efbd1 --- /dev/null +++ b/arch/h8300/Kbuild @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += kernel/ mm/ boot/dts/ diff --git a/arch/h8300/Makefile b/arch/h8300/Makefile index ba0f26cfad61..eb4cb8f6830c 100644 --- a/arch/h8300/Makefile +++ b/arch/h8300/Makefile @@ -30,9 +30,6 @@ ifeq ($(CROSS_COMPILE),) CROSS_COMPILE := $(call cc-cross-prefix, h8300-unknown-linux- h8300-linux-) endif -core-y += arch/$(ARCH)/kernel/ arch/$(ARCH)/mm/ -core-y += arch/$(ARCH)/boot/dts/ - libs-y += arch/$(ARCH)/lib/ boot := arch/h8300/boot diff --git a/arch/h8300/kernel/setup.c b/arch/h8300/kernel/setup.c index c3590b2e9592..61091a76eb7e 100644 --- a/arch/h8300/kernel/setup.c +++ b/arch/h8300/kernel/setup.c @@ -95,10 +95,7 @@ void __init setup_arch(char **cmdline_p) { unflatten_and_copy_device_tree(); - init_mm.start_code = (unsigned long) _stext; - init_mm.end_code = (unsigned long) _etext; - init_mm.end_data = (unsigned long) _edata; - init_mm.brk = (unsigned long) 0; + setup_initial_init_mm(_stext, _etext, _edata, NULL); pr_notice("\r\n\nuClinux " CPU "\n"); pr_notice("Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne\n"); diff --git a/arch/hexagon/Kbuild b/arch/hexagon/Kbuild new file mode 100644 index 000000000000..8421baba1351 --- /dev/null +++ b/arch/hexagon/Kbuild @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += kernel/ mm/ lib/ diff --git a/arch/hexagon/Kconfig b/arch/hexagon/Kconfig index 44a409967af1..e5a852080730 100644 --- a/arch/hexagon/Kconfig +++ b/arch/hexagon/Kconfig @@ -30,6 +30,7 @@ config HEXAGON select MODULES_USE_ELF_RELA select GENERIC_CPU_DEVICES select SET_FS + select ARCH_WANT_LD_ORPHAN_WARN help Qualcomm Hexagon is a processor architecture designed for high performance and low power across a wide variety of applications. diff --git a/arch/hexagon/Makefile b/arch/hexagon/Makefile index 74b644ea8a00..44312bc147d8 100644 --- a/arch/hexagon/Makefile +++ b/arch/hexagon/Makefile @@ -34,7 +34,3 @@ KBUILD_CFLAGS += -ffixed-$(TIR_NAME) -DTHREADINFO_REG=$(TIR_NAME) -D__linux__ KBUILD_AFLAGS += -DTHREADINFO_REG=$(TIR_NAME) head-y := arch/hexagon/kernel/head.o - -core-y += arch/hexagon/kernel/ \ - arch/hexagon/mm/ \ - arch/hexagon/lib/ diff --git a/arch/hexagon/kernel/vmlinux.lds.S b/arch/hexagon/kernel/vmlinux.lds.S index 35b18e55eae8..57465bff1fe4 100644 --- a/arch/hexagon/kernel/vmlinux.lds.S +++ b/arch/hexagon/kernel/vmlinux.lds.S @@ -38,6 +38,8 @@ SECTIONS .text : AT(ADDR(.text)) { _text = .; TEXT_TEXT + IRQENTRY_TEXT + SOFTIRQENTRY_TEXT SCHED_TEXT CPUIDLE_TEXT LOCK_TEXT @@ -59,14 +61,9 @@ SECTIONS _end = .; - /DISCARD/ : { - EXIT_TEXT - EXIT_DATA - EXIT_CALL - } - STABS_DEBUG DWARF_DEBUG ELF_DETAILS + DISCARDS } diff --git a/arch/ia64/Kbuild b/arch/ia64/Kbuild new file mode 100644 index 000000000000..a4e40e534e6a --- /dev/null +++ b/arch/ia64/Kbuild @@ -0,0 +1 @@ +# SPDX-License-Identifier: GPL-2.0-only diff --git a/arch/ia64/include/asm/pgtable.h b/arch/ia64/include/asm/pgtable.h index 3f5dbbd8b9d8..9584b2c5f394 100644 --- a/arch/ia64/include/asm/pgtable.h +++ b/arch/ia64/include/asm/pgtable.h @@ -273,7 +273,7 @@ ia64_phys_addr_valid (unsigned long addr) #define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud))) #define pud_present(pud) (pud_val(pud) != 0UL) #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) -#define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & _PFN_MASK)) +#define pud_pgtable(pud) ((pmd_t *) __va(pud_val(pud) & _PFN_MASK)) #define pud_page(pud) virt_to_page((pud_val(pud) + PAGE_OFFSET)) #if CONFIG_PGTABLE_LEVELS == 4 @@ -281,7 +281,7 @@ ia64_phys_addr_valid (unsigned long addr) #define p4d_bad(p4d) (!ia64_phys_addr_valid(p4d_val(p4d))) #define p4d_present(p4d) (p4d_val(p4d) != 0UL) #define p4d_clear(p4dp) (p4d_val(*(p4dp)) = 0UL) -#define p4d_page_vaddr(p4d) ((unsigned long) __va(p4d_val(p4d) & _PFN_MASK)) +#define p4d_pgtable(p4d) ((pud_t *) __va(p4d_val(p4d) & _PFN_MASK)) #define p4d_page(p4d) virt_to_page((p4d_val(p4d) + PAGE_OFFSET)) #endif diff --git a/arch/m68k/Kconfig.machine b/arch/m68k/Kconfig.machine index d964c1f27399..6a07a6817885 100644 --- a/arch/m68k/Kconfig.machine +++ b/arch/m68k/Kconfig.machine @@ -33,6 +33,7 @@ config MAC depends on MMU select MMU_MOTOROLA if MMU select HAVE_ARCH_NVRAM_OPS + select HAVE_PATA_PLATFORM select LEGACY_TIMER_TICK help This option enables support for the Apple Macintosh series of diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index c54055a3d284..dd0c0ec67f67 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile @@ -97,7 +97,6 @@ head-$(CONFIG_SUN3) := arch/m68k/kernel/sun3-head.o head-$(CONFIG_M68000) := arch/m68k/68000/head.o head-$(CONFIG_COLDFIRE) := arch/m68k/coldfire/head.o -core-y += arch/m68k/ libs-y += arch/m68k/lib/ diff --git a/arch/m68k/coldfire/m525x.c b/arch/m68k/coldfire/m525x.c index 2c4d2ca2f20d..485375112e28 100644 --- a/arch/m68k/coldfire/m525x.c +++ b/arch/m68k/coldfire/m525x.c @@ -26,7 +26,7 @@ DEFINE_CLK(pll, "pll.0", MCF_CLK); DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); static struct clk_lookup m525x_clk_lookup[] = { - CLKDEV_INIT(NULL, "pll.0", &pll), + CLKDEV_INIT(NULL, "pll.0", &clk_pll), CLKDEV_INIT(NULL, "sys.0", &clk_sys), CLKDEV_INIT("mcftmr.0", NULL, &clk_sys), CLKDEV_INIT("mcftmr.1", NULL, &clk_sys), diff --git a/arch/m68k/include/asm/motorola_pgtable.h b/arch/m68k/include/asm/motorola_pgtable.h index a2908164ee6f..022c3abc280d 100644 --- a/arch/m68k/include/asm/motorola_pgtable.h +++ b/arch/m68k/include/asm/motorola_pgtable.h @@ -131,7 +131,7 @@ static inline void pud_set(pud_t *pudp, pmd_t *pmdp) #define __pte_page(pte) ((unsigned long)__va(pte_val(pte) & PAGE_MASK)) #define pmd_page_vaddr(pmd) ((unsigned long)__va(pmd_val(pmd) & _TABLE_MASK)) -#define pud_page_vaddr(pud) ((unsigned long)__va(pud_val(pud) & _TABLE_MASK)) +#define pud_pgtable(pud) ((pmd_t *)__va(pud_val(pud) & _TABLE_MASK)) #define pte_none(pte) (!pte_val(pte)) diff --git a/arch/m68k/kernel/setup_mm.c b/arch/m68k/kernel/setup_mm.c index 017bac3aab80..4b51bfd38e5f 100644 --- a/arch/m68k/kernel/setup_mm.c +++ b/arch/m68k/kernel/setup_mm.c @@ -258,10 +258,7 @@ void __init setup_arch(char **cmdline_p) } } - init_mm.start_code = PAGE_OFFSET; - init_mm.end_code = (unsigned long)_etext; - init_mm.end_data = (unsigned long)_edata; - init_mm.brk = (unsigned long)_end; + setup_initial_init_mm((void *)PAGE_OFFSET, _etext, _edata, _end); #if defined(CONFIG_BOOTPARAM) strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE); diff --git a/arch/m68k/kernel/setup_no.c b/arch/m68k/kernel/setup_no.c index d1b7988efc91..5e4104f07a44 100644 --- a/arch/m68k/kernel/setup_no.c +++ b/arch/m68k/kernel/setup_no.c @@ -87,10 +87,7 @@ void __init setup_arch(char **cmdline_p) memory_start = PAGE_ALIGN(_ramstart); memory_end = _ramend; - init_mm.start_code = (unsigned long) &_stext; - init_mm.end_code = (unsigned long) &_etext; - init_mm.end_data = (unsigned long) &_edata; - init_mm.brk = (unsigned long) 0; + setup_initial_init_mm(_stext, _etext, _edata, NULL); config_BSP(&command_line[0], sizeof(command_line)); diff --git a/arch/microblaze/Kbuild b/arch/microblaze/Kbuild new file mode 100644 index 000000000000..a4e40e534e6a --- /dev/null +++ b/arch/microblaze/Kbuild @@ -0,0 +1 @@ +# SPDX-License-Identifier: GPL-2.0-only diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 258234c35a09..4e942b7ef022 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -332,9 +332,6 @@ head-y := arch/mips/kernel/head.o libs-y += arch/mips/lib/ libs-$(CONFIG_MIPS_FP_SUPPORT) += arch/mips/math-emu/ -# See arch/mips/Kbuild for content of core part of the kernel -core-y += arch/mips/ - drivers-y += arch/mips/crypto/ # suspend and hibernation support diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index e4b7839293e1..3548b3b45269 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips/boot/compressed/Makefile @@ -40,7 +40,7 @@ GCOV_PROFILE := n UBSAN_SANITIZE := n # decompressor objects (linked with vmlinuz) -vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o +vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o $(obj)/bswapsi.o ifdef CONFIG_DEBUG_ZBOOT vmlinuzobjs-$(CONFIG_DEBUG_ZBOOT) += $(obj)/dbg.o @@ -54,7 +54,7 @@ extra-y += uart-ath79.c $(obj)/uart-ath79.c: $(srctree)/arch/mips/ath79/early_printk.c $(call cmd,shipped) -vmlinuzobjs-$(CONFIG_KERNEL_XZ) += $(obj)/ashldi3.o $(obj)/bswapsi.o +vmlinuzobjs-$(CONFIG_KERNEL_XZ) += $(obj)/ashldi3.o extra-y += ashldi3.c $(obj)/ashldi3.c: $(obj)/%.c: $(srctree)/lib/%.c FORCE diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c index 3d70d15ada28..aae1346a509a 100644 --- a/arch/mips/boot/compressed/decompress.c +++ b/arch/mips/boot/compressed/decompress.c @@ -7,6 +7,8 @@ * Author: Wu Zhangjin <wuzhangjin@gmail.com> */ +#define DISABLE_BRANCH_PROFILING + #include <linux/types.h> #include <linux/kernel.h> #include <linux/string.h> diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h index 08f9dd6903b7..86310d6e1035 100644 --- a/arch/mips/include/asm/fpu.h +++ b/arch/mips/include/asm/fpu.h @@ -76,7 +76,7 @@ static inline int __enable_fpu(enum fpu_mode mode) /* we only have a 32-bit FPU */ return SIGFPE; #endif - fallthrough; + /* fallthrough */ case FPU_32BIT: if (cpu_has_fre) { /* clear FRE */ diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index d1477ecb1af9..57561e0e6e8d 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -57,6 +57,9 @@ asmlinkage void plat_irq_dispatch(void); extern void do_IRQ(unsigned int irq); +struct irq_domain; +extern void do_domain_IRQ(struct irq_domain *domain, unsigned int irq); + extern void arch_init_irq(void); extern void spurious_interrupt(void); diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index 046465906c82..41921acdc9d8 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -209,9 +209,9 @@ static inline void p4d_clear(p4d_t *p4dp) p4d_val(*p4dp) = (unsigned long)invalid_pud_table; } -static inline unsigned long p4d_page_vaddr(p4d_t p4d) +static inline pud_t *p4d_pgtable(p4d_t p4d) { - return p4d_val(p4d); + return (pud_t *)p4d_val(p4d); } #define p4d_phys(p4d) virt_to_phys((void *)p4d_val(p4d)) @@ -313,9 +313,9 @@ static inline void pud_clear(pud_t *pudp) #endif #ifndef __PAGETABLE_PMD_FOLDED -static inline unsigned long pud_page_vaddr(pud_t pud) +static inline pmd_t *pud_pgtable(pud_t pud) { - return pud_val(pud); + return (pmd_t *)pud_val(pud); } #define pud_phys(pud) virt_to_phys((void *)pud_val(pud)) #define pud_page(pud) (pfn_to_page(pud_phys(pud) >> PAGE_SHIFT)) diff --git a/arch/mips/include/asm/vdso/vdso.h b/arch/mips/include/asm/vdso/vdso.h index 737ddfc3411c..a327ca21270e 100644 --- a/arch/mips/include/asm/vdso/vdso.h +++ b/arch/mips/include/asm/vdso/vdso.h @@ -67,7 +67,7 @@ static inline const struct vdso_data *get_vdso_data(void) static inline void __iomem *get_gic(const struct vdso_data *data) { - return (void __iomem *)data - PAGE_SIZE; + return (void __iomem *)((unsigned long)data & PAGE_MASK) - PAGE_SIZE; } #endif /* CONFIG_CLKSRC_MIPS_GIC */ diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 85b6c60f285d..d20e002b3246 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -21,6 +21,7 @@ #include <linux/kallsyms.h> #include <linux/kgdb.h> #include <linux/ftrace.h> +#include <linux/irqdomain.h> #include <linux/atomic.h> #include <linux/uaccess.h> @@ -107,3 +108,18 @@ void __irq_entry do_IRQ(unsigned int irq) irq_exit(); } +#ifdef CONFIG_IRQ_DOMAIN +void __irq_entry do_domain_IRQ(struct irq_domain *domain, unsigned int hwirq) +{ + struct irq_desc *desc; + + irq_enter(); + check_stack_overflow(); + + desc = irq_resolve_mapping(domain, hwirq); + if (likely(desc)) + handle_irq_desc(desc); + + irq_exit(); +} +#endif diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index cd4afcdf3725..9adad24c2e65 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1383,6 +1383,7 @@ static void build_r4000_tlb_refill_handler(void) switch (boot_cpu_type()) { default: if (sizeof(long) == 4) { + fallthrough; case CPU_LOONGSON2EF: /* Loongson2 ebase is different than r4k, we have more space */ if ((p - tlb_handler) > 64) @@ -2169,6 +2170,7 @@ static void build_r4000_tlb_load_handler(void) default: if (cpu_has_mips_r2_exec_hazard) { uasm_i_ehb(&p); + fallthrough; case CPU_CAVIUM_OCTEON: case CPU_CAVIUM_OCTEON_PLUS: diff --git a/arch/nds32/Kbuild b/arch/nds32/Kbuild new file mode 100644 index 000000000000..a4e40e534e6a --- /dev/null +++ b/arch/nds32/Kbuild @@ -0,0 +1 @@ +# SPDX-License-Identifier: GPL-2.0-only diff --git a/arch/nds32/boot/.gitignore b/arch/nds32/boot/.gitignore new file mode 100644 index 000000000000..9182a3a1ea0a --- /dev/null +++ b/arch/nds32/boot/.gitignore @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +/Image diff --git a/arch/nds32/kernel/setup.c b/arch/nds32/kernel/setup.c index af82e996f412..41725eaf8bac 100644 --- a/arch/nds32/kernel/setup.c +++ b/arch/nds32/kernel/setup.c @@ -294,10 +294,7 @@ void __init setup_arch(char **cmdline_p) setup_cpuinfo(); - init_mm.start_code = (unsigned long)&_stext; - init_mm.end_code = (unsigned long)&_etext; - init_mm.end_data = (unsigned long)&_edata; - init_mm.brk = (unsigned long)&_end; + setup_initial_init_mm(_stext, _etext, _edata, _end); /* setup bootmem allocator */ setup_memory(); diff --git a/arch/nds32/mm/mmap.c b/arch/nds32/mm/mmap.c index c206b31ce07a..1bdf5e7d1b43 100644 --- a/arch/nds32/mm/mmap.c +++ b/arch/nds32/mm/mmap.c @@ -59,7 +59,7 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr, vma = find_vma(mm, addr); if (TASK_SIZE - len >= addr && - (!vma || addr + len <= vma->vm_start)) + (!vma || addr + len <= vm_start_gap(vma))) return addr; } diff --git a/arch/nios2/Kbuild b/arch/nios2/Kbuild new file mode 100644 index 000000000000..a4e40e534e6a --- /dev/null +++ b/arch/nios2/Kbuild @@ -0,0 +1 @@ +# SPDX-License-Identifier: GPL-2.0-only diff --git a/arch/nios2/kernel/setup.c b/arch/nios2/kernel/setup.c index d2f21957e99c..cf8d687a2644 100644 --- a/arch/nios2/kernel/setup.c +++ b/arch/nios2/kernel/setup.c @@ -156,10 +156,7 @@ void __init setup_arch(char **cmdline_p) memory_start = memblock_start_of_DRAM(); memory_end = memblock_end_of_DRAM(); - init_mm.start_code = (unsigned long) _stext; - init_mm.end_code = (unsigned long) _etext; - init_mm.end_data = (unsigned long) _edata; - init_mm.brk = (unsigned long) _end; + setup_initial_init_mm(_stext, _etext, _edata, _end); init_task.thread.kregs = &fake_regs; /* Keep a copy of command line */ diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile index 410e7abfac69..c52de526e518 100644 --- a/arch/openrisc/Makefile +++ b/arch/openrisc/Makefile @@ -42,7 +42,6 @@ endif head-y := arch/openrisc/kernel/head.o -core-y += arch/openrisc/ libs-y += $(LIBGCC) PHONY += vmlinux.bin diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c index c6f9e7b9f7cb..8ae2da6ac097 100644 --- a/arch/openrisc/kernel/setup.c +++ b/arch/openrisc/kernel/setup.c @@ -293,10 +293,7 @@ void __init setup_arch(char **cmdline_p) #endif /* process 1's initial memory region is the kernel code/data */ - init_mm.start_code = (unsigned long)_stext; - init_mm.end_code = (unsigned long)_etext; - init_mm.end_data = (unsigned long)_edata; - init_mm.brk = (unsigned long)_end; + setup_initial_init_mm(_stext, _etext, _edata, _end); #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start == initrd_end) { diff --git a/arch/parisc/Kbuild b/arch/parisc/Kbuild new file mode 100644 index 000000000000..a4e40e534e6a --- /dev/null +++ b/arch/parisc/Kbuild @@ -0,0 +1 @@ +# SPDX-License-Identifier: GPL-2.0-only diff --git a/arch/parisc/include/asm/pgtable.h b/arch/parisc/include/asm/pgtable.h index 7f33c29764cc..43937af127b1 100644 --- a/arch/parisc/include/asm/pgtable.h +++ b/arch/parisc/include/asm/pgtable.h @@ -322,8 +322,8 @@ static inline void pmd_clear(pmd_t *pmd) { #if CONFIG_PGTABLE_LEVELS == 3 -#define pud_page_vaddr(pud) ((unsigned long) __va(pud_address(pud))) -#define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud)) +#define pud_pgtable(pud) ((pmd_t *) __va(pud_address(pud))) +#define pud_page(pud) virt_to_page((void *)pud_pgtable(pud)) /* For 64 bit we have three level tables */ diff --git a/arch/parisc/kernel/syscalls/Makefile b/arch/parisc/kernel/syscalls/Makefile index 0f2ea5bcb0d7..d63f18dd058d 100644 --- a/arch/parisc/kernel/syscalls/Makefile +++ b/arch/parisc/kernel/syscalls/Makefile @@ -10,25 +10,15 @@ syshdr := $(srctree)/scripts/syscallhdr.sh systbl := $(srctree)/scripts/syscalltbl.sh quiet_cmd_syshdr = SYSHDR $@ - cmd_syshdr = $(CONFIG_SHELL) $(syshdr) --emit-nr --abis $(abis) $< $@ + cmd_syshdr = $(CONFIG_SHELL) $(syshdr) --emit-nr --abis common,$* $< $@ quiet_cmd_systbl = SYSTBL $@ - cmd_systbl = $(CONFIG_SHELL) $(systbl) --abis $(abis) $< $@ + cmd_systbl = $(CONFIG_SHELL) $(systbl) --abis common,$* $< $@ -$(uapi)/unistd_32.h: abis := common,32 -$(uapi)/unistd_32.h: $(syscall) $(syshdr) FORCE +$(uapi)/unistd_%.h: $(syscall) $(syshdr) FORCE $(call if_changed,syshdr) -$(uapi)/unistd_64.h: abis := common,64 -$(uapi)/unistd_64.h: $(syscall) $(syshdr) FORCE - $(call if_changed,syshdr) - -$(kapi)/syscall_table_32.h: abis := common,32 -$(kapi)/syscall_table_32.h: $(syscall) $(systbl) FORCE - $(call if_changed,systbl) - -$(kapi)/syscall_table_64.h: abis := common,64 -$(kapi)/syscall_table_64.h: $(syscall) $(systbl) FORCE +$(kapi)/syscall_table_%.h: $(syscall) $(systbl) FORCE $(call if_changed,systbl) uapisyshdr-y += unistd_32.h unistd_64.h diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index 712c5e8768ce..6505d66f1193 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -267,9 +267,6 @@ head-$(CONFIG_PPC_FPU) += arch/powerpc/kernel/fpu.o head-$(CONFIG_ALTIVEC) += arch/powerpc/kernel/vector.o head-$(CONFIG_PPC_OF_BOOT_TRAMPOLINE) += arch/powerpc/kernel/prom_init.o -# See arch/powerpc/Kbuild for content of core part of the kernel -core-y += arch/powerpc/ - # Default to zImage, override when needed all: zImage diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h index 4d9941b2fe51..5d34a8646f08 100644 --- a/arch/powerpc/include/asm/book3s/64/pgtable.h +++ b/arch/powerpc/include/asm/book3s/64/pgtable.h @@ -1051,8 +1051,15 @@ extern struct page *p4d_page(p4d_t p4d); /* Pointers in the page table tree are physical addresses */ #define __pgtable_ptr_val(ptr) __pa(ptr) -#define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) -#define p4d_page_vaddr(p4d) __va(p4d_val(p4d) & ~P4D_MASKED_BITS) +static inline pud_t *p4d_pgtable(p4d_t p4d) +{ + return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS); +} + +static inline pmd_t *pud_pgtable(pud_t pud) +{ + return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS); +} #define pte_ERROR(e) \ pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h index a46fd37ad552..77797a2a82eb 100644 --- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h @@ -64,6 +64,8 @@ extern void radix__flush_hugetlb_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); extern void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start, unsigned long end, int psize); +void radix__flush_tlb_pwc_range_psize(struct mm_struct *mm, unsigned long start, + unsigned long end, int psize); extern void radix__flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); extern void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start, diff --git a/arch/powerpc/include/asm/nohash/64/pgtable-4k.h b/arch/powerpc/include/asm/nohash/64/pgtable-4k.h index fe2f4c9acd9e..10f5cf444d72 100644 --- a/arch/powerpc/include/asm/nohash/64/pgtable-4k.h +++ b/arch/powerpc/include/asm/nohash/64/pgtable-4k.h @@ -56,10 +56,14 @@ #define p4d_none(p4d) (!p4d_val(p4d)) #define p4d_bad(p4d) (p4d_val(p4d) == 0) #define p4d_present(p4d) (p4d_val(p4d) != 0) -#define p4d_page_vaddr(p4d) (p4d_val(p4d) & ~P4D_MASKED_BITS) #ifndef __ASSEMBLY__ +static inline pud_t *p4d_pgtable(p4d_t p4d) +{ + return (pud_t *) (p4d_val(p4d) & ~P4D_MASKED_BITS); +} + static inline void p4d_clear(p4d_t *p4dp) { *p4dp = __p4d(0); diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h b/arch/powerpc/include/asm/nohash/64/pgtable.h index 53fbfdfac93d..d081704b13fb 100644 --- a/arch/powerpc/include/asm/nohash/64/pgtable.h +++ b/arch/powerpc/include/asm/nohash/64/pgtable.h @@ -162,7 +162,11 @@ static inline void pud_clear(pud_t *pudp) #define pud_bad(pud) (!is_kernel_addr(pud_val(pud)) \ || (pud_val(pud) & PUD_BAD_BITS)) #define pud_present(pud) (pud_val(pud) != 0) -#define pud_page_vaddr(pud) (pud_val(pud) & ~PUD_MASKED_BITS) + +static inline pmd_t *pud_pgtable(pud_t pud) +{ + return (pmd_t *)(pud_val(pud) & ~PUD_MASKED_BITS); +} extern struct page *pud_page(pud_t pud); diff --git a/arch/powerpc/include/asm/tlb.h b/arch/powerpc/include/asm/tlb.h index 160422a439aa..09a9ae5f3656 100644 --- a/arch/powerpc/include/asm/tlb.h +++ b/arch/powerpc/include/asm/tlb.h @@ -83,5 +83,11 @@ static inline int mm_is_thread_local(struct mm_struct *mm) } #endif +#define arch_supports_page_table_move arch_supports_page_table_move +static inline bool arch_supports_page_table_move(void) +{ + return radix_enabled(); +} + #endif /* __KERNEL__ */ #endif /* __ASM_POWERPC_TLB_H */ diff --git a/arch/powerpc/kernel/interrupt_64.S b/arch/powerpc/kernel/interrupt_64.S index 4063e8a3f704..d4212d2ff0b5 100644 --- a/arch/powerpc/kernel/interrupt_64.S +++ b/arch/powerpc/kernel/interrupt_64.S @@ -311,9 +311,13 @@ END_BTB_FLUSH_SECTION * trace_hardirqs_off(). */ li r11,IRQS_ALL_DISABLED - li r12,-1 /* Set MSR_EE and MSR_RI */ stb r11,PACAIRQSOFTMASK(r13) +#ifdef CONFIG_PPC_BOOK3S + li r12,-1 /* Set MSR_EE and MSR_RI */ mtmsrd r12,1 +#else + wrteei 1 +#endif /* Calling convention has r9 = orig r0, r10 = regs */ mr r9,r0 diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c index 26328fd2990c..aa9c2d01424a 100644 --- a/arch/powerpc/kernel/setup-common.c +++ b/arch/powerpc/kernel/setup-common.c @@ -926,10 +926,7 @@ void __init setup_arch(char **cmdline_p) klp_init_thread_info(&init_task); - init_mm.start_code = (unsigned long)_stext; - init_mm.end_code = (unsigned long) _etext; - init_mm.end_data = (unsigned long) _edata; - init_mm.brk = (unsigned long)_end; + setup_initial_init_mm(_stext, _etext, _edata, _end); mm_iommu_init(&init_mm); irqstack_early_init(); diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index 1d1fcc290fca..085fb8ecbf68 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -2697,8 +2697,10 @@ static int kvmppc_core_vcpu_create_hv(struct kvm_vcpu *vcpu) HFSCR_DSCR | HFSCR_VECVSX | HFSCR_FP | HFSCR_PREFIX; if (cpu_has_feature(CPU_FTR_HVMODE)) { vcpu->arch.hfscr &= mfspr(SPRN_HFSCR); +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM if (cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST)) vcpu->arch.hfscr |= HFSCR_TM; +#endif } if (cpu_has_feature(CPU_FTR_TM_COMP)) vcpu->arch.hfscr |= HFSCR_TM; diff --git a/arch/powerpc/kvm/book3s_hv_nested.c b/arch/powerpc/kvm/book3s_hv_nested.c index 8543ad538b0c..898f942eb198 100644 --- a/arch/powerpc/kvm/book3s_hv_nested.c +++ b/arch/powerpc/kvm/book3s_hv_nested.c @@ -302,6 +302,9 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu) if (vcpu->kvm->arch.l1_ptcr == 0) return H_NOT_AVAILABLE; + if (MSR_TM_TRANSACTIONAL(vcpu->arch.shregs.msr)) + return H_BAD_MODE; + /* copy parameters in */ hv_ptr = kvmppc_get_gpr(vcpu, 4); regs_ptr = kvmppc_get_gpr(vcpu, 5); @@ -322,6 +325,23 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu) if (l2_hv.vcpu_token >= NR_CPUS) return H_PARAMETER; + /* + * L1 must have set up a suspended state to enter the L2 in a + * transactional state, and only in that case. These have to be + * filtered out here to prevent causing a TM Bad Thing in the + * host HRFID. We could synthesize a TM Bad Thing back to the L1 + * here but there doesn't seem like much point. + */ + if (MSR_TM_SUSPENDED(vcpu->arch.shregs.msr)) { + if (!MSR_TM_ACTIVE(l2_regs.msr)) + return H_BAD_MODE; + } else { + if (l2_regs.msr & MSR_TS_MASK) + return H_BAD_MODE; + if (WARN_ON_ONCE(vcpu->arch.shregs.msr & MSR_TS_MASK)) + return H_BAD_MODE; + } + /* translate lpid */ l2 = kvmhv_get_nested(vcpu->kvm, l2_hv.lpid, true); if (!l2) diff --git a/arch/powerpc/kvm/book3s_hv_p9_entry.c b/arch/powerpc/kvm/book3s_hv_p9_entry.c index 83f592eadcd2..961b3d70483c 100644 --- a/arch/powerpc/kvm/book3s_hv_p9_entry.c +++ b/arch/powerpc/kvm/book3s_hv_p9_entry.c @@ -317,6 +317,9 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpc */ mtspr(SPRN_HDEC, hdec); +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM +tm_return_to_guest: +#endif mtspr(SPRN_DAR, vcpu->arch.shregs.dar); mtspr(SPRN_DSISR, vcpu->arch.shregs.dsisr); mtspr(SPRN_SRR0, vcpu->arch.shregs.srr0); @@ -415,11 +418,23 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpc * is in real suspend mode and is trying to transition to * transactional mode. */ - if (local_paca->kvm_hstate.fake_suspend && + if (!local_paca->kvm_hstate.fake_suspend && (vcpu->arch.shregs.msr & MSR_TS_S)) { if (kvmhv_p9_tm_emulation_early(vcpu)) { - /* Prevent it being handled again. */ - trap = 0; + /* + * Go straight back into the guest with the + * new NIP/MSR as set by TM emulation. + */ + mtspr(SPRN_HSRR0, vcpu->arch.regs.nip); + mtspr(SPRN_HSRR1, vcpu->arch.shregs.msr); + + /* + * tm_return_to_guest re-loads SRR0/1, DAR, + * DSISR after RI is cleared, in case they had + * been clobbered by a MCE. + */ + __mtmsrd(0, 1); /* clear RI */ + goto tm_return_to_guest; } } #endif @@ -499,6 +514,10 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpc * If we are in real mode, only switch MMU on after the MMU is * switched to host, to avoid the P9_RADIX_PREFETCH_BUG. */ + if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && + vcpu->arch.shregs.msr & MSR_TS_MASK) + msr |= MSR_TS_S; + __mtmsrd(msr, 0); end_timing(vcpu); diff --git a/arch/powerpc/kvm/book3s_rtas.c b/arch/powerpc/kvm/book3s_rtas.c index c5e677508d3b..0f847f1e5ddd 100644 --- a/arch/powerpc/kvm/book3s_rtas.c +++ b/arch/powerpc/kvm/book3s_rtas.c @@ -242,6 +242,17 @@ int kvmppc_rtas_hcall(struct kvm_vcpu *vcpu) * value so we can restore it on the way out. */ orig_rets = args.rets; + if (be32_to_cpu(args.nargs) >= ARRAY_SIZE(args.args)) { + /* + * Don't overflow our args array: ensure there is room for + * at least rets[0] (even if the call specifies 0 nret). + * + * Each handler must then check for the correct nargs and nret + * values, but they may always return failure in rets[0]. + */ + rc = -EINVAL; + goto fail; + } args.rets = &args.args[be32_to_cpu(args.nargs)]; mutex_lock(&vcpu->kvm->arch.rtas_token_lock); @@ -269,9 +280,17 @@ int kvmppc_rtas_hcall(struct kvm_vcpu *vcpu) fail: /* * We only get here if the guest has called RTAS with a bogus - * args pointer. That means we can't get to the args, and so we - * can't fail the RTAS call. So fail right out to userspace, - * which should kill the guest. + * args pointer or nargs/nret values that would overflow the + * array. That means we can't get to the args, and so we can't + * fail the RTAS call. So fail right out to userspace, which + * should kill the guest. + * + * SLOF should actually pass the hcall return value from the + * rtas handler call in r3, so enter_rtas could be modified to + * return a failure indication in r3 and we could return such + * errors to the guest rather than failing to host userspace. + * However old guests that don't test for failure could then + * continue silently after errors, so for now we won't do this. */ return rc; } diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c index be33b5321a76..b4e6f70b97b9 100644 --- a/arch/powerpc/kvm/powerpc.c +++ b/arch/powerpc/kvm/powerpc.c @@ -2048,9 +2048,9 @@ long kvm_arch_vcpu_ioctl(struct file *filp, { struct kvm_enable_cap cap; r = -EFAULT; - vcpu_load(vcpu); if (copy_from_user(&cap, argp, sizeof(cap))) goto out; + vcpu_load(vcpu); r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); vcpu_put(vcpu); break; @@ -2074,9 +2074,9 @@ long kvm_arch_vcpu_ioctl(struct file *filp, case KVM_DIRTY_TLB: { struct kvm_dirty_tlb dirty; r = -EFAULT; - vcpu_load(vcpu); if (copy_from_user(&dirty, argp, sizeof(dirty))) goto out; + vcpu_load(vcpu); r = kvm_vcpu_ioctl_dirty_tlb(vcpu, &dirty); vcpu_put(vcpu); break; diff --git a/arch/powerpc/mm/book3s64/radix_hugetlbpage.c b/arch/powerpc/mm/book3s64/radix_hugetlbpage.c index cb91071eef52..23d3e08911d3 100644 --- a/arch/powerpc/mm/book3s64/radix_hugetlbpage.c +++ b/arch/powerpc/mm/book3s64/radix_hugetlbpage.c @@ -32,7 +32,13 @@ void radix__flush_hugetlb_tlb_range(struct vm_area_struct *vma, unsigned long st struct hstate *hstate = hstate_file(vma->vm_file); psize = hstate_get_psize(hstate); - radix__flush_tlb_range_psize(vma->vm_mm, start, end, psize); + /* + * Flush PWC even if we get PUD_SIZE hugetlb invalidate to keep this simpler. + */ + if (end - start >= PUD_SIZE) + radix__flush_tlb_pwc_range_psize(vma->vm_mm, start, end, psize); + else + radix__flush_tlb_range_psize(vma->vm_mm, start, end, psize); } /* diff --git a/arch/powerpc/mm/book3s64/radix_pgtable.c b/arch/powerpc/mm/book3s64/radix_pgtable.c index 2176a5f70746..e50ddf129c15 100644 --- a/arch/powerpc/mm/book3s64/radix_pgtable.c +++ b/arch/powerpc/mm/book3s64/radix_pgtable.c @@ -820,7 +820,7 @@ static void __meminit remove_pud_table(pud_t *pud_start, unsigned long addr, continue; } - pmd_base = (pmd_t *)pud_page_vaddr(*pud); + pmd_base = pud_pgtable(*pud); remove_pmd_table(pmd_base, addr, next); free_pmd_table(pmd_base, pud); } @@ -854,7 +854,7 @@ static void __meminit remove_pagetable(unsigned long start, unsigned long end) continue; } - pud_base = (pud_t *)p4d_page_vaddr(*p4d); + pud_base = p4d_pgtable(*p4d); remove_pud_table(pud_base, addr, next); free_pud_table(pud_base, p4d); } @@ -1105,7 +1105,7 @@ int pud_free_pmd_page(pud_t *pud, unsigned long addr) pmd_t *pmd; int i; - pmd = (pmd_t *)pud_page_vaddr(*pud); + pmd = pud_pgtable(*pud); pud_clear(pud); flush_tlb_kernel_range(addr, addr + PUD_SIZE); diff --git a/arch/powerpc/mm/book3s64/radix_tlb.c b/arch/powerpc/mm/book3s64/radix_tlb.c index ae12fb5559cb..aefc100d79a7 100644 --- a/arch/powerpc/mm/book3s64/radix_tlb.c +++ b/arch/powerpc/mm/book3s64/radix_tlb.c @@ -1111,14 +1111,13 @@ static unsigned long tlb_local_single_page_flush_ceiling __read_mostly = POWER9_ static inline void __radix__flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long end) - { unsigned long pid; unsigned int page_shift = mmu_psize_defs[mmu_virtual_psize].shift; unsigned long page_size = 1UL << page_shift; unsigned long nr_pages = (end - start) >> page_shift; bool fullmm = (end == TLB_FLUSH_ALL); - bool flush_pid; + bool flush_pid, flush_pwc = false; enum tlb_flush_type type; pid = mm->context.id; @@ -1137,8 +1136,16 @@ static inline void __radix__flush_tlb_range(struct mm_struct *mm, flush_pid = nr_pages > tlb_single_page_flush_ceiling; else flush_pid = nr_pages > tlb_local_single_page_flush_ceiling; + /* + * full pid flush already does the PWC flush. if it is not full pid + * flush check the range is more than PMD and force a pwc flush + * mremap() depends on this behaviour. + */ + if (!flush_pid && (end - start) >= PMD_SIZE) + flush_pwc = true; if (!mmu_has_feature(MMU_FTR_GTSE) && type == FLUSH_TYPE_GLOBAL) { + unsigned long type = H_RPTI_TYPE_TLB; unsigned long tgt = H_RPTI_TARGET_CMMU; unsigned long pg_sizes = psize_to_rpti_pgsize(mmu_virtual_psize); @@ -1146,19 +1153,20 @@ static inline void __radix__flush_tlb_range(struct mm_struct *mm, pg_sizes |= psize_to_rpti_pgsize(MMU_PAGE_2M); if (atomic_read(&mm->context.copros) > 0) tgt |= H_RPTI_TARGET_NMMU; - pseries_rpt_invalidate(pid, tgt, H_RPTI_TYPE_TLB, pg_sizes, - start, end); + if (flush_pwc) + type |= H_RPTI_TYPE_PWC; + pseries_rpt_invalidate(pid, tgt, type, pg_sizes, start, end); } else if (flush_pid) { + /* + * We are now flushing a range larger than PMD size force a RIC_FLUSH_ALL + */ if (type == FLUSH_TYPE_LOCAL) { - _tlbiel_pid(pid, RIC_FLUSH_TLB); + _tlbiel_pid(pid, RIC_FLUSH_ALL); } else { if (cputlb_use_tlbie()) { - if (mm_needs_flush_escalation(mm)) - _tlbie_pid(pid, RIC_FLUSH_ALL); - else - _tlbie_pid(pid, RIC_FLUSH_TLB); + _tlbie_pid(pid, RIC_FLUSH_ALL); } else { - _tlbiel_pid_multicast(mm, pid, RIC_FLUSH_TLB); + _tlbiel_pid_multicast(mm, pid, RIC_FLUSH_ALL); } } } else { @@ -1174,6 +1182,9 @@ static inline void __radix__flush_tlb_range(struct mm_struct *mm, if (type == FLUSH_TYPE_LOCAL) { asm volatile("ptesync": : :"memory"); + if (flush_pwc) + /* For PWC, only one flush is needed */ + __tlbiel_pid(pid, 0, RIC_FLUSH_PWC); __tlbiel_va_range(start, end, pid, page_size, mmu_virtual_psize); if (hflush) __tlbiel_va_range(hstart, hend, pid, @@ -1181,6 +1192,8 @@ static inline void __radix__flush_tlb_range(struct mm_struct *mm, ppc_after_tlbiel_barrier(); } else if (cputlb_use_tlbie()) { asm volatile("ptesync": : :"memory"); + if (flush_pwc) + __tlbie_pid(pid, RIC_FLUSH_PWC); __tlbie_va_range(start, end, pid, page_size, mmu_virtual_psize); if (hflush) __tlbie_va_range(hstart, hend, pid, @@ -1188,10 +1201,10 @@ static inline void __radix__flush_tlb_range(struct mm_struct *mm, asm volatile("eieio; tlbsync; ptesync": : :"memory"); } else { _tlbiel_va_range_multicast(mm, - start, end, pid, page_size, mmu_virtual_psize, false); + start, end, pid, page_size, mmu_virtual_psize, flush_pwc); if (hflush) _tlbiel_va_range_multicast(mm, - hstart, hend, pid, PMD_SIZE, MMU_PAGE_2M, false); + hstart, hend, pid, PMD_SIZE, MMU_PAGE_2M, flush_pwc); } } out: @@ -1265,9 +1278,6 @@ void radix__flush_all_lpid_guest(unsigned int lpid) _tlbie_lpid_guest(lpid, RIC_FLUSH_ALL); } -static void radix__flush_tlb_pwc_range_psize(struct mm_struct *mm, unsigned long start, - unsigned long end, int psize); - void radix__tlb_flush(struct mmu_gather *tlb) { int psize = 0; @@ -1374,8 +1384,8 @@ void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start, return __radix__flush_tlb_range_psize(mm, start, end, psize, false); } -static void radix__flush_tlb_pwc_range_psize(struct mm_struct *mm, unsigned long start, - unsigned long end, int psize) +void radix__flush_tlb_pwc_range_psize(struct mm_struct *mm, unsigned long start, + unsigned long end, int psize) { __radix__flush_tlb_range_psize(mm, start, end, psize, true); } diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c index 34f641d4a2fe..a8d0ce85d39a 100644 --- a/arch/powerpc/mm/fault.c +++ b/arch/powerpc/mm/fault.c @@ -199,9 +199,7 @@ static bool bad_kernel_fault(struct pt_regs *regs, unsigned long error_code, { int is_exec = TRAP(regs) == INTERRUPT_INST_STORAGE; - /* NX faults set DSISR_PROTFAULT on the 8xx, DSISR_NOEXEC_OR_G on others */ - if (is_exec && (error_code & (DSISR_NOEXEC_OR_G | DSISR_KEYFAULT | - DSISR_PROTFAULT))) { + if (is_exec) { pr_crit_ratelimited("kernel tried to execute %s page (%lx) - exploit attempt? (uid: %d)\n", address >= TASK_SIZE ? "exec-protected" : "user", address, diff --git a/arch/powerpc/mm/nohash/8xx.c b/arch/powerpc/mm/nohash/8xx.c index 60780e089118..0df9fe29dd56 100644 --- a/arch/powerpc/mm/nohash/8xx.c +++ b/arch/powerpc/mm/nohash/8xx.c @@ -240,3 +240,13 @@ void __init setup_kuap(bool disabled) mtspr(SPRN_MD_AP, MD_APG_KUAP); } #endif + +int pud_clear_huge(pud_t *pud) +{ + return 0; +} + +int pmd_clear_huge(pmd_t *pmd) +{ + return 0; +} diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c index cc6e2f94517f..78c8cf01db5f 100644 --- a/arch/powerpc/mm/pgtable_64.c +++ b/arch/powerpc/mm/pgtable_64.c @@ -105,7 +105,7 @@ struct page *p4d_page(p4d_t p4d) VM_WARN_ON(!p4d_huge(p4d)); return pte_page(p4d_pte(p4d)); } - return virt_to_page(p4d_page_vaddr(p4d)); + return virt_to_page(p4d_pgtable(p4d)); } #endif @@ -115,7 +115,7 @@ struct page *pud_page(pud_t pud) VM_WARN_ON(!pud_huge(pud)); return pte_page(pud_pte(pud)); } - return virt_to_page(pud_page_vaddr(pud)); + return virt_to_page(pud_pgtable(pud)); } /* diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_comp32.c index cbe5b399ed86..34bb1583fc0c 100644 --- a/arch/powerpc/net/bpf_jit_comp32.c +++ b/arch/powerpc/net/bpf_jit_comp32.c @@ -773,9 +773,17 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * break; /* - * BPF_STX XADD (atomic_add) + * BPF_STX ATOMIC (atomic ops) */ - case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */ + case BPF_STX | BPF_ATOMIC | BPF_W: + if (imm != BPF_ADD) { + pr_err_ratelimited("eBPF filter atomic op code %02x (@%d) unsupported\n", + code, i); + return -ENOTSUPP; + } + + /* *(u32 *)(dst + off) += src */ + bpf_set_seen_register(ctx, tmp_reg); /* Get offset into TMP_REG */ EMIT(PPC_RAW_LI(tmp_reg, off)); @@ -789,7 +797,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * PPC_BCC_SHORT(COND_NE, (ctx->idx - 3) * 4); break; - case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */ + case BPF_STX | BPF_ATOMIC | BPF_DW: /* *(u64 *)(dst + off) += src */ return -EOPNOTSUPP; /* diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_comp64.c index 5cad5b5a7e97..de8595880fee 100644 --- a/arch/powerpc/net/bpf_jit_comp64.c +++ b/arch/powerpc/net/bpf_jit_comp64.c @@ -667,7 +667,7 @@ emit_clear: * BPF_STX ATOMIC (atomic ops) */ case BPF_STX | BPF_ATOMIC | BPF_W: - if (insn->imm != BPF_ADD) { + if (imm != BPF_ADD) { pr_err_ratelimited( "eBPF filter atomic op code %02x (@%d) unsupported\n", code, i); @@ -689,7 +689,7 @@ emit_clear: PPC_BCC_SHORT(COND_NE, tmp_idx); break; case BPF_STX | BPF_ATOMIC | BPF_DW: - if (insn->imm != BPF_ADD) { + if (imm != BPF_ADD) { pr_err_ratelimited( "eBPF filter atomic op code %02x (@%d) unsupported\n", code, i); diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype index 0e1bb1cedd13..6794145603de 100644 --- a/arch/powerpc/platforms/Kconfig.cputype +++ b/arch/powerpc/platforms/Kconfig.cputype @@ -102,6 +102,8 @@ config PPC_BOOK3S_64 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE select ARCH_SUPPORTS_HUGETLBFS select ARCH_SUPPORTS_NUMA_BALANCING + select HAVE_MOVE_PMD + select HAVE_MOVE_PUD select IRQ_WORK select PPC_MM_SLICES select PPC_HAVE_KUEP diff --git a/arch/powerpc/platforms/cell/smp.c b/arch/powerpc/platforms/cell/smp.c index c855a0aeb49c..d7ab868aab54 100644 --- a/arch/powerpc/platforms/cell/smp.c +++ b/arch/powerpc/platforms/cell/smp.c @@ -78,9 +78,6 @@ static inline int smp_startup_cpu(unsigned int lcpu) pcpu = get_hard_smp_processor_id(lcpu); - /* Fixup atomic count: it exited inside IRQ handler. */ - task_thread_info(paca_ptrs[lcpu]->__current)->preempt_count = 0; - /* * If the RTAS start-cpu token does not exist then presume the * cpu is already spinning. diff --git a/arch/powerpc/platforms/pasemi/idle.c b/arch/powerpc/platforms/pasemi/idle.c index 9b88e3cded7d..534b0317fc15 100644 --- a/arch/powerpc/platforms/pasemi/idle.c +++ b/arch/powerpc/platforms/pasemi/idle.c @@ -42,6 +42,7 @@ static int pasemi_system_reset_exception(struct pt_regs *regs) switch (regs->msr & SRR1_WAKEMASK) { case SRR1_WAKEDEC: set_dec(1); + break; case SRR1_WAKEEE: /* * Handle these when interrupts get re-enabled and we take diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c index bdfea6d6ab69..3256a316e884 100644 --- a/arch/powerpc/platforms/powermac/smp.c +++ b/arch/powerpc/platforms/powermac/smp.c @@ -146,6 +146,7 @@ static inline void psurge_clr_ipi(int cpu) switch(psurge_type) { case PSURGE_DUAL: out_8(psurge_sec_intr, ~0); + break; case PSURGE_NONE: break; default: diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c index 096629f54576..f47429323eee 100644 --- a/arch/powerpc/platforms/pseries/smp.c +++ b/arch/powerpc/platforms/pseries/smp.c @@ -105,9 +105,6 @@ static inline int smp_startup_cpu(unsigned int lcpu) return 1; } - /* Fixup atomic count: it exited inside IRQ handler. */ - task_thread_info(paca_ptrs[lcpu]->__current)->preempt_count = 0; - /* * If the RTAS start-cpu token does not exist then presume the * cpu is already spinning. diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c index a8304327072d..dbdbbc2f1dc5 100644 --- a/arch/powerpc/sysdev/xive/common.c +++ b/arch/powerpc/sysdev/xive/common.c @@ -1153,11 +1153,10 @@ static int __init xive_request_ipi(void) * Since the HW interrupt number doesn't have any meaning, * simply use the node number. */ - xid->irq = irq_domain_alloc_irqs(ipi_domain, 1, node, &info); - if (xid->irq < 0) { - ret = xid->irq; + ret = irq_domain_alloc_irqs(ipi_domain, 1, node, &info); + if (ret < 0) goto out_free_xive_ipis; - } + xid->irq = ret; snprintf(xid->name, sizeof(xid->name), "IPI-%d", node); diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 469a70bd8da6..8fcceb8eda07 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -26,8 +26,8 @@ config RISCV select ARCH_HAS_KCOV select ARCH_HAS_MMIOWB select ARCH_HAS_PTE_SPECIAL - select ARCH_HAS_SET_DIRECT_MAP - select ARCH_HAS_SET_MEMORY + select ARCH_HAS_SET_DIRECT_MAP if MMU + select ARCH_HAS_SET_MEMORY if MMU select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL select ARCH_HAS_STRICT_MODULE_RWX if MMU && !XIP_KERNEL select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST @@ -65,11 +65,14 @@ config RISCV select HAVE_ARCH_JUMP_LABEL_RELATIVE if !XIP_KERNEL select HAVE_ARCH_KASAN if MMU && 64BIT select HAVE_ARCH_KASAN_VMALLOC if MMU && 64BIT + select HAVE_ARCH_KFENCE if MMU && 64BIT select HAVE_ARCH_KGDB if !XIP_KERNEL select HAVE_ARCH_KGDB_QXFER_PKT select HAVE_ARCH_MMAP_RND_BITS if MMU select HAVE_ARCH_SECCOMP_FILTER select HAVE_ARCH_TRACEHOOK + select HAVE_ARCH_TRANSPARENT_HUGEPAGE if 64BIT && MMU + select HAVE_ARCH_VMAP_STACK if MMU && 64BIT select HAVE_ASM_MODVERSIONS select HAVE_CONTEXT_TRACKING select HAVE_DEBUG_KMEMLEAK @@ -83,11 +86,14 @@ config RISCV select HAVE_KPROBES if !XIP_KERNEL select HAVE_KPROBES_ON_FTRACE if !XIP_KERNEL select HAVE_KRETPROBES if !XIP_KERNEL + select HAVE_MOVE_PMD + select HAVE_MOVE_PUD select HAVE_PCI select HAVE_PERF_EVENTS select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP select HAVE_REGS_AND_STACK_ACCESS_API + select HAVE_FUNCTION_ARG_ACCESS_API select HAVE_STACKPROTECTOR select HAVE_SYSCALL_TRACEPOINTS select IRQ_DOMAIN @@ -488,13 +494,8 @@ config STACKPROTECTOR_PER_TASK def_bool y depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_TLS -config PHYS_RAM_BASE_FIXED - bool "Explicitly specified physical RAM address" - default n - config PHYS_RAM_BASE hex "Platform Physical RAM address" - depends on PHYS_RAM_BASE_FIXED default "0x80000000" help This is the physical address of RAM in the system. It has to be @@ -507,7 +508,6 @@ config XIP_KERNEL # This prevents XIP from being enabled by all{yes,mod}config, which # fail to build since XIP doesn't support large kernels. depends on !COMPILE_TEST - select PHYS_RAM_BASE_FIXED help Execute-In-Place allows the kernel to run from non-volatile storage directly addressable by the CPU, such as NOR flash. This saves RAM diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 99ecd8bcfd77..bc74afdbf31e 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -99,7 +99,6 @@ endif head-y := arch/riscv/kernel/head.o -core-y += arch/riscv/ core-$(CONFIG_RISCV_ERRATA_ALTERNATIVE) += arch/riscv/errata/ libs-y += arch/riscv/lib/ diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/asm/asm-prototypes.h index 2a652b0c987d..ef386fcf3939 100644 --- a/arch/riscv/include/asm/asm-prototypes.h +++ b/arch/riscv/include/asm/asm-prototypes.h @@ -25,4 +25,7 @@ DECLARE_DO_ERROR_INFO(do_trap_ecall_s); DECLARE_DO_ERROR_INFO(do_trap_ecall_m); DECLARE_DO_ERROR_INFO(do_trap_break); +asmlinkage unsigned long get_overflow_stack(void); +asmlinkage void handle_bad_stack(struct pt_regs *regs); + #endif /* _ASM_RISCV_PROTOTYPES_H */ diff --git a/arch/riscv/include/asm/efi.h b/arch/riscv/include/asm/efi.h index 6d98cd999680..7b3483ba2e84 100644 --- a/arch/riscv/include/asm/efi.h +++ b/arch/riscv/include/asm/efi.h @@ -27,10 +27,10 @@ int efi_set_mapping_permissions(struct mm_struct *mm, efi_memory_desc_t *md); #define ARCH_EFI_IRQ_FLAGS_MASK (SR_IE | SR_SPIE) -/* Load initrd at enough distance from DRAM start */ +/* Load initrd anywhere in system RAM */ static inline unsigned long efi_get_max_initrd_addr(unsigned long image_addr) { - return image_addr + SZ_256M; + return ULONG_MAX; } #define alloc_screen_info(x...) (&screen_info) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index c025a746a148..69605a474270 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -52,19 +52,6 @@ #define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory"); #define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory"); -#define inb(c) ({ u8 __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; }) -#define inw(c) ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; }) -#define inl(c) ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; }) - -#define outb(v,c) ({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) -#define outw(v,c) ({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) -#define outl(v,c) ({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) - -#ifdef CONFIG_64BIT -#define inq(c) ({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(__v); __v; }) -#define outq(v,c) ({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); }) -#endif - /* * Accesses from a single hart to a single I/O address must be ordered. This * allows us to use the raw read macros, but we still need to fence before and diff --git a/arch/riscv/include/asm/kfence.h b/arch/riscv/include/asm/kfence.h new file mode 100644 index 000000000000..d887a54042aa --- /dev/null +++ b/arch/riscv/include/asm/kfence.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _ASM_RISCV_KFENCE_H +#define _ASM_RISCV_KFENCE_H + +#include <linux/kfence.h> +#include <linux/pfn.h> +#include <asm-generic/pgalloc.h> +#include <asm/pgtable.h> + +static inline int split_pmd_page(unsigned long addr) +{ + int i; + unsigned long pfn = PFN_DOWN(__pa((addr & PMD_MASK))); + pmd_t *pmd = pmd_off_k(addr); + pte_t *pte = pte_alloc_one_kernel(&init_mm); + + if (!pte) + return -ENOMEM; + + for (i = 0; i < PTRS_PER_PTE; i++) + set_pte(pte + i, pfn_pte(pfn + i, PAGE_KERNEL)); + set_pmd(pmd, pfn_pmd(PFN_DOWN(__pa(pte)), PAGE_TABLE)); + + flush_tlb_kernel_range(addr, addr + PMD_SIZE); + return 0; +} + +static inline bool arch_kfence_init_pool(void) +{ + int ret; + unsigned long addr; + pmd_t *pmd; + + for (addr = (unsigned long)__kfence_pool; is_kfence_address((void *)addr); + addr += PAGE_SIZE) { + pmd = pmd_off_k(addr); + + if (pmd_leaf(*pmd)) { + ret = split_pmd_page(addr); + if (ret) + return false; + } + } + + return true; +} + +static inline bool kfence_protect_page(unsigned long addr, bool protect) +{ + pte_t *pte = virt_to_kpte(addr); + + if (protect) + set_pte(pte, __pte(pte_val(*pte) & ~_PAGE_PRESENT)); + else + set_pte(pte, __pte(pte_val(*pte) | _PAGE_PRESENT)); + + flush_tlb_kernel_range(addr, addr + PAGE_SIZE); + + return true; +} + +#endif /* _ASM_RISCV_KFENCE_H */ diff --git a/arch/riscv/include/asm/kprobes.h b/arch/riscv/include/asm/kprobes.h index 4647d38018f6..9ea9b5ec3113 100644 --- a/arch/riscv/include/asm/kprobes.h +++ b/arch/riscv/include/asm/kprobes.h @@ -29,18 +29,11 @@ struct prev_kprobe { unsigned int status; }; -/* Single step context for kprobe */ -struct kprobe_step_ctx { - unsigned long ss_pending; - unsigned long match_addr; -}; - /* per-cpu kprobe control block */ struct kprobe_ctlblk { unsigned int kprobe_status; unsigned long saved_status; struct prev_kprobe prev_kprobe; - struct kprobe_step_ctx ss_ctx; }; void arch_remove_kprobe(struct kprobe *p); diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/asm/mmu_context.h index b0659413a080..7030837adc1a 100644 --- a/arch/riscv/include/asm/mmu_context.h +++ b/arch/riscv/include/asm/mmu_context.h @@ -33,6 +33,8 @@ static inline int init_new_context(struct task_struct *tsk, return 0; } +DECLARE_STATIC_KEY_FALSE(use_asid_allocator); + #include <asm-generic/mmu_context.h> #endif /* _ASM_RISCV_MMU_CONTEXT_H */ diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h index 6a7761c86ec2..cca8764aed83 100644 --- a/arch/riscv/include/asm/page.h +++ b/arch/riscv/include/asm/page.h @@ -37,16 +37,6 @@ #ifndef __ASSEMBLY__ -#define PAGE_UP(addr) (((addr)+((PAGE_SIZE)-1))&(~((PAGE_SIZE)-1))) -#define PAGE_DOWN(addr) ((addr)&(~((PAGE_SIZE)-1))) - -/* align addr on a size boundary - adjust address up/down if needed */ -#define _ALIGN_UP(addr, size) (((addr)+((size)-1))&(~((size)-1))) -#define _ALIGN_DOWN(addr, size) ((addr)&(~((size)-1))) - -/* align addr on a size boundary - adjust address up if needed */ -#define _ALIGN(addr, size) _ALIGN_UP(addr, size) - #define clear_page(pgaddr) memset((pgaddr), 0, PAGE_SIZE) #define copy_page(to, from) memcpy((to), (from), PAGE_SIZE) @@ -89,59 +79,68 @@ typedef struct page *pgtable_t; #endif #ifdef CONFIG_MMU -extern unsigned long va_pa_offset; -#ifdef CONFIG_64BIT -extern unsigned long va_kernel_pa_offset; -#endif -#ifdef CONFIG_XIP_KERNEL -extern unsigned long va_kernel_xip_pa_offset; -#endif extern unsigned long pfn_base; #define ARCH_PFN_OFFSET (pfn_base) #else -#define va_pa_offset 0 -#ifdef CONFIG_64BIT -#define va_kernel_pa_offset 0 -#endif #define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT) #endif /* CONFIG_MMU */ -extern unsigned long kernel_virt_addr; - +struct kernel_mapping { + unsigned long virt_addr; + uintptr_t phys_addr; + uintptr_t size; + /* Offset between linear mapping virtual address and kernel load address */ + unsigned long va_pa_offset; #ifdef CONFIG_64BIT -#define linear_mapping_pa_to_va(x) ((void *)((unsigned long)(x) + va_pa_offset)) + /* Offset between kernel mapping virtual address and kernel load address */ + unsigned long va_kernel_pa_offset; +#endif + unsigned long va_kernel_xip_pa_offset; #ifdef CONFIG_XIP_KERNEL + uintptr_t xiprom; + uintptr_t xiprom_sz; +#endif +}; + +extern struct kernel_mapping kernel_map; + +#ifdef CONFIG_64BIT +#define is_kernel_mapping(x) \ + ((x) >= kernel_map.virt_addr && (x) < (kernel_map.virt_addr + kernel_map.size)) +#define is_linear_mapping(x) \ + ((x) >= PAGE_OFFSET && (x) < kernel_map.virt_addr) + +#define linear_mapping_pa_to_va(x) ((void *)((unsigned long)(x) + kernel_map.va_pa_offset)) #define kernel_mapping_pa_to_va(y) ({ \ unsigned long _y = y; \ (_y >= CONFIG_PHYS_RAM_BASE) ? \ - (void *)((unsigned long)(_y) + va_kernel_pa_offset + XIP_OFFSET) : \ - (void *)((unsigned long)(_y) + va_kernel_xip_pa_offset); \ + (void *)((unsigned long)(_y) + kernel_map.va_kernel_pa_offset + XIP_OFFSET) : \ + (void *)((unsigned long)(_y) + kernel_map.va_kernel_xip_pa_offset); \ }) -#else -#define kernel_mapping_pa_to_va(x) ((void *)((unsigned long)(x) + va_kernel_pa_offset)) -#endif #define __pa_to_va_nodebug(x) linear_mapping_pa_to_va(x) -#define linear_mapping_va_to_pa(x) ((unsigned long)(x) - va_pa_offset) -#ifdef CONFIG_XIP_KERNEL +#define linear_mapping_va_to_pa(x) ((unsigned long)(x) - kernel_map.va_pa_offset) #define kernel_mapping_va_to_pa(y) ({ \ unsigned long _y = y; \ - (_y < kernel_virt_addr + XIP_OFFSET) ? \ - ((unsigned long)(_y) - va_kernel_xip_pa_offset) : \ - ((unsigned long)(_y) - va_kernel_pa_offset - XIP_OFFSET); \ + (_y < kernel_map.virt_addr + XIP_OFFSET) ? \ + ((unsigned long)(_y) - kernel_map.va_kernel_xip_pa_offset) : \ + ((unsigned long)(_y) - kernel_map.va_kernel_pa_offset - XIP_OFFSET); \ }) -#else -#define kernel_mapping_va_to_pa(x) ((unsigned long)(x) - va_kernel_pa_offset) -#endif + #define __va_to_pa_nodebug(x) ({ \ unsigned long _x = x; \ - (_x < kernel_virt_addr) ? \ + is_linear_mapping(_x) ? \ linear_mapping_va_to_pa(_x) : kernel_mapping_va_to_pa(_x); \ }) #else -#define __pa_to_va_nodebug(x) ((void *)((unsigned long) (x) + va_pa_offset)) -#define __va_to_pa_nodebug(x) ((unsigned long)(x) - va_pa_offset) -#endif +#define is_kernel_mapping(x) \ + ((x) >= kernel_map.virt_addr && (x) < (kernel_map.virt_addr + kernel_map.size)) +#define is_linear_mapping(x) \ + ((x) >= PAGE_OFFSET) + +#define __pa_to_va_nodebug(x) ((void *)((unsigned long) (x) + kernel_map.va_pa_offset)) +#define __va_to_pa_nodebug(x) ((unsigned long)(x) - kernel_map.va_pa_offset) +#endif /* CONFIG_64BIT */ #ifdef CONFIG_DEBUG_VIRTUAL extern phys_addr_t __virt_to_phys(unsigned long x); diff --git a/arch/riscv/include/asm/pci.h b/arch/riscv/include/asm/pci.h index 658e112c3ce7..7fd52a30e605 100644 --- a/arch/riscv/include/asm/pci.h +++ b/arch/riscv/include/asm/pci.h @@ -18,6 +18,8 @@ /* RISC-V shim does not initialize PCI bus */ #define pcibios_assign_all_busses() 1 +#define ARCH_GENERIC_PCI_MMAP_RESOURCE 1 + extern int isa_dma_bridge_buggy; #ifdef CONFIG_PCI diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h index f3b0da64c6c8..228261aa9628 100644 --- a/arch/riscv/include/asm/pgtable-64.h +++ b/arch/riscv/include/asm/pgtable-64.h @@ -46,8 +46,7 @@ static inline int pud_bad(pud_t pud) #define pud_leaf pud_leaf static inline int pud_leaf(pud_t pud) { - return pud_present(pud) && - (pud_val(pud) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)); + return pud_present(pud) && (pud_val(pud) & _PAGE_LEAF); } static inline void set_pud(pud_t *pudp, pud_t pud) @@ -60,9 +59,9 @@ static inline void pud_clear(pud_t *pudp) set_pud(pudp, __pud(0)); } -static inline unsigned long pud_page_vaddr(pud_t pud) +static inline pmd_t *pud_pgtable(pud_t pud) { - return (unsigned long)pfn_to_virt(pud_val(pud) >> _PAGE_PFN_SHIFT); + return (pmd_t *)pfn_to_virt(pud_val(pud) >> _PAGE_PFN_SHIFT); } static inline struct page *pud_page(pud_t pud) @@ -80,6 +79,8 @@ static inline unsigned long _pmd_pfn(pmd_t pmd) return pmd_val(pmd) >> _PAGE_PFN_SHIFT; } +#define mk_pmd(page, prot) pfn_pmd(page_to_pfn(page), prot) + #define pmd_ERROR(e) \ pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h index bbaeb5d35842..2ee413912926 100644 --- a/arch/riscv/include/asm/pgtable-bits.h +++ b/arch/riscv/include/asm/pgtable-bits.h @@ -39,5 +39,10 @@ #define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \ _PAGE_WRITE | _PAGE_EXEC | \ _PAGE_USER | _PAGE_GLOBAL)) +/* + * when all of R/W/X are zero, the PTE is a pointer to the next level + * of the page table; otherwise, it is a leaf PTE. + */ +#define _PAGE_LEAF (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) #endif /* _ASM_RISCV_PGTABLE_BITS_H */ diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 62f3fe7368f3..39b550310ec6 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -76,6 +76,8 @@ #ifdef CONFIG_XIP_KERNEL #define XIP_OFFSET SZ_8M +#else +#define XIP_OFFSET 0 #endif #ifndef __ASSEMBLY__ @@ -133,7 +135,8 @@ | _PAGE_WRITE \ | _PAGE_PRESENT \ | _PAGE_ACCESSED \ - | _PAGE_DIRTY) + | _PAGE_DIRTY \ + | _PAGE_GLOBAL) #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) #define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) @@ -171,10 +174,23 @@ extern pgd_t swapper_pg_dir[]; #define __S110 PAGE_SHARED_EXEC #define __S111 PAGE_SHARED_EXEC +#ifdef CONFIG_TRANSPARENT_HUGEPAGE +static inline int pmd_present(pmd_t pmd) +{ + /* + * Checking for _PAGE_LEAF is needed too because: + * When splitting a THP, split_huge_page() will temporarily clear + * the present bit, in this situation, pmd_present() and + * pmd_trans_huge() still needs to return true. + */ + return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE | _PAGE_LEAF)); +} +#else static inline int pmd_present(pmd_t pmd) { return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); } +#endif static inline int pmd_none(pmd_t pmd) { @@ -183,14 +199,13 @@ static inline int pmd_none(pmd_t pmd) static inline int pmd_bad(pmd_t pmd) { - return !pmd_present(pmd); + return !pmd_present(pmd) || (pmd_val(pmd) & _PAGE_LEAF); } #define pmd_leaf pmd_leaf static inline int pmd_leaf(pmd_t pmd) { - return pmd_present(pmd) && - (pmd_val(pmd) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)); + return pmd_present(pmd) && (pmd_val(pmd) & _PAGE_LEAF); } static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) @@ -228,6 +243,11 @@ static inline pte_t pmd_pte(pmd_t pmd) return __pte(pmd_val(pmd)); } +static inline pte_t pud_pte(pud_t pud) +{ + return __pte(pud_val(pud)); +} + /* Yields the page frame number (PFN) of a page table entry */ static inline unsigned long pte_pfn(pte_t pte) { @@ -266,8 +286,7 @@ static inline int pte_exec(pte_t pte) static inline int pte_huge(pte_t pte) { - return pte_present(pte) - && (pte_val(pte) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)); + return pte_present(pte) && (pte_val(pte) & _PAGE_LEAF); } static inline int pte_dirty(pte_t pte) @@ -370,6 +389,14 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, local_flush_tlb_page(address); } +static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, + unsigned long address, pmd_t *pmdp) +{ + pte_t *ptep = (pte_t *)pmdp; + + update_mmu_cache(vma, address, ptep); +} + #define __HAVE_ARCH_PTE_SAME static inline int pte_same(pte_t pte_a, pte_t pte_b) { @@ -464,6 +491,137 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma, } /* + * THP functions + */ +static inline pmd_t pte_pmd(pte_t pte) +{ + return __pmd(pte_val(pte)); +} + +static inline pmd_t pmd_mkhuge(pmd_t pmd) +{ + return pmd; +} + +static inline pmd_t pmd_mkinvalid(pmd_t pmd) +{ + return __pmd(pmd_val(pmd) & ~(_PAGE_PRESENT|_PAGE_PROT_NONE)); +} + +#define __pmd_to_phys(pmd) (pmd_val(pmd) >> _PAGE_PFN_SHIFT << PAGE_SHIFT) + +static inline unsigned long pmd_pfn(pmd_t pmd) +{ + return ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT); +} + +static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) +{ + return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); +} + +#define pmd_write pmd_write +static inline int pmd_write(pmd_t pmd) +{ + return pte_write(pmd_pte(pmd)); +} + +static inline int pmd_dirty(pmd_t pmd) +{ + return pte_dirty(pmd_pte(pmd)); +} + +static inline int pmd_young(pmd_t pmd) +{ + return pte_young(pmd_pte(pmd)); +} + +static inline pmd_t pmd_mkold(pmd_t pmd) +{ + return pte_pmd(pte_mkold(pmd_pte(pmd))); +} + +static inline pmd_t pmd_mkyoung(pmd_t pmd) +{ + return pte_pmd(pte_mkyoung(pmd_pte(pmd))); +} + +static inline pmd_t pmd_mkwrite(pmd_t pmd) +{ + return pte_pmd(pte_mkwrite(pmd_pte(pmd))); +} + +static inline pmd_t pmd_wrprotect(pmd_t pmd) +{ + return pte_pmd(pte_wrprotect(pmd_pte(pmd))); +} + +static inline pmd_t pmd_mkclean(pmd_t pmd) +{ + return pte_pmd(pte_mkclean(pmd_pte(pmd))); +} + +static inline pmd_t pmd_mkdirty(pmd_t pmd) +{ + return pte_pmd(pte_mkdirty(pmd_pte(pmd))); +} + +static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, + pmd_t *pmdp, pmd_t pmd) +{ + return set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)); +} + +static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, + pud_t *pudp, pud_t pud) +{ + return set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud)); +} + +#ifdef CONFIG_TRANSPARENT_HUGEPAGE +static inline int pmd_trans_huge(pmd_t pmd) +{ + return pmd_leaf(pmd); +} + +#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS +static inline int pmdp_set_access_flags(struct vm_area_struct *vma, + unsigned long address, pmd_t *pmdp, + pmd_t entry, int dirty) +{ + return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); +} + +#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG +static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, + unsigned long address, pmd_t *pmdp) +{ + return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); +} + +#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR +static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, + unsigned long address, pmd_t *pmdp) +{ + return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); +} + +#define __HAVE_ARCH_PMDP_SET_WRPROTECT +static inline void pmdp_set_wrprotect(struct mm_struct *mm, + unsigned long address, pmd_t *pmdp) +{ + ptep_set_wrprotect(mm, address, (pte_t *)pmdp); +} + +#define pmdp_establish pmdp_establish +static inline pmd_t pmdp_establish(struct vm_area_struct *vma, + unsigned long address, pmd_t *pmdp, pmd_t pmd) +{ + return __pmd(atomic_long_xchg((atomic_long_t *)pmdp, pmd_val(pmd))); +} +#endif /* CONFIG_TRANSPARENT_HUGEPAGE */ + +/* * Encode and decode a swap entry * * Format of swap PTE: @@ -532,7 +690,6 @@ extern uintptr_t _dtb_early_pa; #define dtb_early_pa _dtb_early_pa #endif /* CONFIG_XIP_KERNEL */ -void setup_bootmem(void); void paging_init(void); void misc_mem_init(void); diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h index 09ad4e923510..6ecd461129d2 100644 --- a/arch/riscv/include/asm/ptrace.h +++ b/arch/riscv/include/asm/ptrace.h @@ -141,6 +141,37 @@ static inline unsigned long regs_get_register(struct pt_regs *regs, return *(unsigned long *)((unsigned long)regs + offset); } + +/** + * regs_get_kernel_argument() - get Nth function argument in kernel + * @regs: pt_regs of that context + * @n: function argument number (start from 0) + * + * regs_get_argument() returns @n th argument of the function call. + * + * Note you can get the parameter correctly if the function has no + * more than eight arguments. + */ +static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs, + unsigned int n) +{ + static const int nr_reg_arguments = 8; + static const unsigned int argument_offs[] = { + offsetof(struct pt_regs, a0), + offsetof(struct pt_regs, a1), + offsetof(struct pt_regs, a2), + offsetof(struct pt_regs, a3), + offsetof(struct pt_regs, a4), + offsetof(struct pt_regs, a5), + offsetof(struct pt_regs, a6), + offsetof(struct pt_regs, a7), + }; + + if (n < nr_reg_arguments) + return regs_get_register(regs, argument_offs[n]); + return 0; +} + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PTRACE_H */ diff --git a/arch/riscv/include/asm/sections.h b/arch/riscv/include/asm/sections.h index 8a303fb1ee3b..32336e8a17cb 100644 --- a/arch/riscv/include/asm/sections.h +++ b/arch/riscv/include/asm/sections.h @@ -6,6 +6,7 @@ #define __ASM_SECTIONS_H #include <asm-generic/sections.h> +#include <linux/mm.h> extern char _start[]; extern char _start_kernel[]; @@ -13,4 +14,20 @@ extern char __init_data_begin[], __init_data_end[]; extern char __init_text_begin[], __init_text_end[]; extern char __alt_start[], __alt_end[]; +static inline bool is_va_kernel_text(uintptr_t va) +{ + uintptr_t start = (uintptr_t)_start; + uintptr_t end = (uintptr_t)__init_data_begin; + + return va >= start && va < end; +} + +static inline bool is_va_kernel_lm_alias_text(uintptr_t va) +{ + uintptr_t start = (uintptr_t)lm_alias(_start); + uintptr_t end = (uintptr_t)lm_alias(__init_data_begin); + + return va >= start && va < end; +} + #endif /* __ASM_SECTIONS_H */ diff --git a/arch/riscv/include/asm/set_memory.h b/arch/riscv/include/asm/set_memory.h index 086f757e8ba3..a2c14d4b3993 100644 --- a/arch/riscv/include/asm/set_memory.h +++ b/arch/riscv/include/asm/set_memory.h @@ -16,20 +16,28 @@ int set_memory_rw(unsigned long addr, int numpages); int set_memory_x(unsigned long addr, int numpages); int set_memory_nx(unsigned long addr, int numpages); int set_memory_rw_nx(unsigned long addr, int numpages); -void protect_kernel_text_data(void); +static __always_inline int set_kernel_memory(char *startp, char *endp, + int (*set_memory)(unsigned long start, + int num_pages)) +{ + unsigned long start = (unsigned long)startp; + unsigned long end = (unsigned long)endp; + int num_pages = PAGE_ALIGN(end - start) >> PAGE_SHIFT; + + return set_memory(start, num_pages); +} #else static inline int set_memory_ro(unsigned long addr, int numpages) { return 0; } static inline int set_memory_rw(unsigned long addr, int numpages) { return 0; } static inline int set_memory_x(unsigned long addr, int numpages) { return 0; } static inline int set_memory_nx(unsigned long addr, int numpages) { return 0; } -static inline void protect_kernel_text_data(void) {} static inline int set_memory_rw_nx(unsigned long addr, int numpages) { return 0; } -#endif - -#if defined(CONFIG_64BIT) && defined(CONFIG_STRICT_KERNEL_RWX) -void protect_kernel_linear_mapping_text_rodata(void); -#else -static inline void protect_kernel_linear_mapping_text_rodata(void) {} +static inline int set_kernel_memory(char *startp, char *endp, + int (*set_memory)(unsigned long start, + int num_pages)) +{ + return 0; +} #endif int set_direct_map_invalid_noflush(struct page *page); diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 407bcc96a710..0a3f4f95c555 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -6,6 +6,7 @@ #ifndef _ASM_RISCV_SWITCH_TO_H #define _ASM_RISCV_SWITCH_TO_H +#include <linux/jump_label.h> #include <linux/sched/task_stack.h> #include <asm/processor.h> #include <asm/ptrace.h> @@ -55,9 +56,13 @@ static inline void __switch_to_aux(struct task_struct *prev, fstate_restore(next, task_pt_regs(next)); } -extern bool has_fpu; +extern struct static_key_false cpu_hwcap_fpu; +static __always_inline bool has_fpu(void) +{ + return static_branch_likely(&cpu_hwcap_fpu); +} #else -#define has_fpu false +static __always_inline bool has_fpu(void) { return false; } #define fstate_save(task, regs) do { } while (0) #define fstate_restore(task, regs) do { } while (0) #define __switch_to_aux(__prev, __next) do { } while (0) @@ -70,7 +75,7 @@ extern struct task_struct *__switch_to(struct task_struct *, do { \ struct task_struct *__prev = (prev); \ struct task_struct *__next = (next); \ - if (has_fpu) \ + if (has_fpu()) \ __switch_to_aux(__prev, __next); \ ((last) = __switch_to(__prev, __next)); \ } while (0) diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h index 0e549a3089b3..60da0dcacf14 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -19,6 +19,21 @@ #endif #define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) +/* + * By aligning VMAP'd stacks to 2 * THREAD_SIZE, we can detect overflow by + * checking sp & (1 << THREAD_SHIFT), which we can do cheaply in the entry + * assembly. + */ +#ifdef CONFIG_VMAP_STACK +#define THREAD_ALIGN (2 * THREAD_SIZE) +#else +#define THREAD_ALIGN THREAD_SIZE +#endif + +#define THREAD_SHIFT (PAGE_SHIFT + THREAD_SIZE_ORDER) +#define OVERFLOW_STACK_SIZE SZ_4K +#define SHADOW_OVERFLOW_STACK_SIZE (1024) + #ifndef __ASSEMBLY__ #include <asm/processor.h> diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index c84218ad7afc..801019381dea 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -33,6 +33,11 @@ void flush_tlb_mm(struct mm_struct *mm); void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr); void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); +#ifdef CONFIG_TRANSPARENT_HUGEPAGE +#define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE +void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end); +#endif #else /* CONFIG_SMP && CONFIG_MMU */ #define flush_tlb_all() local_flush_tlb_all() diff --git a/arch/riscv/include/asm/unistd.h b/arch/riscv/include/asm/unistd.h index 977ee6181dab..6c316093a1e5 100644 --- a/arch/riscv/include/asm/unistd.h +++ b/arch/riscv/include/asm/unistd.h @@ -9,6 +9,7 @@ */ #define __ARCH_WANT_SYS_CLONE +#define __ARCH_WANT_MEMFD_SECRET #include <uapi/asm/unistd.h> diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c index 9ef33346853c..90f8ce64fa6f 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -311,4 +311,6 @@ void asm_offsets(void) * ensures the alignment is sane. */ DEFINE(PT_SIZE_ON_STACK, ALIGN(sizeof(struct pt_regs), STACK_ALIGN)); + + OFFSET(KERNEL_MAP_VIRT_ADDR, kernel_mapping, virt_addr); } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index ac202f44a670..d959d207a40d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -19,7 +19,7 @@ unsigned long elf_hwcap __read_mostly; static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; #ifdef CONFIG_FPU -bool has_fpu __read_mostly; +__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu); #endif /** @@ -59,7 +59,7 @@ bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit) } EXPORT_SYMBOL_GPL(__riscv_isa_extension_available); -void riscv_fill_hwcap(void) +void __init riscv_fill_hwcap(void) { struct device_node *node; const char *isa; @@ -146,6 +146,6 @@ void riscv_fill_hwcap(void) #ifdef CONFIG_FPU if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) - has_fpu = true; + static_branch_enable(&cpu_hwcap_fpu); #endif } diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 80d5a9e017b0..98f502654edd 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -30,6 +30,15 @@ ENTRY(handle_exception) _restore_kernel_tpsp: csrr tp, CSR_SCRATCH REG_S sp, TASK_TI_KERNEL_SP(tp) + +#ifdef CONFIG_VMAP_STACK + addi sp, sp, -(PT_SIZE_ON_STACK) + srli sp, sp, THREAD_SHIFT + andi sp, sp, 0x1 + bnez sp, handle_kernel_stack_overflow + REG_L sp, TASK_TI_KERNEL_SP(tp) +#endif + _save_context: REG_S sp, TASK_TI_USER_SP(tp) REG_L sp, TASK_TI_KERNEL_SP(tp) @@ -376,6 +385,105 @@ handle_syscall_trace_exit: call do_syscall_trace_exit j ret_from_exception +#ifdef CONFIG_VMAP_STACK +handle_kernel_stack_overflow: + la sp, shadow_stack + addi sp, sp, SHADOW_OVERFLOW_STACK_SIZE + + //save caller register to shadow stack + addi sp, sp, -(PT_SIZE_ON_STACK) + REG_S x1, PT_RA(sp) + REG_S x5, PT_T0(sp) + REG_S x6, PT_T1(sp) + REG_S x7, PT_T2(sp) + REG_S x10, PT_A0(sp) + REG_S x11, PT_A1(sp) + REG_S x12, PT_A2(sp) + REG_S x13, PT_A3(sp) + REG_S x14, PT_A4(sp) + REG_S x15, PT_A5(sp) + REG_S x16, PT_A6(sp) + REG_S x17, PT_A7(sp) + REG_S x28, PT_T3(sp) + REG_S x29, PT_T4(sp) + REG_S x30, PT_T5(sp) + REG_S x31, PT_T6(sp) + + la ra, restore_caller_reg + tail get_overflow_stack + +restore_caller_reg: + //save per-cpu overflow stack + REG_S a0, -8(sp) + //restore caller register from shadow_stack + REG_L x1, PT_RA(sp) + REG_L x5, PT_T0(sp) + REG_L x6, PT_T1(sp) + REG_L x7, PT_T2(sp) + REG_L x10, PT_A0(sp) + REG_L x11, PT_A1(sp) + REG_L x12, PT_A2(sp) + REG_L x13, PT_A3(sp) + REG_L x14, PT_A4(sp) + REG_L x15, PT_A5(sp) + REG_L x16, PT_A6(sp) + REG_L x17, PT_A7(sp) + REG_L x28, PT_T3(sp) + REG_L x29, PT_T4(sp) + REG_L x30, PT_T5(sp) + REG_L x31, PT_T6(sp) + + //load per-cpu overflow stack + REG_L sp, -8(sp) + addi sp, sp, -(PT_SIZE_ON_STACK) + + //save context to overflow stack + REG_S x1, PT_RA(sp) + REG_S x3, PT_GP(sp) + REG_S x5, PT_T0(sp) + REG_S x6, PT_T1(sp) + REG_S x7, PT_T2(sp) + REG_S x8, PT_S0(sp) + REG_S x9, PT_S1(sp) + REG_S x10, PT_A0(sp) + REG_S x11, PT_A1(sp) + REG_S x12, PT_A2(sp) + REG_S x13, PT_A3(sp) + REG_S x14, PT_A4(sp) + REG_S x15, PT_A5(sp) + REG_S x16, PT_A6(sp) + REG_S x17, PT_A7(sp) + REG_S x18, PT_S2(sp) + REG_S x19, PT_S3(sp) + REG_S x20, PT_S4(sp) + REG_S x21, PT_S5(sp) + REG_S x22, PT_S6(sp) + REG_S x23, PT_S7(sp) + REG_S x24, PT_S8(sp) + REG_S x25, PT_S9(sp) + REG_S x26, PT_S10(sp) + REG_S x27, PT_S11(sp) + REG_S x28, PT_T3(sp) + REG_S x29, PT_T4(sp) + REG_S x30, PT_T5(sp) + REG_S x31, PT_T6(sp) + + REG_L s0, TASK_TI_KERNEL_SP(tp) + csrr s1, CSR_STATUS + csrr s2, CSR_EPC + csrr s3, CSR_TVAL + csrr s4, CSR_CAUSE + csrr s5, CSR_SCRATCH + REG_S s0, PT_SP(sp) + REG_S s1, PT_STATUS(sp) + REG_S s2, PT_EPC(sp) + REG_S s3, PT_BADADDR(sp) + REG_S s4, PT_CAUSE(sp) + REG_S s5, PT_TP(sp) + move a0, sp + tail handle_bad_stack +#endif + END(handle_exception) ENTRY(ret_from_fork) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 89cc58ab52b4..fce5184b22c3 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -81,9 +81,9 @@ pe_head_start: #ifdef CONFIG_MMU relocate: /* Relocate return address */ - la a1, kernel_virt_addr + la a1, kernel_map XIP_FIXUP_OFFSET a1 - REG_L a1, 0(a1) + REG_L a1, KERNEL_MAP_VIRT_ADDR(a1) la a2, _start sub a1, a1, a2 add ra, ra, a1 diff --git a/arch/riscv/kernel/kexec_relocate.S b/arch/riscv/kernel/kexec_relocate.S index 88c3beabe9b4..a80b52a74f58 100644 --- a/arch/riscv/kernel/kexec_relocate.S +++ b/arch/riscv/kernel/kexec_relocate.S @@ -20,7 +20,7 @@ SYM_CODE_START(riscv_kexec_relocate) * s4: Pointer to the destination address for the relocation * s5: (const) Number of words per page * s6: (const) 1, used for subtraction - * s7: (const) va_pa_offset, used when switching MMU off + * s7: (const) kernel_map.va_pa_offset, used when switching MMU off * s8: (const) Physical address of the main loop * s9: (debug) indirection page counter * s10: (debug) entry counter @@ -159,7 +159,7 @@ SYM_CODE_START(riscv_kexec_norelocate) * s0: (const) Phys address to jump to * s1: (const) Phys address of the FDT image * s2: (const) The hartid of the current hart - * s3: (const) va_pa_offset, used when switching MMU off + * s3: (const) kernel_map.va_pa_offset, used when switching MMU off */ mv s0, a1 mv s1, a2 diff --git a/arch/riscv/kernel/machine_kexec.c b/arch/riscv/kernel/machine_kexec.c index 9e99e1db156b..e6eca271a4d6 100644 --- a/arch/riscv/kernel/machine_kexec.c +++ b/arch/riscv/kernel/machine_kexec.c @@ -189,6 +189,6 @@ machine_kexec(struct kimage *image) /* Jump to the relocation code */ pr_notice("Bye...\n"); kexec_method(first_ind_entry, jump_addr, fdt_addr, - this_hart_id, va_pa_offset); + this_hart_id, kernel_map.va_pa_offset); unreachable(); } diff --git a/arch/riscv/kernel/probes/kprobes.c b/arch/riscv/kernel/probes/kprobes.c index 247e33fa5bc7..00088dc6da4b 100644 --- a/arch/riscv/kernel/probes/kprobes.c +++ b/arch/riscv/kernel/probes/kprobes.c @@ -17,7 +17,7 @@ DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL; DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk); static void __kprobes -post_kprobe_handler(struct kprobe_ctlblk *, struct pt_regs *); +post_kprobe_handler(struct kprobe *, struct kprobe_ctlblk *, struct pt_regs *); static void __kprobes arch_prepare_ss_slot(struct kprobe *p) { @@ -43,7 +43,7 @@ static void __kprobes arch_simulate_insn(struct kprobe *p, struct pt_regs *regs) p->ainsn.api.handler((u32)p->opcode, (unsigned long)p->addr, regs); - post_kprobe_handler(kcb, regs); + post_kprobe_handler(p, kcb, regs); } int __kprobes arch_prepare_kprobe(struct kprobe *p) @@ -151,21 +151,6 @@ static void __kprobes kprobes_restore_local_irqflag(struct kprobe_ctlblk *kcb, regs->status = kcb->saved_status; } -static void __kprobes -set_ss_context(struct kprobe_ctlblk *kcb, unsigned long addr, struct kprobe *p) -{ - unsigned long offset = GET_INSN_LENGTH(p->opcode); - - kcb->ss_ctx.ss_pending = true; - kcb->ss_ctx.match_addr = addr + offset; -} - -static void __kprobes clear_ss_context(struct kprobe_ctlblk *kcb) -{ - kcb->ss_ctx.ss_pending = false; - kcb->ss_ctx.match_addr = 0; -} - static void __kprobes setup_singlestep(struct kprobe *p, struct pt_regs *regs, struct kprobe_ctlblk *kcb, int reenter) @@ -184,8 +169,6 @@ static void __kprobes setup_singlestep(struct kprobe *p, /* prepare for single stepping */ slot = (unsigned long)p->ainsn.api.insn; - set_ss_context(kcb, slot, p); /* mark pending ss */ - /* IRQs and single stepping do not mix well. */ kprobes_save_local_irqflag(kcb, regs); @@ -221,13 +204,8 @@ static int __kprobes reenter_kprobe(struct kprobe *p, } static void __kprobes -post_kprobe_handler(struct kprobe_ctlblk *kcb, struct pt_regs *regs) +post_kprobe_handler(struct kprobe *cur, struct kprobe_ctlblk *kcb, struct pt_regs *regs) { - struct kprobe *cur = kprobe_running(); - - if (!cur) - return; - /* return addr restore if non-branching insn */ if (cur->ainsn.api.restore != 0) regs->epc = cur->ainsn.api.restore; @@ -342,16 +320,16 @@ bool __kprobes kprobe_single_step_handler(struct pt_regs *regs) { struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + unsigned long addr = instruction_pointer(regs); + struct kprobe *cur = kprobe_running(); - if ((kcb->ss_ctx.ss_pending) - && (kcb->ss_ctx.match_addr == instruction_pointer(regs))) { - clear_ss_context(kcb); /* clear pending ss */ - + if (cur && (kcb->kprobe_status & (KPROBE_HIT_SS | KPROBE_REENTER)) && + ((unsigned long)&cur->ainsn.api.insn[0] + GET_INSN_LENGTH(cur->opcode) == addr)) { kprobes_restore_local_irqflag(kcb, regs); - - post_kprobe_handler(kcb, regs); + post_kprobe_handler(cur, kcb, regs); return true; } + /* not ours, kprobes should ignore it */ return false; } diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index f9cd57c9c67d..03ac3aa611f5 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -87,7 +87,7 @@ void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long sp) { regs->status = SR_PIE; - if (has_fpu) { + if (has_fpu()) { regs->status |= SR_FS_INITIAL; /* * Restore the initial value to the FP register diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 9a1b7a0603b2..18bd0e4bc36c 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -17,7 +17,6 @@ #include <linux/of_fdt.h> #include <linux/of_platform.h> #include <linux/sched/task.h> -#include <linux/swiotlb.h> #include <linux/smp.h> #include <linux/efi.h> #include <linux/crash_dump.h> @@ -264,10 +263,7 @@ static void __init parse_dtb(void) void __init setup_arch(char **cmdline_p) { parse_dtb(); - init_mm.start_code = (unsigned long) _stext; - init_mm.end_code = (unsigned long) _etext; - init_mm.end_data = (unsigned long) _edata; - init_mm.brk = (unsigned long) _end; + setup_initial_init_mm(_stext, _etext, _edata, _end); *cmdline_p = boot_command_line; @@ -276,7 +272,6 @@ void __init setup_arch(char **cmdline_p) parse_early_param(); efi_init(); - setup_bootmem(); paging_init(); #if IS_ENABLED(CONFIG_BUILTIN_DTB) unflatten_and_copy_device_tree(); @@ -291,15 +286,6 @@ void __init setup_arch(char **cmdline_p) init_resources(); sbi_init(); - if (IS_ENABLED(CONFIG_STRICT_KERNEL_RWX)) { - protect_kernel_text_data(); - protect_kernel_linear_mapping_text_rodata(); - } - -#ifdef CONFIG_SWIOTLB - swiotlb_init(1); -#endif - #ifdef CONFIG_KASAN kasan_init(); #endif @@ -334,11 +320,10 @@ subsys_initcall(topology_init); void free_initmem(void) { - unsigned long init_begin = (unsigned long)__init_begin; - unsigned long init_end = (unsigned long)__init_end; - if (IS_ENABLED(CONFIG_STRICT_KERNEL_RWX)) - set_memory_rw_nx(init_begin, (init_end - init_begin) >> PAGE_SHIFT); + set_kernel_memory(lm_alias(__init_begin), lm_alias(__init_end), + IS_ENABLED(CONFIG_64BIT) ? + set_memory_rw : set_memory_rw_nx); free_initmem_default(POISON_FREE_INITMEM); } diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 65942b3748b4..c2d5ecbe5526 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -90,7 +90,7 @@ static long restore_sigcontext(struct pt_regs *regs, /* sc_regs is structured the same as the start of pt_regs */ err = __copy_from_user(regs, &sc->sc_regs, sizeof(sc->sc_regs)); /* Restore the floating-point state. */ - if (has_fpu) + if (has_fpu()) err |= restore_fp_state(regs, &sc->sc_fpregs); return err; } @@ -143,7 +143,7 @@ static long setup_sigcontext(struct rt_sigframe __user *frame, /* sc_regs is structured the same as the start of pt_regs */ err = __copy_to_user(&sc->sc_regs, regs, sizeof(sc->sc_regs)); /* Save the floating-point state. */ - if (has_fpu) + if (has_fpu()) err |= save_fp_state(regs, &sc->sc_fpregs); return err; } diff --git a/arch/riscv/kernel/stacktrace.c b/arch/riscv/kernel/stacktrace.c index ff467b98c3e3..ac7593607fa6 100644 --- a/arch/riscv/kernel/stacktrace.c +++ b/arch/riscv/kernel/stacktrace.c @@ -132,8 +132,12 @@ unsigned long get_wchan(struct task_struct *task) { unsigned long pc = 0; - if (likely(task && task != current && !task_is_running(task))) + if (likely(task && task != current && !task_is_running(task))) { + if (!try_get_task_stack(task)) + return 0; walk_stackframe(task, NULL, save_wchan, &pc); + put_task_stack(task); + } return pc; } diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 7bc88d8aab97..0a98fd0ddfe9 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -203,3 +203,38 @@ int is_valid_bugaddr(unsigned long pc) void __init trap_init(void) { } + +#ifdef CONFIG_VMAP_STACK +static DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], + overflow_stack)__aligned(16); +/* + * shadow stack, handled_ kernel_ stack_ overflow(in kernel/entry.S) is used + * to get per-cpu overflow stack(get_overflow_stack). + */ +long shadow_stack[SHADOW_OVERFLOW_STACK_SIZE/sizeof(long)]; +asmlinkage unsigned long get_overflow_stack(void) +{ + return (unsigned long)this_cpu_ptr(overflow_stack) + + OVERFLOW_STACK_SIZE; +} + +asmlinkage void handle_bad_stack(struct pt_regs *regs) +{ + unsigned long tsk_stk = (unsigned long)current->stack; + unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack); + + console_verbose(); + + pr_emerg("Insufficient stack space to handle exception!\n"); + pr_emerg("Task stack: [0x%016lx..0x%016lx]\n", + tsk_stk, tsk_stk + THREAD_SIZE); + pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n", + ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE); + + __show_regs(regs); + panic("Kernel stack overflow"); + + for (;;) + wait_for_interrupt(); +} +#endif diff --git a/arch/riscv/kernel/vmlinux-xip.lds.S b/arch/riscv/kernel/vmlinux-xip.lds.S index a3ff09c4c3f9..af776555ded9 100644 --- a/arch/riscv/kernel/vmlinux-xip.lds.S +++ b/arch/riscv/kernel/vmlinux-xip.lds.S @@ -12,7 +12,6 @@ #include <asm/vmlinux.lds.h> #include <asm/page.h> -#include <asm/pgtable.h> #include <asm/cache.h> #include <asm/thread_info.h> diff --git a/arch/riscv/kernel/vmlinux.lds.S b/arch/riscv/kernel/vmlinux.lds.S index 891742ff75a7..502d0826ecb1 100644 --- a/arch/riscv/kernel/vmlinux.lds.S +++ b/arch/riscv/kernel/vmlinux.lds.S @@ -117,7 +117,7 @@ SECTIONS . = ALIGN(SECTION_ALIGN); _data = .; - RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE) + RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_ALIGN) .sdata : { __global_pointer$ = . + 0x800; *(.sdata*) diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S index fceaeb18cc64..63bc691cff91 100644 --- a/arch/riscv/lib/uaccess.S +++ b/arch/riscv/lib/uaccess.S @@ -19,50 +19,160 @@ ENTRY(__asm_copy_from_user) li t6, SR_SUM csrs CSR_STATUS, t6 - add a3, a1, a2 - /* Use word-oriented copy only if low-order bits match */ - andi t0, a0, SZREG-1 - andi t1, a1, SZREG-1 - bne t0, t1, 2f + /* Save for return value */ + mv t5, a2 - addi t0, a1, SZREG-1 - andi t1, a3, ~(SZREG-1) - andi t0, t0, ~(SZREG-1) /* - * a3: terminal address of source region - * t0: lowest XLEN-aligned address in source - * t1: highest XLEN-aligned address in source + * Register allocation for code below: + * a0 - start of uncopied dst + * a1 - start of uncopied src + * a2 - size + * t0 - end of uncopied dst */ - bgeu t0, t1, 2f - bltu a1, t0, 4f + add t0, a0, a2 + + /* + * Use byte copy only if too small. + * SZREG holds 4 for RV32 and 8 for RV64 + */ + li a3, 9*SZREG /* size must be larger than size in word_copy */ + bltu a2, a3, .Lbyte_copy_tail + + /* + * Copy first bytes until dst is aligned to word boundary. + * a0 - start of dst + * t1 - start of aligned dst + */ + addi t1, a0, SZREG-1 + andi t1, t1, ~(SZREG-1) + /* dst is already aligned, skip */ + beq a0, t1, .Lskip_align_dst 1: - fixup REG_L, t2, (a1), 10f - fixup REG_S, t2, (a0), 10f - addi a1, a1, SZREG - addi a0, a0, SZREG - bltu a1, t1, 1b + /* a5 - one byte for copying data */ + fixup lb a5, 0(a1), 10f + addi a1, a1, 1 /* src */ + fixup sb a5, 0(a0), 10f + addi a0, a0, 1 /* dst */ + bltu a0, t1, 1b /* t1 - start of aligned dst */ + +.Lskip_align_dst: + /* + * Now dst is aligned. + * Use shift-copy if src is misaligned. + * Use word-copy if both src and dst are aligned because + * can not use shift-copy which do not require shifting + */ + /* a1 - start of src */ + andi a3, a1, SZREG-1 + bnez a3, .Lshift_copy + +.Lword_copy: + /* + * Both src and dst are aligned, unrolled word copy + * + * a0 - start of aligned dst + * a1 - start of aligned src + * t0 - end of aligned dst + */ + addi t0, t0, -(8*SZREG) /* not to over run */ 2: - bltu a1, a3, 5f + fixup REG_L a4, 0(a1), 10f + fixup REG_L a5, SZREG(a1), 10f + fixup REG_L a6, 2*SZREG(a1), 10f + fixup REG_L a7, 3*SZREG(a1), 10f + fixup REG_L t1, 4*SZREG(a1), 10f + fixup REG_L t2, 5*SZREG(a1), 10f + fixup REG_L t3, 6*SZREG(a1), 10f + fixup REG_L t4, 7*SZREG(a1), 10f + fixup REG_S a4, 0(a0), 10f + fixup REG_S a5, SZREG(a0), 10f + fixup REG_S a6, 2*SZREG(a0), 10f + fixup REG_S a7, 3*SZREG(a0), 10f + fixup REG_S t1, 4*SZREG(a0), 10f + fixup REG_S t2, 5*SZREG(a0), 10f + fixup REG_S t3, 6*SZREG(a0), 10f + fixup REG_S t4, 7*SZREG(a0), 10f + addi a0, a0, 8*SZREG + addi a1, a1, 8*SZREG + bltu a0, t0, 2b + + addi t0, t0, 8*SZREG /* revert to original value */ + j .Lbyte_copy_tail + +.Lshift_copy: + + /* + * Word copy with shifting. + * For misaligned copy we still perform aligned word copy, but + * we need to use the value fetched from the previous iteration and + * do some shifts. + * This is safe because reading is less than a word size. + * + * a0 - start of aligned dst + * a1 - start of src + * a3 - a1 & mask:(SZREG-1) + * t0 - end of uncopied dst + * t1 - end of aligned dst + */ + /* calculating aligned word boundary for dst */ + andi t1, t0, ~(SZREG-1) + /* Converting unaligned src to aligned src */ + andi a1, a1, ~(SZREG-1) + + /* + * Calculate shifts + * t3 - prev shift + * t4 - current shift + */ + slli t3, a3, 3 /* converting bytes in a3 to bits */ + li a5, SZREG*8 + sub t4, a5, t3 + + /* Load the first word to combine with second word */ + fixup REG_L a5, 0(a1), 10f 3: + /* Main shifting copy + * + * a0 - start of aligned dst + * a1 - start of aligned src + * t1 - end of aligned dst + */ + + /* At least one iteration will be executed */ + srl a4, a5, t3 + fixup REG_L a5, SZREG(a1), 10f + addi a1, a1, SZREG + sll a2, a5, t4 + or a2, a2, a4 + fixup REG_S a2, 0(a0), 10f + addi a0, a0, SZREG + bltu a0, t1, 3b + + /* Revert src to original unaligned value */ + add a1, a1, a3 + +.Lbyte_copy_tail: + /* + * Byte copy anything left. + * + * a0 - start of remaining dst + * a1 - start of remaining src + * t0 - end of remaining dst + */ + bgeu a0, t0, .Lout_copy_user /* check if end of copy */ +4: + fixup lb a5, 0(a1), 10f + addi a1, a1, 1 /* src */ + fixup sb a5, 0(a0), 10f + addi a0, a0, 1 /* dst */ + bltu a0, t0, 4b /* t0 - end of dst */ + +.Lout_copy_user: /* Disable access to user memory */ csrc CSR_STATUS, t6 - li a0, 0 + li a0, 0 ret -4: /* Edge case: unalignment */ - fixup lbu, t2, (a1), 10f - fixup sb, t2, (a0), 10f - addi a1, a1, 1 - addi a0, a0, 1 - bltu a1, t0, 4b - j 1b -5: /* Edge case: remainder */ - fixup lbu, t2, (a1), 10f - fixup sb, t2, (a0), 10f - addi a1, a1, 1 - addi a0, a0, 1 - bltu a1, a3, 5b - j 3b ENDPROC(__asm_copy_to_user) ENDPROC(__asm_copy_from_user) EXPORT_SYMBOL(__asm_copy_to_user) @@ -117,7 +227,7 @@ EXPORT_SYMBOL(__clear_user) 10: /* Disable access to user memory */ csrs CSR_STATUS, t6 - mv a0, a2 + mv a0, t5 ret 11: csrs CSR_STATUS, t6 diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index 68aa312fc352..ee3459cb6750 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -18,7 +18,7 @@ #ifdef CONFIG_MMU -static DEFINE_STATIC_KEY_FALSE(use_asid_allocator); +DEFINE_STATIC_KEY_FALSE(use_asid_allocator); static unsigned long asid_bits; static unsigned long num_asids; @@ -213,7 +213,7 @@ static inline void set_mm(struct mm_struct *mm, unsigned int cpu) set_mm_noasid(mm); } -static int asids_init(void) +static int __init asids_init(void) { unsigned long old; @@ -243,8 +243,7 @@ static int asids_init(void) if (num_asids > (2 * num_possible_cpus())) { atomic_long_set(¤t_version, num_asids); - context_asid_map = kcalloc(BITS_TO_LONGS(num_asids), - sizeof(*context_asid_map), GFP_KERNEL); + context_asid_map = bitmap_zalloc(num_asids, GFP_KERNEL); if (!context_asid_map) panic("Failed to allocate bitmap for %lu ASIDs\n", num_asids); @@ -280,11 +279,12 @@ static inline void set_mm(struct mm_struct *mm, unsigned int cpu) * cache flush to be performed before execution resumes on each hart. This * actually performs that local instruction cache flush, which implicitly only * refers to the current hart. + * + * The "cpu" argument must be the current local CPU number. */ -static inline void flush_icache_deferred(struct mm_struct *mm) +static inline void flush_icache_deferred(struct mm_struct *mm, unsigned int cpu) { #ifdef CONFIG_SMP - unsigned int cpu = smp_processor_id(); cpumask_t *mask = &mm->context.icache_stale_mask; if (cpumask_test_cpu(cpu, mask)) { @@ -320,5 +320,5 @@ void switch_mm(struct mm_struct *prev, struct mm_struct *next, set_mm(next, cpu); - flush_icache_deferred(next); + flush_icache_deferred(next, cpu); } diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c index 096463cc6fff..aa08dd2f8fae 100644 --- a/arch/riscv/mm/fault.c +++ b/arch/riscv/mm/fault.c @@ -14,6 +14,7 @@ #include <linux/signal.h> #include <linux/uaccess.h> #include <linux/kprobes.h> +#include <linux/kfence.h> #include <asm/ptrace.h> #include <asm/tlbflush.h> @@ -45,7 +46,15 @@ static inline void no_context(struct pt_regs *regs, unsigned long addr) * Oops. The kernel tried to access some bad page. We'll have to * terminate things with extreme prejudice. */ - msg = (addr < PAGE_SIZE) ? "NULL pointer dereference" : "paging request"; + if (addr < PAGE_SIZE) + msg = "NULL pointer dereference"; + else { + if (kfence_handle_page_fault(addr, regs->cause == EXC_STORE_PAGE_FAULT, regs)) + return; + + msg = "paging request"; + } + die_kernel_fault(msg, addr, regs); } diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 4c4c92ce0bb8..a14bf3910eec 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -11,6 +11,7 @@ #include <linux/memblock.h> #include <linux/initrd.h> #include <linux/swap.h> +#include <linux/swiotlb.h> #include <linux/sizes.h> #include <linux/of_fdt.h> #include <linux/of_reserved_mem.h> @@ -29,10 +30,14 @@ #include "../kernel/head.h" -unsigned long kernel_virt_addr = KERNEL_LINK_ADDR; -EXPORT_SYMBOL(kernel_virt_addr); +struct kernel_mapping kernel_map __ro_after_init; +EXPORT_SYMBOL(kernel_map); #ifdef CONFIG_XIP_KERNEL -#define kernel_virt_addr (*((unsigned long *)XIP_FIXUP(&kernel_virt_addr))) +#define kernel_map (*(struct kernel_mapping *)XIP_FIXUP(&kernel_map)) +#endif + +#ifdef CONFIG_XIP_KERNEL +extern char _xiprom[], _exiprom[]; #endif unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)] @@ -53,7 +58,7 @@ struct pt_alloc_ops { #endif }; -static phys_addr_t dma32_phys_limit __ro_after_init; +static phys_addr_t dma32_phys_limit __initdata; static void __init zone_sizes_init(void) { @@ -67,11 +72,6 @@ static void __init zone_sizes_init(void) free_area_init(max_zone_pfns); } -static void __init setup_zero_page(void) -{ - memset((void *)empty_zero_page, 0, PAGE_SIZE); -} - #if defined(CONFIG_MMU) && defined(CONFIG_DEBUG_VM) static inline void print_mlk(char *name, unsigned long b, unsigned long t) { @@ -113,25 +113,60 @@ void __init mem_init(void) BUG_ON(!mem_map); #endif /* CONFIG_FLATMEM */ +#ifdef CONFIG_SWIOTLB + if (swiotlb_force == SWIOTLB_FORCE || + max_pfn > PFN_DOWN(dma32_phys_limit)) + swiotlb_init(1); + else + swiotlb_force = SWIOTLB_NO_FORCE; +#endif high_memory = (void *)(__va(PFN_PHYS(max_low_pfn))); memblock_free_all(); print_vm_layout(); } -void __init setup_bootmem(void) +/* + * The default maximal physical memory size is -PAGE_OFFSET for 32-bit kernel, + * whereas for 64-bit kernel, the end of the virtual address space is occupied + * by the modules/BPF/kernel mappings which reduces the available size of the + * linear mapping. + * Limit the memory size via mem. + */ +#ifdef CONFIG_64BIT +static phys_addr_t memory_limit = -PAGE_OFFSET - SZ_4G; +#else +static phys_addr_t memory_limit = -PAGE_OFFSET; +#endif + +static int __init early_mem(char *p) +{ + u64 size; + + if (!p) + return 1; + + size = memparse(p, &p) & PAGE_MASK; + memory_limit = min_t(u64, size, memory_limit); + + pr_notice("Memory limited to %lldMB\n", (u64)memory_limit >> 20); + + return 0; +} +early_param("mem", early_mem); + +static void __init setup_bootmem(void) { phys_addr_t vmlinux_end = __pa_symbol(&_end); phys_addr_t vmlinux_start = __pa_symbol(&_start); - phys_addr_t dram_end = memblock_end_of_DRAM(); - phys_addr_t max_mapped_addr = __pa(~(ulong)0); + phys_addr_t __maybe_unused max_mapped_addr; + phys_addr_t dram_end; #ifdef CONFIG_XIP_KERNEL vmlinux_start = __pa_symbol(&_sdata); #endif - /* The maximal physical memory size is -PAGE_OFFSET. */ - memblock_enforce_memory_limit(-PAGE_OFFSET); + memblock_enforce_memory_limit(memory_limit); /* * Reserve from the start of the kernel to the end of the kernel @@ -146,14 +181,22 @@ void __init setup_bootmem(void) #endif memblock_reserve(vmlinux_start, vmlinux_end - vmlinux_start); + dram_end = memblock_end_of_DRAM(); + +#ifndef CONFIG_64BIT /* * memblock allocator is not aware of the fact that last 4K bytes of * the addressable memory can not be mapped because of IS_ERR_VALUE * macro. Make sure that last 4k bytes are not usable by memblock - * if end of dram is equal to maximum addressable memory. + * if end of dram is equal to maximum addressable memory. For 64-bit + * kernel, this problem can't happen here as the end of the virtual + * address space is occupied by the kernel mapping then this check must + * be done in create_kernel_page_table. */ + max_mapped_addr = __pa(~(ulong)0); if (max_mapped_addr == (dram_end - 1)) memblock_set_current_limit(max_mapped_addr - 4096); +#endif min_low_pfn = PFN_UP(memblock_start_of_DRAM()); max_low_pfn = max_pfn = PFN_DOWN(dram_end); @@ -176,15 +219,8 @@ void __init setup_bootmem(void) memblock_allow_resize(); } -#ifdef CONFIG_XIP_KERNEL - -extern char _xiprom[], _exiprom[]; -extern char _sdata[], _edata[]; - -#endif /* CONFIG_XIP_KERNEL */ - #ifdef CONFIG_MMU -static struct pt_alloc_ops _pt_ops __ro_after_init; +static struct pt_alloc_ops _pt_ops __initdata; #ifdef CONFIG_XIP_KERNEL #define pt_ops (*(struct pt_alloc_ops *)XIP_FIXUP(&_pt_ops)) @@ -192,31 +228,12 @@ static struct pt_alloc_ops _pt_ops __ro_after_init; #define pt_ops _pt_ops #endif -/* Offset between linear mapping virtual address and kernel load address */ -unsigned long va_pa_offset __ro_after_init; -EXPORT_SYMBOL(va_pa_offset); -#ifdef CONFIG_XIP_KERNEL -#define va_pa_offset (*((unsigned long *)XIP_FIXUP(&va_pa_offset))) -#endif -/* Offset between kernel mapping virtual address and kernel load address */ -#ifdef CONFIG_64BIT -unsigned long va_kernel_pa_offset; -EXPORT_SYMBOL(va_kernel_pa_offset); -#endif -#ifdef CONFIG_XIP_KERNEL -#define va_kernel_pa_offset (*((unsigned long *)XIP_FIXUP(&va_kernel_pa_offset))) -#endif -unsigned long va_kernel_xip_pa_offset; -EXPORT_SYMBOL(va_kernel_xip_pa_offset); -#ifdef CONFIG_XIP_KERNEL -#define va_kernel_xip_pa_offset (*((unsigned long *)XIP_FIXUP(&va_kernel_xip_pa_offset))) -#endif unsigned long pfn_base __ro_after_init; EXPORT_SYMBOL(pfn_base); pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned_bss; pgd_t trampoline_pg_dir[PTRS_PER_PGD] __page_aligned_bss; -pte_t fixmap_pte[PTRS_PER_PTE] __page_aligned_bss; +static pte_t fixmap_pte[PTRS_PER_PTE] __page_aligned_bss; pgd_t early_pg_dir[PTRS_PER_PGD] __initdata __aligned(PAGE_SIZE); @@ -253,7 +270,7 @@ static inline pte_t *__init get_pte_virt_fixmap(phys_addr_t pa) return (pte_t *)set_fixmap_offset(FIX_PTE, pa); } -static inline pte_t *get_pte_virt_late(phys_addr_t pa) +static inline pte_t *__init get_pte_virt_late(phys_addr_t pa) { return (pte_t *) __va(pa); } @@ -272,7 +289,7 @@ static inline phys_addr_t __init alloc_pte_fixmap(uintptr_t va) return memblock_phys_alloc(PAGE_SIZE, PAGE_SIZE); } -static phys_addr_t alloc_pte_late(uintptr_t va) +static phys_addr_t __init alloc_pte_late(uintptr_t va) { unsigned long vaddr; @@ -296,10 +313,10 @@ static void __init create_pte_mapping(pte_t *ptep, #ifndef __PAGETABLE_PMD_FOLDED -pmd_t trampoline_pmd[PTRS_PER_PMD] __page_aligned_bss; -pmd_t fixmap_pmd[PTRS_PER_PMD] __page_aligned_bss; -pmd_t early_pmd[PTRS_PER_PMD] __initdata __aligned(PAGE_SIZE); -pmd_t early_dtb_pmd[PTRS_PER_PMD] __initdata __aligned(PAGE_SIZE); +static pmd_t trampoline_pmd[PTRS_PER_PMD] __page_aligned_bss; +static pmd_t fixmap_pmd[PTRS_PER_PMD] __page_aligned_bss; +static pmd_t early_pmd[PTRS_PER_PMD] __initdata __aligned(PAGE_SIZE); +static pmd_t early_dtb_pmd[PTRS_PER_PMD] __initdata __aligned(PAGE_SIZE); #ifdef CONFIG_XIP_KERNEL #define trampoline_pmd ((pmd_t *)XIP_FIXUP(trampoline_pmd)) @@ -319,14 +336,14 @@ static pmd_t *__init get_pmd_virt_fixmap(phys_addr_t pa) return (pmd_t *)set_fixmap_offset(FIX_PMD, pa); } -static pmd_t *get_pmd_virt_late(phys_addr_t pa) +static pmd_t *__init get_pmd_virt_late(phys_addr_t pa) { return (pmd_t *) __va(pa); } static phys_addr_t __init alloc_pmd_early(uintptr_t va) { - BUG_ON((va - kernel_virt_addr) >> PGDIR_SHIFT); + BUG_ON((va - kernel_map.virt_addr) >> PGDIR_SHIFT); return (uintptr_t)early_pmd; } @@ -336,7 +353,7 @@ static phys_addr_t __init alloc_pmd_fixmap(uintptr_t va) return memblock_phys_alloc(PAGE_SIZE, PAGE_SIZE); } -static phys_addr_t alloc_pmd_late(uintptr_t va) +static phys_addr_t __init alloc_pmd_late(uintptr_t va) { unsigned long vaddr; @@ -436,6 +453,43 @@ asmlinkage void __init __copy_data(void) } #endif +#ifdef CONFIG_STRICT_KERNEL_RWX +static __init pgprot_t pgprot_from_va(uintptr_t va) +{ + if (is_va_kernel_text(va)) + return PAGE_KERNEL_READ_EXEC; + + /* + * In 64-bit kernel, the kernel mapping is outside the linear mapping so + * we must protect its linear mapping alias from being executed and + * written. + * And rodata section is marked readonly in mark_rodata_ro. + */ + if (IS_ENABLED(CONFIG_64BIT) && is_va_kernel_lm_alias_text(va)) + return PAGE_KERNEL_READ; + + return PAGE_KERNEL; +} + +void mark_rodata_ro(void) +{ + set_kernel_memory(__start_rodata, _data, set_memory_ro); + if (IS_ENABLED(CONFIG_64BIT)) + set_kernel_memory(lm_alias(__start_rodata), lm_alias(_data), + set_memory_ro); + + debug_checkwx(); +} +#else +static __init pgprot_t pgprot_from_va(uintptr_t va) +{ + if (IS_ENABLED(CONFIG_64BIT) && !is_kernel_mapping(va)) + return PAGE_KERNEL; + + return PAGE_KERNEL_EXEC; +} +#endif /* CONFIG_STRICT_KERNEL_RWX */ + /* * setup_vm() is called from head.S with MMU-off. * @@ -454,45 +508,39 @@ asmlinkage void __init __copy_data(void) #error "setup_vm() is called from head.S before relocate so it should not use absolute addressing." #endif -uintptr_t load_pa, load_sz; #ifdef CONFIG_XIP_KERNEL -#define load_pa (*((uintptr_t *)XIP_FIXUP(&load_pa))) -#define load_sz (*((uintptr_t *)XIP_FIXUP(&load_sz))) -#endif - -#ifdef CONFIG_XIP_KERNEL -uintptr_t xiprom, xiprom_sz; -#define xiprom_sz (*((uintptr_t *)XIP_FIXUP(&xiprom_sz))) -#define xiprom (*((uintptr_t *)XIP_FIXUP(&xiprom))) - -static void __init create_kernel_page_table(pgd_t *pgdir, uintptr_t map_size) +static void __init create_kernel_page_table(pgd_t *pgdir, uintptr_t map_size, + __always_unused bool early) { uintptr_t va, end_va; /* Map the flash resident part */ - end_va = kernel_virt_addr + xiprom_sz; - for (va = kernel_virt_addr; va < end_va; va += map_size) + end_va = kernel_map.virt_addr + kernel_map.xiprom_sz; + for (va = kernel_map.virt_addr; va < end_va; va += map_size) create_pgd_mapping(pgdir, va, - xiprom + (va - kernel_virt_addr), + kernel_map.xiprom + (va - kernel_map.virt_addr), map_size, PAGE_KERNEL_EXEC); /* Map the data in RAM */ - end_va = kernel_virt_addr + XIP_OFFSET + load_sz; - for (va = kernel_virt_addr + XIP_OFFSET; va < end_va; va += map_size) + end_va = kernel_map.virt_addr + XIP_OFFSET + kernel_map.size; + for (va = kernel_map.virt_addr + XIP_OFFSET; va < end_va; va += map_size) create_pgd_mapping(pgdir, va, - load_pa + (va - (kernel_virt_addr + XIP_OFFSET)), + kernel_map.phys_addr + (va - (kernel_map.virt_addr + XIP_OFFSET)), map_size, PAGE_KERNEL); } #else -static void __init create_kernel_page_table(pgd_t *pgdir, uintptr_t map_size) +static void __init create_kernel_page_table(pgd_t *pgdir, uintptr_t map_size, + bool early) { uintptr_t va, end_va; - end_va = kernel_virt_addr + load_sz; - for (va = kernel_virt_addr; va < end_va; va += map_size) + end_va = kernel_map.virt_addr + kernel_map.size; + for (va = kernel_map.virt_addr; va < end_va; va += map_size) create_pgd_mapping(pgdir, va, - load_pa + (va - kernel_virt_addr), - map_size, PAGE_KERNEL_EXEC); + kernel_map.phys_addr + (va - kernel_map.virt_addr), + map_size, + early ? + PAGE_KERNEL_EXEC : pgprot_from_va(va)); } #endif @@ -504,25 +552,27 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) pmd_t fix_bmap_spmd, fix_bmap_epmd; #endif + kernel_map.virt_addr = KERNEL_LINK_ADDR; + #ifdef CONFIG_XIP_KERNEL - xiprom = (uintptr_t)CONFIG_XIP_PHYS_ADDR; - xiprom_sz = (uintptr_t)(&_exiprom) - (uintptr_t)(&_xiprom); + kernel_map.xiprom = (uintptr_t)CONFIG_XIP_PHYS_ADDR; + kernel_map.xiprom_sz = (uintptr_t)(&_exiprom) - (uintptr_t)(&_xiprom); - load_pa = (uintptr_t)CONFIG_PHYS_RAM_BASE; - load_sz = (uintptr_t)(&_end) - (uintptr_t)(&_sdata); + kernel_map.phys_addr = (uintptr_t)CONFIG_PHYS_RAM_BASE; + kernel_map.size = (uintptr_t)(&_end) - (uintptr_t)(&_sdata); - va_kernel_xip_pa_offset = kernel_virt_addr - xiprom; + kernel_map.va_kernel_xip_pa_offset = kernel_map.virt_addr - kernel_map.xiprom; #else - load_pa = (uintptr_t)(&_start); - load_sz = (uintptr_t)(&_end) - load_pa; + kernel_map.phys_addr = (uintptr_t)(&_start); + kernel_map.size = (uintptr_t)(&_end) - kernel_map.phys_addr; #endif - va_pa_offset = PAGE_OFFSET - load_pa; + kernel_map.va_pa_offset = PAGE_OFFSET - kernel_map.phys_addr; #ifdef CONFIG_64BIT - va_kernel_pa_offset = kernel_virt_addr - load_pa; + kernel_map.va_kernel_pa_offset = kernel_map.virt_addr - kernel_map.phys_addr; #endif - pfn_base = PFN_DOWN(load_pa); + pfn_base = PFN_DOWN(kernel_map.phys_addr); /* * Enforce boot alignment requirements of RV32 and @@ -532,7 +582,15 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) /* Sanity check alignment and size */ BUG_ON((PAGE_OFFSET % PGDIR_SIZE) != 0); - BUG_ON((load_pa % map_size) != 0); + BUG_ON((kernel_map.phys_addr % map_size) != 0); + +#ifdef CONFIG_64BIT + /* + * The last 4K bytes of the addressable memory can not be mapped because + * of IS_ERR_VALUE macro. + */ + BUG_ON((kernel_map.virt_addr + kernel_map.size) > ADDRESS_SPACE_END - SZ_4K); +#endif pt_ops.alloc_pte = alloc_pte_early; pt_ops.get_pte_virt = get_pte_virt_early; @@ -549,19 +607,19 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) create_pmd_mapping(fixmap_pmd, FIXADDR_START, (uintptr_t)fixmap_pte, PMD_SIZE, PAGE_TABLE); /* Setup trampoline PGD and PMD */ - create_pgd_mapping(trampoline_pg_dir, kernel_virt_addr, + create_pgd_mapping(trampoline_pg_dir, kernel_map.virt_addr, (uintptr_t)trampoline_pmd, PGDIR_SIZE, PAGE_TABLE); #ifdef CONFIG_XIP_KERNEL - create_pmd_mapping(trampoline_pmd, kernel_virt_addr, - xiprom, PMD_SIZE, PAGE_KERNEL_EXEC); + create_pmd_mapping(trampoline_pmd, kernel_map.virt_addr, + kernel_map.xiprom, PMD_SIZE, PAGE_KERNEL_EXEC); #else - create_pmd_mapping(trampoline_pmd, kernel_virt_addr, - load_pa, PMD_SIZE, PAGE_KERNEL_EXEC); + create_pmd_mapping(trampoline_pmd, kernel_map.virt_addr, + kernel_map.phys_addr, PMD_SIZE, PAGE_KERNEL_EXEC); #endif #else /* Setup trampoline PGD */ - create_pgd_mapping(trampoline_pg_dir, kernel_virt_addr, - load_pa, PGDIR_SIZE, PAGE_KERNEL_EXEC); + create_pgd_mapping(trampoline_pg_dir, kernel_map.virt_addr, + kernel_map.phys_addr, PGDIR_SIZE, PAGE_KERNEL_EXEC); #endif /* @@ -569,7 +627,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) * us to reach paging_init(). We map all memory banks later * in setup_vm_final() below. */ - create_kernel_page_table(early_pg_dir, map_size); + create_kernel_page_table(early_pg_dir, map_size, true); #ifndef __PAGETABLE_PMD_FOLDED /* Setup early PMD for DTB */ @@ -645,22 +703,6 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) #endif } -#if defined(CONFIG_64BIT) && defined(CONFIG_STRICT_KERNEL_RWX) -void protect_kernel_linear_mapping_text_rodata(void) -{ - unsigned long text_start = (unsigned long)lm_alias(_start); - unsigned long init_text_start = (unsigned long)lm_alias(__init_text_begin); - unsigned long rodata_start = (unsigned long)lm_alias(__start_rodata); - unsigned long data_start = (unsigned long)lm_alias(_data); - - set_memory_ro(text_start, (init_text_start - text_start) >> PAGE_SHIFT); - set_memory_nx(text_start, (init_text_start - text_start) >> PAGE_SHIFT); - - set_memory_ro(rodata_start, (data_start - rodata_start) >> PAGE_SHIFT); - set_memory_nx(rodata_start, (data_start - rodata_start) >> PAGE_SHIFT); -} -#endif - static void __init setup_vm_final(void) { uintptr_t va, map_size; @@ -689,25 +731,21 @@ static void __init setup_vm_final(void) if (start <= __pa(PAGE_OFFSET) && __pa(PAGE_OFFSET) < end) start = __pa(PAGE_OFFSET); + if (end >= __pa(PAGE_OFFSET) + memory_limit) + end = __pa(PAGE_OFFSET) + memory_limit; map_size = best_map_size(start, end - start); for (pa = start; pa < end; pa += map_size) { va = (uintptr_t)__va(pa); - create_pgd_mapping(swapper_pg_dir, va, pa, - map_size, -#ifdef CONFIG_64BIT - PAGE_KERNEL -#else - PAGE_KERNEL_EXEC -#endif - ); + create_pgd_mapping(swapper_pg_dir, va, pa, map_size, + pgprot_from_va(va)); } } #ifdef CONFIG_64BIT /* Map the kernel */ - create_kernel_page_table(swapper_pg_dir, PMD_SIZE); + create_kernel_page_table(swapper_pg_dir, PMD_SIZE, false); #endif /* Clear fixmap PTE and PMD mappings */ @@ -738,39 +776,6 @@ static inline void setup_vm_final(void) } #endif /* CONFIG_MMU */ -#ifdef CONFIG_STRICT_KERNEL_RWX -void __init protect_kernel_text_data(void) -{ - unsigned long text_start = (unsigned long)_start; - unsigned long init_text_start = (unsigned long)__init_text_begin; - unsigned long init_data_start = (unsigned long)__init_data_begin; - unsigned long rodata_start = (unsigned long)__start_rodata; - unsigned long data_start = (unsigned long)_data; -#if defined(CONFIG_64BIT) && defined(CONFIG_MMU) - unsigned long end_va = kernel_virt_addr + load_sz; -#else - unsigned long end_va = (unsigned long)(__va(PFN_PHYS(max_low_pfn))); -#endif - - set_memory_ro(text_start, (init_text_start - text_start) >> PAGE_SHIFT); - set_memory_ro(init_text_start, (init_data_start - init_text_start) >> PAGE_SHIFT); - set_memory_nx(init_data_start, (rodata_start - init_data_start) >> PAGE_SHIFT); - /* rodata section is marked readonly in mark_rodata_ro */ - set_memory_nx(rodata_start, (data_start - rodata_start) >> PAGE_SHIFT); - set_memory_nx(data_start, (end_va - data_start) >> PAGE_SHIFT); -} - -void mark_rodata_ro(void) -{ - unsigned long rodata_start = (unsigned long)__start_rodata; - unsigned long data_start = (unsigned long)_data; - - set_memory_ro(rodata_start, (data_start - rodata_start) >> PAGE_SHIFT); - - debug_checkwx(); -} -#endif - #ifdef CONFIG_KEXEC_CORE /* * reserve_crashkernel() - reserves memory for crash kernel @@ -858,7 +863,7 @@ static void __init reserve_crashkernel(void) * reserved once we call early_init_fdt_scan_reserved_mem() * later on. */ -static int elfcore_hdr_setup(struct reserved_mem *rmem) +static int __init elfcore_hdr_setup(struct reserved_mem *rmem) { elfcorehdr_addr = rmem->base; elfcorehdr_size = rmem->size; @@ -870,8 +875,8 @@ RESERVEDMEM_OF_DECLARE(elfcorehdr, "linux,elfcorehdr", elfcore_hdr_setup); void __init paging_init(void) { + setup_bootmem(); setup_vm_final(); - setup_zero_page(); } void __init misc_mem_init(void) diff --git a/arch/riscv/mm/physaddr.c b/arch/riscv/mm/physaddr.c index 35703d5ef5fd..e7fd0c253c7b 100644 --- a/arch/riscv/mm/physaddr.c +++ b/arch/riscv/mm/physaddr.c @@ -23,7 +23,7 @@ EXPORT_SYMBOL(__virt_to_phys); phys_addr_t __phys_addr_symbol(unsigned long x) { - unsigned long kernel_start = (unsigned long)kernel_virt_addr; + unsigned long kernel_start = kernel_map.virt_addr; unsigned long kernel_end = (unsigned long)_end; /* diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c index 0536ac84b730..830e7de65e3a 100644 --- a/arch/riscv/mm/ptdump.c +++ b/arch/riscv/mm/ptdump.c @@ -98,8 +98,8 @@ static struct addr_marker address_markers[] = { {0, "vmalloc() end"}, {0, "Linear mapping"}, #ifdef CONFIG_64BIT - {0, "Modules mapping"}, - {0, "Kernel mapping (kernel, BPF)"}, + {0, "Modules/BPF mapping"}, + {0, "Kernel mapping"}, #endif {-1, NULL}, }; @@ -379,7 +379,7 @@ static int __init ptdump_init(void) address_markers[PAGE_OFFSET_NR].start_address = PAGE_OFFSET; #ifdef CONFIG_64BIT address_markers[MODULES_MAPPING_NR].start_address = MODULES_VADDR; - address_markers[KERNEL_MAPPING_NR].start_address = kernel_virt_addr; + address_markers[KERNEL_MAPPING_NR].start_address = kernel_map.virt_addr; #endif kernel_ptd_info.base_addr = KERN_VIRT_START; diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 720b443c4528..64f8201237c2 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -4,36 +4,66 @@ #include <linux/smp.h> #include <linux/sched.h> #include <asm/sbi.h> +#include <asm/mmu_context.h> + +static inline void local_flush_tlb_all_asid(unsigned long asid) +{ + __asm__ __volatile__ ("sfence.vma x0, %0" + : + : "r" (asid) + : "memory"); +} + +static inline void local_flush_tlb_page_asid(unsigned long addr, + unsigned long asid) +{ + __asm__ __volatile__ ("sfence.vma %0, %1" + : + : "r" (addr), "r" (asid) + : "memory"); +} void flush_tlb_all(void) { sbi_remote_sfence_vma(NULL, 0, -1); } -/* - * This function must not be called with cmask being null. - * Kernel may panic if cmask is NULL. - */ -static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start, - unsigned long size) +static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start, + unsigned long size, unsigned long stride) { + struct cpumask *cmask = mm_cpumask(mm); struct cpumask hmask; unsigned int cpuid; + bool broadcast; if (cpumask_empty(cmask)) return; cpuid = get_cpu(); + /* check if the tlbflush needs to be sent to other CPUs */ + broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids; + if (static_branch_unlikely(&use_asid_allocator)) { + unsigned long asid = atomic_long_read(&mm->context.id); - if (cpumask_any_but(cmask, cpuid) >= nr_cpu_ids) { - /* local cpu is the only cpu present in cpumask */ - if (size <= PAGE_SIZE) + if (broadcast) { + riscv_cpuid_to_hartid_mask(cmask, &hmask); + sbi_remote_sfence_vma_asid(cpumask_bits(&hmask), + start, size, asid); + } else if (size <= stride) { + local_flush_tlb_page_asid(start, asid); + } else { + local_flush_tlb_all_asid(asid); + } + } else { + if (broadcast) { + riscv_cpuid_to_hartid_mask(cmask, &hmask); + sbi_remote_sfence_vma(cpumask_bits(&hmask), + start, size); + } else if (size <= stride) { local_flush_tlb_page(start); - else + } else { local_flush_tlb_all(); - } else { - riscv_cpuid_to_hartid_mask(cmask, &hmask); - sbi_remote_sfence_vma(cpumask_bits(&hmask), start, size); + } } put_cpu(); @@ -41,16 +71,23 @@ static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start, void flush_tlb_mm(struct mm_struct *mm) { - __sbi_tlb_flush_range(mm_cpumask(mm), 0, -1); + __sbi_tlb_flush_range(mm, 0, -1, PAGE_SIZE); } void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { - __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE); + __sbi_tlb_flush_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); } void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start); + __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PAGE_SIZE); +} +#ifdef CONFIG_TRANSPARENT_HUGEPAGE +void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end) +{ + __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PMD_SIZE); } +#endif diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 07b2328f29e0..a0e2130f0100 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -163,7 +163,6 @@ config S390 select HAVE_GCC_PLUGINS select HAVE_GENERIC_VDSO select HAVE_IOREMAP_PROT if PCI - select HAVE_IRQ_EXIT_ON_IRQ_STACK select HAVE_KERNEL_BZIP2 select HAVE_KERNEL_GZIP select HAVE_KERNEL_LZ4 @@ -438,6 +437,7 @@ config COMPAT select COMPAT_OLD_SIGACTION select HAVE_UID16 depends on MULTIUSER + depends on !CC_IS_CLANG help Select this option if you want to enable your system kernel to handle system-calls from ELF binaries for 31 bit ESA. This option diff --git a/arch/s390/Makefile b/arch/s390/Makefile index 098abe3a56f3..1e3172877982 100644 --- a/arch/s390/Makefile +++ b/arch/s390/Makefile @@ -129,9 +129,6 @@ OBJCOPYFLAGS := -O binary head-y := arch/s390/kernel/head64.o -# See arch/s390/Kbuild for content of core part of the kernel -core-y += arch/s390/ - libs-y += arch/s390/lib/ drivers-y += drivers/s390/ @@ -166,6 +163,19 @@ archheaders: archprepare: $(Q)$(MAKE) $(build)=$(syscalls) kapi $(Q)$(MAKE) $(build)=$(tools) kapi +ifeq ($(KBUILD_EXTMOD),) +# We need to generate vdso-offsets.h before compiling certain files in kernel/. +# In order to do that, we should use the archprepare target, but we can't since +# asm-offsets.h is included in some files used to generate vdso-offsets.h, and +# asm-offsets.h is built in prepare0, for which archprepare is a dependency. +# Therefore we need to generate the header after prepare0 has been made, hence +# this hack. +prepare: vdso_prepare +vdso_prepare: prepare0 + $(Q)$(MAKE) $(build)=arch/s390/kernel/vdso64 include/generated/vdso64-offsets.h + $(if $(CONFIG_COMPAT),$(Q)$(MAKE) \ + $(build)=arch/s390/kernel/vdso32 include/generated/vdso32-offsets.h) +endif # Don't use tabs in echo arguments define archhelp diff --git a/arch/s390/boot/startup.c b/arch/s390/boot/startup.c index bbe4df6c2f8b..d0cf21641e3a 100644 --- a/arch/s390/boot/startup.c +++ b/arch/s390/boot/startup.c @@ -23,6 +23,7 @@ unsigned long __bootdata_preserved(vmemmap_size); unsigned long __bootdata_preserved(MODULES_VADDR); unsigned long __bootdata_preserved(MODULES_END); unsigned long __bootdata(ident_map_size); +int __bootdata(is_full_image) = 1; u64 __bootdata_preserved(stfle_fac_list[16]); u64 __bootdata_preserved(alt_stfle_fac_list[16]); diff --git a/arch/s390/boot/text_dma.S b/arch/s390/boot/text_dma.S index f7c77cd518f2..5ff5fee02801 100644 --- a/arch/s390/boot/text_dma.S +++ b/arch/s390/boot/text_dma.S @@ -9,16 +9,6 @@ #include <asm/errno.h> #include <asm/sigp.h> -#ifdef CC_USING_EXPOLINE - .pushsection .dma.text.__s390_indirect_jump_r14,"axG" -__dma__s390_indirect_jump_r14: - larl %r1,0f - ex 0,0(%r1) - j . -0: br %r14 - .popsection -#endif - .section .dma.text,"ax" /* * Simplified version of expoline thunk. The normal thunks can not be used here, @@ -27,11 +17,10 @@ __dma__s390_indirect_jump_r14: * affects a few functions that are not performance-relevant. */ .macro BR_EX_DMA_r14 -#ifdef CC_USING_EXPOLINE - jg __dma__s390_indirect_jump_r14 -#else - br %r14 -#endif + larl %r1,0f + ex 0,0(%r1) + j . +0: br %r14 .endm /* diff --git a/arch/s390/boot/uv.c b/arch/s390/boot/uv.c index 82b99b916243..f6b0c4f43c99 100644 --- a/arch/s390/boot/uv.c +++ b/arch/s390/boot/uv.c @@ -36,6 +36,7 @@ void uv_query_info(void) uv_info.max_sec_stor_addr = ALIGN(uvcb.max_guest_stor_addr, PAGE_SIZE); uv_info.max_num_sec_conf = uvcb.max_num_sec_conf; uv_info.max_guest_cpu_id = uvcb.max_guest_cpu_id; + uv_info.uv_feature_indications = uvcb.uv_feature_indications; } #ifdef CONFIG_PROTECTED_VIRTUALIZATION_GUEST diff --git a/arch/s390/configs/debug_defconfig b/arch/s390/configs/debug_defconfig index 86afcc6b56bf..7de253f766e8 100644 --- a/arch/s390/configs/debug_defconfig +++ b/arch/s390/configs/debug_defconfig @@ -5,7 +5,12 @@ CONFIG_WATCH_QUEUE=y CONFIG_AUDIT=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_LSM=y CONFIG_PREEMPT=y +CONFIG_SCHED_CORE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y @@ -28,14 +33,13 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_MISC=y CONFIG_NAMESPACES=y CONFIG_USER_NS=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_SCHED_AUTOGROUP=y CONFIG_EXPERT=y # CONFIG_SYSFS_SYSCALL is not set -CONFIG_BPF_LSM=y -CONFIG_BPF_SYSCALL=y CONFIG_USERFAULTFD=y # CONFIG_COMPAT_BRK is not set CONFIG_PROFILING=y @@ -76,6 +80,7 @@ CONFIG_BLK_DEV_THROTTLING=y CONFIG_BLK_WBT=y CONFIG_BLK_CGROUP_IOLATENCY=y CONFIG_BLK_CGROUP_IOCOST=y +CONFIG_BLK_CGROUP_IOPRIO=y CONFIG_BLK_INLINE_ENCRYPTION=y CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y CONFIG_PARTITION_ADVANCED=y @@ -95,6 +100,7 @@ CONFIG_CLEANCACHE=y CONFIG_FRONTSWAP=y CONFIG_CMA_DEBUG=y CONFIG_CMA_DEBUGFS=y +CONFIG_CMA_SYSFS=y CONFIG_CMA_AREAS=7 CONFIG_MEM_SOFT_DIRTY=y CONFIG_ZSWAP=y @@ -158,6 +164,7 @@ CONFIG_IPV6_RPL_LWTUNNEL=y CONFIG_MPTCP=y CONFIG_NETFILTER=y CONFIG_BRIDGE_NETFILTER=m +CONFIG_NETFILTER_NETLINK_HOOK=m CONFIG_NF_CONNTRACK=m CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_EVENTS=y @@ -280,6 +287,7 @@ CONFIG_IP_VS_FTP=m CONFIG_IP_VS_PE_SIP=m CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y +CONFIG_NF_LOG_IPV4=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m @@ -384,12 +392,11 @@ CONFIG_VSOCKETS=m CONFIG_VIRTIO_VSOCKETS=m CONFIG_NETLINK_DIAG=m CONFIG_CGROUP_NET_PRIO=y -CONFIG_BPF_JIT=y CONFIG_NET_PKTGEN=m CONFIG_PCI=y -CONFIG_PCI_IOV=y # CONFIG_PCIEASPM is not set CONFIG_PCI_DEBUG=y +CONFIG_PCI_IOV=y CONFIG_HOTPLUG_PCI=y CONFIG_HOTPLUG_PCI_S390=y CONFIG_DEVTMPFS=y @@ -436,7 +443,7 @@ CONFIG_MD_MULTIPATH=m CONFIG_MD_FAULTY=m CONFIG_MD_CLUSTER=m CONFIG_BCACHE=m -CONFIG_BLK_DEV_DM=m +CONFIG_BLK_DEV_DM=y CONFIG_DM_UNSTRIPED=m CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m @@ -453,6 +460,7 @@ CONFIG_DM_MULTIPATH_ST=m CONFIG_DM_MULTIPATH_HST=m CONFIG_DM_MULTIPATH_IOA=m CONFIG_DM_DELAY=m +CONFIG_DM_INIT=y CONFIG_DM_UEVENT=y CONFIG_DM_FLAKEY=m CONFIG_DM_VERITY=m @@ -495,6 +503,7 @@ CONFIG_NLMON=m # CONFIG_NET_VENDOR_GOOGLE is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_NET_VENDOR_MARVELL is not set CONFIG_MLX4_EN=m CONFIG_MLX5_CORE=m @@ -551,7 +560,6 @@ CONFIG_INPUT_EVDEV=y CONFIG_LEGACY_PTY_COUNT=0 CONFIG_VIRTIO_CONSOLE=m CONFIG_HW_RANDOM_VIRTIO=m -CONFIG_RAW_DRIVER=m CONFIG_HANGCHECK_TIMER=m CONFIG_TN3270_FS=y CONFIG_PPS=m @@ -574,7 +582,6 @@ CONFIG_SYNC_FILE=y CONFIG_VFIO=m CONFIG_VFIO_PCI=m CONFIG_VFIO_MDEV=m -CONFIG_VFIO_MDEV_DEVICE=m CONFIG_VIRTIO_PCI=m CONFIG_VIRTIO_BALLOON=m CONFIG_VIRTIO_INPUT=y @@ -619,6 +626,7 @@ CONFIG_FUSE_FS=y CONFIG_CUSE=m CONFIG_VIRTIO_FS=m CONFIG_OVERLAY_FS=m +CONFIG_NETFS_STATS=y CONFIG_FSCACHE=m CONFIG_CACHEFILES=m CONFIG_ISO9660_FS=y @@ -654,7 +662,6 @@ CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_NFSD_V4_SECURITY_LABEL=y CONFIG_CIFS=m -CONFIG_CIFS_STATS2=y CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_UPCALL=y CONFIG_CIFS_XATTR=y @@ -682,6 +689,7 @@ CONFIG_SECURITY_SELINUX_BOOTPARAM=y CONFIG_SECURITY_SELINUX_DISABLE=y CONFIG_SECURITY_LOCKDOWN_LSM=y CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y +CONFIG_SECURITY_LANDLOCK=y CONFIG_INTEGRITY_SIGNATURE=y CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y CONFIG_IMA=y @@ -696,6 +704,7 @@ CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_DH=m CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECDSA=m CONFIG_CRYPTO_ECRDSA=m CONFIG_CRYPTO_SM2=m CONFIG_CRYPTO_CURVE25519=m @@ -843,7 +852,6 @@ CONFIG_FAULT_INJECTION_DEBUG_FS=y CONFIG_FAIL_FUNCTION=y CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y CONFIG_LKDTM=m -CONFIG_TEST_LIST_SORT=y CONFIG_TEST_MIN_HEAP=y CONFIG_TEST_SORT=y CONFIG_KPROBES_SANITY_TEST=y @@ -853,3 +861,4 @@ CONFIG_PERCPU_TEST=m CONFIG_ATOMIC64_SELFTEST=y CONFIG_TEST_BITOPS=m CONFIG_TEST_BPF=m +CONFIG_TEST_LIVEPATCH=m diff --git a/arch/s390/configs/defconfig b/arch/s390/configs/defconfig index 71b49ea5b058..b671642967ba 100644 --- a/arch/s390/configs/defconfig +++ b/arch/s390/configs/defconfig @@ -4,6 +4,11 @@ CONFIG_WATCH_QUEUE=y CONFIG_AUDIT=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_LSM=y +CONFIG_SCHED_CORE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y @@ -26,14 +31,13 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_MISC=y CONFIG_NAMESPACES=y CONFIG_USER_NS=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_SCHED_AUTOGROUP=y CONFIG_EXPERT=y # CONFIG_SYSFS_SYSCALL is not set -CONFIG_BPF_LSM=y -CONFIG_BPF_SYSCALL=y CONFIG_USERFAULTFD=y # CONFIG_COMPAT_BRK is not set CONFIG_PROFILING=y @@ -70,6 +74,7 @@ CONFIG_BLK_DEV_THROTTLING=y CONFIG_BLK_WBT=y CONFIG_BLK_CGROUP_IOLATENCY=y CONFIG_BLK_CGROUP_IOCOST=y +CONFIG_BLK_CGROUP_IOPRIO=y CONFIG_BLK_INLINE_ENCRYPTION=y CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y CONFIG_PARTITION_ADVANCED=y @@ -87,6 +92,7 @@ CONFIG_KSM=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_CLEANCACHE=y CONFIG_FRONTSWAP=y +CONFIG_CMA_SYSFS=y CONFIG_CMA_AREAS=7 CONFIG_MEM_SOFT_DIRTY=y CONFIG_ZSWAP=y @@ -149,6 +155,7 @@ CONFIG_IPV6_RPL_LWTUNNEL=y CONFIG_MPTCP=y CONFIG_NETFILTER=y CONFIG_BRIDGE_NETFILTER=m +CONFIG_NETFILTER_NETLINK_HOOK=m CONFIG_NF_CONNTRACK=m CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_EVENTS=y @@ -271,6 +278,7 @@ CONFIG_IP_VS_FTP=m CONFIG_IP_VS_PE_SIP=m CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y +CONFIG_NF_LOG_IPV4=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m @@ -374,11 +382,10 @@ CONFIG_VSOCKETS=m CONFIG_VIRTIO_VSOCKETS=m CONFIG_NETLINK_DIAG=m CONFIG_CGROUP_NET_PRIO=y -CONFIG_BPF_JIT=y CONFIG_NET_PKTGEN=m CONFIG_PCI=y -CONFIG_PCI_IOV=y # CONFIG_PCIEASPM is not set +CONFIG_PCI_IOV=y CONFIG_HOTPLUG_PCI=y CONFIG_HOTPLUG_PCI_S390=y CONFIG_UEVENT_HELPER=y @@ -427,7 +434,7 @@ CONFIG_MD_MULTIPATH=m CONFIG_MD_FAULTY=m CONFIG_MD_CLUSTER=m CONFIG_BCACHE=m -CONFIG_BLK_DEV_DM=m +CONFIG_BLK_DEV_DM=y CONFIG_DM_UNSTRIPED=m CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m @@ -444,6 +451,7 @@ CONFIG_DM_MULTIPATH_ST=m CONFIG_DM_MULTIPATH_HST=m CONFIG_DM_MULTIPATH_IOA=m CONFIG_DM_DELAY=m +CONFIG_DM_INIT=y CONFIG_DM_UEVENT=y CONFIG_DM_FLAKEY=m CONFIG_DM_VERITY=m @@ -487,6 +495,7 @@ CONFIG_NLMON=m # CONFIG_NET_VENDOR_GOOGLE is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set # CONFIG_NET_VENDOR_MARVELL is not set CONFIG_MLX4_EN=m CONFIG_MLX5_CORE=m @@ -543,7 +552,6 @@ CONFIG_INPUT_EVDEV=y CONFIG_LEGACY_PTY_COUNT=0 CONFIG_VIRTIO_CONSOLE=m CONFIG_HW_RANDOM_VIRTIO=m -CONFIG_RAW_DRIVER=m CONFIG_HANGCHECK_TIMER=m CONFIG_TN3270_FS=y # CONFIG_PTP_1588_CLOCK is not set @@ -566,7 +574,6 @@ CONFIG_SYNC_FILE=y CONFIG_VFIO=m CONFIG_VFIO_PCI=m CONFIG_VFIO_MDEV=m -CONFIG_VFIO_MDEV_DEVICE=m CONFIG_VIRTIO_PCI=m CONFIG_VIRTIO_BALLOON=m CONFIG_VIRTIO_INPUT=y @@ -607,6 +614,7 @@ CONFIG_FUSE_FS=y CONFIG_CUSE=m CONFIG_VIRTIO_FS=m CONFIG_OVERLAY_FS=m +CONFIG_NETFS_STATS=y CONFIG_FSCACHE=m CONFIG_CACHEFILES=m CONFIG_ISO9660_FS=y @@ -642,7 +650,6 @@ CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_NFSD_V4_SECURITY_LABEL=y CONFIG_CIFS=m -CONFIG_CIFS_STATS2=y CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_UPCALL=y CONFIG_CIFS_XATTR=y @@ -669,6 +676,7 @@ CONFIG_SECURITY_SELINUX_BOOTPARAM=y CONFIG_SECURITY_SELINUX_DISABLE=y CONFIG_SECURITY_LOCKDOWN_LSM=y CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y +CONFIG_SECURITY_LANDLOCK=y CONFIG_INTEGRITY_SIGNATURE=y CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y CONFIG_IMA=y @@ -684,6 +692,7 @@ CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_DH=m CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECDSA=m CONFIG_CRYPTO_ECRDSA=m CONFIG_CRYPTO_SM2=m CONFIG_CRYPTO_CURVE25519=m @@ -754,6 +763,7 @@ CONFIG_CRC8=m CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=0 CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y CONFIG_DEBUG_INFO=y CONFIG_DEBUG_INFO_DWARF4=y CONFIG_GDB_SCRIPTS=y @@ -781,3 +791,4 @@ CONFIG_LKDTM=m CONFIG_PERCPU_TEST=m CONFIG_ATOMIC64_SELFTEST=y CONFIG_TEST_BPF=m +CONFIG_TEST_LIVEPATCH=m diff --git a/arch/s390/configs/zfcpdump_defconfig b/arch/s390/configs/zfcpdump_defconfig index 76123a4b26ab..d576aaab27c9 100644 --- a/arch/s390/configs/zfcpdump_defconfig +++ b/arch/s390/configs/zfcpdump_defconfig @@ -29,9 +29,9 @@ CONFIG_PARTITION_ADVANCED=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_COMPACTION is not set # CONFIG_MIGRATION is not set -# CONFIG_BOUNCE is not set CONFIG_NET=y # CONFIG_IUCV is not set +# CONFIG_PCPU_DEV_REFCNT is not set # CONFIG_ETHTOOL_NETLINK is not set CONFIG_DEVTMPFS=y CONFIG_BLK_DEV_RAM=y @@ -51,7 +51,6 @@ CONFIG_ZFCP=y # CONFIG_SERIO is not set # CONFIG_HVC_IUCV is not set # CONFIG_HW_RANDOM_S390 is not set -CONFIG_RAW_DRIVER=y # CONFIG_HMC_DRV is not set # CONFIG_S390_TAPE is not set # CONFIG_VMCP is not set diff --git a/arch/s390/include/asm/ap.h b/arch/s390/include/asm/ap.h index 837d1699b109..3afbee21dc1f 100644 --- a/arch/s390/include/asm/ap.h +++ b/arch/s390/include/asm/ap.h @@ -53,18 +53,20 @@ struct ap_queue_status { */ static inline bool ap_instructions_available(void) { - register unsigned long reg0 asm ("0") = AP_MKQID(0, 0); - register unsigned long reg1 asm ("1") = 0; - register unsigned long reg2 asm ("2") = 0; + unsigned long reg0 = AP_MKQID(0, 0); + unsigned long reg1 = 0; asm volatile( - " .long 0xb2af0000\n" /* PQAP(TAPQ) */ - "0: la %0,1\n" + " lgr 0,%[reg0]\n" /* qid into gr0 */ + " lghi 1,0\n" /* 0 into gr1 */ + " lghi 2,0\n" /* 0 into gr2 */ + " .long 0xb2af0000\n" /* PQAP(TAPQ) */ + "0: la %[reg1],1\n" /* 1 into reg1 */ "1:\n" EX_TABLE(0b, 1b) - : "+d" (reg1), "+d" (reg2) - : "d" (reg0) - : "cc"); + : [reg1] "+&d" (reg1) + : [reg0] "d" (reg0) + : "cc", "0", "1", "2"); return reg1 != 0; } @@ -77,14 +79,18 @@ static inline bool ap_instructions_available(void) */ static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info) { - register unsigned long reg0 asm ("0") = qid; - register struct ap_queue_status reg1 asm ("1"); - register unsigned long reg2 asm ("2"); - - asm volatile(".long 0xb2af0000" /* PQAP(TAPQ) */ - : "=d" (reg1), "=d" (reg2) - : "d" (reg0) - : "cc"); + struct ap_queue_status reg1; + unsigned long reg2; + + asm volatile( + " lgr 0,%[qid]\n" /* qid into gr0 */ + " lghi 2,0\n" /* 0 into gr2 */ + " .long 0xb2af0000\n" /* PQAP(TAPQ) */ + " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ + " lgr %[reg2],2\n" /* gr2 into reg2 */ + : [reg1] "=&d" (reg1), [reg2] "=&d" (reg2) + : [qid] "d" (qid) + : "cc", "0", "1", "2"); if (info) *info = reg2; return reg1; @@ -115,14 +121,16 @@ static inline struct ap_queue_status ap_test_queue(ap_qid_t qid, */ static inline struct ap_queue_status ap_rapq(ap_qid_t qid) { - register unsigned long reg0 asm ("0") = qid | (1UL << 24); - register struct ap_queue_status reg1 asm ("1"); + unsigned long reg0 = qid | (1UL << 24); /* fc 1UL is RAPQ */ + struct ap_queue_status reg1; asm volatile( - ".long 0xb2af0000" /* PQAP(RAPQ) */ - : "=d" (reg1) - : "d" (reg0) - : "cc"); + " lgr 0,%[reg0]\n" /* qid arg into gr0 */ + " .long 0xb2af0000\n" /* PQAP(RAPQ) */ + " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ + : [reg1] "=&d" (reg1) + : [reg0] "d" (reg0) + : "cc", "0", "1"); return reg1; } @@ -134,14 +142,16 @@ static inline struct ap_queue_status ap_rapq(ap_qid_t qid) */ static inline struct ap_queue_status ap_zapq(ap_qid_t qid) { - register unsigned long reg0 asm ("0") = qid | (2UL << 24); - register struct ap_queue_status reg1 asm ("1"); + unsigned long reg0 = qid | (2UL << 24); /* fc 2UL is ZAPQ */ + struct ap_queue_status reg1; asm volatile( - ".long 0xb2af0000" /* PQAP(ZAPQ) */ - : "=d" (reg1) - : "d" (reg0) - : "cc"); + " lgr 0,%[reg0]\n" /* qid arg into gr0 */ + " .long 0xb2af0000\n" /* PQAP(ZAPQ) */ + " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ + : [reg1] "=&d" (reg1) + : [reg0] "d" (reg0) + : "cc", "0", "1"); return reg1; } @@ -172,18 +182,20 @@ struct ap_config_info { */ static inline int ap_qci(struct ap_config_info *config) { - register unsigned long reg0 asm ("0") = 4UL << 24; - register unsigned long reg1 asm ("1") = -EOPNOTSUPP; - register struct ap_config_info *reg2 asm ("2") = config; + unsigned long reg0 = 4UL << 24; /* fc 4UL is QCI */ + unsigned long reg1 = -EOPNOTSUPP; + struct ap_config_info *reg2 = config; asm volatile( - ".long 0xb2af0000\n" /* PQAP(QCI) */ - "0: la %0,0\n" + " lgr 0,%[reg0]\n" /* QCI fc into gr0 */ + " lgr 2,%[reg2]\n" /* ptr to config into gr2 */ + " .long 0xb2af0000\n" /* PQAP(QCI) */ + "0: la %[reg1],0\n" /* good case, QCI fc available */ "1:\n" EX_TABLE(0b, 1b) - : "+d" (reg1) - : "d" (reg0), "d" (reg2) - : "cc", "memory"); + : [reg1] "+&d" (reg1) + : [reg0] "d" (reg0), [reg2] "d" (reg2) + : "cc", "memory", "0", "2"); return reg1; } @@ -220,21 +232,25 @@ static inline struct ap_queue_status ap_aqic(ap_qid_t qid, struct ap_qirq_ctrl qirqctrl, void *ind) { - register unsigned long reg0 asm ("0") = qid | (3UL << 24); - register union { + unsigned long reg0 = qid | (3UL << 24); /* fc 3UL is AQIC */ + union { unsigned long value; struct ap_qirq_ctrl qirqctrl; struct ap_queue_status status; - } reg1 asm ("1"); - register void *reg2 asm ("2") = ind; + } reg1; + void *reg2 = ind; reg1.qirqctrl = qirqctrl; asm volatile( - ".long 0xb2af0000" /* PQAP(AQIC) */ - : "+d" (reg1) - : "d" (reg0), "d" (reg2) - : "cc"); + " lgr 0,%[reg0]\n" /* qid param into gr0 */ + " lgr 1,%[reg1]\n" /* irq ctrl into gr1 */ + " lgr 2,%[reg2]\n" /* ni addr into gr2 */ + " .long 0xb2af0000\n" /* PQAP(AQIC) */ + " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ + : [reg1] "+&d" (reg1) + : [reg0] "d" (reg0), [reg2] "d" (reg2) + : "cc", "0", "1", "2"); return reg1.status; } @@ -268,21 +284,24 @@ union ap_qact_ap_info { static inline struct ap_queue_status ap_qact(ap_qid_t qid, int ifbit, union ap_qact_ap_info *apinfo) { - register unsigned long reg0 asm ("0") = qid | (5UL << 24) - | ((ifbit & 0x01) << 22); - register union { + unsigned long reg0 = qid | (5UL << 24) | ((ifbit & 0x01) << 22); + union { unsigned long value; struct ap_queue_status status; - } reg1 asm ("1"); - register unsigned long reg2 asm ("2"); + } reg1; + unsigned long reg2; reg1.value = apinfo->val; asm volatile( - ".long 0xb2af0000" /* PQAP(QACT) */ - : "+d" (reg1), "=d" (reg2) - : "d" (reg0) - : "cc"); + " lgr 0,%[reg0]\n" /* qid param into gr0 */ + " lgr 1,%[reg1]\n" /* qact in info into gr1 */ + " .long 0xb2af0000\n" /* PQAP(QACT) */ + " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ + " lgr %[reg2],2\n" /* qact out info into reg2 */ + : [reg1] "+&d" (reg1), [reg2] "=&d" (reg2) + : [reg0] "d" (reg0) + : "cc", "0", "1", "2"); apinfo->val = reg2; return reg1.status; } @@ -303,19 +322,24 @@ static inline struct ap_queue_status ap_nqap(ap_qid_t qid, unsigned long long psmid, void *msg, size_t length) { - register unsigned long reg0 asm ("0") = qid | 0x40000000UL; - register struct ap_queue_status reg1 asm ("1"); - register unsigned long reg2 asm ("2") = (unsigned long) msg; - register unsigned long reg3 asm ("3") = (unsigned long) length; - register unsigned long reg4 asm ("4") = (unsigned int) (psmid >> 32); - register unsigned long reg5 asm ("5") = psmid & 0xffffffff; + unsigned long reg0 = qid | 0x40000000UL; /* 0x4... is last msg part */ + union register_pair nqap_r1, nqap_r2; + struct ap_queue_status reg1; + + nqap_r1.even = (unsigned int)(psmid >> 32); + nqap_r1.odd = psmid & 0xffffffff; + nqap_r2.even = (unsigned long)msg; + nqap_r2.odd = (unsigned long)length; asm volatile ( - "0: .long 0xb2ad0042\n" /* NQAP */ - " brc 2,0b" - : "+d" (reg0), "=d" (reg1), "+d" (reg2), "+d" (reg3) - : "d" (reg4), "d" (reg5) - : "cc", "memory"); + " lgr 0,%[reg0]\n" /* qid param in gr0 */ + "0: .insn rre,0xb2ad0000,%[nqap_r1],%[nqap_r2]\n" + " brc 2,0b\n" /* handle partial completion */ + " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ + : [reg0] "+&d" (reg0), [reg1] "=&d" (reg1), + [nqap_r2] "+&d" (nqap_r2.pair) + : [nqap_r1] "d" (nqap_r1.pair) + : "cc", "memory", "0", "1"); return reg1; } @@ -325,6 +349,8 @@ static inline struct ap_queue_status ap_nqap(ap_qid_t qid, * @psmid: Pointer to program supplied message identifier * @msg: The message text * @length: The message length + * @reslength: Resitual length on return + * @resgr0: input: gr0 value (only used if != 0), output: resitual gr0 content * * Returns AP queue status structure. * Condition code 1 on DQAP means the receive has taken place @@ -336,27 +362,65 @@ static inline struct ap_queue_status ap_nqap(ap_qid_t qid, * Note that gpr2 is used by the DQAP instruction to keep track of * any 'residual' length, in case the instruction gets interrupted. * Hence it gets zeroed before the instruction. + * If the message does not fit into the buffer, this function will + * return with a truncated message and the reply in the firmware queue + * is not removed. This is indicated to the caller with an + * ap_queue_status response_code value of all bits on (0xFF) and (if + * the reslength ptr is given) the remaining length is stored in + * *reslength and (if the resgr0 ptr is given) the updated gr0 value + * for further processing of this msg entry is stored in *resgr0. The + * caller needs to detect this situation and should invoke ap_dqap + * with a valid resgr0 ptr and a value in there != 0 to indicate that + * *resgr0 is to be used instead of qid to further process this entry. */ static inline struct ap_queue_status ap_dqap(ap_qid_t qid, unsigned long long *psmid, - void *msg, size_t length) + void *msg, size_t length, + size_t *reslength, + unsigned long *resgr0) { - register unsigned long reg0 asm("0") = qid | 0x80000000UL; - register struct ap_queue_status reg1 asm ("1"); - register unsigned long reg2 asm("2") = 0UL; - register unsigned long reg4 asm("4") = (unsigned long) msg; - register unsigned long reg5 asm("5") = (unsigned long) length; - register unsigned long reg6 asm("6") = 0UL; - register unsigned long reg7 asm("7") = 0UL; + unsigned long reg0 = resgr0 && *resgr0 ? *resgr0 : qid | 0x80000000UL; + struct ap_queue_status reg1; + unsigned long reg2; + union register_pair rp1, rp2; + rp1.even = 0UL; + rp1.odd = 0UL; + rp2.even = (unsigned long)msg; + rp2.odd = (unsigned long)length; asm volatile( - "0: .long 0xb2ae0064\n" /* DQAP */ - " brc 6,0b\n" - : "+d" (reg0), "=d" (reg1), "+d" (reg2), - "+d" (reg4), "+d" (reg5), "+d" (reg6), "+d" (reg7) - : : "cc", "memory"); - *psmid = (((unsigned long long) reg6) << 32) + reg7; + " lgr 0,%[reg0]\n" /* qid param into gr0 */ + " lghi 2,0\n" /* 0 into gr2 (res length) */ + "0: ltgr %N[rp2],%N[rp2]\n" /* check buf len */ + " jz 2f\n" /* go out if buf len is 0 */ + "1: .insn rre,0xb2ae0000,%[rp1],%[rp2]\n" + " brc 6,0b\n" /* handle partial complete */ + "2: lgr %[reg0],0\n" /* gr0 (qid + info) into reg0 */ + " lgr %[reg1],1\n" /* gr1 (status) into reg1 */ + " lgr %[reg2],2\n" /* gr2 (res length) into reg2 */ + : [reg0] "+&d" (reg0), [reg1] "=&d" (reg1), [reg2] "=&d" (reg2), + [rp1] "+&d" (rp1.pair), [rp2] "+&d" (rp2.pair) + : + : "cc", "memory", "0", "1", "2"); + + if (reslength) + *reslength = reg2; + if (reg2 != 0 && rp2.odd == 0) { + /* + * Partially complete, status in gr1 is not set. + * Signal the caller that this dqap is only partially received + * with a special status response code 0xFF and *resgr0 updated + */ + reg1.response_code = 0xFF; + if (resgr0) + *resgr0 = reg0; + } else { + *psmid = (((unsigned long long)rp1.even) << 32) + rp1.odd; + if (resgr0) + *resgr0 = 0; + } + return reg1; } diff --git a/arch/s390/include/asm/cpu_mcf.h b/arch/s390/include/asm/cpu_mcf.h index 4dcefddb7751..ca0e0e5ddbc4 100644 --- a/arch/s390/include/asm/cpu_mcf.h +++ b/arch/s390/include/asm/cpu_mcf.h @@ -32,39 +32,22 @@ static const u64 cpumf_ctr_ctl[CPUMF_CTR_SET_MAX] = { [CPUMF_CTR_SET_MT_DIAG] = 0x20, }; -static inline void ctr_set_enable(u64 *state, int ctr_set) -{ - *state |= cpumf_ctr_ctl[ctr_set] << CPUMF_LCCTL_ENABLE_SHIFT; -} -static inline void ctr_set_disable(u64 *state, int ctr_set) -{ - *state &= ~(cpumf_ctr_ctl[ctr_set] << CPUMF_LCCTL_ENABLE_SHIFT); -} -static inline void ctr_set_start(u64 *state, int ctr_set) -{ - *state |= cpumf_ctr_ctl[ctr_set] << CPUMF_LCCTL_ACTCTL_SHIFT; -} -static inline void ctr_set_stop(u64 *state, int ctr_set) -{ - *state &= ~(cpumf_ctr_ctl[ctr_set] << CPUMF_LCCTL_ACTCTL_SHIFT); -} - -static inline void ctr_set_multiple_enable(u64 *state, u64 ctrsets) +static inline void ctr_set_enable(u64 *state, u64 ctrsets) { *state |= ctrsets << CPUMF_LCCTL_ENABLE_SHIFT; } -static inline void ctr_set_multiple_disable(u64 *state, u64 ctrsets) +static inline void ctr_set_disable(u64 *state, u64 ctrsets) { *state &= ~(ctrsets << CPUMF_LCCTL_ENABLE_SHIFT); } -static inline void ctr_set_multiple_start(u64 *state, u64 ctrsets) +static inline void ctr_set_start(u64 *state, u64 ctrsets) { *state |= ctrsets << CPUMF_LCCTL_ACTCTL_SHIFT; } -static inline void ctr_set_multiple_stop(u64 *state, u64 ctrsets) +static inline void ctr_set_stop(u64 *state, u64 ctrsets) { *state &= ~(ctrsets << CPUMF_LCCTL_ACTCTL_SHIFT); } @@ -92,8 +75,15 @@ struct cpu_cf_events { struct cpumf_ctr_info info; atomic_t ctr_set[CPUMF_CTR_SET_MAX]; atomic64_t alert; - u64 state; + u64 state; /* For perf_event_open SVC */ + u64 dev_state; /* For /dev/hwctr */ unsigned int flags; + size_t used; /* Bytes used in data */ + size_t usedss; /* Bytes used in start/stop */ + unsigned char start[PAGE_SIZE]; /* Counter set at event add */ + unsigned char stop[PAGE_SIZE]; /* Counter set at event delete */ + unsigned char data[PAGE_SIZE]; /* Counter set at /dev/hwctr */ + unsigned int sets; /* # Counter set saved in memory */ }; DECLARE_PER_CPU(struct cpu_cf_events, cpu_cf_events); @@ -124,4 +114,6 @@ static inline int stccm_avail(void) size_t cpum_cf_ctrset_size(enum cpumf_ctr_set ctrset, struct cpumf_ctr_info *info); +int cfset_online_cpu(unsigned int cpu); +int cfset_offline_cpu(unsigned int cpu); #endif /* _ASM_S390_CPU_MCF_H */ diff --git a/arch/s390/include/asm/ctl_reg.h b/arch/s390/include/asm/ctl_reg.h index ed5efbb531c4..adc0179fa34e 100644 --- a/arch/s390/include/asm/ctl_reg.h +++ b/arch/s390/include/asm/ctl_reg.h @@ -21,8 +21,6 @@ #define CR0_INTERRUPT_KEY_SUBMASK BIT(63 - 57) #define CR0_MEASUREMENT_ALERT_SUBMASK BIT(63 - 58) -#define CR2_GUARDED_STORAGE BIT(63 - 59) - #define CR14_UNUSED_32 BIT(63 - 32) #define CR14_UNUSED_33 BIT(63 - 33) #define CR14_CHANNEL_REPORT_SUBMASK BIT(63 - 35) diff --git a/arch/s390/include/asm/elf.h b/arch/s390/include/asm/elf.h index 66d51ad090ab..bd00c94620d3 100644 --- a/arch/s390/include/asm/elf.h +++ b/arch/s390/include/asm/elf.h @@ -144,10 +144,6 @@ typedef s390_compat_regs compat_elf_gregset_t; #include <linux/sched/mm.h> /* for task_struct */ #include <asm/mmu_context.h> -#include <asm/vdso.h> - -extern unsigned int vdso_enabled; - /* * This is used to ensure we don't load something for the wrong architecture. */ @@ -176,7 +172,7 @@ struct arch_elf_state { !current->mm->context.alloc_pgste) { \ set_thread_flag(TIF_PGSTE); \ set_pt_regs_flag(task_pt_regs(current), \ - PIF_SYSCALL_RESTART); \ + PIF_EXECVE_PGSTE_RESTART); \ _state->rc = -EAGAIN; \ } \ _state->rc; \ @@ -268,11 +264,10 @@ do { \ #define STACK_RND_MASK MMAP_RND_MASK /* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */ -#define ARCH_DLINFO \ -do { \ - if (vdso_enabled) \ - NEW_AUX_ENT(AT_SYSINFO_EHDR, \ - (unsigned long)current->mm->context.vdso_base); \ +#define ARCH_DLINFO \ +do { \ + NEW_AUX_ENT(AT_SYSINFO_EHDR, \ + (unsigned long)current->mm->context.vdso_base); \ } while (0) struct linux_binprm; diff --git a/arch/s390/include/asm/entry-common.h b/arch/s390/include/asm/entry-common.h index baa8005090c3..17aead80aadb 100644 --- a/arch/s390/include/asm/entry-common.h +++ b/arch/s390/include/asm/entry-common.h @@ -14,7 +14,6 @@ #define ARCH_EXIT_TO_USER_MODE_WORK (_TIF_GUARDED_STORAGE | _TIF_PER_TRAP) void do_per_trap(struct pt_regs *regs); -void do_syscall(struct pt_regs *regs); #ifdef CONFIG_DEBUG_ENTRY static __always_inline void arch_check_user_regs(struct pt_regs *regs) diff --git a/arch/s390/include/asm/ftrace.h b/arch/s390/include/asm/ftrace.h index 695c61989f97..345cbe982a8b 100644 --- a/arch/s390/include/asm/ftrace.h +++ b/arch/s390/include/asm/ftrace.h @@ -19,6 +19,7 @@ void ftrace_caller(void); extern char ftrace_graph_caller_end; extern unsigned long ftrace_plt; +extern void *ftrace_func; struct dyn_arch_ftrace { }; diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h index 9b4473f76e56..161a9e12bfb8 100644 --- a/arch/s390/include/asm/kvm_host.h +++ b/arch/s390/include/asm/kvm_host.h @@ -445,15 +445,15 @@ struct kvm_vcpu_stat { u64 instruction_sigp_init_cpu_reset; u64 instruction_sigp_cpu_reset; u64 instruction_sigp_unknown; - u64 diagnose_10; - u64 diagnose_44; - u64 diagnose_9c; - u64 diagnose_9c_ignored; - u64 diagnose_9c_forward; - u64 diagnose_258; - u64 diagnose_308; - u64 diagnose_500; - u64 diagnose_other; + u64 instruction_diagnose_10; + u64 instruction_diagnose_44; + u64 instruction_diagnose_9c; + u64 diag_9c_ignored; + u64 diag_9c_forward; + u64 instruction_diagnose_258; + u64 instruction_diagnose_308; + u64 instruction_diagnose_500; + u64 instruction_diagnose_other; u64 pfault_sync; }; diff --git a/arch/s390/include/asm/linkage.h b/arch/s390/include/asm/linkage.h index a0a7a2c72bd4..24e8fed150cf 100644 --- a/arch/s390/include/asm/linkage.h +++ b/arch/s390/include/asm/linkage.h @@ -5,7 +5,7 @@ #include <asm/asm-const.h> #include <linux/stringify.h> -#define __ALIGN .align 4, 0x07 +#define __ALIGN .align 16, 0x07 #define __ALIGN_STR __stringify(__ALIGN) /* diff --git a/arch/s390/include/asm/nmi.h b/arch/s390/include/asm/nmi.h index 20e51c9ff240..2db45d7e68aa 100644 --- a/arch/s390/include/asm/nmi.h +++ b/arch/s390/include/asm/nmi.h @@ -23,12 +23,16 @@ #define MCCK_CODE_SYSTEM_DAMAGE BIT(63) #define MCCK_CODE_EXT_DAMAGE BIT(63 - 5) #define MCCK_CODE_CP BIT(63 - 9) -#define MCCK_CODE_CPU_TIMER_VALID BIT(63 - 46) +#define MCCK_CODE_STG_ERROR BIT(63 - 16) +#define MCCK_CODE_STG_KEY_ERROR BIT(63 - 18) +#define MCCK_CODE_STG_DEGRAD BIT(63 - 19) #define MCCK_CODE_PSW_MWP_VALID BIT(63 - 20) #define MCCK_CODE_PSW_IA_VALID BIT(63 - 23) +#define MCCK_CODE_STG_FAIL_ADDR BIT(63 - 24) #define MCCK_CODE_CR_VALID BIT(63 - 29) #define MCCK_CODE_GS_VALID BIT(63 - 36) #define MCCK_CODE_FC_VALID BIT(63 - 43) +#define MCCK_CODE_CPU_TIMER_VALID BIT(63 - 46) #ifndef __ASSEMBLY__ diff --git a/arch/s390/include/asm/preempt.h b/arch/s390/include/asm/preempt.h index 23ff51be7e29..d9d5350cc3ec 100644 --- a/arch/s390/include/asm/preempt.h +++ b/arch/s390/include/asm/preempt.h @@ -29,12 +29,6 @@ static inline void preempt_count_set(int pc) old, new) != old); } -#define init_task_preempt_count(p) do { } while (0) - -#define init_idle_preempt_count(p, cpu) do { \ - S390_lowcore.preempt_count = PREEMPT_DISABLED; \ -} while (0) - static inline void set_preempt_need_resched(void) { __atomic_and(~PREEMPT_NEED_RESCHED, &S390_lowcore.preempt_count); @@ -88,12 +82,6 @@ static inline void preempt_count_set(int pc) S390_lowcore.preempt_count = pc; } -#define init_task_preempt_count(p) do { } while (0) - -#define init_idle_preempt_count(p, cpu) do { \ - S390_lowcore.preempt_count = PREEMPT_DISABLED; \ -} while (0) - static inline void set_preempt_need_resched(void) { } @@ -130,6 +118,10 @@ static inline bool should_resched(int preempt_offset) #endif /* CONFIG_HAVE_MARCH_Z196_FEATURES */ +#define init_task_preempt_count(p) do { } while (0) +/* Deferred to CPU bringup time */ +#define init_idle_preempt_count(p, cpu) do { } while (0) + #ifdef CONFIG_PREEMPTION extern void preempt_schedule(void); #define __preempt_schedule() preempt_schedule() diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h index c7850d649373..61b22aa990e7 100644 --- a/arch/s390/include/asm/ptrace.h +++ b/arch/s390/include/asm/ptrace.h @@ -11,15 +11,15 @@ #include <uapi/asm/ptrace.h> #include <asm/tpi.h> -#define PIF_SYSCALL 0 /* inside a system call */ -#define PIF_SYSCALL_RESTART 1 /* restart the current system call */ -#define PIF_SYSCALL_RET_SET 2 /* return value was set via ptrace */ -#define PIF_GUEST_FAULT 3 /* indicates program check in sie64a */ +#define PIF_SYSCALL 0 /* inside a system call */ +#define PIF_EXECVE_PGSTE_RESTART 1 /* restart execve for PGSTE binaries */ +#define PIF_SYSCALL_RET_SET 2 /* return value was set via ptrace */ +#define PIF_GUEST_FAULT 3 /* indicates program check in sie64a */ -#define _PIF_SYSCALL BIT(PIF_SYSCALL) -#define _PIF_SYSCALL_RESTART BIT(PIF_SYSCALL_RESTART) -#define _PIF_SYSCALL_RET_SET BIT(PIF_SYSCALL_RET_SET) -#define _PIF_GUEST_FAULT BIT(PIF_GUEST_FAULT) +#define _PIF_SYSCALL BIT(PIF_SYSCALL) +#define _PIF_EXECVE_PGSTE_RESTART BIT(PIF_EXECVE_PGSTE_RESTART) +#define _PIF_SYSCALL_RET_SET BIT(PIF_SYSCALL_RET_SET) +#define _PIF_GUEST_FAULT BIT(PIF_GUEST_FAULT) #ifndef __ASSEMBLY__ @@ -162,6 +162,14 @@ static inline int test_pt_regs_flag(struct pt_regs *regs, int flag) return !!(regs->flags & (1UL << flag)); } +static inline int test_and_clear_pt_regs_flag(struct pt_regs *regs, int flag) +{ + int ret = test_pt_regs_flag(regs, flag); + + clear_pt_regs_flag(regs, flag); + return ret; +} + /* * These are defined as per linux/ptrace.h, which see. */ diff --git a/arch/s390/include/asm/setup.h b/arch/s390/include/asm/setup.h index a8b75da3c1b8..3a77aa96d092 100644 --- a/arch/s390/include/asm/setup.h +++ b/arch/s390/include/asm/setup.h @@ -159,6 +159,8 @@ static inline unsigned long kaslr_offset(void) return __kaslr_offset; } +extern int is_full_image; + static inline u32 gen_lpswe(unsigned long addr) { BUILD_BUG_ON(addr > 0xfff); diff --git a/arch/s390/include/asm/softirq_stack.h b/arch/s390/include/asm/softirq_stack.h new file mode 100644 index 000000000000..fd17f25704bd --- /dev/null +++ b/arch/s390/include/asm/softirq_stack.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __ASM_S390_SOFTIRQ_STACK_H +#define __ASM_S390_SOFTIRQ_STACK_H + +#include <asm/lowcore.h> +#include <asm/stacktrace.h> + +static inline void do_softirq_own_stack(void) +{ + call_on_stack(0, S390_lowcore.async_stack, void, __do_softirq); +} + +#endif /* __ASM_S390_SOFTIRQ_STACK_H */ diff --git a/arch/s390/include/asm/stacktrace.h b/arch/s390/include/asm/stacktrace.h index 76c6034428be..3d8a4b94c620 100644 --- a/arch/s390/include/asm/stacktrace.h +++ b/arch/s390/include/asm/stacktrace.h @@ -74,23 +74,6 @@ struct stack_frame { ((unsigned long)__builtin_frame_address(0) - \ offsetof(struct stack_frame, back_chain)) -#define CALL_ARGS_0() \ - register unsigned long r2 asm("2") -#define CALL_ARGS_1(arg1) \ - register unsigned long r2 asm("2") = (unsigned long)(arg1) -#define CALL_ARGS_2(arg1, arg2) \ - CALL_ARGS_1(arg1); \ - register unsigned long r3 asm("3") = (unsigned long)(arg2) -#define CALL_ARGS_3(arg1, arg2, arg3) \ - CALL_ARGS_2(arg1, arg2); \ - register unsigned long r4 asm("4") = (unsigned long)(arg3) -#define CALL_ARGS_4(arg1, arg2, arg3, arg4) \ - CALL_ARGS_3(arg1, arg2, arg3); \ - register unsigned long r4 asm("5") = (unsigned long)(arg4) -#define CALL_ARGS_5(arg1, arg2, arg3, arg4, arg5) \ - CALL_ARGS_4(arg1, arg2, arg3, arg4); \ - register unsigned long r4 asm("6") = (unsigned long)(arg5) - /* * To keep this simple mark register 2-6 as being changed (volatile) * by the called function, even though register 6 is saved/nonvolatile. @@ -109,34 +92,113 @@ struct stack_frame { #define CALL_CLOBBER_1 CALL_CLOBBER_2, "3" #define CALL_CLOBBER_0 CALL_CLOBBER_1 -#define CALL_ON_STACK(fn, stack, nr, args...) \ +#define CALL_LARGS_0(...) \ + long dummy = 0 +#define CALL_LARGS_1(t1, a1) \ + long arg1 = (long)(t1)(a1) +#define CALL_LARGS_2(t1, a1, t2, a2) \ + CALL_LARGS_1(t1, a1); \ + long arg2 = (long)(t2)(a2) +#define CALL_LARGS_3(t1, a1, t2, a2, t3, a3) \ + CALL_LARGS_2(t1, a1, t2, a2); \ + long arg3 = (long)(t3)(a3) +#define CALL_LARGS_4(t1, a1, t2, a2, t3, a3, t4, a4) \ + CALL_LARGS_3(t1, a1, t2, a2, t3, a3); \ + long arg4 = (long)(t4)(a4) +#define CALL_LARGS_5(t1, a1, t2, a2, t3, a3, t4, a4, t5, a5) \ + CALL_LARGS_4(t1, a1, t2, a2, t3, a3, t4, a4); \ + long arg5 = (long)(t5)(a5) + +#define CALL_REGS_0 \ + register long r2 asm("2") = dummy +#define CALL_REGS_1 \ + register long r2 asm("2") = arg1 +#define CALL_REGS_2 \ + CALL_REGS_1; \ + register long r3 asm("3") = arg2 +#define CALL_REGS_3 \ + CALL_REGS_2; \ + register long r4 asm("4") = arg3 +#define CALL_REGS_4 \ + CALL_REGS_3; \ + register long r5 asm("5") = arg4 +#define CALL_REGS_5 \ + CALL_REGS_4; \ + register long r6 asm("6") = arg5 + +#define CALL_TYPECHECK_0(...) +#define CALL_TYPECHECK_1(t, a, ...) \ + typecheck(t, a) +#define CALL_TYPECHECK_2(t, a, ...) \ + CALL_TYPECHECK_1(__VA_ARGS__); \ + typecheck(t, a) +#define CALL_TYPECHECK_3(t, a, ...) \ + CALL_TYPECHECK_2(__VA_ARGS__); \ + typecheck(t, a) +#define CALL_TYPECHECK_4(t, a, ...) \ + CALL_TYPECHECK_3(__VA_ARGS__); \ + typecheck(t, a) +#define CALL_TYPECHECK_5(t, a, ...) \ + CALL_TYPECHECK_4(__VA_ARGS__); \ + typecheck(t, a) + +#define CALL_PARM_0(...) void +#define CALL_PARM_1(t, a, ...) t +#define CALL_PARM_2(t, a, ...) t, CALL_PARM_1(__VA_ARGS__) +#define CALL_PARM_3(t, a, ...) t, CALL_PARM_2(__VA_ARGS__) +#define CALL_PARM_4(t, a, ...) t, CALL_PARM_3(__VA_ARGS__) +#define CALL_PARM_5(t, a, ...) t, CALL_PARM_4(__VA_ARGS__) +#define CALL_PARM_6(t, a, ...) t, CALL_PARM_5(__VA_ARGS__) + +/* + * Use call_on_stack() to call a function switching to a specified + * stack. Proper sign and zero extension of function arguments is + * done. Usage: + * + * rc = call_on_stack(nr, stack, rettype, fn, t1, a1, t2, a2, ...) + * + * - nr specifies the number of function arguments of fn. + * - stack specifies the stack to be used. + * - fn is the function to be called. + * - rettype is the return type of fn. + * - t1, a1, ... are pairs, where t1 must match the type of the first + * argument of fn, t2 the second, etc. a1 is the corresponding + * first function argument (not name), etc. + */ +#define call_on_stack(nr, stack, rettype, fn, ...) \ ({ \ + rettype (*__fn)(CALL_PARM_##nr(__VA_ARGS__)) = fn; \ unsigned long frame = current_frame_address(); \ - CALL_ARGS_##nr(args); \ + unsigned long __stack = stack; \ unsigned long prev; \ + CALL_LARGS_##nr(__VA_ARGS__); \ + CALL_REGS_##nr; \ \ + CALL_TYPECHECK_##nr(__VA_ARGS__); \ asm volatile( \ - " la %[_prev],0(15)\n" \ + " lgr %[_prev],15\n" \ " lg 15,%[_stack]\n" \ " stg %[_frame],%[_bc](15)\n" \ " brasl 14,%[_fn]\n" \ - " la 15,0(%[_prev])\n" \ - : [_prev] "=&a" (prev), CALL_FMT_##nr \ - : [_stack] "R" (stack), \ + " lgr 15,%[_prev]\n" \ + : [_prev] "=&d" (prev), CALL_FMT_##nr \ + : [_stack] "R" (__stack), \ [_bc] "i" (offsetof(struct stack_frame, back_chain)), \ [_frame] "d" (frame), \ - [_fn] "X" (fn) : CALL_CLOBBER_##nr); \ - r2; \ + [_fn] "X" (__fn) : CALL_CLOBBER_##nr); \ + (rettype)r2; \ }) -#define CALL_ON_STACK_NORETURN(fn, stack) \ +#define call_on_stack_noreturn(fn, stack) \ ({ \ + void (*__fn)(void) = fn; \ + \ asm volatile( \ " la 15,0(%[_stack])\n" \ " xc %[_bc](8,15),%[_bc](15)\n" \ " brasl 14,%[_fn]\n" \ ::[_bc] "i" (offsetof(struct stack_frame, back_chain)), \ - [_stack] "a" (stack), [_fn] "X" (fn)); \ + [_stack] "a" (stack), [_fn] "X" (__fn)); \ BUG(); \ }) diff --git a/arch/s390/include/asm/uv.h b/arch/s390/include/asm/uv.h index 7b98d4caee77..12c5f006c136 100644 --- a/arch/s390/include/asm/uv.h +++ b/arch/s390/include/asm/uv.h @@ -73,6 +73,10 @@ enum uv_cmds_inst { BIT_UVC_CMD_UNPIN_PAGE_SHARED = 22, }; +enum uv_feat_ind { + BIT_UV_FEAT_MISC = 0, +}; + struct uv_cb_header { u16 len; u16 cmd; /* Command Code */ @@ -97,7 +101,8 @@ struct uv_cb_qui { u64 max_guest_stor_addr; u8 reserved88[158 - 136]; u16 max_guest_cpu_id; - u8 reserveda0[200 - 160]; + u64 uv_feature_indications; + u8 reserveda0[200 - 168]; } __packed __aligned(8); /* Initialize Ultravisor */ @@ -274,6 +279,7 @@ struct uv_info { unsigned long max_sec_stor_addr; unsigned int max_num_sec_conf; unsigned short max_guest_cpu_id; + unsigned long uv_feature_indications; }; extern struct uv_info uv_info; diff --git a/arch/s390/include/asm/vdso.h b/arch/s390/include/asm/vdso.h index b45e3dddd2c2..53165aa7813a 100644 --- a/arch/s390/include/asm/vdso.h +++ b/arch/s390/include/asm/vdso.h @@ -4,18 +4,31 @@ #include <vdso/datapage.h> -/* Default link address for the vDSO */ -#define VDSO64_LBASE 0 +#ifndef __ASSEMBLY__ -#define __VVAR_PAGES 2 +#include <generated/vdso64-offsets.h> +#ifdef CONFIG_COMPAT +#include <generated/vdso32-offsets.h> +#endif -#define VDSO_VERSION_STRING LINUX_2.6.29 - -#ifndef __ASSEMBLY__ +#define VDSO64_SYMBOL(tsk, name) ((tsk)->mm->context.vdso_base + (vdso64_offset_##name)) +#ifdef CONFIG_COMPAT +#define VDSO32_SYMBOL(tsk, name) ((tsk)->mm->context.vdso_base + (vdso32_offset_##name)) +#else +#define VDSO32_SYMBOL(tsk, name) (-1UL) +#endif extern struct vdso_data *vdso_data; int vdso_getcpu_init(void); #endif /* __ASSEMBLY__ */ + +/* Default link address for the vDSO */ +#define VDSO_LBASE 0 + +#define __VVAR_PAGES 2 + +#define VDSO_VERSION_STRING LINUX_2.6.29 + #endif /* __S390_VDSO_H__ */ diff --git a/arch/s390/include/asm/vdso/gettimeofday.h b/arch/s390/include/asm/vdso/gettimeofday.h index 383c53c3dddd..d6465b22ffe3 100644 --- a/arch/s390/include/asm/vdso/gettimeofday.h +++ b/arch/s390/include/asm/vdso/gettimeofday.h @@ -8,7 +8,6 @@ #include <asm/timex.h> #include <asm/unistd.h> -#include <asm/vdso.h> #include <linux/compiler.h> #define vdso_calc_delta __arch_vdso_calc_delta diff --git a/arch/s390/kernel/Makefile b/arch/s390/kernel/Makefile index 68ca1834316f..4a44ba5a2d73 100644 --- a/arch/s390/kernel/Makefile +++ b/arch/s390/kernel/Makefile @@ -71,10 +71,10 @@ obj-$(CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT) += ima_arch.o obj-$(CONFIG_PERF_EVENTS) += perf_event.o perf_cpum_cf_common.o obj-$(CONFIG_PERF_EVENTS) += perf_cpum_cf.o perf_cpum_sf.o obj-$(CONFIG_PERF_EVENTS) += perf_cpum_cf_events.o perf_regs.o -obj-$(CONFIG_PERF_EVENTS) += perf_cpum_cf_diag.o obj-$(CONFIG_TRACEPOINTS) += trace.o obj-$(findstring y, $(CONFIG_PROTECTED_VIRTUALIZATION_GUEST) $(CONFIG_PGSTE)) += uv.o # vdso obj-y += vdso64/ +obj-$(CONFIG_COMPAT) += vdso32/ diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c index f53605a3dfcd..77ff2130cb04 100644 --- a/arch/s390/kernel/asm-offsets.c +++ b/arch/s390/kernel/asm-offsets.c @@ -14,8 +14,6 @@ #include <linux/pgtable.h> #include <asm/idle.h> #include <asm/gmap.h> -#include <asm/nmi.h> -#include <asm/setup.h> #include <asm/stacktrace.h> int main(void) @@ -108,7 +106,6 @@ int main(void) OFFSET(__LC_LAST_UPDATE_CLOCK, lowcore, last_update_clock); OFFSET(__LC_INT_CLOCK, lowcore, int_clock); OFFSET(__LC_MCCK_CLOCK, lowcore, mcck_clock); - OFFSET(__LC_CLOCK_COMPARATOR, lowcore, clock_comparator); OFFSET(__LC_BOOT_CLOCK, lowcore, boot_clock); OFFSET(__LC_CURRENT, lowcore, current_task); OFFSET(__LC_KERNEL_STACK, lowcore, kernel_stack); @@ -145,9 +142,6 @@ int main(void) OFFSET(__LC_CREGS_SAVE_AREA, lowcore, cregs_save_area); OFFSET(__LC_PGM_TDB, lowcore, pgm_tdb); BLANK(); - /* extended machine check save area */ - OFFSET(__MCESA_GS_SAVE_AREA, mcesa, guarded_storage_save_area); - BLANK(); /* gmap/sie offsets */ OFFSET(__GMAP_ASCE, gmap, asce); OFFSET(__SIE_PROG0C, kvm_s390_sie_block, prog0c); diff --git a/arch/s390/kernel/compat_signal.c b/arch/s390/kernel/compat_signal.c index 1d0e17ec93eb..cca142fbb516 100644 --- a/arch/s390/kernel/compat_signal.c +++ b/arch/s390/kernel/compat_signal.c @@ -28,6 +28,7 @@ #include <linux/uaccess.h> #include <asm/lowcore.h> #include <asm/switch_to.h> +#include <asm/vdso.h> #include "compat_linux.h" #include "compat_ptrace.h" #include "entry.h" @@ -118,7 +119,6 @@ static int restore_sigregs32(struct pt_regs *regs,_sigregs32 __user *sregs) fpregs_load((_s390_fp_regs *) &user_sregs.fpregs, ¤t->thread.fpu); clear_pt_regs_flag(regs, PIF_SYSCALL); /* No longer in a system call */ - clear_pt_regs_flag(regs, PIF_SYSCALL_RESTART); return 0; } @@ -304,11 +304,7 @@ static int setup_frame32(struct ksignal *ksig, sigset_t *set, restorer = (unsigned long __force) ksig->ka.sa.sa_restorer | PSW32_ADDR_AMODE; } else { - /* Signal frames without vectors registers are short ! */ - __u16 __user *svc = (void __user *) frame + frame_size - 2; - if (__put_user(S390_SYSCALL_OPCODE | __NR_sigreturn, svc)) - return -EFAULT; - restorer = (unsigned long __force) svc | PSW32_ADDR_AMODE; + restorer = VDSO32_SYMBOL(current, sigreturn); } /* Set up registers for signal handler */ @@ -371,10 +367,7 @@ static int setup_rt_frame32(struct ksignal *ksig, sigset_t *set, restorer = (unsigned long __force) ksig->ka.sa.sa_restorer | PSW32_ADDR_AMODE; } else { - __u16 __user *svc = &frame->svc_insn; - if (__put_user(S390_SYSCALL_OPCODE | __NR_rt_sigreturn, svc)) - return -EFAULT; - restorer = (unsigned long __force) svc | PSW32_ADDR_AMODE; + restorer = VDSO32_SYMBOL(current, rt_sigreturn); } /* Create siginfo on the signal stack */ diff --git a/arch/s390/kernel/early.c b/arch/s390/kernel/early.c index c2cf79d353cf..fb84e3fc1686 100644 --- a/arch/s390/kernel/early.c +++ b/arch/s390/kernel/early.c @@ -33,6 +33,8 @@ #include <asm/switch_to.h> #include "entry.h" +int __bootdata(is_full_image); + static void __init reset_tod_clock(void) { union tod_clock clk; @@ -279,7 +281,7 @@ static void __init setup_boot_command_line(void) static void __init check_image_bootable(void) { - if (!memcmp(EP_STRING, (void *)EP_OFFSET, strlen(EP_STRING))) + if (is_full_image) return; sclp_early_printk("Linux kernel boot failure: An attempt to boot a vmlinux ELF image failed.\n"); diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S index 3e8c6669373a..5a2f70cbd3a9 100644 --- a/arch/s390/kernel/entry.S +++ b/arch/s390/kernel/entry.S @@ -14,7 +14,6 @@ #include <asm/alternative-asm.h> #include <asm/processor.h> #include <asm/cache.h> -#include <asm/ctl_reg.h> #include <asm/dwarf.h> #include <asm/errno.h> #include <asm/ptrace.h> @@ -129,6 +128,24 @@ _LPP_OFFSET = __LC_LPP "jnz .+8; .long 0xb2e8d000", 82 .endm + /* + * The CHKSTG macro jumps to the provided label in case the + * machine check interruption code reports one of unrecoverable + * storage errors: + * - Storage error uncorrected + * - Storage key error uncorrected + * - Storage degradation with Failing-storage-address validity + */ + .macro CHKSTG errlabel + TSTMSK __LC_MCCK_CODE,(MCCK_CODE_STG_ERROR|MCCK_CODE_STG_KEY_ERROR) + jnz \errlabel + TSTMSK __LC_MCCK_CODE,MCCK_CODE_STG_DEGRAD + jz oklabel\@ + TSTMSK __LC_MCCK_CODE,MCCK_CODE_STG_FAIL_ADDR + jnz \errlabel +oklabel\@: + .endm + #if IS_ENABLED(CONFIG_KVM) /* * The OUTSIDE macro jumps to the provided label in case the value @@ -148,6 +165,13 @@ _LPP_OFFSET = __LC_LPP clgr %r14,%r13 jhe \outside_label .endm + + .macro SIEEXIT + lg %r9,__SF_SIE_CONTROL(%r15) # get control block pointer + ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE + lctlg %c1,%c1,__LC_KERNEL_ASCE # load primary asce + larl %r9,sie_exit # skip forward to sie_exit + .endm #endif GEN_BR_THUNK %r14 @@ -235,7 +259,6 @@ ENTRY(sie64a) # are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable. # Other instructions between sie64a and .Lsie_done should not cause program # interrupts. So lets use 3 nops as a landing pad for all possible rewinds. -# See also .Lcleanup_sie .Lrewind_pad6: nopr 7 .Lrewind_pad4: @@ -341,10 +364,7 @@ ENTRY(pgm_check_handler) #if IS_ENABLED(CONFIG_KVM) # cleanup critical section for program checks in sie64a OUTSIDE %r9,.Lsie_gmap,.Lsie_done,1f - lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer - ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE - lctlg %c1,%c1,__LC_KERNEL_ASCE # load primary asce - larl %r9,sie_exit # skip forward to sie_exit + SIEEXIT lghi %r10,_PIF_GUEST_FAULT #endif 1: tmhh %r8,0x4000 # PER bit set in old PSW ? @@ -410,7 +430,8 @@ ENTRY(\name) jnz 1f #if IS_ENABLED(CONFIG_KVM) OUTSIDE %r9,.Lsie_gmap,.Lsie_done,0f - brasl %r14,.Lcleanup_sie + BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST) + SIEEXIT #endif 0: CHECK_STACK __LC_SAVE_AREA_ASYNC aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE) @@ -484,8 +505,6 @@ ENTRY(mcck_int_handler) BPOFF la %r1,4095 # validate r1 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # validate cpu timer - sckc __LC_CLOCK_COMPARATOR # validate comparator - lam %a0,%a15,__LC_AREGS_SAVE_AREA-4095(%r1) # validate acrs lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# validate gprs lg %r12,__LC_CURRENT lmg %r8,%r9,__LC_MCK_OLD_PSW @@ -496,41 +515,7 @@ ENTRY(mcck_int_handler) la %r14,4095 lctlg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r14) # validate ctl regs ptlb - lg %r11,__LC_MCESAD-4095(%r14) # extended machine check save area - nill %r11,0xfc00 # MCESA_ORIGIN_MASK - TSTMSK __LC_CREGS_SAVE_AREA+16-4095(%r14),CR2_GUARDED_STORAGE - jno 0f - TSTMSK __LC_MCCK_CODE,MCCK_CODE_GS_VALID - jno 0f - .insn rxy,0xe3000000004d,0,__MCESA_GS_SAVE_AREA(%r11) # LGSC -0: l %r14,__LC_FP_CREG_SAVE_AREA-4095(%r14) - TSTMSK __LC_MCCK_CODE,MCCK_CODE_FC_VALID - jo 0f - sr %r14,%r14 -0: sfpc %r14 - TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX - jo 0f - lghi %r14,__LC_FPREGS_SAVE_AREA - ld %f0,0(%r14) - ld %f1,8(%r14) - ld %f2,16(%r14) - ld %f3,24(%r14) - ld %f4,32(%r14) - ld %f5,40(%r14) - ld %f6,48(%r14) - ld %f7,56(%r14) - ld %f8,64(%r14) - ld %f9,72(%r14) - ld %f10,80(%r14) - ld %f11,88(%r14) - ld %f12,96(%r14) - ld %f13,104(%r14) - ld %f14,112(%r14) - ld %f15,120(%r14) - j 1f -0: VLM %v0,%v15,0,%r11 - VLM %v16,%v31,256,%r11 -1: lghi %r14,__LC_CPU_TIMER_SAVE_AREA + lghi %r14,__LC_CPU_TIMER_SAVE_AREA mvc __LC_MCCK_ENTER_TIMER(8),0(%r14) TSTMSK __LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID jo 3f @@ -546,24 +531,29 @@ ENTRY(mcck_int_handler) 3: TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_MWP_VALID jno .Lmcck_panic tmhh %r8,0x0001 # interrupting from user ? - jnz 4f + jnz 6f TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_IA_VALID jno .Lmcck_panic -4: ssm __LC_PGM_NEW_PSW # turn dat on, keep irqs off - tmhh %r8,0x0001 # interrupting from user ? - jnz .Lmcck_user #if IS_ENABLED(CONFIG_KVM) - OUTSIDE %r9,.Lsie_gmap,.Lsie_done,.Lmcck_stack - OUTSIDE %r9,.Lsie_entry,.Lsie_skip,5f + OUTSIDE %r9,.Lsie_gmap,.Lsie_done,6f + OUTSIDE %r9,.Lsie_entry,.Lsie_skip,4f oi __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST -5: brasl %r14,.Lcleanup_sie -#endif + j 5f +4: CHKSTG .Lmcck_panic +5: larl %r14,.Lstosm_tmp + stosm 0(%r14),0x04 # turn dat on, keep irqs off + BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST) + SIEEXIT j .Lmcck_stack -.Lmcck_user: +#endif +6: CHKSTG .Lmcck_panic + larl %r14,.Lstosm_tmp + stosm 0(%r14),0x04 # turn dat on, keep irqs off + tmhh %r8,0x0001 # interrupting from user ? + jz .Lmcck_stack BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP .Lmcck_stack: lg %r15,__LC_MCCK_STACK -.Lmcck_skip: la %r11,STACK_FRAME_OVERHEAD(%r15) stctg %c1,%c1,__PT_CR1(%r11) lctlg %c1,%c1,__LC_KERNEL_ASCE @@ -605,8 +595,33 @@ ENTRY(mcck_int_handler) b __LC_RETURN_MCCK_LPSWE .Lmcck_panic: - lg %r15,__LC_NODAT_STACK - j .Lmcck_skip + /* + * Iterate over all possible CPU addresses in the range 0..0xffff + * and stop each CPU using signal processor. Use compare and swap + * to allow just one CPU-stopper and prevent concurrent CPUs from + * stopping each other while leaving the others running. + */ + lhi %r5,0 + lhi %r6,1 + larl %r7,.Lstop_lock + cs %r5,%r6,0(%r7) # single CPU-stopper only + jnz 4f + larl %r7,.Lthis_cpu + stap 0(%r7) # this CPU address + lh %r4,0(%r7) + nilh %r4,0 + lhi %r0,1 + sll %r0,16 # CPU counter + lhi %r3,0 # next CPU address +0: cr %r3,%r4 + je 2f +1: sigp %r1,%r3,SIGP_STOP # stop next CPU + brc SIGP_CC_BUSY,1b +2: ahi %r3,1 + brct %r0,0b +3: sigp %r1,%r4,SIGP_STOP # stop this CPU + brc SIGP_CC_BUSY,3b +4: j 4b ENDPROC(mcck_int_handler) # @@ -657,15 +672,11 @@ ENTRY(stack_overflow) ENDPROC(stack_overflow) #endif -#if IS_ENABLED(CONFIG_KVM) -.Lcleanup_sie: - BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST) - lg %r9,__SF_SIE_CONTROL(%r15) # get control block pointer - ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE - lctlg %c1,%c1,__LC_KERNEL_ASCE - larl %r9,sie_exit # skip forward to sie_exit - BR_EX %r14,%r13 -#endif + .section .data, "aw" + .align 4 +.Lstop_lock: .long 0 +.Lthis_cpu: .short 0 +.Lstosm_tmp: .byte 0 .section .rodata, "a" #define SYSCALL(esame,emu) .quad __s390x_ ## esame .globl sys_call_table diff --git a/arch/s390/kernel/ftrace.c b/arch/s390/kernel/ftrace.c index c6ddeb5029b4..2d8f595d9196 100644 --- a/arch/s390/kernel/ftrace.c +++ b/arch/s390/kernel/ftrace.c @@ -40,6 +40,7 @@ * trampoline (ftrace_plt), which clobbers also r1. */ +void *ftrace_func __read_mostly = ftrace_stub; unsigned long ftrace_plt; int ftrace_modify_call(struct dyn_ftrace *rec, unsigned long old_addr, @@ -85,6 +86,7 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) int ftrace_update_ftrace_func(ftrace_func_t func) { + ftrace_func = func; return 0; } diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c index c0df4060d28d..234d085257eb 100644 --- a/arch/s390/kernel/irq.c +++ b/arch/s390/kernel/irq.c @@ -110,15 +110,17 @@ static int on_async_stack(void) { unsigned long frame = current_frame_address(); - return !!!((S390_lowcore.async_stack - frame) >> (PAGE_SHIFT + THREAD_SIZE_ORDER)); + return ((S390_lowcore.async_stack ^ frame) & ~(THREAD_SIZE - 1)) == 0; } static void do_irq_async(struct pt_regs *regs, int irq) { - if (on_async_stack()) + if (on_async_stack()) { do_IRQ(regs, irq); - else - CALL_ON_STACK(do_IRQ, S390_lowcore.async_stack, 2, regs, irq); + } else { + call_on_stack(2, S390_lowcore.async_stack, void, do_IRQ, + struct pt_regs *, regs, int, irq); + } } static int irq_pending(struct pt_regs *regs) @@ -266,24 +268,6 @@ unsigned int arch_dynirq_lower_bound(unsigned int from) } /* - * Switch to the asynchronous interrupt stack for softirq execution. - */ -void do_softirq_own_stack(void) -{ - unsigned long old, new; - - old = current_stack_pointer(); - /* Check against async. stack address range. */ - new = S390_lowcore.async_stack; - if (((new - old) >> (PAGE_SHIFT + THREAD_SIZE_ORDER)) != 0) { - CALL_ON_STACK(__do_softirq, new, 0); - } else { - /* We are already on the async stack. */ - __do_softirq(); - } -} - -/* * ext_int_hash[index] is the list head for all external interrupts that hash * to this index. */ diff --git a/arch/s390/kernel/kprobes.c b/arch/s390/kernel/kprobes.c index 528bb31815c3..52d056a5f89f 100644 --- a/arch/s390/kernel/kprobes.c +++ b/arch/s390/kernel/kprobes.c @@ -92,11 +92,6 @@ static void copy_instruction(struct kprobe *p) } NOKPROBE_SYMBOL(copy_instruction); -static inline int is_kernel_addr(void *addr) -{ - return addr < (void *)_end; -} - static int s390_get_insn_slot(struct kprobe *p) { /* @@ -105,7 +100,7 @@ static int s390_get_insn_slot(struct kprobe *p) * field can be patched and executed within the insn slot. */ p->ainsn.insn = NULL; - if (is_kernel_addr(p->addr)) + if (is_kernel((unsigned long)p->addr)) p->ainsn.insn = get_s390_insn_slot(); else if (is_module_addr(p->addr)) p->ainsn.insn = get_insn_slot(); @@ -117,7 +112,7 @@ static void s390_free_insn_slot(struct kprobe *p) { if (!p->ainsn.insn) return; - if (is_kernel_addr(p->addr)) + if (is_kernel((unsigned long)p->addr)) free_s390_insn_slot(p->ainsn.insn, 0); else free_insn_slot(p->ainsn.insn, 0); diff --git a/arch/s390/kernel/machine_kexec.c b/arch/s390/kernel/machine_kexec.c index d91989c7bd6a..1005a6935fbe 100644 --- a/arch/s390/kernel/machine_kexec.c +++ b/arch/s390/kernel/machine_kexec.c @@ -132,7 +132,8 @@ static bool kdump_csum_valid(struct kimage *image) int rc; preempt_disable(); - rc = CALL_ON_STACK(do_start_kdump, S390_lowcore.nodat_stack, 1, image); + rc = call_on_stack(1, S390_lowcore.nodat_stack, unsigned long, do_start_kdump, + unsigned long, (unsigned long)image); preempt_enable(); return rc == 0; #else diff --git a/arch/s390/kernel/mcount.S b/arch/s390/kernel/mcount.S index faf64c2f90f5..6b13797143a7 100644 --- a/arch/s390/kernel/mcount.S +++ b/arch/s390/kernel/mcount.S @@ -59,13 +59,13 @@ ENTRY(ftrace_caller) #ifdef CONFIG_HAVE_MARCH_Z196_FEATURES aghik %r2,%r0,-MCOUNT_INSN_SIZE lgrl %r4,function_trace_op - lgrl %r1,ftrace_trace_function + lgrl %r1,ftrace_func #else lgr %r2,%r0 aghi %r2,-MCOUNT_INSN_SIZE larl %r4,function_trace_op lg %r4,0(%r4) - larl %r1,ftrace_trace_function + larl %r1,ftrace_func lg %r1,0(%r1) #endif lgr %r3,%r14 diff --git a/arch/s390/kernel/nmi.c b/arch/s390/kernel/nmi.c index 11f8c296f60d..20f8e1868853 100644 --- a/arch/s390/kernel/nmi.c +++ b/arch/s390/kernel/nmi.c @@ -189,12 +189,16 @@ void noinstr s390_handle_mcck(void) * returns 0 if all required registers are available * returns 1 otherwise */ -static int notrace s390_check_registers(union mci mci, int umode) +static int notrace s390_validate_registers(union mci mci, int umode) { + struct mcesa *mcesa; + void *fpt_save_area; union ctlreg2 cr2; int kill_task; + u64 zero; kill_task = 0; + zero = 0; if (!mci.gr) { /* @@ -205,14 +209,6 @@ static int notrace s390_check_registers(union mci mci, int umode) s390_handle_damage(); kill_task = 1; } - /* Check control registers */ - if (!mci.cr) { - /* - * Control registers have unknown contents. - * Can't recover and therefore stopping machine. - */ - s390_handle_damage(); - } if (!mci.fp) { /* * Floating point registers can't be restored. If the @@ -225,35 +221,89 @@ static int notrace s390_check_registers(union mci mci, int umode) if (!test_cpu_flag(CIF_FPU)) kill_task = 1; } + fpt_save_area = &S390_lowcore.floating_pt_save_area; if (!mci.fc) { /* * Floating point control register can't be restored. * If the kernel currently uses the floating pointer * registers and needs the FPC register the system is * stopped. If the process has its floating pointer - * registers loaded it is terminated. + * registers loaded it is terminated. Otherwise the + * FPC is just validated. */ if (S390_lowcore.fpu_flags & KERNEL_FPC) s390_handle_damage(); + asm volatile( + " lfpc %0\n" + : + : "Q" (zero)); if (!test_cpu_flag(CIF_FPU)) kill_task = 1; + } else { + asm volatile( + " lfpc %0\n" + : + : "Q" (S390_lowcore.fpt_creg_save_area)); } - if (MACHINE_HAS_VX) { + mcesa = (struct mcesa *)(S390_lowcore.mcesad & MCESA_ORIGIN_MASK); + if (!MACHINE_HAS_VX) { + /* Validate floating point registers */ + asm volatile( + " ld 0,0(%0)\n" + " ld 1,8(%0)\n" + " ld 2,16(%0)\n" + " ld 3,24(%0)\n" + " ld 4,32(%0)\n" + " ld 5,40(%0)\n" + " ld 6,48(%0)\n" + " ld 7,56(%0)\n" + " ld 8,64(%0)\n" + " ld 9,72(%0)\n" + " ld 10,80(%0)\n" + " ld 11,88(%0)\n" + " ld 12,96(%0)\n" + " ld 13,104(%0)\n" + " ld 14,112(%0)\n" + " ld 15,120(%0)\n" + : + : "a" (fpt_save_area) + : "memory"); + } else { + /* Validate vector registers */ + union ctlreg0 cr0; + if (!mci.vr) { /* * Vector registers can't be restored. If the kernel * currently uses vector registers the system is * stopped. If the process has its vector registers - * loaded it is terminated. + * loaded it is terminated. Otherwise just validate + * the registers. */ if (S390_lowcore.fpu_flags & KERNEL_VXR) s390_handle_damage(); if (!test_cpu_flag(CIF_FPU)) kill_task = 1; } + cr0.val = S390_lowcore.cregs_save_area[0]; + cr0.afp = cr0.vx = 1; + __ctl_load(cr0.val, 0, 0); + asm volatile( + " la 1,%0\n" + " .word 0xe70f,0x1000,0x0036\n" /* vlm 0,15,0(1) */ + " .word 0xe70f,0x1100,0x0c36\n" /* vlm 16,31,256(1) */ + : + : "Q" (*(struct vx_array *)mcesa->vector_save_area) + : "1"); + __ctl_load(S390_lowcore.cregs_save_area[0], 0, 0); } - /* Check if access registers are valid */ + /* Validate access registers */ + asm volatile( + " lam 0,15,0(%0)\n" + : + : "a" (&S390_lowcore.access_regs_save_area) + : "memory"); if (!mci.ar) { /* * Access registers have unknown contents. @@ -261,7 +311,7 @@ static int notrace s390_check_registers(union mci mci, int umode) */ kill_task = 1; } - /* Check guarded storage registers */ + /* Validate guarded storage registers */ cr2.val = S390_lowcore.cregs_save_area[2]; if (cr2.gse) { if (!mci.gs) { @@ -271,31 +321,26 @@ static int notrace s390_check_registers(union mci mci, int umode) * It has to be terminated. */ kill_task = 1; + } else { + load_gs_cb((struct gs_cb *)mcesa->guarded_storage_save_area); } } - /* Check if old PSW is valid */ - if (!mci.wp) { - /* - * Can't tell if we come from user or kernel mode - * -> stopping machine. - */ - s390_handle_damage(); - } - /* Check for invalid kernel instruction address */ - if (!mci.ia && !umode) { - /* - * The instruction address got lost while running - * in the kernel -> stopping machine. - */ - s390_handle_damage(); - } + /* + * The getcpu vdso syscall reads CPU number from the programmable + * field of the TOD clock. Disregard the TOD programmable register + * validity bit and load the CPU number into the TOD programmable + * field unconditionally. + */ + set_tod_programmable_field(raw_smp_processor_id()); + /* Validate clock comparator register */ + set_clock_comparator(S390_lowcore.clock_comparator); if (!mci.ms || !mci.pm || !mci.ia) kill_task = 1; return kill_task; } -NOKPROBE_SYMBOL(s390_check_registers); +NOKPROBE_SYMBOL(s390_validate_registers); /* * Backup the guest's machine check info to its description block @@ -353,11 +398,6 @@ int notrace s390_do_machine_check(struct pt_regs *regs) mci.val = S390_lowcore.mcck_interruption_code; mcck = this_cpu_ptr(&cpu_mcck); - if (mci.sd) { - /* System damage -> stopping machine */ - s390_handle_damage(); - } - /* * Reinject the instruction processing damages' machine checks * including Delayed Access Exception into the guest @@ -398,7 +438,7 @@ int notrace s390_do_machine_check(struct pt_regs *regs) s390_handle_damage(); } } - if (s390_check_registers(mci, user_mode(regs))) { + if (s390_validate_registers(mci, user_mode(regs))) { /* * Couldn't restore all register contents for the * user space process -> mark task for termination. @@ -428,21 +468,6 @@ int notrace s390_do_machine_check(struct pt_regs *regs) mcck_pending = 1; } - /* - * Reinject storage related machine checks into the guest if they - * happen when the guest is running. - */ - if (!test_cpu_flag(CIF_MCCK_GUEST)) { - if (mci.se) - /* Storage error uncorrected */ - s390_handle_damage(); - if (mci.ke) - /* Storage key-error uncorrected */ - s390_handle_damage(); - if (mci.ds && mci.fa) - /* Storage degradation */ - s390_handle_damage(); - } if (mci.cp) { /* Channel report word pending */ mcck->channel_report = 1; diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_cf.c index 1b7a0525fbed..d7dc36ec0a60 100644 --- a/arch/s390/kernel/perf_cpum_cf.c +++ b/arch/s390/kernel/perf_cpum_cf.c @@ -2,8 +2,9 @@ /* * Performance event support for s390x - CPU-measurement Counter Facility * - * Copyright IBM Corp. 2012, 2019 + * Copyright IBM Corp. 2012, 2021 * Author(s): Hendrik Brueckner <brueckner@linux.ibm.com> + * Thomas Richter <tmricht@linux.ibm.com> */ #define KMSG_COMPONENT "cpum_cf" #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt @@ -14,7 +15,223 @@ #include <linux/notifier.h> #include <linux/init.h> #include <linux/export.h> +#include <linux/miscdevice.h> + #include <asm/cpu_mcf.h> +#include <asm/hwctrset.h> +#include <asm/debug.h> + +static unsigned int cfdiag_cpu_speed; /* CPU speed for CF_DIAG trailer */ +static debug_info_t *cf_dbg; + +#define CF_DIAG_CTRSET_DEF 0xfeef /* Counter set header mark */ + /* interval in seconds */ + +/* Counter sets are stored as data stream in a page sized memory buffer and + * exported to user space via raw data attached to the event sample data. + * Each counter set starts with an eight byte header consisting of: + * - a two byte eye catcher (0xfeef) + * - a one byte counter set number + * - a two byte counter set size (indicates the number of counters in this set) + * - a three byte reserved value (must be zero) to make the header the same + * size as a counter value. + * All counter values are eight byte in size. + * + * All counter sets are followed by a 64 byte trailer. + * The trailer consists of a: + * - flag field indicating valid fields when corresponding bit set + * - the counter facility first and second version number + * - the CPU speed if nonzero + * - the time stamp the counter sets have been collected + * - the time of day (TOD) base value + * - the machine type. + * + * The counter sets are saved when the process is prepared to be executed on a + * CPU and saved again when the process is going to be removed from a CPU. + * The difference of both counter sets are calculated and stored in the event + * sample data area. + */ +struct cf_ctrset_entry { /* CPU-M CF counter set entry (8 byte) */ + unsigned int def:16; /* 0-15 Data Entry Format */ + unsigned int set:16; /* 16-31 Counter set identifier */ + unsigned int ctr:16; /* 32-47 Number of stored counters */ + unsigned int res1:16; /* 48-63 Reserved */ +}; + +struct cf_trailer_entry { /* CPU-M CF_DIAG trailer (64 byte) */ + /* 0 - 7 */ + union { + struct { + unsigned int clock_base:1; /* TOD clock base set */ + unsigned int speed:1; /* CPU speed set */ + /* Measurement alerts */ + unsigned int mtda:1; /* Loss of MT ctr. data alert */ + unsigned int caca:1; /* Counter auth. change alert */ + unsigned int lcda:1; /* Loss of counter data alert */ + }; + unsigned long flags; /* 0-63 All indicators */ + }; + /* 8 - 15 */ + unsigned int cfvn:16; /* 64-79 Ctr First Version */ + unsigned int csvn:16; /* 80-95 Ctr Second Version */ + unsigned int cpu_speed:32; /* 96-127 CPU speed */ + /* 16 - 23 */ + unsigned long timestamp; /* 128-191 Timestamp (TOD) */ + /* 24 - 55 */ + union { + struct { + unsigned long progusage1; + unsigned long progusage2; + unsigned long progusage3; + unsigned long tod_base; + }; + unsigned long progusage[4]; + }; + /* 56 - 63 */ + unsigned int mach_type:16; /* Machine type */ + unsigned int res1:16; /* Reserved */ + unsigned int res2:32; /* Reserved */ +}; + +/* Create the trailer data at the end of a page. */ +static void cfdiag_trailer(struct cf_trailer_entry *te) +{ + struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); + struct cpuid cpuid; + + te->cfvn = cpuhw->info.cfvn; /* Counter version numbers */ + te->csvn = cpuhw->info.csvn; + + get_cpu_id(&cpuid); /* Machine type */ + te->mach_type = cpuid.machine; + te->cpu_speed = cfdiag_cpu_speed; + if (te->cpu_speed) + te->speed = 1; + te->clock_base = 1; /* Save clock base */ + te->tod_base = tod_clock_base.tod; + te->timestamp = get_tod_clock_fast(); +} + +/* Read a counter set. The counter set number determines the counter set and + * the CPUM-CF first and second version number determine the number of + * available counters in each counter set. + * Each counter set starts with header containing the counter set number and + * the number of eight byte counters. + * + * The functions returns the number of bytes occupied by this counter set + * including the header. + * If there is no counter in the counter set, this counter set is useless and + * zero is returned on this case. + * + * Note that the counter sets may not be enabled or active and the stcctm + * instruction might return error 3. Depending on error_ok value this is ok, + * for example when called from cpumf_pmu_start() call back function. + */ +static size_t cfdiag_getctrset(struct cf_ctrset_entry *ctrdata, int ctrset, + size_t room, bool error_ok) +{ + struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); + size_t ctrset_size, need = 0; + int rc = 3; /* Assume write failure */ + + ctrdata->def = CF_DIAG_CTRSET_DEF; + ctrdata->set = ctrset; + ctrdata->res1 = 0; + ctrset_size = cpum_cf_ctrset_size(ctrset, &cpuhw->info); + + if (ctrset_size) { /* Save data */ + need = ctrset_size * sizeof(u64) + sizeof(*ctrdata); + if (need <= room) { + rc = ctr_stcctm(ctrset, ctrset_size, + (u64 *)(ctrdata + 1)); + } + if (rc != 3 || error_ok) + ctrdata->ctr = ctrset_size; + else + need = 0; + } + + debug_sprintf_event(cf_dbg, 3, + "%s ctrset %d ctrset_size %zu cfvn %d csvn %d" + " need %zd rc %d\n", __func__, ctrset, ctrset_size, + cpuhw->info.cfvn, cpuhw->info.csvn, need, rc); + return need; +} + +/* Read out all counter sets and save them in the provided data buffer. + * The last 64 byte host an artificial trailer entry. + */ +static size_t cfdiag_getctr(void *data, size_t sz, unsigned long auth, + bool error_ok) +{ + struct cf_trailer_entry *trailer; + size_t offset = 0, done; + int i; + + memset(data, 0, sz); + sz -= sizeof(*trailer); /* Always room for trailer */ + for (i = CPUMF_CTR_SET_BASIC; i < CPUMF_CTR_SET_MAX; ++i) { + struct cf_ctrset_entry *ctrdata = data + offset; + + if (!(auth & cpumf_ctr_ctl[i])) + continue; /* Counter set not authorized */ + + done = cfdiag_getctrset(ctrdata, i, sz - offset, error_ok); + offset += done; + } + trailer = data + offset; + cfdiag_trailer(trailer); + return offset + sizeof(*trailer); +} + +/* Calculate the difference for each counter in a counter set. */ +static void cfdiag_diffctrset(u64 *pstart, u64 *pstop, int counters) +{ + for (; --counters >= 0; ++pstart, ++pstop) + if (*pstop >= *pstart) + *pstop -= *pstart; + else + *pstop = *pstart - *pstop + 1; +} + +/* Scan the counter sets and calculate the difference of each counter + * in each set. The result is the increment of each counter during the + * period the counter set has been activated. + * + * Return true on success. + */ +static int cfdiag_diffctr(struct cpu_cf_events *cpuhw, unsigned long auth) +{ + struct cf_trailer_entry *trailer_start, *trailer_stop; + struct cf_ctrset_entry *ctrstart, *ctrstop; + size_t offset = 0; + + auth &= (1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1; + do { + ctrstart = (struct cf_ctrset_entry *)(cpuhw->start + offset); + ctrstop = (struct cf_ctrset_entry *)(cpuhw->stop + offset); + + if (memcmp(ctrstop, ctrstart, sizeof(*ctrstop))) { + pr_err_once("cpum_cf_diag counter set compare error " + "in set %i\n", ctrstart->set); + return 0; + } + auth &= ~cpumf_ctr_ctl[ctrstart->set]; + if (ctrstart->def == CF_DIAG_CTRSET_DEF) { + cfdiag_diffctrset((u64 *)(ctrstart + 1), + (u64 *)(ctrstop + 1), ctrstart->ctr); + offset += ctrstart->ctr * sizeof(u64) + + sizeof(*ctrstart); + } + } while (ctrstart->def && auth); + + /* Save time_stamp from start of event in stop's trailer */ + trailer_start = (struct cf_trailer_entry *)(cpuhw->start + offset); + trailer_stop = (struct cf_trailer_entry *)(cpuhw->stop + offset); + trailer_stop->progusage[0] = trailer_start->timestamp; + + return 1; +} static enum cpumf_ctr_set get_counter_set(u64 event) { @@ -34,7 +251,8 @@ static enum cpumf_ctr_set get_counter_set(u64 event) return set; } -static int validate_ctr_version(const struct hw_perf_event *hwc) +static int validate_ctr_version(const struct hw_perf_event *hwc, + enum cpumf_ctr_set set) { struct cpu_cf_events *cpuhw; int err = 0; @@ -43,7 +261,7 @@ static int validate_ctr_version(const struct hw_perf_event *hwc) cpuhw = &get_cpu_var(cpu_cf_events); /* check required version for counter sets */ - switch (hwc->config_base) { + switch (set) { case CPUMF_CTR_SET_BASIC: case CPUMF_CTR_SET_USER: if (cpuhw->info.cfvn < 1) @@ -86,6 +304,8 @@ static int validate_ctr_version(const struct hw_perf_event *hwc) (cpuhw->info.act_ctl & mtdiag_ctl))) err = -EOPNOTSUPP; break; + case CPUMF_CTR_SET_MAX: + err = -EOPNOTSUPP; } put_cpu_var(cpu_cf_events); @@ -95,7 +315,6 @@ static int validate_ctr_version(const struct hw_perf_event *hwc) static int validate_ctr_auth(const struct hw_perf_event *hwc) { struct cpu_cf_events *cpuhw; - u64 ctrs_state; int err = 0; cpuhw = &get_cpu_var(cpu_cf_events); @@ -105,8 +324,7 @@ static int validate_ctr_auth(const struct hw_perf_event *hwc) * return with -ENOENT in order to fall back to other * PMUs that might suffice the event request. */ - ctrs_state = cpumf_ctr_ctl[hwc->config_base]; - if (!(ctrs_state & cpuhw->info.auth_ctl)) + if (!(hwc->config_base & cpuhw->info.auth_ctl)) err = -ENOENT; put_cpu_var(cpu_cf_events); @@ -126,7 +344,7 @@ static void cpumf_pmu_enable(struct pmu *pmu) if (cpuhw->flags & PMU_F_ENABLED) return; - err = lcctl(cpuhw->state); + err = lcctl(cpuhw->state | cpuhw->dev_state); if (err) { pr_err("Enabling the performance measuring unit " "failed with rc=%x\n", err); @@ -151,6 +369,7 @@ static void cpumf_pmu_disable(struct pmu *pmu) return; inactive = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1); + inactive |= cpuhw->dev_state; err = lcctl(inactive); if (err) { pr_err("Disabling the performance measuring unit " @@ -199,6 +418,14 @@ static const int cpumf_generic_events_user[] = { [PERF_COUNT_HW_BUS_CYCLES] = -1, }; +static void cpumf_hw_inuse(void) +{ + mutex_lock(&pmc_reserve_mutex); + if (atomic_inc_return(&num_events) == 1) + __kernel_cpumcf_begin(); + mutex_unlock(&pmc_reserve_mutex); +} + static int __hw_perf_event_init(struct perf_event *event, unsigned int type) { struct perf_event_attr *attr = &event->attr; @@ -258,11 +485,11 @@ static int __hw_perf_event_init(struct perf_event *event, unsigned int type) /* * Use the hardware perf event structure to store the * counter number in the 'config' member and the counter - * set number in the 'config_base'. The counter set number - * is then later used to enable/disable the counter(s). + * set number in the 'config_base' as bit mask. + * It is later used to enable/disable the counter(s). */ hwc->config = ev; - hwc->config_base = set; + hwc->config_base = cpumf_ctr_ctl[set]; break; case CPUMF_CTR_SET_MAX: /* The counter could not be associated to a counter set */ @@ -270,22 +497,13 @@ static int __hw_perf_event_init(struct perf_event *event, unsigned int type) } /* Initialize for using the CPU-measurement counter facility */ - if (!atomic_inc_not_zero(&num_events)) { - mutex_lock(&pmc_reserve_mutex); - if (atomic_read(&num_events) == 0 && __kernel_cpumcf_begin()) - err = -EBUSY; - else - atomic_inc(&num_events); - mutex_unlock(&pmc_reserve_mutex); - } - if (err) - return err; + cpumf_hw_inuse(); event->destroy = hw_perf_event_destroy; /* Finally, validate version and authorization of the counter set */ err = validate_ctr_auth(hwc); if (!err) - err = validate_ctr_version(hwc); + err = validate_ctr_version(hwc, set); return err; } @@ -361,6 +579,7 @@ static void cpumf_pmu_start(struct perf_event *event, int flags) { struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); struct hw_perf_event *hwc = &event->hw; + int i; if (!(hwc->state & PERF_HES_STOPPED)) return; @@ -376,29 +595,92 @@ static void cpumf_pmu_start(struct perf_event *event, int flags) * needs to be synchronized. At this point, the counter set can be in * the inactive or disabled state. */ - hw_perf_event_reset(event); + if (hwc->config == PERF_EVENT_CPUM_CF_DIAG) { + cpuhw->usedss = cfdiag_getctr(cpuhw->start, + sizeof(cpuhw->start), + hwc->config_base, true); + } else { + hw_perf_event_reset(event); + } - /* increment refcount for this counter set */ - atomic_inc(&cpuhw->ctr_set[hwc->config_base]); + /* Increment refcount for counter sets */ + for (i = CPUMF_CTR_SET_BASIC; i < CPUMF_CTR_SET_MAX; ++i) + if ((hwc->config_base & cpumf_ctr_ctl[i])) + atomic_inc(&cpuhw->ctr_set[i]); +} + +/* Create perf event sample with the counter sets as raw data. The sample + * is then pushed to the event subsystem and the function checks for + * possible event overflows. If an event overflow occurs, the PMU is + * stopped. + * + * Return non-zero if an event overflow occurred. + */ +static int cfdiag_push_sample(struct perf_event *event, + struct cpu_cf_events *cpuhw) +{ + struct perf_sample_data data; + struct perf_raw_record raw; + struct pt_regs regs; + int overflow; + + /* Setup perf sample */ + perf_sample_data_init(&data, 0, event->hw.last_period); + memset(®s, 0, sizeof(regs)); + memset(&raw, 0, sizeof(raw)); + + if (event->attr.sample_type & PERF_SAMPLE_CPU) + data.cpu_entry.cpu = event->cpu; + if (event->attr.sample_type & PERF_SAMPLE_RAW) { + raw.frag.size = cpuhw->usedss; + raw.frag.data = cpuhw->stop; + raw.size = raw.frag.size; + data.raw = &raw; + } + + overflow = perf_event_overflow(event, &data, ®s); + debug_sprintf_event(cf_dbg, 3, + "%s event %#llx sample_type %#llx raw %d ov %d\n", + __func__, event->hw.config, + event->attr.sample_type, raw.size, overflow); + if (overflow) + event->pmu->stop(event, 0); + + perf_event_update_userpage(event); + return overflow; } static void cpumf_pmu_stop(struct perf_event *event, int flags) { struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); struct hw_perf_event *hwc = &event->hw; + int i; if (!(hwc->state & PERF_HES_STOPPED)) { /* Decrement reference count for this counter set and if this * is the last used counter in the set, clear activation * control and set the counter set state to inactive. */ - if (!atomic_dec_return(&cpuhw->ctr_set[hwc->config_base])) - ctr_set_stop(&cpuhw->state, hwc->config_base); + for (i = CPUMF_CTR_SET_BASIC; i < CPUMF_CTR_SET_MAX; ++i) { + if (!(hwc->config_base & cpumf_ctr_ctl[i])) + continue; + if (!atomic_dec_return(&cpuhw->ctr_set[i])) + ctr_set_stop(&cpuhw->state, cpumf_ctr_ctl[i]); + } hwc->state |= PERF_HES_STOPPED; } if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { - hw_perf_event_update(event); + if (hwc->config == PERF_EVENT_CPUM_CF_DIAG) { + local64_inc(&event->count); + cpuhw->usedss = cfdiag_getctr(cpuhw->stop, + sizeof(cpuhw->stop), + event->hw.config_base, + false); + if (cfdiag_diffctr(cpuhw, event->hw.config_base)) + cfdiag_push_sample(event, cpuhw); + } else + hw_perf_event_update(event); hwc->state |= PERF_HES_UPTODATE; } } @@ -419,6 +701,7 @@ static int cpumf_pmu_add(struct perf_event *event, int flags) static void cpumf_pmu_del(struct perf_event *event, int flags) { struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); + int i; cpumf_pmu_stop(event, PERF_EF_UPDATE); @@ -430,8 +713,9 @@ static void cpumf_pmu_del(struct perf_event *event, int flags) * clear enable control and resets all counters in a set. Therefore, * cpumf_pmu_start() always has to reenable a counter set. */ - if (!atomic_read(&cpuhw->ctr_set[event->hw.config_base])) - ctr_set_disable(&cpuhw->state, event->hw.config_base); + for (i = CPUMF_CTR_SET_BASIC; i < CPUMF_CTR_SET_MAX; ++i) + if (!atomic_read(&cpuhw->ctr_set[i])) + ctr_set_disable(&cpuhw->state, cpumf_ctr_ctl[i]); } /* Performance monitoring unit for s390x */ @@ -448,6 +732,7 @@ static struct pmu cpumf_pmu = { .read = cpumf_pmu_read, }; +static int cfset_init(void); static int __init cpumf_pmu_init(void) { int rc; @@ -455,10 +740,689 @@ static int __init cpumf_pmu_init(void) if (!kernel_cpumcf_avail()) return -ENODEV; + /* Setup s390dbf facility */ + cf_dbg = debug_register(KMSG_COMPONENT, 2, 1, 128); + if (!cf_dbg) { + pr_err("Registration of s390dbf(cpum_cf) failed\n"); + return -ENOMEM; + } + debug_register_view(cf_dbg, &debug_sprintf_view); + cpumf_pmu.attr_groups = cpumf_cf_event_group(); rc = perf_pmu_register(&cpumf_pmu, "cpum_cf", -1); - if (rc) + if (rc) { + debug_unregister_view(cf_dbg, &debug_sprintf_view); + debug_unregister(cf_dbg); pr_err("Registering the cpum_cf PMU failed with rc=%i\n", rc); + } else if (stccm_avail()) { /* Setup counter set device */ + cfset_init(); + } + return rc; +} + +/* Support for the CPU Measurement Facility counter set extraction using + * device /dev/hwctr. This allows user space programs to extract complete + * counter set via normal file operations. + */ + +static atomic_t cfset_opencnt = ATOMIC_INIT(0); /* Excl. access */ +static DEFINE_MUTEX(cfset_ctrset_mutex);/* Synchronize access to hardware */ +struct cfset_call_on_cpu_parm { /* Parm struct for smp_call_on_cpu */ + unsigned int sets; /* Counter set bit mask */ + atomic_t cpus_ack; /* # CPUs successfully executed func */ +}; + +static struct cfset_request { /* CPUs and counter set bit mask */ + unsigned long ctrset; /* Bit mask of counter set to read */ + cpumask_t mask; /* CPU mask to read from */ +} cfset_request; + +static void cfset_ctrset_clear(void) +{ + cpumask_clear(&cfset_request.mask); + cfset_request.ctrset = 0; +} + +/* The /dev/hwctr device access uses PMU_F_IN_USE to mark the device access + * path is currently used. + * The cpu_cf_events::dev_state is used to denote counter sets in use by this + * interface. It is always or'ed in. If this interface is not active, its + * value is zero and no additional counter sets will be included. + * + * The cpu_cf_events::state is used by the perf_event_open SVC and remains + * unchanged. + * + * perf_pmu_enable() and perf_pmu_enable() and its call backs + * cpumf_pmu_enable() and cpumf_pmu_disable() are called by the + * performance measurement subsystem to enable per process + * CPU Measurement counter facility. + * The XXX_enable() and XXX_disable functions are used to turn off + * x86 performance monitoring interrupt (PMI) during scheduling. + * s390 uses these calls to temporarily stop and resume the active CPU + * counters sets during scheduling. + * + * We do allow concurrent access of perf_event_open() SVC and /dev/hwctr + * device access. The perf_event_open() SVC interface makes a lot of effort + * to only run the counters while the calling process is actively scheduled + * to run. + * When /dev/hwctr interface is also used at the same time, the counter sets + * will keep running, even when the process is scheduled off a CPU. + * However this is not a problem and does not lead to wrong counter values + * for the perf_event_open() SVC. The current counter value will be recorded + * during schedule-in. At schedule-out time the current counter value is + * extracted again and the delta is calculated and added to the event. + */ +/* Stop all counter sets via ioctl interface */ +static void cfset_ioctl_off(void *parm) +{ + struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); + struct cfset_call_on_cpu_parm *p = parm; + int rc; + + cpuhw->dev_state = 0; + for (rc = CPUMF_CTR_SET_BASIC; rc < CPUMF_CTR_SET_MAX; ++rc) + if ((p->sets & cpumf_ctr_ctl[rc])) + atomic_dec(&cpuhw->ctr_set[rc]); + rc = lcctl(cpuhw->state); /* Keep perf_event_open counter sets */ + if (rc) + pr_err("Counter set stop %#llx of /dev/%s failed rc=%i\n", + cpuhw->state, S390_HWCTR_DEVICE, rc); + cpuhw->flags &= ~PMU_F_IN_USE; + debug_sprintf_event(cf_dbg, 4, "%s rc %d state %#llx dev_state %#llx\n", + __func__, rc, cpuhw->state, cpuhw->dev_state); +} + +/* Start counter sets on particular CPU */ +static void cfset_ioctl_on(void *parm) +{ + struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); + struct cfset_call_on_cpu_parm *p = parm; + int rc; + + cpuhw->flags |= PMU_F_IN_USE; + ctr_set_enable(&cpuhw->dev_state, p->sets); + ctr_set_start(&cpuhw->dev_state, p->sets); + for (rc = CPUMF_CTR_SET_BASIC; rc < CPUMF_CTR_SET_MAX; ++rc) + if ((p->sets & cpumf_ctr_ctl[rc])) + atomic_inc(&cpuhw->ctr_set[rc]); + rc = lcctl(cpuhw->dev_state | cpuhw->state); /* Start counter sets */ + if (!rc) + atomic_inc(&p->cpus_ack); + else + pr_err("Counter set start %#llx of /dev/%s failed rc=%i\n", + cpuhw->dev_state | cpuhw->state, S390_HWCTR_DEVICE, rc); + debug_sprintf_event(cf_dbg, 4, "%s rc %d state %#llx dev_state %#llx\n", + __func__, rc, cpuhw->state, cpuhw->dev_state); +} + +static void cfset_release_cpu(void *p) +{ + struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); + int rc; + + debug_sprintf_event(cf_dbg, 4, "%s state %#llx dev_state %#llx\n", + __func__, cpuhw->state, cpuhw->dev_state); + rc = lcctl(cpuhw->state); /* Keep perf_event_open counter sets */ + if (rc) + pr_err("Counter set release %#llx of /dev/%s failed rc=%i\n", + cpuhw->state, S390_HWCTR_DEVICE, rc); + cpuhw->dev_state = 0; +} + +/* Release function is also called when application gets terminated without + * doing a proper ioctl(..., S390_HWCTR_STOP, ...) command. + */ +static int cfset_release(struct inode *inode, struct file *file) +{ + on_each_cpu(cfset_release_cpu, NULL, 1); + hw_perf_event_destroy(NULL); + cfset_ctrset_clear(); + atomic_set(&cfset_opencnt, 0); + return 0; +} + +static int cfset_open(struct inode *inode, struct file *file) +{ + if (!capable(CAP_SYS_ADMIN)) + return -EPERM; + /* Only one user space program can open /dev/hwctr */ + if (atomic_xchg(&cfset_opencnt, 1)) + return -EBUSY; + + cpumf_hw_inuse(); + file->private_data = NULL; + /* nonseekable_open() never fails */ + return nonseekable_open(inode, file); +} + +static int cfset_all_stop(void) +{ + struct cfset_call_on_cpu_parm p = { + .sets = cfset_request.ctrset, + }; + cpumask_var_t mask; + + if (!alloc_cpumask_var(&mask, GFP_KERNEL)) + return -ENOMEM; + cpumask_and(mask, &cfset_request.mask, cpu_online_mask); + on_each_cpu_mask(mask, cfset_ioctl_off, &p, 1); + free_cpumask_var(mask); + return 0; +} + +static int cfset_all_start(void) +{ + struct cfset_call_on_cpu_parm p = { + .sets = cfset_request.ctrset, + .cpus_ack = ATOMIC_INIT(0), + }; + cpumask_var_t mask; + int rc = 0; + + if (!alloc_cpumask_var(&mask, GFP_KERNEL)) + return -ENOMEM; + cpumask_and(mask, &cfset_request.mask, cpu_online_mask); + on_each_cpu_mask(mask, cfset_ioctl_on, &p, 1); + if (atomic_read(&p.cpus_ack) != cpumask_weight(mask)) { + on_each_cpu_mask(mask, cfset_ioctl_off, &p, 1); + rc = -EIO; + debug_sprintf_event(cf_dbg, 4, "%s CPUs missing", __func__); + } + free_cpumask_var(mask); return rc; } -subsys_initcall(cpumf_pmu_init); + + +/* Return the maximum required space for all possible CPUs in case one + * CPU will be onlined during the START, READ, STOP cycles. + * To find out the size of the counter sets, any one CPU will do. They + * all have the same counter sets. + */ +static size_t cfset_needspace(unsigned int sets) +{ + struct cpu_cf_events *cpuhw = get_cpu_ptr(&cpu_cf_events); + size_t bytes = 0; + int i; + + for (i = CPUMF_CTR_SET_BASIC; i < CPUMF_CTR_SET_MAX; ++i) { + if (!(sets & cpumf_ctr_ctl[i])) + continue; + bytes += cpum_cf_ctrset_size(i, &cpuhw->info) * sizeof(u64) + + sizeof(((struct s390_ctrset_setdata *)0)->set) + + sizeof(((struct s390_ctrset_setdata *)0)->no_cnts); + } + bytes = sizeof(((struct s390_ctrset_read *)0)->no_cpus) + nr_cpu_ids * + (bytes + sizeof(((struct s390_ctrset_cpudata *)0)->cpu_nr) + + sizeof(((struct s390_ctrset_cpudata *)0)->no_sets)); + put_cpu_ptr(&cpu_cf_events); + return bytes; +} + +static int cfset_all_copy(unsigned long arg, cpumask_t *mask) +{ + struct s390_ctrset_read __user *ctrset_read; + unsigned int cpu, cpus, rc; + void __user *uptr; + + ctrset_read = (struct s390_ctrset_read __user *)arg; + uptr = ctrset_read->data; + for_each_cpu(cpu, mask) { + struct cpu_cf_events *cpuhw = per_cpu_ptr(&cpu_cf_events, cpu); + struct s390_ctrset_cpudata __user *ctrset_cpudata; + + ctrset_cpudata = uptr; + rc = put_user(cpu, &ctrset_cpudata->cpu_nr); + rc |= put_user(cpuhw->sets, &ctrset_cpudata->no_sets); + rc |= copy_to_user(ctrset_cpudata->data, cpuhw->data, + cpuhw->used); + if (rc) + return -EFAULT; + uptr += sizeof(struct s390_ctrset_cpudata) + cpuhw->used; + cond_resched(); + } + cpus = cpumask_weight(mask); + if (put_user(cpus, &ctrset_read->no_cpus)) + return -EFAULT; + debug_sprintf_event(cf_dbg, 4, "%s copied %ld\n", __func__, + uptr - (void __user *)ctrset_read->data); + return 0; +} + +static size_t cfset_cpuset_read(struct s390_ctrset_setdata *p, int ctrset, + int ctrset_size, size_t room) +{ + size_t need = 0; + int rc = -1; + + need = sizeof(*p) + sizeof(u64) * ctrset_size; + if (need <= room) { + p->set = cpumf_ctr_ctl[ctrset]; + p->no_cnts = ctrset_size; + rc = ctr_stcctm(ctrset, ctrset_size, (u64 *)p->cv); + if (rc == 3) /* Nothing stored */ + need = 0; + } + return need; +} + +/* Read all counter sets. */ +static void cfset_cpu_read(void *parm) +{ + struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); + struct cfset_call_on_cpu_parm *p = parm; + int set, set_size; + size_t space; + + /* No data saved yet */ + cpuhw->used = 0; + cpuhw->sets = 0; + memset(cpuhw->data, 0, sizeof(cpuhw->data)); + + /* Scan the counter sets */ + for (set = CPUMF_CTR_SET_BASIC; set < CPUMF_CTR_SET_MAX; ++set) { + struct s390_ctrset_setdata *sp = (void *)cpuhw->data + + cpuhw->used; + + if (!(p->sets & cpumf_ctr_ctl[set])) + continue; /* Counter set not in list */ + set_size = cpum_cf_ctrset_size(set, &cpuhw->info); + space = sizeof(cpuhw->data) - cpuhw->used; + space = cfset_cpuset_read(sp, set, set_size, space); + if (space) { + cpuhw->used += space; + cpuhw->sets += 1; + } + } + debug_sprintf_event(cf_dbg, 4, "%s sets %d used %zd\n", __func__, + cpuhw->sets, cpuhw->used); +} + +static int cfset_all_read(unsigned long arg) +{ + struct cfset_call_on_cpu_parm p; + cpumask_var_t mask; + int rc; + + if (!alloc_cpumask_var(&mask, GFP_KERNEL)) + return -ENOMEM; + + p.sets = cfset_request.ctrset; + cpumask_and(mask, &cfset_request.mask, cpu_online_mask); + on_each_cpu_mask(mask, cfset_cpu_read, &p, 1); + rc = cfset_all_copy(arg, mask); + free_cpumask_var(mask); + return rc; +} + +static long cfset_ioctl_read(unsigned long arg) +{ + struct s390_ctrset_read read; + int ret = 0; + + if (copy_from_user(&read, (char __user *)arg, sizeof(read))) + return -EFAULT; + ret = cfset_all_read(arg); + return ret; +} + +static long cfset_ioctl_stop(void) +{ + int ret = ENXIO; + + if (cfset_request.ctrset) { + ret = cfset_all_stop(); + cfset_ctrset_clear(); + } + return ret; +} + +static long cfset_ioctl_start(unsigned long arg) +{ + struct s390_ctrset_start __user *ustart; + struct s390_ctrset_start start; + void __user *umask; + unsigned int len; + int ret = 0; + size_t need; + + if (cfset_request.ctrset) + return -EBUSY; + ustart = (struct s390_ctrset_start __user *)arg; + if (copy_from_user(&start, ustart, sizeof(start))) + return -EFAULT; + if (start.version != S390_HWCTR_START_VERSION) + return -EINVAL; + if (start.counter_sets & ~(cpumf_ctr_ctl[CPUMF_CTR_SET_BASIC] | + cpumf_ctr_ctl[CPUMF_CTR_SET_USER] | + cpumf_ctr_ctl[CPUMF_CTR_SET_CRYPTO] | + cpumf_ctr_ctl[CPUMF_CTR_SET_EXT] | + cpumf_ctr_ctl[CPUMF_CTR_SET_MT_DIAG])) + return -EINVAL; /* Invalid counter set */ + if (!start.counter_sets) + return -EINVAL; /* No counter set at all? */ + cpumask_clear(&cfset_request.mask); + len = min_t(u64, start.cpumask_len, cpumask_size()); + umask = (void __user *)start.cpumask; + if (copy_from_user(&cfset_request.mask, umask, len)) + return -EFAULT; + if (cpumask_empty(&cfset_request.mask)) + return -EINVAL; + need = cfset_needspace(start.counter_sets); + if (put_user(need, &ustart->data_bytes)) + ret = -EFAULT; + if (ret) + goto out; + cfset_request.ctrset = start.counter_sets; + ret = cfset_all_start(); +out: + if (ret) + cfset_ctrset_clear(); + debug_sprintf_event(cf_dbg, 4, "%s sets %#lx need %ld ret %d\n", + __func__, cfset_request.ctrset, need, ret); + return ret; +} + +/* Entry point to the /dev/hwctr device interface. + * The ioctl system call supports three subcommands: + * S390_HWCTR_START: Start the specified counter sets on a CPU list. The + * counter set keeps running until explicitly stopped. Returns the number + * of bytes needed to store the counter values. If another S390_HWCTR_START + * ioctl subcommand is called without a previous S390_HWCTR_STOP stop + * command, -EBUSY is returned. + * S390_HWCTR_READ: Read the counter set values from specified CPU list given + * with the S390_HWCTR_START command. + * S390_HWCTR_STOP: Stops the counter sets on the CPU list given with the + * previous S390_HWCTR_START subcommand. + */ +static long cfset_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + int ret; + + get_online_cpus(); + mutex_lock(&cfset_ctrset_mutex); + switch (cmd) { + case S390_HWCTR_START: + ret = cfset_ioctl_start(arg); + break; + case S390_HWCTR_STOP: + ret = cfset_ioctl_stop(); + break; + case S390_HWCTR_READ: + ret = cfset_ioctl_read(arg); + break; + default: + ret = -ENOTTY; + break; + } + mutex_unlock(&cfset_ctrset_mutex); + put_online_cpus(); + return ret; +} + +static const struct file_operations cfset_fops = { + .owner = THIS_MODULE, + .open = cfset_open, + .release = cfset_release, + .unlocked_ioctl = cfset_ioctl, + .compat_ioctl = cfset_ioctl, + .llseek = no_llseek +}; + +static struct miscdevice cfset_dev = { + .name = S390_HWCTR_DEVICE, + .minor = MISC_DYNAMIC_MINOR, + .fops = &cfset_fops, +}; + +int cfset_online_cpu(unsigned int cpu) +{ + struct cfset_call_on_cpu_parm p; + + mutex_lock(&cfset_ctrset_mutex); + if (cfset_request.ctrset) { + p.sets = cfset_request.ctrset; + cfset_ioctl_on(&p); + cpumask_set_cpu(cpu, &cfset_request.mask); + } + mutex_unlock(&cfset_ctrset_mutex); + return 0; +} + +int cfset_offline_cpu(unsigned int cpu) +{ + struct cfset_call_on_cpu_parm p; + + mutex_lock(&cfset_ctrset_mutex); + if (cfset_request.ctrset) { + p.sets = cfset_request.ctrset; + cfset_ioctl_off(&p); + cpumask_clear_cpu(cpu, &cfset_request.mask); + } + mutex_unlock(&cfset_ctrset_mutex); + return 0; +} + +static void cfdiag_read(struct perf_event *event) +{ + debug_sprintf_event(cf_dbg, 3, "%s event %#llx count %ld\n", __func__, + event->attr.config, local64_read(&event->count)); +} + +static int get_authctrsets(void) +{ + struct cpu_cf_events *cpuhw; + unsigned long auth = 0; + enum cpumf_ctr_set i; + + cpuhw = &get_cpu_var(cpu_cf_events); + for (i = CPUMF_CTR_SET_BASIC; i < CPUMF_CTR_SET_MAX; ++i) { + if (cpuhw->info.auth_ctl & cpumf_ctr_ctl[i]) + auth |= cpumf_ctr_ctl[i]; + } + put_cpu_var(cpu_cf_events); + return auth; +} + +/* Setup the event. Test for authorized counter sets and only include counter + * sets which are authorized at the time of the setup. Including unauthorized + * counter sets result in specification exception (and panic). + */ +static int cfdiag_event_init2(struct perf_event *event) +{ + struct perf_event_attr *attr = &event->attr; + int err = 0; + + /* Set sample_period to indicate sampling */ + event->hw.config = attr->config; + event->hw.sample_period = attr->sample_period; + local64_set(&event->hw.period_left, event->hw.sample_period); + local64_set(&event->count, 0); + event->hw.last_period = event->hw.sample_period; + + /* Add all authorized counter sets to config_base. The + * the hardware init function is either called per-cpu or just once + * for all CPUS (event->cpu == -1). This depends on the whether + * counting is started for all CPUs or on a per workload base where + * the perf event moves from one CPU to another CPU. + * Checking the authorization on any CPU is fine as the hardware + * applies the same authorization settings to all CPUs. + */ + event->hw.config_base = get_authctrsets(); + + /* No authorized counter sets, nothing to count/sample */ + if (!event->hw.config_base) + err = -EINVAL; + + debug_sprintf_event(cf_dbg, 5, "%s err %d config_base %#lx\n", + __func__, err, event->hw.config_base); + return err; +} + +static int cfdiag_event_init(struct perf_event *event) +{ + struct perf_event_attr *attr = &event->attr; + int err = -ENOENT; + + if (event->attr.config != PERF_EVENT_CPUM_CF_DIAG || + event->attr.type != event->pmu->type) + goto out; + + /* Raw events are used to access counters directly, + * hence do not permit excludes. + * This event is useless without PERF_SAMPLE_RAW to return counter set + * values as raw data. + */ + if (attr->exclude_kernel || attr->exclude_user || attr->exclude_hv || + !(attr->sample_type & (PERF_SAMPLE_CPU | PERF_SAMPLE_RAW))) { + err = -EOPNOTSUPP; + goto out; + } + + /* Initialize for using the CPU-measurement counter facility */ + cpumf_hw_inuse(); + event->destroy = hw_perf_event_destroy; + + err = cfdiag_event_init2(event); + if (unlikely(err)) + event->destroy(event); +out: + return err; +} + +/* Create cf_diag/events/CF_DIAG event sysfs file. This counter is used + * to collect the complete counter sets for a scheduled process. Target + * are complete counter sets attached as raw data to the artificial event. + * This results in complete counter sets available when a process is + * scheduled. Contains the delta of every counter while the process was + * running. + */ +CPUMF_EVENT_ATTR(CF_DIAG, CF_DIAG, PERF_EVENT_CPUM_CF_DIAG); + +static struct attribute *cfdiag_events_attr[] = { + CPUMF_EVENT_PTR(CF_DIAG, CF_DIAG), + NULL, +}; + +PMU_FORMAT_ATTR(event, "config:0-63"); + +static struct attribute *cfdiag_format_attr[] = { + &format_attr_event.attr, + NULL, +}; + +static struct attribute_group cfdiag_events_group = { + .name = "events", + .attrs = cfdiag_events_attr, +}; +static struct attribute_group cfdiag_format_group = { + .name = "format", + .attrs = cfdiag_format_attr, +}; +static const struct attribute_group *cfdiag_attr_groups[] = { + &cfdiag_events_group, + &cfdiag_format_group, + NULL, +}; + +/* Performance monitoring unit for event CF_DIAG. Since this event + * is also started and stopped via the perf_event_open() system call, use + * the same event enable/disable call back functions. They do not + * have a pointer to the perf_event strcture as first parameter. + * + * The functions XXX_add, XXX_del, XXX_start and XXX_stop are also common. + * Reuse them and distinguish the event (always first parameter) via + * 'config' member. + */ +static struct pmu cf_diag = { + .task_ctx_nr = perf_sw_context, + .event_init = cfdiag_event_init, + .pmu_enable = cpumf_pmu_enable, + .pmu_disable = cpumf_pmu_disable, + .add = cpumf_pmu_add, + .del = cpumf_pmu_del, + .start = cpumf_pmu_start, + .stop = cpumf_pmu_stop, + .read = cfdiag_read, + + .attr_groups = cfdiag_attr_groups +}; + +/* Calculate memory needed to store all counter sets together with header and + * trailer data. This is independent of the counter set authorization which + * can vary depending on the configuration. + */ +static size_t cfdiag_maxsize(struct cpumf_ctr_info *info) +{ + size_t max_size = sizeof(struct cf_trailer_entry); + enum cpumf_ctr_set i; + + for (i = CPUMF_CTR_SET_BASIC; i < CPUMF_CTR_SET_MAX; ++i) { + size_t size = cpum_cf_ctrset_size(i, info); + + if (size) + max_size += size * sizeof(u64) + + sizeof(struct cf_ctrset_entry); + } + return max_size; +} + +/* Get the CPU speed, try sampling facility first and CPU attributes second. */ +static void cfdiag_get_cpu_speed(void) +{ + if (cpum_sf_avail()) { /* Sampling facility first */ + struct hws_qsi_info_block si; + + memset(&si, 0, sizeof(si)); + if (!qsi(&si)) { + cfdiag_cpu_speed = si.cpu_speed; + return; + } + } + + /* Fallback: CPU speed extract static part. Used in case + * CPU Measurement Sampling Facility is turned off. + */ + if (test_facility(34)) { + unsigned long mhz = __ecag(ECAG_CPU_ATTRIBUTE, 0); + + if (mhz != -1UL) + cfdiag_cpu_speed = mhz & 0xffffffff; + } +} + +static int cfset_init(void) +{ + struct cpumf_ctr_info info; + size_t need; + int rc; + + if (qctri(&info)) + return -ENODEV; + + cfdiag_get_cpu_speed(); + /* Make sure the counter set data fits into predefined buffer. */ + need = cfdiag_maxsize(&info); + if (need > sizeof(((struct cpu_cf_events *)0)->start)) { + pr_err("Insufficient memory for PMU(cpum_cf_diag) need=%zu\n", + need); + return -ENOMEM; + } + + rc = misc_register(&cfset_dev); + if (rc) { + pr_err("Registration of /dev/%s failed rc=%i\n", + cfset_dev.name, rc); + goto out; + } + + rc = perf_pmu_register(&cf_diag, "cpum_cf_diag", -1); + if (rc) { + misc_deregister(&cfset_dev); + pr_err("Registration of PMU(cpum_cf_diag) failed with rc=%i\n", + rc); + } +out: + return rc; +} + +device_initcall(cpumf_pmu_init); diff --git a/arch/s390/kernel/perf_cpum_cf_common.c b/arch/s390/kernel/perf_cpum_cf_common.c index 2300fbaac556..30f0242de4a5 100644 --- a/arch/s390/kernel/perf_cpum_cf_common.c +++ b/arch/s390/kernel/perf_cpum_cf_common.c @@ -29,7 +29,11 @@ DEFINE_PER_CPU(struct cpu_cf_events, cpu_cf_events) = { }, .alert = ATOMIC64_INIT(0), .state = 0, + .dev_state = 0, .flags = 0, + .used = 0, + .usedss = 0, + .sets = 0 }; /* Indicator whether the CPU-Measurement Counter Facility Support is ready */ static bool cpum_cf_initalized; @@ -96,25 +100,10 @@ bool kernel_cpumcf_avail(void) } EXPORT_SYMBOL(kernel_cpumcf_avail); - -/* Reserve/release functions for sharing perf hardware */ -static DEFINE_SPINLOCK(cpumcf_owner_lock); -static void *cpumcf_owner; - /* Initialize the CPU-measurement counter facility */ int __kernel_cpumcf_begin(void) { int flags = PMC_INIT; - int err = 0; - - spin_lock(&cpumcf_owner_lock); - if (cpumcf_owner) - err = -EBUSY; - else - cpumcf_owner = __builtin_return_address(0); - spin_unlock(&cpumcf_owner_lock); - if (err) - return err; on_each_cpu(cpum_cf_setup_cpu, &flags, 1); irq_subclass_register(IRQ_SUBCLASS_MEASUREMENT_ALERT); @@ -144,10 +133,6 @@ void __kernel_cpumcf_end(void) on_each_cpu(cpum_cf_setup_cpu, &flags, 1); irq_subclass_unregister(IRQ_SUBCLASS_MEASUREMENT_ALERT); - - spin_lock(&cpumcf_owner_lock); - cpumcf_owner = NULL; - spin_unlock(&cpumcf_owner_lock); } EXPORT_SYMBOL(__kernel_cpumcf_end); @@ -161,11 +146,13 @@ static int cpum_cf_setup(unsigned int cpu, int flags) static int cpum_cf_online_cpu(unsigned int cpu) { - return cpum_cf_setup(cpu, PMC_INIT); + cpum_cf_setup(cpu, PMC_INIT); + return cfset_online_cpu(cpu); } static int cpum_cf_offline_cpu(unsigned int cpu) { + cfset_offline_cpu(cpu); return cpum_cf_setup(cpu, PMC_RELEASE); } diff --git a/arch/s390/kernel/perf_cpum_cf_diag.c b/arch/s390/kernel/perf_cpum_cf_diag.c deleted file mode 100644 index 08c985c1097c..000000000000 --- a/arch/s390/kernel/perf_cpum_cf_diag.c +++ /dev/null @@ -1,1148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Performance event support for s390x - CPU-measurement Counter Sets - * - * Copyright IBM Corp. 2019, 2021 - * Author(s): Hendrik Brueckner <brueckner@linux.ibm.com> - * Thomas Richer <tmricht@linux.ibm.com> - */ -#define KMSG_COMPONENT "cpum_cf_diag" -#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt - -#include <linux/kernel.h> -#include <linux/kernel_stat.h> -#include <linux/percpu.h> -#include <linux/notifier.h> -#include <linux/init.h> -#include <linux/export.h> -#include <linux/slab.h> -#include <linux/processor.h> -#include <linux/miscdevice.h> -#include <linux/mutex.h> - -#include <asm/ctl_reg.h> -#include <asm/irq.h> -#include <asm/cpu_mcf.h> -#include <asm/timex.h> -#include <asm/debug.h> - -#include <asm/hwctrset.h> - -#define CF_DIAG_CTRSET_DEF 0xfeef /* Counter set header mark */ - /* interval in seconds */ -static unsigned int cf_diag_cpu_speed; -static debug_info_t *cf_diag_dbg; - -struct cf_diag_csd { /* Counter set data per CPU */ - size_t used; /* Bytes used in data/start */ - unsigned char start[PAGE_SIZE]; /* Counter set at event start */ - unsigned char data[PAGE_SIZE]; /* Counter set at event delete */ - unsigned int sets; /* # Counter set saved in data */ -}; -static DEFINE_PER_CPU(struct cf_diag_csd, cf_diag_csd); - -/* Counter sets are stored as data stream in a page sized memory buffer and - * exported to user space via raw data attached to the event sample data. - * Each counter set starts with an eight byte header consisting of: - * - a two byte eye catcher (0xfeef) - * - a one byte counter set number - * - a two byte counter set size (indicates the number of counters in this set) - * - a three byte reserved value (must be zero) to make the header the same - * size as a counter value. - * All counter values are eight byte in size. - * - * All counter sets are followed by a 64 byte trailer. - * The trailer consists of a: - * - flag field indicating valid fields when corresponding bit set - * - the counter facility first and second version number - * - the CPU speed if nonzero - * - the time stamp the counter sets have been collected - * - the time of day (TOD) base value - * - the machine type. - * - * The counter sets are saved when the process is prepared to be executed on a - * CPU and saved again when the process is going to be removed from a CPU. - * The difference of both counter sets are calculated and stored in the event - * sample data area. - */ - -struct cf_ctrset_entry { /* CPU-M CF counter set entry (8 byte) */ - unsigned int def:16; /* 0-15 Data Entry Format */ - unsigned int set:16; /* 16-31 Counter set identifier */ - unsigned int ctr:16; /* 32-47 Number of stored counters */ - unsigned int res1:16; /* 48-63 Reserved */ -}; - -struct cf_trailer_entry { /* CPU-M CF_DIAG trailer (64 byte) */ - /* 0 - 7 */ - union { - struct { - unsigned int clock_base:1; /* TOD clock base set */ - unsigned int speed:1; /* CPU speed set */ - /* Measurement alerts */ - unsigned int mtda:1; /* Loss of MT ctr. data alert */ - unsigned int caca:1; /* Counter auth. change alert */ - unsigned int lcda:1; /* Loss of counter data alert */ - }; - unsigned long flags; /* 0-63 All indicators */ - }; - /* 8 - 15 */ - unsigned int cfvn:16; /* 64-79 Ctr First Version */ - unsigned int csvn:16; /* 80-95 Ctr Second Version */ - unsigned int cpu_speed:32; /* 96-127 CPU speed */ - /* 16 - 23 */ - unsigned long timestamp; /* 128-191 Timestamp (TOD) */ - /* 24 - 55 */ - union { - struct { - unsigned long progusage1; - unsigned long progusage2; - unsigned long progusage3; - unsigned long tod_base; - }; - unsigned long progusage[4]; - }; - /* 56 - 63 */ - unsigned int mach_type:16; /* Machine type */ - unsigned int res1:16; /* Reserved */ - unsigned int res2:32; /* Reserved */ -}; - -/* Create the trailer data at the end of a page. */ -static void cf_diag_trailer(struct cf_trailer_entry *te) -{ - struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); - struct cpuid cpuid; - - te->cfvn = cpuhw->info.cfvn; /* Counter version numbers */ - te->csvn = cpuhw->info.csvn; - - get_cpu_id(&cpuid); /* Machine type */ - te->mach_type = cpuid.machine; - te->cpu_speed = cf_diag_cpu_speed; - if (te->cpu_speed) - te->speed = 1; - te->clock_base = 1; /* Save clock base */ - te->tod_base = tod_clock_base.tod; - te->timestamp = get_tod_clock_fast(); -} - -/* - * Change the CPUMF state to active. - * Enable and activate the CPU-counter sets according - * to the per-cpu control state. - */ -static void cf_diag_enable(struct pmu *pmu) -{ - struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); - int err; - - debug_sprintf_event(cf_diag_dbg, 5, - "%s pmu %p cpu %d flags %#x state %#llx\n", - __func__, pmu, smp_processor_id(), cpuhw->flags, - cpuhw->state); - if (cpuhw->flags & PMU_F_ENABLED) - return; - - err = lcctl(cpuhw->state); - if (err) { - pr_err("Enabling the performance measuring unit " - "failed with rc=%x\n", err); - return; - } - cpuhw->flags |= PMU_F_ENABLED; -} - -/* - * Change the CPUMF state to inactive. - * Disable and enable (inactive) the CPU-counter sets according - * to the per-cpu control state. - */ -static void cf_diag_disable(struct pmu *pmu) -{ - struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); - u64 inactive; - int err; - - debug_sprintf_event(cf_diag_dbg, 5, - "%s pmu %p cpu %d flags %#x state %#llx\n", - __func__, pmu, smp_processor_id(), cpuhw->flags, - cpuhw->state); - if (!(cpuhw->flags & PMU_F_ENABLED)) - return; - - inactive = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1); - err = lcctl(inactive); - if (err) { - pr_err("Disabling the performance measuring unit " - "failed with rc=%x\n", err); - return; - } - cpuhw->flags &= ~PMU_F_ENABLED; -} - -/* Number of perf events counting hardware events */ -static atomic_t cf_diag_events = ATOMIC_INIT(0); -/* Used to avoid races in calling reserve/release_cpumf_hardware */ -static DEFINE_MUTEX(cf_diag_reserve_mutex); - -/* Release the PMU if event is the last perf event */ -static void cf_diag_perf_event_destroy(struct perf_event *event) -{ - debug_sprintf_event(cf_diag_dbg, 5, - "%s event %p cpu %d cf_diag_events %d\n", - __func__, event, smp_processor_id(), - atomic_read(&cf_diag_events)); - if (atomic_dec_return(&cf_diag_events) == 0) - __kernel_cpumcf_end(); -} - -static int get_authctrsets(void) -{ - struct cpu_cf_events *cpuhw; - unsigned long auth = 0; - enum cpumf_ctr_set i; - - cpuhw = &get_cpu_var(cpu_cf_events); - for (i = CPUMF_CTR_SET_BASIC; i < CPUMF_CTR_SET_MAX; ++i) { - if (cpuhw->info.auth_ctl & cpumf_ctr_ctl[i]) - auth |= cpumf_ctr_ctl[i]; - } - put_cpu_var(cpu_cf_events); - return auth; -} - -/* Setup the event. Test for authorized counter sets and only include counter - * sets which are authorized at the time of the setup. Including unauthorized - * counter sets result in specification exception (and panic). - */ -static int __hw_perf_event_init(struct perf_event *event) -{ - struct perf_event_attr *attr = &event->attr; - int err = 0; - - debug_sprintf_event(cf_diag_dbg, 5, "%s event %p cpu %d\n", __func__, - event, event->cpu); - - event->hw.config = attr->config; - - /* Add all authorized counter sets to config_base. The - * the hardware init function is either called per-cpu or just once - * for all CPUS (event->cpu == -1). This depends on the whether - * counting is started for all CPUs or on a per workload base where - * the perf event moves from one CPU to another CPU. - * Checking the authorization on any CPU is fine as the hardware - * applies the same authorization settings to all CPUs. - */ - event->hw.config_base = get_authctrsets(); - - /* No authorized counter sets, nothing to count/sample */ - if (!event->hw.config_base) { - err = -EINVAL; - goto out; - } - - /* Set sample_period to indicate sampling */ - event->hw.sample_period = attr->sample_period; - local64_set(&event->hw.period_left, event->hw.sample_period); - event->hw.last_period = event->hw.sample_period; -out: - debug_sprintf_event(cf_diag_dbg, 5, "%s err %d config_base %#lx\n", - __func__, err, event->hw.config_base); - return err; -} - -/* Return 0 if the CPU-measurement counter facility is currently free - * and an error otherwise. - */ -static int cf_diag_perf_event_inuse(void) -{ - int err = 0; - - if (!atomic_inc_not_zero(&cf_diag_events)) { - mutex_lock(&cf_diag_reserve_mutex); - if (atomic_read(&cf_diag_events) == 0 && - __kernel_cpumcf_begin()) - err = -EBUSY; - else - err = atomic_inc_return(&cf_diag_events); - mutex_unlock(&cf_diag_reserve_mutex); - } - return err; -} - -static int cf_diag_event_init(struct perf_event *event) -{ - struct perf_event_attr *attr = &event->attr; - int err = -ENOENT; - - debug_sprintf_event(cf_diag_dbg, 5, - "%s event %p cpu %d config %#llx type:%u " - "sample_type %#llx cf_diag_events %d\n", __func__, - event, event->cpu, attr->config, event->pmu->type, - attr->sample_type, atomic_read(&cf_diag_events)); - - if (event->attr.config != PERF_EVENT_CPUM_CF_DIAG || - event->attr.type != event->pmu->type) - goto out; - - /* Raw events are used to access counters directly, - * hence do not permit excludes. - * This event is usesless without PERF_SAMPLE_RAW to return counter set - * values as raw data. - */ - if (attr->exclude_kernel || attr->exclude_user || attr->exclude_hv || - !(attr->sample_type & (PERF_SAMPLE_CPU | PERF_SAMPLE_RAW))) { - err = -EOPNOTSUPP; - goto out; - } - - /* Initialize for using the CPU-measurement counter facility */ - err = cf_diag_perf_event_inuse(); - if (err < 0) - goto out; - event->destroy = cf_diag_perf_event_destroy; - - err = __hw_perf_event_init(event); - if (unlikely(err)) - event->destroy(event); -out: - debug_sprintf_event(cf_diag_dbg, 5, "%s err %d\n", __func__, err); - return err; -} - -static void cf_diag_read(struct perf_event *event) -{ - debug_sprintf_event(cf_diag_dbg, 5, "%s event %p\n", __func__, event); -} - -/* Calculate memory needed to store all counter sets together with header and - * trailer data. This is independend of the counter set authorization which - * can vary depending on the configuration. - */ -static size_t cf_diag_ctrset_maxsize(struct cpumf_ctr_info *info) -{ - size_t max_size = sizeof(struct cf_trailer_entry); - enum cpumf_ctr_set i; - - for (i = CPUMF_CTR_SET_BASIC; i < CPUMF_CTR_SET_MAX; ++i) { - size_t size = cpum_cf_ctrset_size(i, info); - - if (size) - max_size += size * sizeof(u64) + - sizeof(struct cf_ctrset_entry); - } - debug_sprintf_event(cf_diag_dbg, 5, "%s max_size %zu\n", __func__, - max_size); - - return max_size; -} - -/* Read a counter set. The counter set number determines which counter set and - * the CPUM-CF first and second version number determine the number of - * available counters in this counter set. - * Each counter set starts with header containing the counter set number and - * the number of 8 byte counters. - * - * The functions returns the number of bytes occupied by this counter set - * including the header. - * If there is no counter in the counter set, this counter set is useless and - * zero is returned on this case. - */ -static size_t cf_diag_getctrset(struct cf_ctrset_entry *ctrdata, int ctrset, - size_t room) -{ - struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); - size_t ctrset_size, need = 0; - int rc = 3; /* Assume write failure */ - - ctrdata->def = CF_DIAG_CTRSET_DEF; - ctrdata->set = ctrset; - ctrdata->res1 = 0; - ctrset_size = cpum_cf_ctrset_size(ctrset, &cpuhw->info); - - if (ctrset_size) { /* Save data */ - need = ctrset_size * sizeof(u64) + sizeof(*ctrdata); - if (need <= room) - rc = ctr_stcctm(ctrset, ctrset_size, - (u64 *)(ctrdata + 1)); - if (rc != 3) - ctrdata->ctr = ctrset_size; - else - need = 0; - } - - debug_sprintf_event(cf_diag_dbg, 6, - "%s ctrset %d ctrset_size %zu cfvn %d csvn %d" - " need %zd rc %d\n", - __func__, ctrset, ctrset_size, cpuhw->info.cfvn, - cpuhw->info.csvn, need, rc); - return need; -} - -/* Read out all counter sets and save them in the provided data buffer. - * The last 64 byte host an artificial trailer entry. - */ -static size_t cf_diag_getctr(void *data, size_t sz, unsigned long auth) -{ - struct cf_trailer_entry *trailer; - size_t offset = 0, done; - int i; - - memset(data, 0, sz); - sz -= sizeof(*trailer); /* Always room for trailer */ - for (i = CPUMF_CTR_SET_BASIC; i < CPUMF_CTR_SET_MAX; ++i) { - struct cf_ctrset_entry *ctrdata = data + offset; - - if (!(auth & cpumf_ctr_ctl[i])) - continue; /* Counter set not authorized */ - - done = cf_diag_getctrset(ctrdata, i, sz - offset); - offset += done; - debug_sprintf_event(cf_diag_dbg, 6, - "%s ctrset %d offset %zu done %zu\n", - __func__, i, offset, done); - } - trailer = data + offset; - cf_diag_trailer(trailer); - return offset + sizeof(*trailer); -} - -/* Calculate the difference for each counter in a counter set. */ -static void cf_diag_diffctrset(u64 *pstart, u64 *pstop, int counters) -{ - for (; --counters >= 0; ++pstart, ++pstop) - if (*pstop >= *pstart) - *pstop -= *pstart; - else - *pstop = *pstart - *pstop; -} - -/* Scan the counter sets and calculate the difference of each counter - * in each set. The result is the increment of each counter during the - * period the counter set has been activated. - * - * Return true on success. - */ -static int cf_diag_diffctr(struct cf_diag_csd *csd, unsigned long auth) -{ - struct cf_trailer_entry *trailer_start, *trailer_stop; - struct cf_ctrset_entry *ctrstart, *ctrstop; - size_t offset = 0; - - auth &= (1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1; - do { - ctrstart = (struct cf_ctrset_entry *)(csd->start + offset); - ctrstop = (struct cf_ctrset_entry *)(csd->data + offset); - - if (memcmp(ctrstop, ctrstart, sizeof(*ctrstop))) { - pr_err("cpum_cf_diag counter set compare error " - "in set %i\n", ctrstart->set); - return 0; - } - auth &= ~cpumf_ctr_ctl[ctrstart->set]; - if (ctrstart->def == CF_DIAG_CTRSET_DEF) { - cf_diag_diffctrset((u64 *)(ctrstart + 1), - (u64 *)(ctrstop + 1), ctrstart->ctr); - offset += ctrstart->ctr * sizeof(u64) + - sizeof(*ctrstart); - } - debug_sprintf_event(cf_diag_dbg, 6, - "%s set %d ctr %d offset %zu auth %lx\n", - __func__, ctrstart->set, ctrstart->ctr, - offset, auth); - } while (ctrstart->def && auth); - - /* Save time_stamp from start of event in stop's trailer */ - trailer_start = (struct cf_trailer_entry *)(csd->start + offset); - trailer_stop = (struct cf_trailer_entry *)(csd->data + offset); - trailer_stop->progusage[0] = trailer_start->timestamp; - - return 1; -} - -/* Create perf event sample with the counter sets as raw data. The sample - * is then pushed to the event subsystem and the function checks for - * possible event overflows. If an event overflow occurs, the PMU is - * stopped. - * - * Return non-zero if an event overflow occurred. - */ -static int cf_diag_push_sample(struct perf_event *event, - struct cf_diag_csd *csd) -{ - struct perf_sample_data data; - struct perf_raw_record raw; - struct pt_regs regs; - int overflow; - - /* Setup perf sample */ - perf_sample_data_init(&data, 0, event->hw.last_period); - memset(®s, 0, sizeof(regs)); - memset(&raw, 0, sizeof(raw)); - - if (event->attr.sample_type & PERF_SAMPLE_CPU) - data.cpu_entry.cpu = event->cpu; - if (event->attr.sample_type & PERF_SAMPLE_RAW) { - raw.frag.size = csd->used; - raw.frag.data = csd->data; - raw.size = csd->used; - data.raw = &raw; - } - - overflow = perf_event_overflow(event, &data, ®s); - debug_sprintf_event(cf_diag_dbg, 6, - "%s event %p cpu %d sample_type %#llx raw %d " - "ov %d\n", __func__, event, event->cpu, - event->attr.sample_type, raw.size, overflow); - if (overflow) - event->pmu->stop(event, 0); - - perf_event_update_userpage(event); - return overflow; -} - -static void cf_diag_start(struct perf_event *event, int flags) -{ - struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); - struct cf_diag_csd *csd = this_cpu_ptr(&cf_diag_csd); - struct hw_perf_event *hwc = &event->hw; - - debug_sprintf_event(cf_diag_dbg, 5, - "%s event %p cpu %d flags %#x hwc-state %#x\n", - __func__, event, event->cpu, flags, hwc->state); - if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED))) - return; - - /* (Re-)enable and activate all counter sets */ - lcctl(0); /* Reset counter sets */ - hwc->state = 0; - ctr_set_multiple_enable(&cpuhw->state, hwc->config_base); - lcctl(cpuhw->state); /* Enable counter sets */ - csd->used = cf_diag_getctr(csd->start, sizeof(csd->start), - event->hw.config_base); - ctr_set_multiple_start(&cpuhw->state, hwc->config_base); - /* Function cf_diag_enable() starts the counter sets. */ -} - -static void cf_diag_stop(struct perf_event *event, int flags) -{ - struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); - struct cf_diag_csd *csd = this_cpu_ptr(&cf_diag_csd); - struct hw_perf_event *hwc = &event->hw; - - debug_sprintf_event(cf_diag_dbg, 5, - "%s event %p cpu %d flags %#x hwc-state %#x\n", - __func__, event, event->cpu, flags, hwc->state); - - /* Deactivate all counter sets */ - ctr_set_multiple_stop(&cpuhw->state, hwc->config_base); - local64_inc(&event->count); - csd->used = cf_diag_getctr(csd->data, sizeof(csd->data), - event->hw.config_base); - if (cf_diag_diffctr(csd, event->hw.config_base)) - cf_diag_push_sample(event, csd); - hwc->state |= PERF_HES_STOPPED; -} - -static int cf_diag_add(struct perf_event *event, int flags) -{ - struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); - int err = 0; - - debug_sprintf_event(cf_diag_dbg, 5, - "%s event %p cpu %d flags %#x cpuhw %p\n", - __func__, event, event->cpu, flags, cpuhw); - - if (cpuhw->flags & PMU_F_IN_USE) { - err = -EAGAIN; - goto out; - } - - event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED; - - cpuhw->flags |= PMU_F_IN_USE; - if (flags & PERF_EF_START) - cf_diag_start(event, PERF_EF_RELOAD); -out: - debug_sprintf_event(cf_diag_dbg, 5, "%s err %d\n", __func__, err); - return err; -} - -static void cf_diag_del(struct perf_event *event, int flags) -{ - struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); - - debug_sprintf_event(cf_diag_dbg, 5, - "%s event %p cpu %d flags %#x\n", - __func__, event, event->cpu, flags); - - cf_diag_stop(event, PERF_EF_UPDATE); - ctr_set_multiple_stop(&cpuhw->state, event->hw.config_base); - ctr_set_multiple_disable(&cpuhw->state, event->hw.config_base); - cpuhw->flags &= ~PMU_F_IN_USE; -} - -/* Default counter set events and format attribute groups */ - -CPUMF_EVENT_ATTR(CF_DIAG, CF_DIAG, PERF_EVENT_CPUM_CF_DIAG); - -static struct attribute *cf_diag_events_attr[] = { - CPUMF_EVENT_PTR(CF_DIAG, CF_DIAG), - NULL, -}; - -PMU_FORMAT_ATTR(event, "config:0-63"); - -static struct attribute *cf_diag_format_attr[] = { - &format_attr_event.attr, - NULL, -}; - -static struct attribute_group cf_diag_events_group = { - .name = "events", - .attrs = cf_diag_events_attr, -}; -static struct attribute_group cf_diag_format_group = { - .name = "format", - .attrs = cf_diag_format_attr, -}; -static const struct attribute_group *cf_diag_attr_groups[] = { - &cf_diag_events_group, - &cf_diag_format_group, - NULL, -}; - -/* Performance monitoring unit for s390x */ -static struct pmu cf_diag = { - .task_ctx_nr = perf_sw_context, - .pmu_enable = cf_diag_enable, - .pmu_disable = cf_diag_disable, - .event_init = cf_diag_event_init, - .add = cf_diag_add, - .del = cf_diag_del, - .start = cf_diag_start, - .stop = cf_diag_stop, - .read = cf_diag_read, - - .attr_groups = cf_diag_attr_groups -}; - -/* Get the CPU speed, try sampling facility first and CPU attributes second. */ -static void cf_diag_get_cpu_speed(void) -{ - if (cpum_sf_avail()) { /* Sampling facility first */ - struct hws_qsi_info_block si; - - memset(&si, 0, sizeof(si)); - if (!qsi(&si)) { - cf_diag_cpu_speed = si.cpu_speed; - return; - } - } - - if (test_facility(34)) { /* CPU speed extract static part */ - unsigned long mhz = __ecag(ECAG_CPU_ATTRIBUTE, 0); - - if (mhz != -1UL) - cf_diag_cpu_speed = mhz & 0xffffffff; - } -} - -/* Code to create device and file I/O operations */ -static atomic_t ctrset_opencnt = ATOMIC_INIT(0); /* Excl. access */ - -static int cf_diag_open(struct inode *inode, struct file *file) -{ - int err = 0; - - if (!capable(CAP_SYS_ADMIN)) - return -EPERM; - if (atomic_xchg(&ctrset_opencnt, 1)) - return -EBUSY; - - /* Avoid concurrent access with perf_event_open() system call */ - mutex_lock(&cf_diag_reserve_mutex); - if (atomic_read(&cf_diag_events) || __kernel_cpumcf_begin()) - err = -EBUSY; - mutex_unlock(&cf_diag_reserve_mutex); - if (err) { - atomic_set(&ctrset_opencnt, 0); - return err; - } - file->private_data = NULL; - debug_sprintf_event(cf_diag_dbg, 2, "%s\n", __func__); - /* nonseekable_open() never fails */ - return nonseekable_open(inode, file); -} - -/* Variables for ioctl() interface support */ -static DEFINE_MUTEX(cf_diag_ctrset_mutex); -static struct cf_diag_ctrset { - unsigned long ctrset; /* Bit mask of counter set to read */ - cpumask_t mask; /* CPU mask to read from */ -} cf_diag_ctrset; - -static void cf_diag_ctrset_clear(void) -{ - cpumask_clear(&cf_diag_ctrset.mask); - cf_diag_ctrset.ctrset = 0; -} - -static void cf_diag_release_cpu(void *p) -{ - struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); - - debug_sprintf_event(cf_diag_dbg, 3, "%s cpu %d\n", __func__, - smp_processor_id()); - lcctl(0); /* Reset counter sets */ - cpuhw->state = 0; /* Save state in CPU hardware state */ -} - -/* Release function is also called when application gets terminated without - * doing a proper ioctl(..., S390_HWCTR_STOP, ...) command. - * Since only one application is allowed to open the device, simple stop all - * CPU counter sets. - */ -static int cf_diag_release(struct inode *inode, struct file *file) -{ - on_each_cpu(cf_diag_release_cpu, NULL, 1); - cf_diag_ctrset_clear(); - atomic_set(&ctrset_opencnt, 0); - __kernel_cpumcf_end(); - debug_sprintf_event(cf_diag_dbg, 2, "%s\n", __func__); - return 0; -} - -struct cf_diag_call_on_cpu_parm { /* Parm struct for smp_call_on_cpu */ - unsigned int sets; /* Counter set bit mask */ - atomic_t cpus_ack; /* # CPUs successfully executed func */ -}; - -static int cf_diag_all_copy(unsigned long arg, cpumask_t *mask) -{ - struct s390_ctrset_read __user *ctrset_read; - unsigned int cpu, cpus, rc; - void __user *uptr; - - ctrset_read = (struct s390_ctrset_read __user *)arg; - uptr = ctrset_read->data; - for_each_cpu(cpu, mask) { - struct cf_diag_csd *csd = per_cpu_ptr(&cf_diag_csd, cpu); - struct s390_ctrset_cpudata __user *ctrset_cpudata; - - ctrset_cpudata = uptr; - debug_sprintf_event(cf_diag_dbg, 5, "%s cpu %d used %zd\n", - __func__, cpu, csd->used); - rc = put_user(cpu, &ctrset_cpudata->cpu_nr); - rc |= put_user(csd->sets, &ctrset_cpudata->no_sets); - rc |= copy_to_user(ctrset_cpudata->data, csd->data, csd->used); - if (rc) - return -EFAULT; - uptr += sizeof(struct s390_ctrset_cpudata) + csd->used; - cond_resched(); - } - cpus = cpumask_weight(mask); - if (put_user(cpus, &ctrset_read->no_cpus)) - return -EFAULT; - debug_sprintf_event(cf_diag_dbg, 5, "%s copied %ld\n", - __func__, uptr - (void __user *)ctrset_read->data); - return 0; -} - -static size_t cf_diag_cpuset_read(struct s390_ctrset_setdata *p, int ctrset, - int ctrset_size, size_t room) -{ - size_t need = 0; - int rc = -1; - - need = sizeof(*p) + sizeof(u64) * ctrset_size; - debug_sprintf_event(cf_diag_dbg, 5, - "%s room %zd need %zd set %#x set_size %d\n", - __func__, room, need, ctrset, ctrset_size); - if (need <= room) { - p->set = cpumf_ctr_ctl[ctrset]; - p->no_cnts = ctrset_size; - rc = ctr_stcctm(ctrset, ctrset_size, (u64 *)p->cv); - if (rc == 3) /* Nothing stored */ - need = 0; - } - debug_sprintf_event(cf_diag_dbg, 5, "%s need %zd rc %d\n", __func__, - need, rc); - return need; -} - -/* Read all counter sets. Since the perf_event_open() system call with - * event cpum_cf_diag/.../ is blocked when this interface is active, reuse - * the perf_event_open() data buffer to store the counter sets. - */ -static void cf_diag_cpu_read(void *parm) -{ - struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); - struct cf_diag_csd *csd = this_cpu_ptr(&cf_diag_csd); - struct cf_diag_call_on_cpu_parm *p = parm; - int set, set_size; - size_t space; - - debug_sprintf_event(cf_diag_dbg, 5, - "%s new %#x flags %#x state %#llx\n", - __func__, p->sets, cpuhw->flags, - cpuhw->state); - /* No data saved yet */ - csd->used = 0; - csd->sets = 0; - memset(csd->data, 0, sizeof(csd->data)); - - /* Scan the counter sets */ - for (set = CPUMF_CTR_SET_BASIC; set < CPUMF_CTR_SET_MAX; ++set) { - struct s390_ctrset_setdata *sp = (void *)csd->data + csd->used; - - if (!(p->sets & cpumf_ctr_ctl[set])) - continue; /* Counter set not in list */ - set_size = cpum_cf_ctrset_size(set, &cpuhw->info); - space = sizeof(csd->data) - csd->used; - space = cf_diag_cpuset_read(sp, set, set_size, space); - if (space) { - csd->used += space; - csd->sets += 1; - } - debug_sprintf_event(cf_diag_dbg, 5, "%s sp %px space %zd\n", - __func__, sp, space); - } - debug_sprintf_event(cf_diag_dbg, 5, "%s sets %d used %zd\n", __func__, - csd->sets, csd->used); -} - -static int cf_diag_all_read(unsigned long arg) -{ - struct cf_diag_call_on_cpu_parm p; - cpumask_var_t mask; - int rc; - - debug_sprintf_event(cf_diag_dbg, 5, "%s\n", __func__); - if (!alloc_cpumask_var(&mask, GFP_KERNEL)) - return -ENOMEM; - - p.sets = cf_diag_ctrset.ctrset; - cpumask_and(mask, &cf_diag_ctrset.mask, cpu_online_mask); - on_each_cpu_mask(mask, cf_diag_cpu_read, &p, 1); - rc = cf_diag_all_copy(arg, mask); - free_cpumask_var(mask); - debug_sprintf_event(cf_diag_dbg, 5, "%s rc %d\n", __func__, rc); - return rc; -} - -/* Stop all counter sets via ioctl interface */ -static void cf_diag_ioctl_off(void *parm) -{ - struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); - struct cf_diag_call_on_cpu_parm *p = parm; - int rc; - - debug_sprintf_event(cf_diag_dbg, 5, - "%s new %#x flags %#x state %#llx\n", - __func__, p->sets, cpuhw->flags, - cpuhw->state); - - ctr_set_multiple_disable(&cpuhw->state, p->sets); - ctr_set_multiple_stop(&cpuhw->state, p->sets); - rc = lcctl(cpuhw->state); /* Stop counter sets */ - if (!cpuhw->state) - cpuhw->flags &= ~PMU_F_IN_USE; - debug_sprintf_event(cf_diag_dbg, 5, - "%s rc %d flags %#x state %#llx\n", __func__, - rc, cpuhw->flags, cpuhw->state); -} - -/* Start counter sets on particular CPU */ -static void cf_diag_ioctl_on(void *parm) -{ - struct cpu_cf_events *cpuhw = this_cpu_ptr(&cpu_cf_events); - struct cf_diag_call_on_cpu_parm *p = parm; - int rc; - - debug_sprintf_event(cf_diag_dbg, 5, - "%s new %#x flags %#x state %#llx\n", - __func__, p->sets, cpuhw->flags, - cpuhw->state); - - if (!(cpuhw->flags & PMU_F_IN_USE)) - cpuhw->state = 0; - cpuhw->flags |= PMU_F_IN_USE; - rc = lcctl(cpuhw->state); /* Reset unused counter sets */ - ctr_set_multiple_enable(&cpuhw->state, p->sets); - ctr_set_multiple_start(&cpuhw->state, p->sets); - rc |= lcctl(cpuhw->state); /* Start counter sets */ - if (!rc) - atomic_inc(&p->cpus_ack); - debug_sprintf_event(cf_diag_dbg, 5, "%s rc %d state %#llx\n", - __func__, rc, cpuhw->state); -} - -static int cf_diag_all_stop(void) -{ - struct cf_diag_call_on_cpu_parm p = { - .sets = cf_diag_ctrset.ctrset, - }; - cpumask_var_t mask; - - if (!alloc_cpumask_var(&mask, GFP_KERNEL)) - return -ENOMEM; - cpumask_and(mask, &cf_diag_ctrset.mask, cpu_online_mask); - on_each_cpu_mask(mask, cf_diag_ioctl_off, &p, 1); - free_cpumask_var(mask); - return 0; -} - -static int cf_diag_all_start(void) -{ - struct cf_diag_call_on_cpu_parm p = { - .sets = cf_diag_ctrset.ctrset, - .cpus_ack = ATOMIC_INIT(0), - }; - cpumask_var_t mask; - int rc = 0; - - if (!alloc_cpumask_var(&mask, GFP_KERNEL)) - return -ENOMEM; - cpumask_and(mask, &cf_diag_ctrset.mask, cpu_online_mask); - on_each_cpu_mask(mask, cf_diag_ioctl_on, &p, 1); - if (atomic_read(&p.cpus_ack) != cpumask_weight(mask)) { - on_each_cpu_mask(mask, cf_diag_ioctl_off, &p, 1); - rc = -EIO; - } - free_cpumask_var(mask); - return rc; -} - -/* Return the maximum required space for all possible CPUs in case one - * CPU will be onlined during the START, READ, STOP cycles. - * To find out the size of the counter sets, any one CPU will do. They - * all have the same counter sets. - */ -static size_t cf_diag_needspace(unsigned int sets) -{ - struct cpu_cf_events *cpuhw = get_cpu_ptr(&cpu_cf_events); - size_t bytes = 0; - int i; - - for (i = CPUMF_CTR_SET_BASIC; i < CPUMF_CTR_SET_MAX; ++i) { - if (!(sets & cpumf_ctr_ctl[i])) - continue; - bytes += cpum_cf_ctrset_size(i, &cpuhw->info) * sizeof(u64) + - sizeof(((struct s390_ctrset_setdata *)0)->set) + - sizeof(((struct s390_ctrset_setdata *)0)->no_cnts); - } - bytes = sizeof(((struct s390_ctrset_read *)0)->no_cpus) + nr_cpu_ids * - (bytes + sizeof(((struct s390_ctrset_cpudata *)0)->cpu_nr) + - sizeof(((struct s390_ctrset_cpudata *)0)->no_sets)); - debug_sprintf_event(cf_diag_dbg, 5, "%s bytes %ld\n", __func__, - bytes); - put_cpu_ptr(&cpu_cf_events); - return bytes; -} - -static long cf_diag_ioctl_read(unsigned long arg) -{ - struct s390_ctrset_read read; - int ret = 0; - - debug_sprintf_event(cf_diag_dbg, 5, "%s\n", __func__); - if (copy_from_user(&read, (char __user *)arg, sizeof(read))) - return -EFAULT; - ret = cf_diag_all_read(arg); - debug_sprintf_event(cf_diag_dbg, 5, "%s ret %d\n", __func__, ret); - return ret; -} - -static long cf_diag_ioctl_stop(void) -{ - int ret; - - debug_sprintf_event(cf_diag_dbg, 5, "%s\n", __func__); - ret = cf_diag_all_stop(); - cf_diag_ctrset_clear(); - debug_sprintf_event(cf_diag_dbg, 5, "%s ret %d\n", __func__, ret); - return ret; -} - -static long cf_diag_ioctl_start(unsigned long arg) -{ - struct s390_ctrset_start __user *ustart; - struct s390_ctrset_start start; - void __user *umask; - unsigned int len; - int ret = 0; - size_t need; - - if (cf_diag_ctrset.ctrset) - return -EBUSY; - ustart = (struct s390_ctrset_start __user *)arg; - if (copy_from_user(&start, ustart, sizeof(start))) - return -EFAULT; - if (start.version != S390_HWCTR_START_VERSION) - return -EINVAL; - if (start.counter_sets & ~(cpumf_ctr_ctl[CPUMF_CTR_SET_BASIC] | - cpumf_ctr_ctl[CPUMF_CTR_SET_USER] | - cpumf_ctr_ctl[CPUMF_CTR_SET_CRYPTO] | - cpumf_ctr_ctl[CPUMF_CTR_SET_EXT] | - cpumf_ctr_ctl[CPUMF_CTR_SET_MT_DIAG])) - return -EINVAL; /* Invalid counter set */ - if (!start.counter_sets) - return -EINVAL; /* No counter set at all? */ - cpumask_clear(&cf_diag_ctrset.mask); - len = min_t(u64, start.cpumask_len, cpumask_size()); - umask = (void __user *)start.cpumask; - if (copy_from_user(&cf_diag_ctrset.mask, umask, len)) - return -EFAULT; - if (cpumask_empty(&cf_diag_ctrset.mask)) - return -EINVAL; - need = cf_diag_needspace(start.counter_sets); - if (put_user(need, &ustart->data_bytes)) - ret = -EFAULT; - if (ret) - goto out; - cf_diag_ctrset.ctrset = start.counter_sets; - ret = cf_diag_all_start(); -out: - if (ret) - cf_diag_ctrset_clear(); - debug_sprintf_event(cf_diag_dbg, 2, "%s sets %#lx need %ld ret %d\n", - __func__, cf_diag_ctrset.ctrset, need, ret); - return ret; -} - -static long cf_diag_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) -{ - int ret; - - debug_sprintf_event(cf_diag_dbg, 2, "%s cmd %#x arg %lx\n", __func__, - cmd, arg); - get_online_cpus(); - mutex_lock(&cf_diag_ctrset_mutex); - switch (cmd) { - case S390_HWCTR_START: - ret = cf_diag_ioctl_start(arg); - break; - case S390_HWCTR_STOP: - ret = cf_diag_ioctl_stop(); - break; - case S390_HWCTR_READ: - ret = cf_diag_ioctl_read(arg); - break; - default: - ret = -ENOTTY; - break; - } - mutex_unlock(&cf_diag_ctrset_mutex); - put_online_cpus(); - debug_sprintf_event(cf_diag_dbg, 2, "%s ret %d\n", __func__, ret); - return ret; -} - -static const struct file_operations cf_diag_fops = { - .owner = THIS_MODULE, - .open = cf_diag_open, - .release = cf_diag_release, - .unlocked_ioctl = cf_diag_ioctl, - .compat_ioctl = cf_diag_ioctl, - .llseek = no_llseek -}; - -static struct miscdevice cf_diag_dev = { - .name = S390_HWCTR_DEVICE, - .minor = MISC_DYNAMIC_MINOR, - .fops = &cf_diag_fops, -}; - -static int cf_diag_online_cpu(unsigned int cpu) -{ - struct cf_diag_call_on_cpu_parm p; - - mutex_lock(&cf_diag_ctrset_mutex); - if (!cf_diag_ctrset.ctrset) - goto out; - p.sets = cf_diag_ctrset.ctrset; - cf_diag_ioctl_on(&p); -out: - mutex_unlock(&cf_diag_ctrset_mutex); - return 0; -} - -static int cf_diag_offline_cpu(unsigned int cpu) -{ - struct cf_diag_call_on_cpu_parm p; - - mutex_lock(&cf_diag_ctrset_mutex); - if (!cf_diag_ctrset.ctrset) - goto out; - p.sets = cf_diag_ctrset.ctrset; - cf_diag_ioctl_off(&p); -out: - mutex_unlock(&cf_diag_ctrset_mutex); - return 0; -} - -/* Initialize the counter set PMU to generate complete counter set data as - * event raw data. This relies on the CPU Measurement Counter Facility device - * already being loaded and initialized. - */ -static int __init cf_diag_init(void) -{ - struct cpumf_ctr_info info; - size_t need; - int rc; - - if (!kernel_cpumcf_avail() || !stccm_avail() || qctri(&info)) - return -ENODEV; - cf_diag_get_cpu_speed(); - - /* Make sure the counter set data fits into predefined buffer. */ - need = cf_diag_ctrset_maxsize(&info); - if (need > sizeof(((struct cf_diag_csd *)0)->start)) { - pr_err("Insufficient memory for PMU(cpum_cf_diag) need=%zu\n", - need); - return -ENOMEM; - } - - rc = misc_register(&cf_diag_dev); - if (rc) { - pr_err("Registration of /dev/" S390_HWCTR_DEVICE - "failed rc=%d\n", rc); - goto out; - } - - /* Setup s390dbf facility */ - cf_diag_dbg = debug_register(KMSG_COMPONENT, 2, 1, 128); - if (!cf_diag_dbg) { - pr_err("Registration of s390dbf(cpum_cf_diag) failed\n"); - rc = -ENOMEM; - goto out_dbf; - } - debug_register_view(cf_diag_dbg, &debug_sprintf_view); - - rc = perf_pmu_register(&cf_diag, "cpum_cf_diag", -1); - if (rc) { - pr_err("Registration of PMU(cpum_cf_diag) failed with rc=%i\n", - rc); - goto out_perf; - } - rc = cpuhp_setup_state_nocalls(CPUHP_AP_PERF_S390_CFD_ONLINE, - "perf/s390/cfd:online", - cf_diag_online_cpu, cf_diag_offline_cpu); - if (!rc) - goto out; - - pr_err("Registration of CPUHP_AP_PERF_S390_CFD_ONLINE failed rc=%i\n", - rc); - perf_pmu_unregister(&cf_diag); -out_perf: - debug_unregister_view(cf_diag_dbg, &debug_sprintf_view); - debug_unregister(cf_diag_dbg); -out_dbf: - misc_deregister(&cf_diag_dev); -out: - return rc; -} -device_initcall(cf_diag_init); diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c index 7ae5dde9c54d..350e94d0cac2 100644 --- a/arch/s390/kernel/process.c +++ b/arch/s390/kernel/process.c @@ -166,6 +166,12 @@ int copy_thread(unsigned long clone_flags, unsigned long new_stackp, p->thread.acrs[1] = (unsigned int)tls; } } + /* + * s390 stores the svc return address in arch_data when calling + * sigreturn()/restart_syscall() via vdso. 1 means no valid address + * stored. + */ + p->restart_block.arch_data = 1; return 0; } diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c index b58ee83f30e3..ff0f9e838916 100644 --- a/arch/s390/kernel/setup.c +++ b/arch/s390/kernel/setup.c @@ -354,7 +354,7 @@ void __init arch_call_rest_init(void) set_task_stack_end_magic(current); stack += STACK_INIT_OFFSET; S390_lowcore.kernel_stack = stack; - CALL_ON_STACK_NORETURN(rest_init, stack); + call_on_stack_noreturn(rest_init, stack); } static void __init setup_lowcore_dat_off(void) @@ -442,6 +442,7 @@ static void __init setup_lowcore_dat_off(void) lc->br_r1_trampoline = 0x07f1; /* br %r1 */ lc->return_lpswe = gen_lpswe(__LC_RETURN_PSW); lc->return_mcck_lpswe = gen_lpswe(__LC_RETURN_MCCK_PSW); + lc->preempt_count = PREEMPT_DISABLED; set_prefix((u32)(unsigned long) lc); lowcore_ptr[0] = lc; @@ -1028,10 +1029,7 @@ void __init setup_arch(char **cmdline_p) ROOT_DEV = Root_RAM0; - init_mm.start_code = (unsigned long) _text; - init_mm.end_code = (unsigned long) _etext; - init_mm.end_data = (unsigned long) _edata; - init_mm.brk = (unsigned long) _end; + setup_initial_init_mm(_text, _etext, _edata, _end); if (IS_ENABLED(CONFIG_EXPOLINE_AUTO)) nospec_auto_detect(); diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c index 080e7aed181f..78ef53b29958 100644 --- a/arch/s390/kernel/signal.c +++ b/arch/s390/kernel/signal.c @@ -32,6 +32,7 @@ #include <linux/uaccess.h> #include <asm/lowcore.h> #include <asm/switch_to.h> +#include <asm/vdso.h> #include "entry.h" /* @@ -171,7 +172,6 @@ static int restore_sigregs(struct pt_regs *regs, _sigregs __user *sregs) fpregs_load(&user_sregs.fpregs, ¤t->thread.fpu); clear_pt_regs_flag(regs, PIF_SYSCALL); /* No longer in a system call */ - clear_pt_regs_flag(regs, PIF_SYSCALL_RESTART); return 0; } @@ -334,15 +334,10 @@ static int setup_frame(int sig, struct k_sigaction *ka, /* Set up to return from userspace. If provided, use a stub already in userspace. */ - if (ka->sa.sa_flags & SA_RESTORER) { + if (ka->sa.sa_flags & SA_RESTORER) restorer = (unsigned long) ka->sa.sa_restorer; - } else { - /* Signal frame without vector registers are short ! */ - __u16 __user *svc = (void __user *) frame + frame_size - 2; - if (__put_user(S390_SYSCALL_OPCODE | __NR_sigreturn, svc)) - return -EFAULT; - restorer = (unsigned long) svc; - } + else + restorer = VDSO64_SYMBOL(current, sigreturn); /* Set up registers for signal handler */ regs->gprs[14] = restorer; @@ -397,14 +392,10 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, /* Set up to return from userspace. If provided, use a stub already in userspace. */ - if (ksig->ka.sa.sa_flags & SA_RESTORER) { + if (ksig->ka.sa.sa_flags & SA_RESTORER) restorer = (unsigned long) ksig->ka.sa.sa_restorer; - } else { - __u16 __user *svc = &frame->svc_insn; - if (__put_user(S390_SYSCALL_OPCODE | __NR_rt_sigreturn, svc)) - return -EFAULT; - restorer = (unsigned long) svc; - } + else + restorer = VDSO64_SYMBOL(current, rt_sigreturn); /* Create siginfo on the signal stack */ if (copy_siginfo_to_user(&frame->info, &ksig->info)) @@ -501,7 +492,7 @@ void arch_do_signal_or_restart(struct pt_regs *regs, bool has_signal) } /* No longer in a system call */ clear_pt_regs_flag(regs, PIF_SYSCALL); - clear_pt_regs_flag(regs, PIF_SYSCALL_RESTART); + rseq_signal_deliver(&ksig, regs); if (is_compat_task()) handle_signal32(&ksig, oldset, regs); @@ -517,14 +508,20 @@ void arch_do_signal_or_restart(struct pt_regs *regs, bool has_signal) switch (regs->gprs[2]) { case -ERESTART_RESTARTBLOCK: /* Restart with sys_restart_syscall */ - regs->int_code = __NR_restart_syscall; - fallthrough; + regs->gprs[2] = regs->orig_gpr2; + current->restart_block.arch_data = regs->psw.addr; + if (is_compat_task()) + regs->psw.addr = VDSO32_SYMBOL(current, restart_syscall); + else + regs->psw.addr = VDSO64_SYMBOL(current, restart_syscall); + if (test_thread_flag(TIF_SINGLE_STEP)) + clear_thread_flag(TIF_PER_TRAP); + break; case -ERESTARTNOHAND: case -ERESTARTSYS: case -ERESTARTNOINTR: - /* Restart system call with magic TIF bit. */ regs->gprs[2] = regs->orig_gpr2; - set_pt_regs_flag(regs, PIF_SYSCALL_RESTART); + regs->psw.addr = __rewind_psw(regs->psw, regs->int_code >> 16); if (test_thread_flag(TIF_SINGLE_STEP)) clear_thread_flag(TIF_PER_TRAP); break; diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index ff42d3aa0f00..8984711f72ed 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -210,6 +210,7 @@ static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) lc->br_r1_trampoline = 0x07f1; /* br %r1 */ lc->return_lpswe = gen_lpswe(__LC_RETURN_PSW); lc->return_mcck_lpswe = gen_lpswe(__LC_RETURN_MCCK_PSW); + lc->preempt_count = PREEMPT_DISABLED; if (nmi_alloc_per_cpu(lc)) goto out; lowcore_ptr[cpu] = lc; @@ -300,24 +301,28 @@ static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data) pcpu_sigp_retry(pcpu, SIGP_RESTART, 0); } +typedef void (pcpu_delegate_fn)(void *); + /* * Call function via PSW restart on pcpu and stop the current cpu. */ -static void __pcpu_delegate(void (*func)(void*), void *data) +static void __pcpu_delegate(pcpu_delegate_fn *func, void *data) { func(data); /* should not return */ } static void __no_sanitize_address pcpu_delegate(struct pcpu *pcpu, - void (*func)(void *), + pcpu_delegate_fn *func, void *data, unsigned long stack) { struct lowcore *lc = lowcore_ptr[pcpu - pcpu_devices]; unsigned long source_cpu = stap(); __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); - if (pcpu->address == source_cpu) - CALL_ON_STACK(__pcpu_delegate, stack, 2, func, data); + if (pcpu->address == source_cpu) { + call_on_stack(2, stack, void, __pcpu_delegate, + pcpu_delegate_fn *, func, void *, data); + } /* Stop target cpu (if func returns this stops the current cpu). */ pcpu_sigp_retry(pcpu, SIGP_STOP, 0); /* Restart func on the target cpu and stop the current cpu. */ @@ -898,7 +903,7 @@ static void __no_sanitize_address smp_start_secondary(void *cpuvoid) S390_lowcore.restart_source = -1UL; __ctl_load(S390_lowcore.cregs_save_area, 0, 15); __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); - CALL_ON_STACK_NORETURN(smp_init_secondary, S390_lowcore.kernel_stack); + call_on_stack_noreturn(smp_init_secondary, S390_lowcore.kernel_stack); } /* Upping and downing of CPUs */ diff --git a/arch/s390/kernel/syscall.c b/arch/s390/kernel/syscall.c index 76f7916cc30f..8fe2d23b64f4 100644 --- a/arch/s390/kernel/syscall.c +++ b/arch/s390/kernel/syscall.c @@ -108,7 +108,7 @@ SYSCALL_DEFINE0(ni_syscall) return -ENOSYS; } -void do_syscall(struct pt_regs *regs) +static void do_syscall(struct pt_regs *regs) { unsigned long nr; @@ -121,6 +121,10 @@ void do_syscall(struct pt_regs *regs) regs->gprs[2] = nr; + if (nr == __NR_restart_syscall && !(current->restart_block.arch_data & 1)) { + regs->psw.addr = current->restart_block.arch_data; + current->restart_block.arch_data = 1; + } nr = syscall_enter_from_user_mode_work(regs, nr); /* @@ -130,13 +134,16 @@ void do_syscall(struct pt_regs *regs) * work, the ptrace code sets PIF_SYSCALL_RET_SET, which is checked here * and if set, the syscall will be skipped. */ - if (!test_pt_regs_flag(regs, PIF_SYSCALL_RET_SET)) { - regs->gprs[2] = -ENOSYS; - if (likely(nr < NR_syscalls)) - regs->gprs[2] = current->thread.sys_call_table[nr](regs); - } else { - clear_pt_regs_flag(regs, PIF_SYSCALL_RET_SET); - } + + if (unlikely(test_and_clear_pt_regs_flag(regs, PIF_SYSCALL_RET_SET))) + goto out; + regs->gprs[2] = -ENOSYS; + if (likely(nr >= NR_syscalls)) + goto out; + do { + regs->gprs[2] = current->thread.sys_call_table[nr](regs); + } while (test_and_clear_pt_regs_flag(regs, PIF_EXECVE_PGSTE_RESTART)); +out: syscall_exit_to_user_mode_work(regs); } @@ -154,13 +161,8 @@ void noinstr __do_syscall(struct pt_regs *regs, int per_trap) if (per_trap) set_thread_flag(TIF_PER_TRAP); - for (;;) { - regs->flags = 0; - set_pt_regs_flag(regs, PIF_SYSCALL); - do_syscall(regs); - if (!test_pt_regs_flag(regs, PIF_SYSCALL_RESTART)) - break; - local_irq_enable(); - } + regs->flags = 0; + set_pt_regs_flag(regs, PIF_SYSCALL); + do_syscall(regs); exit_to_user_mode(); } diff --git a/arch/s390/kernel/traps.c b/arch/s390/kernel/traps.c index 019c5748b607..76947275fe8b 100644 --- a/arch/s390/kernel/traps.c +++ b/arch/s390/kernel/traps.c @@ -277,6 +277,8 @@ static void __init test_monitor_call(void) { int val = 1; + if (!IS_ENABLED(CONFIG_BUG)) + return; asm volatile( " mc 0,0\n" "0: xgr %0,%0\n" @@ -299,10 +301,9 @@ static void (*pgm_check_table[128])(struct pt_regs *regs); void noinstr __do_pgm_check(struct pt_regs *regs) { unsigned long last_break = S390_lowcore.breaking_event_addr; - unsigned int trapnr, syscall_redirect = 0; + unsigned int trapnr; irqentry_state_t state; - add_random_kstack_offset(); regs->int_code = *(u32 *)&S390_lowcore.pgm_ilc; regs->int_parm_long = S390_lowcore.trans_exc_code; @@ -344,18 +345,9 @@ void noinstr __do_pgm_check(struct pt_regs *regs) trapnr = regs->int_code & PGM_INT_CODE_MASK; if (trapnr) pgm_check_table[trapnr](regs); - syscall_redirect = user_mode(regs) && test_pt_regs_flag(regs, PIF_SYSCALL); out: local_irq_disable(); irqentry_exit(regs, state); - - if (syscall_redirect) { - enter_from_user_mode(regs); - local_irq_enable(); - regs->orig_gpr2 = regs->gprs[2]; - do_syscall(regs); - exit_to_user_mode(); - } } /* diff --git a/arch/s390/kernel/uprobes.c b/arch/s390/kernel/uprobes.c index bbf8622bbf5d..bd3ef121c379 100644 --- a/arch/s390/kernel/uprobes.c +++ b/arch/s390/kernel/uprobes.c @@ -126,6 +126,7 @@ int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, case DIE_SSTEP: if (uprobe_post_sstep_notifier(regs)) return NOTIFY_STOP; + break; default: break; } diff --git a/arch/s390/kernel/uv.c b/arch/s390/kernel/uv.c index 6be2167943bb..aeb0a15bcbb7 100644 --- a/arch/s390/kernel/uv.c +++ b/arch/s390/kernel/uv.c @@ -358,6 +358,15 @@ static ssize_t uv_query_facilities(struct kobject *kobj, static struct kobj_attribute uv_query_facilities_attr = __ATTR(facilities, 0444, uv_query_facilities, NULL); +static ssize_t uv_query_feature_indications(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%lx\n", uv_info.uv_feature_indications); +} + +static struct kobj_attribute uv_query_feature_indications_attr = + __ATTR(feature_indications, 0444, uv_query_feature_indications, NULL); + static ssize_t uv_query_max_guest_cpus(struct kobject *kobj, struct kobj_attribute *attr, char *page) { @@ -390,6 +399,7 @@ static struct kobj_attribute uv_query_max_guest_addr_attr = static struct attribute *uv_query_attrs[] = { &uv_query_facilities_attr.attr, + &uv_query_feature_indications_attr.attr, &uv_query_max_guest_cpus_attr.attr, &uv_query_max_guest_vms_attr.attr, &uv_query_max_guest_addr_attr.attr, diff --git a/arch/s390/kernel/vdso.c b/arch/s390/kernel/vdso.c index 8c4e07d533c8..99694260cac9 100644 --- a/arch/s390/kernel/vdso.c +++ b/arch/s390/kernel/vdso.c @@ -20,7 +20,7 @@ #include <asm/vdso.h> extern char vdso64_start[], vdso64_end[]; -static unsigned int vdso_pages; +extern char vdso32_start[], vdso32_end[]; static struct vm_special_mapping vvar_mapping; @@ -37,18 +37,6 @@ enum vvar_pages { VVAR_NR_PAGES, }; -unsigned int __read_mostly vdso_enabled = 1; - -static int __init vdso_setup(char *str) -{ - bool enabled; - - if (!kstrtobool(str, &enabled)) - vdso_enabled = enabled; - return 1; -} -__setup("vdso=", vdso_setup); - #ifdef CONFIG_TIME_NS struct vdso_data *arch_get_vdso_data(void *vvar_page) { @@ -155,7 +143,12 @@ static struct vm_special_mapping vvar_mapping = { .fault = vvar_fault, }; -static struct vm_special_mapping vdso_mapping = { +static struct vm_special_mapping vdso64_mapping = { + .name = "[vdso]", + .mremap = vdso_mremap, +}; + +static struct vm_special_mapping vdso32_mapping = { .name = "[vdso]", .mremap = vdso_mremap, }; @@ -171,16 +164,22 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) { unsigned long vdso_text_len, vdso_mapping_len; unsigned long vvar_start, vdso_text_start; + struct vm_special_mapping *vdso_mapping; struct mm_struct *mm = current->mm; struct vm_area_struct *vma; int rc; BUILD_BUG_ON(VVAR_NR_PAGES != __VVAR_PAGES); - if (!vdso_enabled || is_compat_task()) - return 0; if (mmap_write_lock_killable(mm)) return -EINTR; - vdso_text_len = vdso_pages << PAGE_SHIFT; + + if (is_compat_task()) { + vdso_text_len = vdso32_end - vdso32_start; + vdso_mapping = &vdso32_mapping; + } else { + vdso_text_len = vdso64_end - vdso64_start; + vdso_mapping = &vdso64_mapping; + } vdso_mapping_len = vdso_text_len + VVAR_NR_PAGES * PAGE_SIZE; vvar_start = get_unmapped_area(NULL, 0, vdso_mapping_len, 0, 0); rc = vvar_start; @@ -198,7 +197,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) vma = _install_special_mapping(mm, vdso_text_start, vdso_text_len, VM_READ|VM_EXEC| VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC, - &vdso_mapping); + vdso_mapping); if (IS_ERR(vma)) { do_munmap(mm, vvar_start, PAGE_SIZE, NULL); rc = PTR_ERR(vma); @@ -211,21 +210,25 @@ out: return rc; } -static int __init vdso_init(void) +static struct page ** __init vdso_setup_pages(void *start, void *end) { - struct page **pages; + int pages = (end - start) >> PAGE_SHIFT; + struct page **pagelist; int i; - vdso_pages = (vdso64_end - vdso64_start) >> PAGE_SHIFT; - pages = kcalloc(vdso_pages + 1, sizeof(struct page *), GFP_KERNEL); - if (!pages) { - vdso_enabled = 0; - return -ENOMEM; - } - for (i = 0; i < vdso_pages; i++) - pages[i] = virt_to_page(vdso64_start + i * PAGE_SIZE); - pages[vdso_pages] = NULL; - vdso_mapping.pages = pages; + pagelist = kcalloc(pages + 1, sizeof(struct page *), GFP_KERNEL); + if (!pagelist) + panic("%s: Cannot allocate page list for VDSO", __func__); + for (i = 0; i < pages; i++) + pagelist[i] = virt_to_page(start + i * PAGE_SIZE); + return pagelist; +} + +static int __init vdso_init(void) +{ + vdso64_mapping.pages = vdso_setup_pages(vdso64_start, vdso64_end); + if (IS_ENABLED(CONFIG_COMPAT)) + vdso32_mapping.pages = vdso_setup_pages(vdso32_start, vdso32_end); return 0; } arch_initcall(vdso_init); diff --git a/arch/s390/kernel/vdso32/.gitignore b/arch/s390/kernel/vdso32/.gitignore new file mode 100644 index 000000000000..5167384843b9 --- /dev/null +++ b/arch/s390/kernel/vdso32/.gitignore @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +vdso32.lds diff --git a/arch/s390/kernel/vdso32/Makefile b/arch/s390/kernel/vdso32/Makefile new file mode 100644 index 000000000000..3457dcf10396 --- /dev/null +++ b/arch/s390/kernel/vdso32/Makefile @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0 +# List of files in the vdso + +KCOV_INSTRUMENT := n +ARCH_REL_TYPE_ABS := R_390_COPY|R_390_GLOB_DAT|R_390_JMP_SLOT|R_390_RELATIVE +ARCH_REL_TYPE_ABS += R_390_GOT|R_390_PLT + +include $(srctree)/lib/vdso/Makefile +obj-vdso32 = vdso_user_wrapper-32.o note-32.o + +# Build rules + +targets := $(obj-vdso32) vdso32.so vdso32.so.dbg +obj-vdso32 := $(addprefix $(obj)/, $(obj-vdso32)) + +KBUILD_AFLAGS += -DBUILD_VDSO +KBUILD_CFLAGS += -DBUILD_VDSO -DDISABLE_BRANCH_PROFILING + +KBUILD_AFLAGS_32 := $(filter-out -m64,$(KBUILD_AFLAGS)) +KBUILD_AFLAGS_32 += -m31 -s + +KBUILD_CFLAGS_32 := $(filter-out -m64,$(KBUILD_CFLAGS)) +KBUILD_CFLAGS_32 += -m31 -fPIC -shared -fno-common -fno-builtin + +LDFLAGS_vdso32.so.dbg += -fPIC -shared -nostdlib -soname=linux-vdso32.so.1 \ + --hash-style=both --build-id=sha1 -melf_s390 -T + +$(targets:%=$(obj)/%.dbg): KBUILD_CFLAGS = $(KBUILD_CFLAGS_32) +$(targets:%=$(obj)/%.dbg): KBUILD_AFLAGS = $(KBUILD_AFLAGS_32) + +obj-y += vdso32_wrapper.o +targets += vdso32.lds +CPPFLAGS_vdso32.lds += -P -C -U$(ARCH) + +# Disable gcov profiling, ubsan and kasan for VDSO code +GCOV_PROFILE := n +UBSAN_SANITIZE := n +KASAN_SANITIZE := n + +# Force dependency (incbin is bad) +$(obj)/vdso32_wrapper.o : $(obj)/vdso32.so + +$(obj)/vdso32.so.dbg: $(src)/vdso32.lds $(obj-vdso32) FORCE + $(call if_changed,ld) + +# strip rule for the .so file +$(obj)/%.so: OBJCOPYFLAGS := -S +$(obj)/%.so: $(obj)/%.so.dbg FORCE + $(call if_changed,objcopy) + +$(obj-vdso32): %-32.o: %.S FORCE + $(call if_changed_dep,vdso32as) + +# actual build commands +quiet_cmd_vdso32as = VDSO32A $@ + cmd_vdso32as = $(CC) $(a_flags) -c -o $@ $< +quiet_cmd_vdso32cc = VDSO32C $@ + cmd_vdso32cc = $(CC) $(c_flags) -c -o $@ $< + +# install commands for the unstripped file +quiet_cmd_vdso_install = INSTALL $@ + cmd_vdso_install = cp $(obj)/$@.dbg $(MODLIB)/vdso/$@ + +vdso32.so: $(obj)/vdso32.so.dbg + @mkdir -p $(MODLIB)/vdso + $(call cmd,vdso_install) + +vdso_install: vdso32.so + +# Generate VDSO offsets using helper script +gen-vdsosym := $(srctree)/$(src)/gen_vdso_offsets.sh +quiet_cmd_vdsosym = VDSOSYM $@ + cmd_vdsosym = $(NM) $< | $(gen-vdsosym) | LC_ALL=C sort > $@ + +include/generated/vdso32-offsets.h: $(obj)/vdso32.so.dbg FORCE + $(call if_changed,vdsosym) diff --git a/arch/s390/kernel/vdso32/gen_vdso_offsets.sh b/arch/s390/kernel/vdso32/gen_vdso_offsets.sh new file mode 100755 index 000000000000..9c4f951e227d --- /dev/null +++ b/arch/s390/kernel/vdso32/gen_vdso_offsets.sh @@ -0,0 +1,15 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +# +# Match symbols in the DSO that look like VDSO_*; produce a header file +# of constant offsets into the shared object. +# +# Doing this inside the Makefile will break the $(filter-out) function, +# causing Kbuild to rebuild the vdso-offsets header file every time. +# +# Inspired by arm64 version. +# + +LC_ALL=C +sed -n 's/\([0-9a-f]*\) . __kernel_compat_\(.*\)/\#define vdso32_offset_\2\t0x\1/p' diff --git a/arch/s390/kernel/vdso32/note.S b/arch/s390/kernel/vdso32/note.S new file mode 100644 index 000000000000..db19d0680a0a --- /dev/null +++ b/arch/s390/kernel/vdso32/note.S @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This supplies .note.* sections to go into the PT_NOTE inside the vDSO text. + * Here we can supply some information useful to userland. + */ + +#include <linux/uts.h> +#include <linux/version.h> +#include <linux/elfnote.h> + +ELFNOTE_START(Linux, 0, "a") + .long LINUX_VERSION_CODE +ELFNOTE_END diff --git a/arch/s390/kernel/vdso32/vdso32.lds.S b/arch/s390/kernel/vdso32/vdso32.lds.S new file mode 100644 index 000000000000..bff50b6acd6d --- /dev/null +++ b/arch/s390/kernel/vdso32/vdso32.lds.S @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This is the infamous ld script for the 64 bits vdso + * library + */ + +#include <asm/page.h> +#include <asm/vdso.h> + +OUTPUT_FORMAT("elf32-s390", "elf32-s390", "elf32-s390") +OUTPUT_ARCH(s390:31-bit) +ENTRY(_start) + +SECTIONS +{ + PROVIDE(_vdso_data = . - __VVAR_PAGES * PAGE_SIZE); +#ifdef CONFIG_TIME_NS + PROVIDE(_timens_data = _vdso_data + PAGE_SIZE); +#endif + . = VDSO_LBASE + SIZEOF_HEADERS; + + .hash : { *(.hash) } :text + .gnu.hash : { *(.gnu.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + + .note : { *(.note.*) } :text :note + + . = ALIGN(16); + .text : { + *(.text .stub .text.* .gnu.linkonce.t.*) + } :text + PROVIDE(__etext = .); + PROVIDE(_etext = .); + PROVIDE(etext = .); + + /* + * Other stuff is appended to the text segment: + */ + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } + .rodata1 : { *(.rodata1) } + + .dynamic : { *(.dynamic) } :text :dynamic + + .eh_frame_hdr : { *(.eh_frame_hdr) } :text :eh_frame_hdr + .eh_frame : { KEEP (*(.eh_frame)) } :text + .gcc_except_table : { *(.gcc_except_table .gcc_except_table.*) } + + .rela.dyn ALIGN(8) : { *(.rela.dyn) } + .got ALIGN(8) : { *(.got .toc) } + + _end = .; + PROVIDE(end = .); + + /* + * Stabs debugging sections are here too. + */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + /* + * DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the + * beginning of the section so we begin them at 0. + */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } + + /DISCARD/ : { + *(.note.GNU-stack) + *(.branch_lt) + *(.data .data.* .gnu.linkonce.d.* .sdata*) + *(.bss .sbss .dynbss .dynsbss) + } +} + +/* + * Very old versions of ld do not recognize this name token; use the constant. + */ +#define PT_GNU_EH_FRAME 0x6474e550 + +/* + * We must supply the ELF program headers explicitly to get just one + * PT_LOAD segment, and set the flags explicitly to make segments read-only. + */ +PHDRS +{ + text PT_LOAD FILEHDR PHDRS FLAGS(5); /* PF_R|PF_X */ + dynamic PT_DYNAMIC FLAGS(4); /* PF_R */ + note PT_NOTE FLAGS(4); /* PF_R */ + eh_frame_hdr PT_GNU_EH_FRAME; +} + +/* + * This controls what symbols we export from the DSO. + */ +VERSION +{ + VDSO_VERSION_STRING { + global: + /* + * Has to be there for the kernel to find + */ + __kernel_compat_restart_syscall; + __kernel_compat_rt_sigreturn; + __kernel_compat_sigreturn; + local: *; + }; +} diff --git a/arch/s390/kernel/vdso32/vdso32_wrapper.S b/arch/s390/kernel/vdso32/vdso32_wrapper.S new file mode 100644 index 000000000000..de2fb930471a --- /dev/null +++ b/arch/s390/kernel/vdso32/vdso32_wrapper.S @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include <linux/init.h> +#include <linux/linkage.h> +#include <asm/page.h> + + __PAGE_ALIGNED_DATA + + .globl vdso32_start, vdso32_end + .balign PAGE_SIZE +vdso32_start: + .incbin "arch/s390/kernel/vdso32/vdso32.so" + .balign PAGE_SIZE +vdso32_end: + + .previous diff --git a/arch/s390/kernel/vdso32/vdso_user_wrapper.S b/arch/s390/kernel/vdso32/vdso_user_wrapper.S new file mode 100644 index 000000000000..3f42f27f978c --- /dev/null +++ b/arch/s390/kernel/vdso32/vdso_user_wrapper.S @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#include <asm/unistd.h> +#include <asm/dwarf.h> + +.macro vdso_syscall func,syscall + .globl __kernel_compat_\func + .type __kernel_compat_\func,@function + .align 8 +__kernel_compat_\func: + CFI_STARTPROC + svc \syscall + /* Make sure we notice when a syscall returns, which shouldn't happen */ + .word 0 + CFI_ENDPROC + .size __kernel_compat_\func,.-__kernel_compat_\func +.endm + +vdso_syscall restart_syscall,__NR_restart_syscall +vdso_syscall sigreturn,__NR_sigreturn +vdso_syscall rt_sigreturn,__NR_rt_sigreturn diff --git a/arch/s390/kernel/vdso64/Makefile b/arch/s390/kernel/vdso64/Makefile index a6e0fb6b91d6..2a2092ce19f1 100644 --- a/arch/s390/kernel/vdso64/Makefile +++ b/arch/s390/kernel/vdso64/Makefile @@ -74,3 +74,11 @@ vdso64.so: $(obj)/vdso64.so.dbg $(call cmd,vdso_install) vdso_install: vdso64.so + +# Generate VDSO offsets using helper script +gen-vdsosym := $(srctree)/$(src)/gen_vdso_offsets.sh +quiet_cmd_vdsosym = VDSOSYM $@ + cmd_vdsosym = $(NM) $< | $(gen-vdsosym) | LC_ALL=C sort > $@ + +include/generated/vdso64-offsets.h: $(obj)/vdso64.so.dbg FORCE + $(call if_changed,vdsosym) diff --git a/arch/s390/kernel/vdso64/gen_vdso_offsets.sh b/arch/s390/kernel/vdso64/gen_vdso_offsets.sh new file mode 100755 index 000000000000..37f05cb38dad --- /dev/null +++ b/arch/s390/kernel/vdso64/gen_vdso_offsets.sh @@ -0,0 +1,15 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +# +# Match symbols in the DSO that look like VDSO_*; produce a header file +# of constant offsets into the shared object. +# +# Doing this inside the Makefile will break the $(filter-out) function, +# causing Kbuild to rebuild the vdso-offsets header file every time. +# +# Inspired by arm64 version. +# + +LC_ALL=C +sed -n 's/\([0-9a-f]*\) . __kernel_\(.*\)/\#define vdso64_offset_\2\t0x\1/p' diff --git a/arch/s390/kernel/vdso64/vdso64.lds.S b/arch/s390/kernel/vdso64/vdso64.lds.S index 518f1ea405f4..d4fb336d747b 100644 --- a/arch/s390/kernel/vdso64/vdso64.lds.S +++ b/arch/s390/kernel/vdso64/vdso64.lds.S @@ -17,7 +17,7 @@ SECTIONS #ifdef CONFIG_TIME_NS PROVIDE(_timens_data = _vdso_data + PAGE_SIZE); #endif - . = VDSO64_LBASE + SIZEOF_HEADERS; + . = VDSO_LBASE + SIZEOF_HEADERS; .hash : { *(.hash) } :text .gnu.hash : { *(.gnu.hash) } @@ -137,6 +137,9 @@ VERSION __kernel_clock_gettime; __kernel_clock_getres; __kernel_getcpu; + __kernel_restart_syscall; + __kernel_rt_sigreturn; + __kernel_sigreturn; local: *; }; } diff --git a/arch/s390/kernel/vdso64/vdso_user_wrapper.S b/arch/s390/kernel/vdso64/vdso_user_wrapper.S index f773505c7e63..97f0c0a669a5 100644 --- a/arch/s390/kernel/vdso64/vdso_user_wrapper.S +++ b/arch/s390/kernel/vdso64/vdso_user_wrapper.S @@ -37,3 +37,20 @@ vdso_func gettimeofday vdso_func clock_getres vdso_func clock_gettime vdso_func getcpu + +.macro vdso_syscall func,syscall + .globl __kernel_\func + .type __kernel_\func,@function + .align 8 +__kernel_\func: + CFI_STARTPROC + svc \syscall + /* Make sure we notice when a syscall returns, which shouldn't happen */ + .word 0 + CFI_ENDPROC + .size __kernel_\func,.-__kernel_\func +.endm + +vdso_syscall restart_syscall,__NR_restart_syscall +vdso_syscall sigreturn,__NR_sigreturn +vdso_syscall rt_sigreturn,__NR_rt_sigreturn diff --git a/arch/s390/kvm/diag.c b/arch/s390/kvm/diag.c index 02c146f9e5cd..807fa9da1e72 100644 --- a/arch/s390/kvm/diag.c +++ b/arch/s390/kvm/diag.c @@ -24,7 +24,7 @@ static int diag_release_pages(struct kvm_vcpu *vcpu) start = vcpu->run->s.regs.gprs[(vcpu->arch.sie_block->ipa & 0xf0) >> 4]; end = vcpu->run->s.regs.gprs[vcpu->arch.sie_block->ipa & 0xf] + PAGE_SIZE; - vcpu->stat.diagnose_10++; + vcpu->stat.instruction_diagnose_10++; if (start & ~PAGE_MASK || end & ~PAGE_MASK || start >= end || start < 2 * PAGE_SIZE) @@ -74,7 +74,7 @@ static int __diag_page_ref_service(struct kvm_vcpu *vcpu) VCPU_EVENT(vcpu, 3, "diag page reference parameter block at 0x%llx", vcpu->run->s.regs.gprs[rx]); - vcpu->stat.diagnose_258++; + vcpu->stat.instruction_diagnose_258++; if (vcpu->run->s.regs.gprs[rx] & 7) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); rc = read_guest(vcpu, vcpu->run->s.regs.gprs[rx], rx, &parm, sizeof(parm)); @@ -145,7 +145,7 @@ static int __diag_page_ref_service(struct kvm_vcpu *vcpu) static int __diag_time_slice_end(struct kvm_vcpu *vcpu) { VCPU_EVENT(vcpu, 5, "%s", "diag time slice end"); - vcpu->stat.diagnose_44++; + vcpu->stat.instruction_diagnose_44++; kvm_vcpu_on_spin(vcpu, true); return 0; } @@ -169,7 +169,7 @@ static int __diag_time_slice_end_directed(struct kvm_vcpu *vcpu) int tid; tid = vcpu->run->s.regs.gprs[(vcpu->arch.sie_block->ipa & 0xf0) >> 4]; - vcpu->stat.diagnose_9c++; + vcpu->stat.instruction_diagnose_9c++; /* yield to self */ if (tid == vcpu->vcpu_id) @@ -192,7 +192,7 @@ static int __diag_time_slice_end_directed(struct kvm_vcpu *vcpu) VCPU_EVENT(vcpu, 5, "diag time slice end directed to %d: yield forwarded", tid); - vcpu->stat.diagnose_9c_forward++; + vcpu->stat.diag_9c_forward++; return 0; } @@ -203,7 +203,7 @@ static int __diag_time_slice_end_directed(struct kvm_vcpu *vcpu) return 0; no_yield: VCPU_EVENT(vcpu, 5, "diag time slice end directed to %d: ignored", tid); - vcpu->stat.diagnose_9c_ignored++; + vcpu->stat.diag_9c_ignored++; return 0; } @@ -213,7 +213,7 @@ static int __diag_ipl_functions(struct kvm_vcpu *vcpu) unsigned long subcode = vcpu->run->s.regs.gprs[reg] & 0xffff; VCPU_EVENT(vcpu, 3, "diag ipl functions, subcode %lx", subcode); - vcpu->stat.diagnose_308++; + vcpu->stat.instruction_diagnose_308++; switch (subcode) { case 3: vcpu->run->s390_reset_flags = KVM_S390_RESET_CLEAR; @@ -245,7 +245,7 @@ static int __diag_virtio_hypercall(struct kvm_vcpu *vcpu) { int ret; - vcpu->stat.diagnose_500++; + vcpu->stat.instruction_diagnose_500++; /* No virtio-ccw notification? Get out quickly. */ if (!vcpu->kvm->arch.css_support || (vcpu->run->s.regs.gprs[1] != KVM_S390_VIRTIO_CCW_NOTIFY)) @@ -299,7 +299,7 @@ int kvm_s390_handle_diag(struct kvm_vcpu *vcpu) case 0x500: return __diag_virtio_hypercall(vcpu); default: - vcpu->stat.diagnose_other++; + vcpu->stat.instruction_diagnose_other++; return -EOPNOTSUPP; } } diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index b655a7d82bf0..4527ac7b5961 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -163,15 +163,15 @@ const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { STATS_DESC_COUNTER(VCPU, instruction_sigp_init_cpu_reset), STATS_DESC_COUNTER(VCPU, instruction_sigp_cpu_reset), STATS_DESC_COUNTER(VCPU, instruction_sigp_unknown), - STATS_DESC_COUNTER(VCPU, diagnose_10), - STATS_DESC_COUNTER(VCPU, diagnose_44), - STATS_DESC_COUNTER(VCPU, diagnose_9c), - STATS_DESC_COUNTER(VCPU, diagnose_9c_ignored), - STATS_DESC_COUNTER(VCPU, diagnose_9c_forward), - STATS_DESC_COUNTER(VCPU, diagnose_258), - STATS_DESC_COUNTER(VCPU, diagnose_308), - STATS_DESC_COUNTER(VCPU, diagnose_500), - STATS_DESC_COUNTER(VCPU, diagnose_other), + STATS_DESC_COUNTER(VCPU, instruction_diagnose_10), + STATS_DESC_COUNTER(VCPU, instruction_diagnose_44), + STATS_DESC_COUNTER(VCPU, instruction_diagnose_9c), + STATS_DESC_COUNTER(VCPU, diag_9c_ignored), + STATS_DESC_COUNTER(VCPU, diag_9c_forward), + STATS_DESC_COUNTER(VCPU, instruction_diagnose_258), + STATS_DESC_COUNTER(VCPU, instruction_diagnose_308), + STATS_DESC_COUNTER(VCPU, instruction_diagnose_500), + STATS_DESC_COUNTER(VCPU, instruction_diagnose_other), STATS_DESC_COUNTER(VCPU, pfault_sync) }; static_assert(ARRAY_SIZE(kvm_vcpu_stats_desc) == diff --git a/arch/s390/lib/string.c b/arch/s390/lib/string.c index ec5b76bde4d8..cfcdf76d6a95 100644 --- a/arch/s390/lib/string.c +++ b/arch/s390/lib/string.c @@ -162,7 +162,7 @@ char *strcat(char *dest, const char *src) " jo 0b\n" "1: mvst %[dummy],%[src]\n" " jo 1b\n" - : [dummy] "=&a" (dummy), [dest] "+&a" (dest), [src] "+&a" (src) + : [dummy] "+&a" (dummy), [dest] "+&a" (dest), [src] "+&a" (src) : : "cc", "memory", "0"); return ret; diff --git a/arch/s390/lib/test_unwind.c b/arch/s390/lib/test_unwind.c index 2f32802f79ce..ecf327d743a0 100644 --- a/arch/s390/lib/test_unwind.c +++ b/arch/s390/lib/test_unwind.c @@ -120,7 +120,7 @@ static struct unwindme *unwindme; #define UWM_REGS 0x2 /* Pass regs to test_unwind(). */ #define UWM_SP 0x4 /* Pass sp to test_unwind(). */ #define UWM_CALLER 0x8 /* Unwind starting from caller. */ -#define UWM_SWITCH_STACK 0x10 /* Use CALL_ON_STACK. */ +#define UWM_SWITCH_STACK 0x10 /* Use call_on_stack. */ #define UWM_IRQ 0x20 /* Unwind from irq context. */ #define UWM_PGM 0x40 /* Unwind from program check handler. */ @@ -211,7 +211,8 @@ static noinline int unwindme_func2(struct unwindme *u) if (u->flags & UWM_SWITCH_STACK) { local_irq_save(flags); local_mcck_disable(); - rc = CALL_ON_STACK(unwindme_func3, S390_lowcore.nodat_stack, 1, u); + rc = call_on_stack(1, S390_lowcore.nodat_stack, + int, unwindme_func3, struct unwindme *, u); local_mcck_enable(); local_irq_restore(flags); return rc; diff --git a/arch/s390/lib/uaccess.c b/arch/s390/lib/uaccess.c index 67606d932825..7ec8b1fa0f08 100644 --- a/arch/s390/lib/uaccess.c +++ b/arch/s390/lib/uaccess.c @@ -224,7 +224,7 @@ static inline unsigned long copy_in_user_mvcos(void __user *to, const void __use EX_TABLE(0b,3b) : "+a" (size), "+a" (to), "+a" (from), "+a" (tmp1), "=a" (tmp2) : [spec] "d" (0x810081UL) - : "cc", "memory"); + : "cc", "memory", "0"); return size; } diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c index 8ae3dc5783fd..e33c43b38afe 100644 --- a/arch/s390/mm/fault.c +++ b/arch/s390/mm/fault.c @@ -285,26 +285,6 @@ static noinline void do_sigbus(struct pt_regs *regs) (void __user *)(regs->int_parm_long & __FAIL_ADDR_MASK)); } -static noinline int signal_return(struct pt_regs *regs) -{ - u16 instruction; - int rc; - - rc = __get_user(instruction, (u16 __user *) regs->psw.addr); - if (rc) - return rc; - if (instruction == 0x0a77) { - set_pt_regs_flag(regs, PIF_SYSCALL); - regs->int_code = 0x00040077; - return 0; - } else if (instruction == 0x0aad) { - set_pt_regs_flag(regs, PIF_SYSCALL); - regs->int_code = 0x000400ad; - return 0; - } - return -EACCES; -} - static noinline void do_fault_error(struct pt_regs *regs, int access, vm_fault_t fault) { @@ -312,9 +292,6 @@ static noinline void do_fault_error(struct pt_regs *regs, int access, switch (fault) { case VM_FAULT_BADACCESS: - if (access == VM_EXEC && signal_return(regs) == 0) - break; - fallthrough; case VM_FAULT_BADMAP: /* Bad memory access. Check if it is kernel or user space. */ if (user_mode(regs)) { @@ -792,6 +769,32 @@ void do_secure_storage_access(struct pt_regs *regs) struct page *page; int rc; + /* + * bit 61 tells us if the address is valid, if it's not we + * have a major problem and should stop the kernel or send a + * SIGSEGV to the process. Unfortunately bit 61 is not + * reliable without the misc UV feature so we need to check + * for that as well. + */ + if (test_bit_inv(BIT_UV_FEAT_MISC, &uv_info.uv_feature_indications) && + !test_bit_inv(61, ®s->int_parm_long)) { + /* + * When this happens, userspace did something that it + * was not supposed to do, e.g. branching into secure + * memory. Trigger a segmentation fault. + */ + if (user_mode(regs)) { + send_sig(SIGSEGV, current, 0); + return; + } + + /* + * The kernel should never run into this case and we + * have no way out of this situation. + */ + panic("Unexpected PGM 0x3d with TEID bit 61=0"); + } + switch (get_fault_type(regs)) { case USER_FAULT: mm = current->mm; diff --git a/arch/s390/mm/maccess.c b/arch/s390/mm/maccess.c index 1f1f906344ff..a0f54bd5e98a 100644 --- a/arch/s390/mm/maccess.c +++ b/arch/s390/mm/maccess.c @@ -125,12 +125,18 @@ static unsigned long __no_sanitize_address _memcpy_real(unsigned long dest, */ int memcpy_real(void *dest, void *src, size_t count) { + unsigned long _dest = (unsigned long)dest; + unsigned long _src = (unsigned long)src; + unsigned long _count = (unsigned long)count; int rc; if (S390_lowcore.nodat_stack != 0) { preempt_disable(); - rc = CALL_ON_STACK(_memcpy_real, S390_lowcore.nodat_stack, 3, - dest, src, count); + rc = call_on_stack(3, S390_lowcore.nodat_stack, + unsigned long, _memcpy_real, + unsigned long, _dest, + unsigned long, _src, + unsigned long, _count); preempt_enable(); return rc; } @@ -139,8 +145,7 @@ int memcpy_real(void *dest, void *src, size_t count) * not set up yet. Just call _memcpy_real on the early boot * stack */ - return _memcpy_real((unsigned long) dest,(unsigned long) src, - (unsigned long) count); + return _memcpy_real(_dest, _src, _count); } /* diff --git a/arch/s390/net/bpf_jit_comp.c b/arch/s390/net/bpf_jit_comp.c index 63cae0476bb4..2ae419f5115a 100644 --- a/arch/s390/net/bpf_jit_comp.c +++ b/arch/s390/net/bpf_jit_comp.c @@ -112,7 +112,7 @@ static inline void reg_set_seen(struct bpf_jit *jit, u32 b1) { u32 r1 = reg2hex[b1]; - if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15) + if (r1 >= 6 && r1 <= 15 && !jit->seen_reg[r1]) jit->seen_reg[r1] = 1; } diff --git a/arch/sh/Kbuild b/arch/sh/Kbuild new file mode 100644 index 000000000000..48c2a091a072 --- /dev/null +++ b/arch/sh/Kbuild @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += kernel/ mm/ boards/ +obj-$(CONFIG_SH_FPU_EMU) += math-emu/ +obj-$(CONFIG_USE_BUILTIN_DTB) += boot/dts/ diff --git a/arch/sh/Makefile b/arch/sh/Makefile index 44bcb80e791a..88ddb6f1c75b 100644 --- a/arch/sh/Makefile +++ b/arch/sh/Makefile @@ -116,11 +116,6 @@ export ld-bfd head-y := arch/sh/kernel/head_32.o -core-y += arch/sh/kernel/ arch/sh/mm/ arch/sh/boards/ -core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/ - -core-$(CONFIG_USE_BUILTIN_DTB) += arch/sh/boot/dts/ - # Mach groups machdir-$(CONFIG_SOLUTION_ENGINE) += mach-se machdir-$(CONFIG_SH_HP6XX) += mach-hp6xx diff --git a/arch/sh/include/asm/pgtable-3level.h b/arch/sh/include/asm/pgtable-3level.h index 82d74472dfcd..56bf35c2f29c 100644 --- a/arch/sh/include/asm/pgtable-3level.h +++ b/arch/sh/include/asm/pgtable-3level.h @@ -32,9 +32,9 @@ typedef struct { unsigned long long pmd; } pmd_t; #define pmd_val(x) ((x).pmd) #define __pmd(x) ((pmd_t) { (x) } ) -static inline unsigned long pud_page_vaddr(pud_t pud) +static inline pmd_t *pud_pgtable(pud_t pud) { - return pud_val(pud); + return (pmd_t *)pud_val(pud); } /* only used by the stubbed out hugetlb gup code, should never be called */ diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index 4144be650d41..1fcb6659822a 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -294,10 +294,7 @@ void __init setup_arch(char **cmdline_p) if (!MOUNT_ROOT_RDONLY) root_mountflags &= ~MS_RDONLY; - init_mm.start_code = (unsigned long) _text; - init_mm.end_code = (unsigned long) _etext; - init_mm.end_data = (unsigned long) _edata; - init_mm.brk = (unsigned long) _end; + setup_initial_init_mm(_text, _etext, _edata, _end); code_resource.start = virt_to_phys(_text); code_resource.end = virt_to_phys(_etext)-1; diff --git a/arch/sparc/Makefile b/arch/sparc/Makefile index bee99e65fe23..4e65245bc755 100644 --- a/arch/sparc/Makefile +++ b/arch/sparc/Makefile @@ -58,9 +58,6 @@ endif head-y := arch/sparc/kernel/head_$(BITS).o -# See arch/sparc/Kbuild for the core part of the kernel -core-y += arch/sparc/ - libs-y += arch/sparc/prom/ libs-y += arch/sparc/lib/ diff --git a/arch/sparc/include/asm/cmpxchg_64.h b/arch/sparc/include/asm/cmpxchg_64.h index 8c39a9981187..12d00a42c0a3 100644 --- a/arch/sparc/include/asm/cmpxchg_64.h +++ b/arch/sparc/include/asm/cmpxchg_64.h @@ -201,7 +201,7 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr, #define arch_cmpxchg64_local(ptr, o, n) \ ({ \ BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ - cmpxchg_local((ptr), (o), (n)); \ + arch_cmpxchg_local((ptr), (o), (n)); \ }) #define arch_cmpxchg64(ptr, o, n) arch_cmpxchg64_local((ptr), (o), (n)) diff --git a/arch/sparc/include/asm/pgtable_32.h b/arch/sparc/include/asm/pgtable_32.h index ebaf374b55ab..ffccfe3b22ed 100644 --- a/arch/sparc/include/asm/pgtable_32.h +++ b/arch/sparc/include/asm/pgtable_32.h @@ -151,13 +151,13 @@ static inline unsigned long pmd_page_vaddr(pmd_t pmd) return (unsigned long)__nocache_va(v << 4); } -static inline unsigned long pud_page_vaddr(pud_t pud) +static inline pmd_t *pud_pgtable(pud_t pud) { if (srmmu_device_memory(pud_val(pud))) { - return ~0; + return (pmd_t *)~0; } else { unsigned long v = pud_val(pud) & SRMMU_PTD_PMASK; - return (unsigned long)__nocache_va(v << 4); + return (pmd_t *)__nocache_va(v << 4); } } diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h index e0ee48ec3903..4679e45c8348 100644 --- a/arch/sparc/include/asm/pgtable_64.h +++ b/arch/sparc/include/asm/pgtable_64.h @@ -841,23 +841,23 @@ static inline unsigned long pmd_page_vaddr(pmd_t pmd) return ((unsigned long) __va(pfn << PAGE_SHIFT)); } -static inline unsigned long pud_page_vaddr(pud_t pud) +static inline pmd_t *pud_pgtable(pud_t pud) { pte_t pte = __pte(pud_val(pud)); unsigned long pfn; pfn = pte_pfn(pte); - return ((unsigned long) __va(pfn << PAGE_SHIFT)); + return ((pmd_t *) __va(pfn << PAGE_SHIFT)); } #define pmd_page(pmd) virt_to_page((void *)pmd_page_vaddr(pmd)) -#define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud)) +#define pud_page(pud) virt_to_page((void *)pud_pgtable(pud)) #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) #define pud_present(pud) (pud_val(pud) != 0U) #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) -#define p4d_page_vaddr(p4d) \ - ((unsigned long) __va(p4d_val(p4d))) +#define p4d_pgtable(p4d) \ + ((pud_t *) __va(p4d_val(p4d))) #define p4d_present(p4d) (p4d_val(p4d) != 0U) #define p4d_clear(p4dp) (p4d_val(*(p4dp)) = 0UL) diff --git a/arch/sparc/kernel/syscalls/Makefile b/arch/sparc/kernel/syscalls/Makefile index 0f2ea5bcb0d7..d63f18dd058d 100644 --- a/arch/sparc/kernel/syscalls/Makefile +++ b/arch/sparc/kernel/syscalls/Makefile @@ -10,25 +10,15 @@ syshdr := $(srctree)/scripts/syscallhdr.sh systbl := $(srctree)/scripts/syscalltbl.sh quiet_cmd_syshdr = SYSHDR $@ - cmd_syshdr = $(CONFIG_SHELL) $(syshdr) --emit-nr --abis $(abis) $< $@ + cmd_syshdr = $(CONFIG_SHELL) $(syshdr) --emit-nr --abis common,$* $< $@ quiet_cmd_systbl = SYSTBL $@ - cmd_systbl = $(CONFIG_SHELL) $(systbl) --abis $(abis) $< $@ + cmd_systbl = $(CONFIG_SHELL) $(systbl) --abis common,$* $< $@ -$(uapi)/unistd_32.h: abis := common,32 -$(uapi)/unistd_32.h: $(syscall) $(syshdr) FORCE +$(uapi)/unistd_%.h: $(syscall) $(syshdr) FORCE $(call if_changed,syshdr) -$(uapi)/unistd_64.h: abis := common,64 -$(uapi)/unistd_64.h: $(syscall) $(syshdr) FORCE - $(call if_changed,syshdr) - -$(kapi)/syscall_table_32.h: abis := common,32 -$(kapi)/syscall_table_32.h: $(syscall) $(systbl) FORCE - $(call if_changed,systbl) - -$(kapi)/syscall_table_64.h: abis := common,64 -$(kapi)/syscall_table_64.h: $(syscall) $(systbl) FORCE +$(kapi)/syscall_table_%.h: $(syscall) $(systbl) FORCE $(call if_changed,systbl) uapisyshdr-y += unistd_32.h unistd_64.h diff --git a/arch/um/Kbuild b/arch/um/Kbuild new file mode 100644 index 000000000000..a4e40e534e6a --- /dev/null +++ b/arch/um/Kbuild @@ -0,0 +1 @@ +# SPDX-License-Identifier: GPL-2.0-only diff --git a/arch/um/Kconfig b/arch/um/Kconfig index 57cfd9a1c082..0561b73cfd9a 100644 --- a/arch/um/Kconfig +++ b/arch/um/Kconfig @@ -15,7 +15,7 @@ config UML select HAVE_FUTEX_CMPXCHG if FUTEX select HAVE_DEBUG_KMEMLEAK select HAVE_DEBUG_BUGVERBOSE - select NO_DMA + select NO_DMA if !UML_DMA_EMULATION select GENERIC_IRQ_SHOW select GENERIC_CPU_DEVICES select HAVE_GCC_PLUGINS @@ -26,7 +26,22 @@ config MMU bool default y +config UML_DMA_EMULATION + bool + config NO_IOMEM + bool "disable IOMEM" if EXPERT + depends on !INDIRECT_IOMEM + default y + +config UML_IOMEM_EMULATION + bool + select INDIRECT_IOMEM + select GENERIC_PCI_IOMAP + select GENERIC_IOMAP + select NO_GENERIC_PCI_IOPORT_MAP + +config NO_IOPORT_MAP def_bool y config ISA @@ -61,6 +76,9 @@ config NR_CPUS range 1 1 default 1 +config ARCH_HAS_CACHE_LINE_SIZE + def_bool y + source "arch/$(HEADER_ARCH)/um/Kconfig" config MAY_HAVE_RUNTIME_DEPS @@ -91,6 +109,19 @@ config LD_SCRIPT_DYN depends on !LD_SCRIPT_STATIC select MODULE_REL_CRCS if MODVERSIONS +config LD_SCRIPT_DYN_RPATH + bool "set rpath in the binary" if EXPERT + default y + depends on LD_SCRIPT_DYN + help + Add /lib (and /lib64 for 64-bit) to the linux binary's rpath + explicitly. + + You may need to turn this off if compiling for nix systems + that have their libraries in random /nix directories and + might otherwise unexpected use libraries from /lib or /lib64 + instead of the desired ones. + config HOSTFS tristate "Host filesystem" help diff --git a/arch/um/Makefile b/arch/um/Makefile index 1cea46ff9bb7..12a7acef0357 100644 --- a/arch/um/Makefile +++ b/arch/um/Makefile @@ -118,7 +118,8 @@ archprepare: $(Q)$(MAKE) $(build)=$(HOST_DIR)/um include/generated/user_constants.h LINK-$(CONFIG_LD_SCRIPT_STATIC) += -static -LINK-$(CONFIG_LD_SCRIPT_DYN) += -Wl,-rpath,/lib $(call cc-option, -no-pie) +LINK-$(CONFIG_LD_SCRIPT_DYN) += $(call cc-option, -no-pie) +LINK-$(CONFIG_LD_SCRIPT_DYN_RPATH) += -Wl,-rpath,/lib CFLAGS_NO_HARDENING := $(call cc-option, -fno-PIC,) $(call cc-option, -fno-pic,) \ -fno-stack-protector $(call cc-option, -fno-stack-protector-all) diff --git a/arch/um/drivers/Kconfig b/arch/um/drivers/Kconfig index 03ba34b61115..f145842c40b9 100644 --- a/arch/um/drivers/Kconfig +++ b/arch/um/drivers/Kconfig @@ -357,3 +357,23 @@ config UML_RTC rtcwake, especially in time-travel mode. This driver enables that by providing a fake RTC clock that causes a wakeup at the right time. + +config UML_PCI_OVER_VIRTIO + bool "Enable PCI over VIRTIO device simulation" + # in theory, just VIRTIO is enough, but that causes recursion + depends on VIRTIO_UML + select FORCE_PCI + select UML_IOMEM_EMULATION + select UML_DMA_EMULATION + select PCI_MSI + select PCI_MSI_IRQ_DOMAIN + select PCI_LOCKLESS_CONFIG + +config UML_PCI_OVER_VIRTIO_DEVICE_ID + int "set the virtio device ID for PCI emulation" + default -1 + depends on UML_PCI_OVER_VIRTIO + help + There's no official device ID assigned (yet), set the one you + wish to use for experimentation here. The default of -1 is + not valid and will cause the driver to fail at probe. diff --git a/arch/um/drivers/Makefile b/arch/um/drivers/Makefile index dcc64a02f81f..803666e85414 100644 --- a/arch/um/drivers/Makefile +++ b/arch/um/drivers/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_BLK_DEV_COW_COMMON) += cow_user.o obj-$(CONFIG_UML_RANDOM) += random.o obj-$(CONFIG_VIRTIO_UML) += virtio_uml.o obj-$(CONFIG_UML_RTC) += rtc.o +obj-$(CONFIG_UML_PCI_OVER_VIRTIO) += virt-pci.o # pcap_user.o must be added explicitly. USER_OBJS := fd.o null.o pty.o tty.o xterm.o slip_common.o pcap_user.o vde_user.o vector_user.o diff --git a/arch/um/drivers/chan_user.c b/arch/um/drivers/chan_user.c index d8845d4aac6a..6040817c036f 100644 --- a/arch/um/drivers/chan_user.c +++ b/arch/um/drivers/chan_user.c @@ -256,7 +256,8 @@ static int winch_tramp(int fd, struct tty_port *port, int *fd_out, goto out_close; } - if (os_set_fd_block(*fd_out, 0)) { + err = os_set_fd_block(*fd_out, 0); + if (err) { printk(UM_KERN_ERR "winch_tramp: failed to set thread_fd " "non-blocking.\n"); goto out_close; diff --git a/arch/um/drivers/slip_user.c b/arch/um/drivers/slip_user.c index 482a19c5105c..7334019c9e60 100644 --- a/arch/um/drivers/slip_user.c +++ b/arch/um/drivers/slip_user.c @@ -145,7 +145,8 @@ static int slip_open(void *data) } sfd = err; - if (set_up_tty(sfd)) + err = set_up_tty(sfd); + if (err) goto out_close2; pri->slave = sfd; diff --git a/arch/um/drivers/ubd_kern.c b/arch/um/drivers/ubd_kern.c index 8e0b43cf089f..e497185dd393 100644 --- a/arch/um/drivers/ubd_kern.c +++ b/arch/um/drivers/ubd_kern.c @@ -125,9 +125,7 @@ static const struct block_device_operations ubd_blops = { }; /* Protected by ubd_lock */ -static int fake_major = UBD_MAJOR; static struct gendisk *ubd_gendisk[MAX_DEV]; -static struct gendisk *fake_gendisk[MAX_DEV]; #ifdef CONFIG_BLK_DEV_UBD_SYNC #define OPEN_FLAGS ((struct openflags) { .r = 1, .w = 1, .s = 1, .c = 0, \ @@ -197,54 +195,19 @@ struct ubd { /* Protected by ubd_lock */ static struct ubd ubd_devs[MAX_DEV] = { [0 ... MAX_DEV - 1] = DEFAULT_UBD }; -/* Only changed by fake_ide_setup which is a setup */ -static int fake_ide = 0; -static struct proc_dir_entry *proc_ide_root = NULL; -static struct proc_dir_entry *proc_ide = NULL; - static blk_status_t ubd_queue_rq(struct blk_mq_hw_ctx *hctx, const struct blk_mq_queue_data *bd); -static void make_proc_ide(void) -{ - proc_ide_root = proc_mkdir("ide", NULL); - proc_ide = proc_mkdir("ide0", proc_ide_root); -} - -static int fake_ide_media_proc_show(struct seq_file *m, void *v) -{ - seq_puts(m, "disk\n"); - return 0; -} - -static void make_ide_entries(const char *dev_name) -{ - struct proc_dir_entry *dir, *ent; - char name[64]; - - if(proc_ide_root == NULL) make_proc_ide(); - - dir = proc_mkdir(dev_name, proc_ide); - if(!dir) return; - - ent = proc_create_single("media", S_IRUGO, dir, - fake_ide_media_proc_show); - if(!ent) return; - snprintf(name, sizeof(name), "ide0/%s", dev_name); - proc_symlink(dev_name, proc_ide_root, name); -} - static int fake_ide_setup(char *str) { - fake_ide = 1; + pr_warn("The fake_ide option has been removed\n"); return 1; } - __setup("fake_ide", fake_ide_setup); __uml_help(fake_ide_setup, "fake_ide\n" -" Create ide0 entries that map onto ubd devices.\n\n" +" Obsolete stub.\n\n" ); static int parse_unit(char **ptr) @@ -280,36 +243,14 @@ static int ubd_setup_common(char *str, int *index_out, char **error_out) if(index_out) *index_out = -1; n = *str; if(n == '='){ - char *end; - int major; - str++; if(!strcmp(str, "sync")){ global_openflags = of_sync(global_openflags); return err; } - err = -EINVAL; - major = simple_strtoul(str, &end, 0); - if((*end != '\0') || (end == str)){ - *error_out = "Didn't parse major number"; - return err; - } - - mutex_lock(&ubd_lock); - if (fake_major != UBD_MAJOR) { - *error_out = "Can't assign a fake major twice"; - goto out1; - } - - fake_major = major; - - printk(KERN_INFO "Setting extra ubd major number to %d\n", - major); - err = 0; - out1: - mutex_unlock(&ubd_lock); - return err; + pr_warn("fake major not supported any more\n"); + return 0; } n = parse_unit(&str); @@ -874,7 +815,6 @@ static void ubd_device_release(struct device *dev) { struct ubd *ubd_dev = dev_get_drvdata(dev); - blk_cleanup_queue(ubd_dev->queue); blk_mq_free_tag_set(&ubd_dev->tag_set); *ubd_dev = ((struct ubd) DEFAULT_UBD); } @@ -914,41 +854,25 @@ static const struct attribute_group *ubd_attr_groups[] = { NULL, }; -static int ubd_disk_register(int major, u64 size, int unit, - struct gendisk **disk_out) +static void ubd_disk_register(int major, u64 size, int unit, + struct gendisk *disk) { - struct device *parent = NULL; - struct gendisk *disk; - - disk = alloc_disk(1 << UBD_SHIFT); - if(disk == NULL) - return -ENOMEM; - disk->major = major; disk->first_minor = unit << UBD_SHIFT; + disk->minors = 1 << UBD_SHIFT; disk->fops = &ubd_blops; set_capacity(disk, size / 512); - if (major == UBD_MAJOR) - sprintf(disk->disk_name, "ubd%c", 'a' + unit); - else - sprintf(disk->disk_name, "ubd_fake%d", unit); - - /* sysfs register (not for ide fake devices) */ - if (major == UBD_MAJOR) { - ubd_devs[unit].pdev.id = unit; - ubd_devs[unit].pdev.name = DRIVER_NAME; - ubd_devs[unit].pdev.dev.release = ubd_device_release; - dev_set_drvdata(&ubd_devs[unit].pdev.dev, &ubd_devs[unit]); - platform_device_register(&ubd_devs[unit].pdev); - parent = &ubd_devs[unit].pdev.dev; - } + sprintf(disk->disk_name, "ubd%c", 'a' + unit); + + ubd_devs[unit].pdev.id = unit; + ubd_devs[unit].pdev.name = DRIVER_NAME; + ubd_devs[unit].pdev.dev.release = ubd_device_release; + dev_set_drvdata(&ubd_devs[unit].pdev.dev, &ubd_devs[unit]); + platform_device_register(&ubd_devs[unit].pdev); disk->private_data = &ubd_devs[unit]; disk->queue = ubd_devs[unit].queue; - device_add_disk(parent, disk, ubd_attr_groups); - - *disk_out = disk; - return 0; + device_add_disk(&ubd_devs[unit].pdev.dev, disk, ubd_attr_groups); } #define ROUND_BLOCK(n) ((n + (SECTOR_SIZE - 1)) & (-SECTOR_SIZE)) @@ -960,6 +884,7 @@ static const struct blk_mq_ops ubd_mq_ops = { static int ubd_add(int n, char **error_out) { struct ubd *ubd_dev = &ubd_devs[n]; + struct gendisk *disk; int err = 0; if(ubd_dev->file == NULL) @@ -984,43 +909,24 @@ static int ubd_add(int n, char **error_out) if (err) goto out; - ubd_dev->queue = blk_mq_init_queue(&ubd_dev->tag_set); - if (IS_ERR(ubd_dev->queue)) { - err = PTR_ERR(ubd_dev->queue); + disk = blk_mq_alloc_disk(&ubd_dev->tag_set, ubd_dev); + if (IS_ERR(disk)) { + err = PTR_ERR(disk); goto out_cleanup_tags; } + ubd_dev->queue = disk->queue; - ubd_dev->queue->queuedata = ubd_dev; blk_queue_write_cache(ubd_dev->queue, true, false); - blk_queue_max_segments(ubd_dev->queue, MAX_SG); blk_queue_segment_boundary(ubd_dev->queue, PAGE_SIZE - 1); - err = ubd_disk_register(UBD_MAJOR, ubd_dev->size, n, &ubd_gendisk[n]); - if(err){ - *error_out = "Failed to register device"; - goto out_cleanup_tags; - } - - if (fake_major != UBD_MAJOR) - ubd_disk_register(fake_major, ubd_dev->size, n, - &fake_gendisk[n]); - - /* - * Perhaps this should also be under the "if (fake_major)" above - * using the fake_disk->disk_name - */ - if (fake_ide) - make_ide_entries(ubd_gendisk[n]->disk_name); - - err = 0; -out: - return err; + ubd_disk_register(UBD_MAJOR, ubd_dev->size, n, disk); + ubd_gendisk[n] = disk; + return 0; out_cleanup_tags: blk_mq_free_tag_set(&ubd_dev->tag_set); - if (!(IS_ERR(ubd_dev->queue))) - blk_cleanup_queue(ubd_dev->queue); - goto out; +out: + return err; } static int ubd_config(char *str, char **error_out) @@ -1123,13 +1029,7 @@ static int ubd_remove(int n, char **error_out) ubd_gendisk[n] = NULL; if(disk != NULL){ del_gendisk(disk); - put_disk(disk); - } - - if(fake_gendisk[n] != NULL){ - del_gendisk(fake_gendisk[n]); - put_disk(fake_gendisk[n]); - fake_gendisk[n] = NULL; + blk_cleanup_disk(disk); } err = 0; @@ -1188,14 +1088,6 @@ static int __init ubd_init(void) if (register_blkdev(UBD_MAJOR, "ubd")) return -1; - if (fake_major != UBD_MAJOR) { - char name[sizeof("ubd_nnn\0")]; - - snprintf(name, sizeof(name), "ubd_%d", fake_major); - if (register_blkdev(fake_major, "ubd")) - return -1; - } - irq_req_buffer = kmalloc_array(UBD_REQ_BUFFER_SIZE, sizeof(struct io_thread_req *), GFP_KERNEL @@ -1242,8 +1134,7 @@ static int __init ubd_driver_init(void){ * enough. So use anyway the io thread. */ } stack = alloc_stack(0, 0); - io_pid = start_io_thread(stack + PAGE_SIZE - sizeof(void *), - &thread_fd); + io_pid = start_io_thread(stack + PAGE_SIZE, &thread_fd); if(io_pid < 0){ printk(KERN_ERR "ubd : Failed to start I/O thread (errno = %d) - " diff --git a/arch/um/drivers/virt-pci.c b/arch/um/drivers/virt-pci.c new file mode 100644 index 000000000000..0b802834f40a --- /dev/null +++ b/arch/um/drivers/virt-pci.c @@ -0,0 +1,895 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Intel Corporation + * Author: Johannes Berg <johannes@sipsolutions.net> + */ +#include <linux/module.h> +#include <linux/pci.h> +#include <linux/virtio.h> +#include <linux/virtio_config.h> +#include <linux/logic_iomem.h> +#include <linux/irqdomain.h> +#include <linux/virtio_pcidev.h> +#include <linux/virtio-uml.h> +#include <linux/delay.h> +#include <linux/msi.h> +#include <asm/unaligned.h> +#include <irq_kern.h> + +#define MAX_DEVICES 8 +#define MAX_MSI_VECTORS 32 +#define CFG_SPACE_SIZE 4096 + +/* for MSI-X we have a 32-bit payload */ +#define MAX_IRQ_MSG_SIZE (sizeof(struct virtio_pcidev_msg) + sizeof(u32)) +#define NUM_IRQ_MSGS 10 + +#define HANDLE_NO_FREE(ptr) ((void *)((unsigned long)(ptr) | 1)) +#define HANDLE_IS_NO_FREE(ptr) ((unsigned long)(ptr) & 1) + +struct um_pci_device { + struct virtio_device *vdev; + + /* for now just standard BARs */ + u8 resptr[PCI_STD_NUM_BARS]; + + struct virtqueue *cmd_vq, *irq_vq; + +#define UM_PCI_STAT_WAITING 0 + unsigned long status; + + int irq; +}; + +struct um_pci_device_reg { + struct um_pci_device *dev; + void __iomem *iomem; +}; + +static struct pci_host_bridge *bridge; +static DEFINE_MUTEX(um_pci_mtx); +static struct um_pci_device_reg um_pci_devices[MAX_DEVICES]; +static struct fwnode_handle *um_pci_fwnode; +static struct irq_domain *um_pci_inner_domain; +static struct irq_domain *um_pci_msi_domain; +static unsigned long um_pci_msi_used[BITS_TO_LONGS(MAX_MSI_VECTORS)]; + +#define UM_VIRT_PCI_MAXDELAY 40000 + +static int um_pci_send_cmd(struct um_pci_device *dev, + struct virtio_pcidev_msg *cmd, + unsigned int cmd_size, + const void *extra, unsigned int extra_size, + void *out, unsigned int out_size) +{ + struct scatterlist out_sg, extra_sg, in_sg; + struct scatterlist *sgs_list[] = { + [0] = &out_sg, + [1] = extra ? &extra_sg : &in_sg, + [2] = extra ? &in_sg : NULL, + }; + int delay_count = 0; + int ret, len; + bool posted; + + if (WARN_ON(cmd_size < sizeof(*cmd))) + return -EINVAL; + + switch (cmd->op) { + case VIRTIO_PCIDEV_OP_CFG_WRITE: + case VIRTIO_PCIDEV_OP_MMIO_WRITE: + case VIRTIO_PCIDEV_OP_MMIO_MEMSET: + /* in PCI, writes are posted, so don't wait */ + posted = !out; + WARN_ON(!posted); + break; + default: + posted = false; + break; + } + + if (posted) { + u8 *ncmd = kmalloc(cmd_size + extra_size, GFP_ATOMIC); + + if (ncmd) { + memcpy(ncmd, cmd, cmd_size); + if (extra) + memcpy(ncmd + cmd_size, extra, extra_size); + cmd = (void *)ncmd; + cmd_size += extra_size; + extra = NULL; + extra_size = 0; + } else { + /* try without allocating memory */ + posted = false; + } + } + + sg_init_one(&out_sg, cmd, cmd_size); + if (extra) + sg_init_one(&extra_sg, extra, extra_size); + if (out) + sg_init_one(&in_sg, out, out_size); + + /* add to internal virtio queue */ + ret = virtqueue_add_sgs(dev->cmd_vq, sgs_list, + extra ? 2 : 1, + out ? 1 : 0, + posted ? cmd : HANDLE_NO_FREE(cmd), + GFP_ATOMIC); + if (ret) + return ret; + + if (posted) { + virtqueue_kick(dev->cmd_vq); + return 0; + } + + /* kick and poll for getting a response on the queue */ + set_bit(UM_PCI_STAT_WAITING, &dev->status); + virtqueue_kick(dev->cmd_vq); + + while (1) { + void *completed = virtqueue_get_buf(dev->cmd_vq, &len); + + if (completed == HANDLE_NO_FREE(cmd)) + break; + + if (completed && !HANDLE_IS_NO_FREE(completed)) + kfree(completed); + + if (WARN_ONCE(virtqueue_is_broken(dev->cmd_vq) || + ++delay_count > UM_VIRT_PCI_MAXDELAY, + "um virt-pci delay: %d", delay_count)) { + ret = -EIO; + break; + } + udelay(1); + } + clear_bit(UM_PCI_STAT_WAITING, &dev->status); + + return ret; +} + +static unsigned long um_pci_cfgspace_read(void *priv, unsigned int offset, + int size) +{ + struct um_pci_device_reg *reg = priv; + struct um_pci_device *dev = reg->dev; + struct virtio_pcidev_msg hdr = { + .op = VIRTIO_PCIDEV_OP_CFG_READ, + .size = size, + .addr = offset, + }; + /* maximum size - we may only use parts of it */ + u8 data[8]; + + if (!dev) + return ~0ULL; + + memset(data, 0xff, sizeof(data)); + + switch (size) { + case 1: + case 2: + case 4: +#ifdef CONFIG_64BIT + case 8: +#endif + break; + default: + WARN(1, "invalid config space read size %d\n", size); + return ~0ULL; + } + + if (um_pci_send_cmd(dev, &hdr, sizeof(hdr), NULL, 0, + data, sizeof(data))) + return ~0ULL; + + switch (size) { + case 1: + return data[0]; + case 2: + return le16_to_cpup((void *)data); + case 4: + return le32_to_cpup((void *)data); +#ifdef CONFIG_64BIT + case 8: + return le64_to_cpup((void *)data); +#endif + default: + return ~0ULL; + } +} + +static void um_pci_cfgspace_write(void *priv, unsigned int offset, int size, + unsigned long val) +{ + struct um_pci_device_reg *reg = priv; + struct um_pci_device *dev = reg->dev; + struct { + struct virtio_pcidev_msg hdr; + /* maximum size - we may only use parts of it */ + u8 data[8]; + } msg = { + .hdr = { + .op = VIRTIO_PCIDEV_OP_CFG_WRITE, + .size = size, + .addr = offset, + }, + }; + + if (!dev) + return; + + switch (size) { + case 1: + msg.data[0] = (u8)val; + break; + case 2: + put_unaligned_le16(val, (void *)msg.data); + break; + case 4: + put_unaligned_le32(val, (void *)msg.data); + break; +#ifdef CONFIG_64BIT + case 8: + put_unaligned_le64(val, (void *)msg.data); + break; +#endif + default: + WARN(1, "invalid config space write size %d\n", size); + return; + } + + WARN_ON(um_pci_send_cmd(dev, &msg.hdr, sizeof(msg), NULL, 0, NULL, 0)); +} + +static const struct logic_iomem_ops um_pci_device_cfgspace_ops = { + .read = um_pci_cfgspace_read, + .write = um_pci_cfgspace_write, +}; + +static void um_pci_bar_copy_from(void *priv, void *buffer, + unsigned int offset, int size) +{ + u8 *resptr = priv; + struct um_pci_device *dev = container_of(resptr - *resptr, + struct um_pci_device, + resptr[0]); + struct virtio_pcidev_msg hdr = { + .op = VIRTIO_PCIDEV_OP_MMIO_READ, + .bar = *resptr, + .size = size, + .addr = offset, + }; + + memset(buffer, 0xff, size); + + um_pci_send_cmd(dev, &hdr, sizeof(hdr), NULL, 0, buffer, size); +} + +static unsigned long um_pci_bar_read(void *priv, unsigned int offset, + int size) +{ + /* maximum size - we may only use parts of it */ + u8 data[8]; + + switch (size) { + case 1: + case 2: + case 4: +#ifdef CONFIG_64BIT + case 8: +#endif + break; + default: + WARN(1, "invalid config space read size %d\n", size); + return ~0ULL; + } + + um_pci_bar_copy_from(priv, data, offset, size); + + switch (size) { + case 1: + return data[0]; + case 2: + return le16_to_cpup((void *)data); + case 4: + return le32_to_cpup((void *)data); +#ifdef CONFIG_64BIT + case 8: + return le64_to_cpup((void *)data); +#endif + default: + return ~0ULL; + } +} + +static void um_pci_bar_copy_to(void *priv, unsigned int offset, + const void *buffer, int size) +{ + u8 *resptr = priv; + struct um_pci_device *dev = container_of(resptr - *resptr, + struct um_pci_device, + resptr[0]); + struct virtio_pcidev_msg hdr = { + .op = VIRTIO_PCIDEV_OP_MMIO_WRITE, + .bar = *resptr, + .size = size, + .addr = offset, + }; + + um_pci_send_cmd(dev, &hdr, sizeof(hdr), buffer, size, NULL, 0); +} + +static void um_pci_bar_write(void *priv, unsigned int offset, int size, + unsigned long val) +{ + /* maximum size - we may only use parts of it */ + u8 data[8]; + + switch (size) { + case 1: + data[0] = (u8)val; + break; + case 2: + put_unaligned_le16(val, (void *)data); + break; + case 4: + put_unaligned_le32(val, (void *)data); + break; +#ifdef CONFIG_64BIT + case 8: + put_unaligned_le64(val, (void *)data); + break; +#endif + default: + WARN(1, "invalid config space write size %d\n", size); + return; + } + + um_pci_bar_copy_to(priv, offset, data, size); +} + +static void um_pci_bar_set(void *priv, unsigned int offset, u8 value, int size) +{ + u8 *resptr = priv; + struct um_pci_device *dev = container_of(resptr - *resptr, + struct um_pci_device, + resptr[0]); + struct { + struct virtio_pcidev_msg hdr; + u8 data; + } msg = { + .hdr = { + .op = VIRTIO_PCIDEV_OP_CFG_WRITE, + .bar = *resptr, + .size = size, + .addr = offset, + }, + .data = value, + }; + + um_pci_send_cmd(dev, &msg.hdr, sizeof(msg), NULL, 0, NULL, 0); +} + +static const struct logic_iomem_ops um_pci_device_bar_ops = { + .read = um_pci_bar_read, + .write = um_pci_bar_write, + .set = um_pci_bar_set, + .copy_from = um_pci_bar_copy_from, + .copy_to = um_pci_bar_copy_to, +}; + +static void __iomem *um_pci_map_bus(struct pci_bus *bus, unsigned int devfn, + int where) +{ + struct um_pci_device_reg *dev; + unsigned int busn = bus->number; + + if (busn > 0) + return NULL; + + /* not allowing functions for now ... */ + if (devfn % 8) + return NULL; + + if (devfn / 8 >= ARRAY_SIZE(um_pci_devices)) + return NULL; + + dev = &um_pci_devices[devfn / 8]; + if (!dev) + return NULL; + + return (void __iomem *)((unsigned long)dev->iomem + where); +} + +static struct pci_ops um_pci_ops = { + .map_bus = um_pci_map_bus, + .read = pci_generic_config_read, + .write = pci_generic_config_write, +}; + +static void um_pci_rescan(void) +{ + pci_lock_rescan_remove(); + pci_rescan_bus(bridge->bus); + pci_unlock_rescan_remove(); +} + +static void um_pci_irq_vq_addbuf(struct virtqueue *vq, void *buf, bool kick) +{ + struct scatterlist sg[1]; + + sg_init_one(sg, buf, MAX_IRQ_MSG_SIZE); + if (virtqueue_add_inbuf(vq, sg, 1, buf, GFP_ATOMIC)) + kfree(buf); + else if (kick) + virtqueue_kick(vq); +} + +static void um_pci_handle_irq_message(struct virtqueue *vq, + struct virtio_pcidev_msg *msg) +{ + struct virtio_device *vdev = vq->vdev; + struct um_pci_device *dev = vdev->priv; + + /* we should properly chain interrupts, but on ARCH=um we don't care */ + + switch (msg->op) { + case VIRTIO_PCIDEV_OP_INT: + generic_handle_irq(dev->irq); + break; + case VIRTIO_PCIDEV_OP_MSI: + /* our MSI message is just the interrupt number */ + if (msg->size == sizeof(u32)) + generic_handle_irq(le32_to_cpup((void *)msg->data)); + else + generic_handle_irq(le16_to_cpup((void *)msg->data)); + break; + case VIRTIO_PCIDEV_OP_PME: + /* nothing to do - we already woke up due to the message */ + break; + default: + dev_err(&vdev->dev, "unexpected virt-pci message %d\n", msg->op); + break; + } +} + +static void um_pci_cmd_vq_cb(struct virtqueue *vq) +{ + struct virtio_device *vdev = vq->vdev; + struct um_pci_device *dev = vdev->priv; + void *cmd; + int len; + + if (test_bit(UM_PCI_STAT_WAITING, &dev->status)) + return; + + while ((cmd = virtqueue_get_buf(vq, &len))) { + if (WARN_ON(HANDLE_IS_NO_FREE(cmd))) + continue; + kfree(cmd); + } +} + +static void um_pci_irq_vq_cb(struct virtqueue *vq) +{ + struct virtio_pcidev_msg *msg; + int len; + + while ((msg = virtqueue_get_buf(vq, &len))) { + if (len >= sizeof(*msg)) + um_pci_handle_irq_message(vq, msg); + + /* recycle the message buffer */ + um_pci_irq_vq_addbuf(vq, msg, true); + } +} + +static int um_pci_init_vqs(struct um_pci_device *dev) +{ + struct virtqueue *vqs[2]; + static const char *const names[2] = { "cmd", "irq" }; + vq_callback_t *cbs[2] = { um_pci_cmd_vq_cb, um_pci_irq_vq_cb }; + int err, i; + + err = virtio_find_vqs(dev->vdev, 2, vqs, cbs, names, NULL); + if (err) + return err; + + dev->cmd_vq = vqs[0]; + dev->irq_vq = vqs[1]; + + for (i = 0; i < NUM_IRQ_MSGS; i++) { + void *msg = kzalloc(MAX_IRQ_MSG_SIZE, GFP_KERNEL); + + if (msg) + um_pci_irq_vq_addbuf(dev->irq_vq, msg, false); + } + + virtqueue_kick(dev->irq_vq); + + return 0; +} + +static int um_pci_virtio_probe(struct virtio_device *vdev) +{ + struct um_pci_device *dev; + int i, free = -1; + int err = -ENOSPC; + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + dev->vdev = vdev; + vdev->priv = dev; + + mutex_lock(&um_pci_mtx); + for (i = 0; i < MAX_DEVICES; i++) { + if (um_pci_devices[i].dev) + continue; + free = i; + break; + } + + if (free < 0) + goto error; + + err = um_pci_init_vqs(dev); + if (err) + goto error; + + dev->irq = irq_alloc_desc(numa_node_id()); + if (dev->irq < 0) { + err = dev->irq; + goto error; + } + um_pci_devices[free].dev = dev; + vdev->priv = dev; + + mutex_unlock(&um_pci_mtx); + + device_set_wakeup_enable(&vdev->dev, true); + + /* + * In order to do suspend-resume properly, don't allow VQs + * to be suspended. + */ + virtio_uml_set_no_vq_suspend(vdev, true); + + um_pci_rescan(); + return 0; +error: + mutex_unlock(&um_pci_mtx); + kfree(dev); + return err; +} + +static void um_pci_virtio_remove(struct virtio_device *vdev) +{ + struct um_pci_device *dev = vdev->priv; + int i; + + /* Stop all virtqueues */ + vdev->config->reset(vdev); + vdev->config->del_vqs(vdev); + + device_set_wakeup_enable(&vdev->dev, false); + + mutex_lock(&um_pci_mtx); + for (i = 0; i < MAX_DEVICES; i++) { + if (um_pci_devices[i].dev != dev) + continue; + um_pci_devices[i].dev = NULL; + irq_free_desc(dev->irq); + } + mutex_unlock(&um_pci_mtx); + + um_pci_rescan(); + + kfree(dev); +} + +static struct virtio_device_id id_table[] = { + { CONFIG_UML_PCI_OVER_VIRTIO_DEVICE_ID, VIRTIO_DEV_ANY_ID }, + { 0 }, +}; +MODULE_DEVICE_TABLE(virtio, id_table); + +static struct virtio_driver um_pci_virtio_driver = { + .driver.name = "virtio-pci", + .driver.owner = THIS_MODULE, + .id_table = id_table, + .probe = um_pci_virtio_probe, + .remove = um_pci_virtio_remove, +}; + +static struct resource virt_cfgspace_resource = { + .name = "PCI config space", + .start = 0xf0000000 - MAX_DEVICES * CFG_SPACE_SIZE, + .end = 0xf0000000 - 1, + .flags = IORESOURCE_MEM, +}; + +static long um_pci_map_cfgspace(unsigned long offset, size_t size, + const struct logic_iomem_ops **ops, + void **priv) +{ + if (WARN_ON(size > CFG_SPACE_SIZE || offset % CFG_SPACE_SIZE)) + return -EINVAL; + + if (offset / CFG_SPACE_SIZE < MAX_DEVICES) { + *ops = &um_pci_device_cfgspace_ops; + *priv = &um_pci_devices[offset / CFG_SPACE_SIZE]; + return 0; + } + + WARN(1, "cannot map offset 0x%lx/0x%zx\n", offset, size); + return -ENOENT; +} + +static const struct logic_iomem_region_ops um_pci_cfgspace_ops = { + .map = um_pci_map_cfgspace, +}; + +static struct resource virt_iomem_resource = { + .name = "PCI iomem", + .start = 0xf0000000, + .end = 0xffffffff, + .flags = IORESOURCE_MEM, +}; + +struct um_pci_map_iomem_data { + unsigned long offset; + size_t size; + const struct logic_iomem_ops **ops; + void **priv; + long ret; +}; + +static int um_pci_map_iomem_walk(struct pci_dev *pdev, void *_data) +{ + struct um_pci_map_iomem_data *data = _data; + struct um_pci_device_reg *reg = &um_pci_devices[pdev->devfn / 8]; + struct um_pci_device *dev; + int i; + + if (!reg->dev) + return 0; + + for (i = 0; i < ARRAY_SIZE(dev->resptr); i++) { + struct resource *r = &pdev->resource[i]; + + if ((r->flags & IORESOURCE_TYPE_BITS) != IORESOURCE_MEM) + continue; + + /* + * must be the whole or part of the resource, + * not allowed to only overlap + */ + if (data->offset < r->start || data->offset > r->end) + continue; + if (data->offset + data->size - 1 > r->end) + continue; + + dev = reg->dev; + *data->ops = &um_pci_device_bar_ops; + dev->resptr[i] = i; + *data->priv = &dev->resptr[i]; + data->ret = data->offset - r->start; + + /* no need to continue */ + return 1; + } + + return 0; +} + +static long um_pci_map_iomem(unsigned long offset, size_t size, + const struct logic_iomem_ops **ops, + void **priv) +{ + struct um_pci_map_iomem_data data = { + /* we want the full address here */ + .offset = offset + virt_iomem_resource.start, + .size = size, + .ops = ops, + .priv = priv, + .ret = -ENOENT, + }; + + pci_walk_bus(bridge->bus, um_pci_map_iomem_walk, &data); + return data.ret; +} + +static const struct logic_iomem_region_ops um_pci_iomem_ops = { + .map = um_pci_map_iomem, +}; + +static void um_pci_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) +{ + /* + * This is a very low address and not actually valid 'physical' memory + * in UML, so we can simply map MSI(-X) vectors to there, it cannot be + * legitimately written to by the device in any other way. + * We use the (virtual) IRQ number here as the message to simplify the + * code that receives the message, where for now we simply trust the + * device to send the correct message. + */ + msg->address_hi = 0; + msg->address_lo = 0xa0000; + msg->data = data->irq; +} + +static struct irq_chip um_pci_msi_bottom_irq_chip = { + .name = "UM virtio MSI", + .irq_compose_msi_msg = um_pci_compose_msi_msg, +}; + +static int um_pci_inner_domain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *args) +{ + unsigned long bit; + + WARN_ON(nr_irqs != 1); + + mutex_lock(&um_pci_mtx); + bit = find_first_zero_bit(um_pci_msi_used, MAX_MSI_VECTORS); + if (bit >= MAX_MSI_VECTORS) { + mutex_unlock(&um_pci_mtx); + return -ENOSPC; + } + + set_bit(bit, um_pci_msi_used); + mutex_unlock(&um_pci_mtx); + + irq_domain_set_info(domain, virq, bit, &um_pci_msi_bottom_irq_chip, + domain->host_data, handle_simple_irq, + NULL, NULL); + + return 0; +} + +static void um_pci_inner_domain_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + + mutex_lock(&um_pci_mtx); + + if (!test_bit(d->hwirq, um_pci_msi_used)) + pr_err("trying to free unused MSI#%lu\n", d->hwirq); + else + __clear_bit(d->hwirq, um_pci_msi_used); + + mutex_unlock(&um_pci_mtx); +} + +static const struct irq_domain_ops um_pci_inner_domain_ops = { + .alloc = um_pci_inner_domain_alloc, + .free = um_pci_inner_domain_free, +}; + +static struct irq_chip um_pci_msi_irq_chip = { + .name = "UM virtio PCIe MSI", + .irq_mask = pci_msi_mask_irq, + .irq_unmask = pci_msi_unmask_irq, +}; + +static struct msi_domain_info um_pci_msi_domain_info = { + .flags = MSI_FLAG_USE_DEF_DOM_OPS | + MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSIX, + .chip = &um_pci_msi_irq_chip, +}; + +static struct resource busn_resource = { + .name = "PCI busn", + .start = 0, + .end = 0, + .flags = IORESOURCE_BUS, +}; + +static int um_pci_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin) +{ + struct um_pci_device_reg *reg = &um_pci_devices[pdev->devfn / 8]; + + if (WARN_ON(!reg->dev)) + return -EINVAL; + + /* Yes, we map all pins to the same IRQ ... doesn't matter for now. */ + return reg->dev->irq; +} + +void *pci_root_bus_fwnode(struct pci_bus *bus) +{ + return um_pci_fwnode; +} + +int um_pci_init(void) +{ + int err, i; + + WARN_ON(logic_iomem_add_region(&virt_cfgspace_resource, + &um_pci_cfgspace_ops)); + WARN_ON(logic_iomem_add_region(&virt_iomem_resource, + &um_pci_iomem_ops)); + + if (WARN(CONFIG_UML_PCI_OVER_VIRTIO_DEVICE_ID < 0, + "No virtio device ID configured for PCI - no PCI support\n")) + return 0; + + bridge = pci_alloc_host_bridge(0); + if (!bridge) + return -ENOMEM; + + um_pci_fwnode = irq_domain_alloc_named_fwnode("um-pci"); + if (!um_pci_fwnode) { + err = -ENOMEM; + goto free; + } + + um_pci_inner_domain = __irq_domain_add(um_pci_fwnode, MAX_MSI_VECTORS, + MAX_MSI_VECTORS, 0, + &um_pci_inner_domain_ops, NULL); + if (!um_pci_inner_domain) { + err = -ENOMEM; + goto free; + } + + um_pci_msi_domain = pci_msi_create_irq_domain(um_pci_fwnode, + &um_pci_msi_domain_info, + um_pci_inner_domain); + if (!um_pci_msi_domain) { + err = -ENOMEM; + goto free; + } + + pci_add_resource(&bridge->windows, &virt_iomem_resource); + pci_add_resource(&bridge->windows, &busn_resource); + bridge->ops = &um_pci_ops; + bridge->map_irq = um_pci_map_irq; + + for (i = 0; i < MAX_DEVICES; i++) { + resource_size_t start; + + start = virt_cfgspace_resource.start + i * CFG_SPACE_SIZE; + um_pci_devices[i].iomem = ioremap(start, CFG_SPACE_SIZE); + if (WARN(!um_pci_devices[i].iomem, "failed to map %d\n", i)) { + err = -ENOMEM; + goto free; + } + } + + err = pci_host_probe(bridge); + if (err) + goto free; + + err = register_virtio_driver(&um_pci_virtio_driver); + if (err) + goto free; + return 0; +free: + if (um_pci_inner_domain) + irq_domain_remove(um_pci_inner_domain); + if (um_pci_fwnode) + irq_domain_free_fwnode(um_pci_fwnode); + pci_free_resource_list(&bridge->windows); + pci_free_host_bridge(bridge); + return err; +} +module_init(um_pci_init); + +void um_pci_exit(void) +{ + unregister_virtio_driver(&um_pci_virtio_driver); + irq_domain_remove(um_pci_msi_domain); + irq_domain_remove(um_pci_inner_domain); + pci_free_resource_list(&bridge->windows); + pci_free_host_bridge(bridge); +} +module_exit(um_pci_exit); diff --git a/arch/um/drivers/virtio_uml.c b/arch/um/drivers/virtio_uml.c index 91ddf74ca888..4412d6febade 100644 --- a/arch/um/drivers/virtio_uml.c +++ b/arch/um/drivers/virtio_uml.c @@ -56,6 +56,7 @@ struct virtio_uml_device { u8 status; u8 registered:1; u8 suspended:1; + u8 no_vq_suspend:1; u8 config_changed_irq:1; uint64_t vq_irq_vq_map; @@ -1098,6 +1099,19 @@ static void virtio_uml_release_dev(struct device *d) kfree(vu_dev); } +void virtio_uml_set_no_vq_suspend(struct virtio_device *vdev, + bool no_vq_suspend) +{ + struct virtio_uml_device *vu_dev = to_virtio_uml_device(vdev); + + if (WARN_ON(vdev->config != &virtio_uml_config_ops)) + return; + + vu_dev->no_vq_suspend = no_vq_suspend; + dev_info(&vdev->dev, "%sabled VQ suspend\n", + no_vq_suspend ? "dis" : "en"); +} + /* Platform device */ static int virtio_uml_probe(struct platform_device *pdev) @@ -1302,13 +1316,16 @@ MODULE_DEVICE_TABLE(of, virtio_uml_match); static int virtio_uml_suspend(struct platform_device *pdev, pm_message_t state) { struct virtio_uml_device *vu_dev = platform_get_drvdata(pdev); - struct virtqueue *vq; - virtio_device_for_each_vq((&vu_dev->vdev), vq) { - struct virtio_uml_vq_info *info = vq->priv; + if (!vu_dev->no_vq_suspend) { + struct virtqueue *vq; - info->suspended = true; - vhost_user_set_vring_enable(vu_dev, vq->index, false); + virtio_device_for_each_vq((&vu_dev->vdev), vq) { + struct virtio_uml_vq_info *info = vq->priv; + + info->suspended = true; + vhost_user_set_vring_enable(vu_dev, vq->index, false); + } } if (!device_may_wakeup(&vu_dev->vdev.dev)) { @@ -1322,13 +1339,16 @@ static int virtio_uml_suspend(struct platform_device *pdev, pm_message_t state) static int virtio_uml_resume(struct platform_device *pdev) { struct virtio_uml_device *vu_dev = platform_get_drvdata(pdev); - struct virtqueue *vq; - virtio_device_for_each_vq((&vu_dev->vdev), vq) { - struct virtio_uml_vq_info *info = vq->priv; + if (!vu_dev->no_vq_suspend) { + struct virtqueue *vq; + + virtio_device_for_each_vq((&vu_dev->vdev), vq) { + struct virtio_uml_vq_info *info = vq->priv; - info->suspended = false; - vhost_user_set_vring_enable(vu_dev, vq->index, true); + info->suspended = false; + vhost_user_set_vring_enable(vu_dev, vq->index, true); + } } vu_dev->suspended = false; diff --git a/arch/um/include/asm/Kbuild b/arch/um/include/asm/Kbuild index d7492e5a1bbb..e5a7b552bb38 100644 --- a/arch/um/include/asm/Kbuild +++ b/arch/um/include/asm/Kbuild @@ -7,8 +7,8 @@ generic-y += device.h generic-y += emergency-restart.h generic-y += exec.h generic-y += extable.h +generic-y += fb.h generic-y += ftrace.h -generic-y += futex.h generic-y += hw_irq.h generic-y += irq_regs.h generic-y += irq_work.h @@ -17,7 +17,6 @@ generic-y += mcs_spinlock.h generic-y += mmiowb.h generic-y += module.lds.h generic-y += param.h -generic-y += pci.h generic-y += percpu.h generic-y += preempt.h generic-y += softirq_stack.h @@ -27,3 +26,4 @@ generic-y += trace_clock.h generic-y += word-at-a-time.h generic-y += kprobes.h generic-y += mm_hooks.h +generic-y += vga.h diff --git a/arch/um/include/asm/cacheflush.h b/arch/um/include/asm/cacheflush.h new file mode 100644 index 000000000000..4c9858cd36ec --- /dev/null +++ b/arch/um/include/asm/cacheflush.h @@ -0,0 +1,9 @@ +#ifndef __UM_ASM_CACHEFLUSH_H +#define __UM_ASM_CACHEFLUSH_H + +#include <asm/tlbflush.h> +#define flush_cache_vmap flush_tlb_kernel_range +#define flush_cache_vunmap flush_tlb_kernel_range + +#include <asm-generic/cacheflush.h> +#endif /* __UM_ASM_CACHEFLUSH_H */ diff --git a/arch/um/include/asm/cpufeature.h b/arch/um/include/asm/cpufeature.h new file mode 100644 index 000000000000..19cd7ed6ec3c --- /dev/null +++ b/arch/um/include/asm/cpufeature.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_UM_CPUFEATURE_H +#define _ASM_UM_CPUFEATURE_H + +#include <asm/processor.h> + +#if defined(__KERNEL__) && !defined(__ASSEMBLY__) + +#include <asm/asm.h> +#include <linux/bitops.h> + +extern const char * const x86_cap_flags[NCAPINTS*32]; +extern const char * const x86_power_flags[32]; +#define X86_CAP_FMT "%s" +#define x86_cap_flag(flag) x86_cap_flags[flag] + +/* + * In order to save room, we index into this array by doing + * X86_BUG_<name> - NCAPINTS*32. + */ +extern const char * const x86_bug_flags[NBUGINTS*32]; + +#define test_cpu_cap(c, bit) \ + test_bit(bit, (unsigned long *)((c)->x86_capability)) + +/* + * There are 32 bits/features in each mask word. The high bits + * (selected with (bit>>5) give us the word number and the low 5 + * bits give us the bit/feature number inside the word. + * (1UL<<((bit)&31) gives us a mask for the feature_bit so we can + * see if it is set in the mask word. + */ +#define CHECK_BIT_IN_MASK_WORD(maskname, word, bit) \ + (((bit)>>5)==(word) && (1UL<<((bit)&31) & maskname##word )) + +#define cpu_has(c, bit) \ + test_cpu_cap(c, bit) + +#define this_cpu_has(bit) \ + (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ + x86_this_cpu_test_bit(bit, \ + (unsigned long __percpu *)&cpu_info.x86_capability)) + +/* + * This macro is for detection of features which need kernel + * infrastructure to be used. It may *not* directly test the CPU + * itself. Use the cpu_has() family if you want true runtime + * testing of CPU features, like in hypervisor code where you are + * supporting a possible guest feature where host support for it + * is not relevant. + */ +#define cpu_feature_enabled(bit) \ + (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : static_cpu_has(bit)) + +#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) + +#define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability)) + +extern void setup_clear_cpu_cap(unsigned int bit); + +#define setup_force_cpu_cap(bit) do { \ + set_cpu_cap(&boot_cpu_data, bit); \ + set_bit(bit, (unsigned long *)cpu_caps_set); \ +} while (0) + +#define setup_force_cpu_bug(bit) setup_force_cpu_cap(bit) + +#if defined(__clang__) && !defined(CONFIG_CC_HAS_ASM_GOTO) + +/* + * Workaround for the sake of BPF compilation which utilizes kernel + * headers, but clang does not support ASM GOTO and fails the build. + */ +#ifndef __BPF_TRACING__ +#warning "Compiler lacks ASM_GOTO support. Add -D __BPF_TRACING__ to your compiler arguments" +#endif + +#define static_cpu_has(bit) boot_cpu_has(bit) + +#else + +/* + * Static testing of CPU features. Used the same as boot_cpu_has(). It + * statically patches the target code for additional performance. Use + * static_cpu_has() only in fast paths, where every cycle counts. Which + * means that the boot_cpu_has() variant is already fast enough for the + * majority of cases and you should stick to using it as it is generally + * only two instructions: a RIP-relative MOV and a TEST. + */ +static __always_inline bool _static_cpu_has(u16 bit) +{ + asm_volatile_goto("1: jmp 6f\n" + "2:\n" + ".skip -(((5f-4f) - (2b-1b)) > 0) * " + "((5f-4f) - (2b-1b)),0x90\n" + "3:\n" + ".section .altinstructions,\"a\"\n" + " .long 1b - .\n" /* src offset */ + " .long 4f - .\n" /* repl offset */ + " .word %P[always]\n" /* always replace */ + " .byte 3b - 1b\n" /* src len */ + " .byte 5f - 4f\n" /* repl len */ + " .byte 3b - 2b\n" /* pad len */ + ".previous\n" + ".section .altinstr_replacement,\"ax\"\n" + "4: jmp %l[t_no]\n" + "5:\n" + ".previous\n" + ".section .altinstructions,\"a\"\n" + " .long 1b - .\n" /* src offset */ + " .long 0\n" /* no replacement */ + " .word %P[feature]\n" /* feature bit */ + " .byte 3b - 1b\n" /* src len */ + " .byte 0\n" /* repl len */ + " .byte 0\n" /* pad len */ + ".previous\n" + ".section .altinstr_aux,\"ax\"\n" + "6:\n" + " testb %[bitnum],%[cap_byte]\n" + " jnz %l[t_yes]\n" + " jmp %l[t_no]\n" + ".previous\n" + : : [feature] "i" (bit), + [always] "i" (X86_FEATURE_ALWAYS), + [bitnum] "i" (1 << (bit & 7)), + [cap_byte] "m" (((const char *)boot_cpu_data.x86_capability)[bit >> 3]) + : : t_yes, t_no); +t_yes: + return true; +t_no: + return false; +} + +#define static_cpu_has(bit) \ +( \ + __builtin_constant_p(boot_cpu_has(bit)) ? \ + boot_cpu_has(bit) : \ + _static_cpu_has(bit) \ +) +#endif + +#define cpu_has_bug(c, bit) cpu_has(c, (bit)) +#define set_cpu_bug(c, bit) set_cpu_cap(c, (bit)) + +#define static_cpu_has_bug(bit) static_cpu_has((bit)) +#define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit)) +#define boot_cpu_set_bug(bit) set_cpu_cap(&boot_cpu_data, (bit)) + +#define MAX_CPU_FEATURES (NCAPINTS * 32) +#define cpu_have_feature boot_cpu_has + +#define CPU_FEATURE_TYPEFMT "x86,ven%04Xfam%04Xmod%04X" +#define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \ + boot_cpu_data.x86_model + +#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ +#endif /* _ASM_UM_CPUFEATURE_H */ diff --git a/arch/um/include/asm/fpu/api.h b/arch/um/include/asm/fpu/api.h new file mode 100644 index 000000000000..71bfd9ef3938 --- /dev/null +++ b/arch/um/include/asm/fpu/api.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef _ASM_UM_FPU_API_H +#define _ASM_UM_FPU_API_H + +/* Copyright (c) 2020 Cambridge Greys Ltd + * Copyright (c) 2020 Red Hat Inc. + * A set of "dummy" defines to allow the direct inclusion + * of x86 optimized copy, xor, etc routines into the + * UML code tree. */ + +#define kernel_fpu_begin() (void)0 +#define kernel_fpu_end() (void)0 + +static inline bool irq_fpu_usable(void) +{ + return true; +} + + +#endif diff --git a/arch/um/include/asm/futex.h b/arch/um/include/asm/futex.h new file mode 100644 index 000000000000..780aa6bfc050 --- /dev/null +++ b/arch/um/include/asm/futex.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_UM_FUTEX_H +#define _ASM_UM_FUTEX_H + +#include <linux/futex.h> +#include <linux/uaccess.h> +#include <asm/errno.h> + + +int arch_futex_atomic_op_inuser(int op, u32 oparg, int *oval, u32 __user *uaddr); +int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval); + +#endif diff --git a/arch/um/include/asm/io.h b/arch/um/include/asm/io.h index 6ce18d343997..9ea42cc746d9 100644 --- a/arch/um/include/asm/io.h +++ b/arch/um/include/asm/io.h @@ -3,16 +3,23 @@ #define _ASM_UM_IO_H #include <linux/types.h> +/* get emulated iomem (if desired) */ +#include <asm-generic/logic_io.h> + +#ifndef ioremap #define ioremap ioremap static inline void __iomem *ioremap(phys_addr_t offset, size_t size) { return NULL; } +#endif /* ioremap */ +#ifndef iounmap #define iounmap iounmap static inline void iounmap(void __iomem *addr) { } +#endif /* iounmap */ #include <asm-generic/io.h> diff --git a/arch/um/include/asm/irq.h b/arch/um/include/asm/irq.h index 3f5d3e8228fc..e187c789369d 100644 --- a/arch/um/include/asm/irq.h +++ b/arch/um/include/asm/irq.h @@ -31,7 +31,13 @@ #endif -#define NR_IRQS 64 +#define UM_LAST_SIGNAL_IRQ 64 +/* If we have (simulated) PCI MSI, allow 64 more interrupt numbers for it */ +#ifdef CONFIG_PCI_MSI +#define NR_IRQS (UM_LAST_SIGNAL_IRQ + 64) +#else +#define NR_IRQS UM_LAST_SIGNAL_IRQ +#endif /* CONFIG_PCI_MSI */ #include <asm-generic/irq.h> #endif diff --git a/arch/um/include/asm/irqflags.h b/arch/um/include/asm/irqflags.h index 0642ad9035d1..dab5744e9253 100644 --- a/arch/um/include/asm/irqflags.h +++ b/arch/um/include/asm/irqflags.h @@ -2,15 +2,15 @@ #ifndef __UM_IRQFLAGS_H #define __UM_IRQFLAGS_H -extern int get_signals(void); -extern int set_signals(int enable); -extern void block_signals(void); -extern void unblock_signals(void); +extern int signals_enabled; +int set_signals(int enable); +void block_signals(void); +void unblock_signals(void); #define arch_local_save_flags arch_local_save_flags static inline unsigned long arch_local_save_flags(void) { - return get_signals(); + return signals_enabled; } #define arch_local_irq_restore arch_local_irq_restore diff --git a/arch/um/include/asm/msi.h b/arch/um/include/asm/msi.h new file mode 100644 index 000000000000..c8c6c381f394 --- /dev/null +++ b/arch/um/include/asm/msi.h @@ -0,0 +1 @@ +#include <asm-generic/msi.h> diff --git a/arch/um/include/asm/pci.h b/arch/um/include/asm/pci.h new file mode 100644 index 000000000000..da13fd5519ef --- /dev/null +++ b/arch/um/include/asm/pci.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_UM_PCI_H +#define __ASM_UM_PCI_H +#include <linux/types.h> +#include <asm/io.h> + +#define PCIBIOS_MIN_IO 0 +#define PCIBIOS_MIN_MEM 0 + +#define pcibios_assign_all_busses() 1 + +extern int isa_dma_bridge_buggy; + +#ifdef CONFIG_PCI +static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) +{ + /* no legacy IRQs */ + return -ENODEV; +} +#endif + +#ifdef CONFIG_PCI_DOMAINS +static inline int pci_proc_domain(struct pci_bus *bus) +{ + /* always show the domain in /proc */ + return 1; +} +#endif /* CONFIG_PCI */ + +#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN +/* + * This is a bit of an annoying hack, and it assumes we only have + * the virt-pci (if anything). Which is true, but still. + */ +void *pci_root_bus_fwnode(struct pci_bus *bus); +#define pci_root_bus_fwnode pci_root_bus_fwnode +#endif + +#endif /* __ASM_UM_PCI_H */ diff --git a/arch/um/include/asm/pgtable-3level.h b/arch/um/include/asm/pgtable-3level.h index 9289a86643a9..cb896e6121c8 100644 --- a/arch/um/include/asm/pgtable-3level.h +++ b/arch/um/include/asm/pgtable-3level.h @@ -83,7 +83,7 @@ static inline void pud_clear (pud_t *pud) } #define pud_page(pud) phys_to_page(pud_val(pud) & PAGE_MASK) -#define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & PAGE_MASK)) +#define pud_pgtable(pud) ((pmd_t *) __va(pud_val(pud) & PAGE_MASK)) static inline unsigned long pte_pfn(pte_t pte) { diff --git a/arch/um/include/asm/processor-generic.h b/arch/um/include/asm/processor-generic.h index afd9b267cf81..b5cf0ed116d9 100644 --- a/arch/um/include/asm/processor-generic.h +++ b/arch/um/include/asm/processor-generic.h @@ -16,6 +16,8 @@ struct task_struct; #include <linux/prefetch.h> +#include <asm/cpufeatures.h> + struct mm_struct; struct thread_struct { @@ -90,12 +92,18 @@ extern void start_thread(struct pt_regs *regs, unsigned long entry, struct cpuinfo_um { unsigned long loops_per_jiffy; int ipi_pipe[2]; + int cache_alignment; + union { + __u32 x86_capability[NCAPINTS + NBUGINTS]; + unsigned long x86_capability_alignment; + }; }; extern struct cpuinfo_um boot_cpu_data; #define cpu_data (&boot_cpu_data) #define current_cpu_data boot_cpu_data +#define cache_line_size() (boot_cpu_data.cache_alignment) #define KSTK_REG(tsk, reg) get_thread_reg(reg, &tsk->thread.switch_buf) extern unsigned long get_wchan(struct task_struct *p); diff --git a/arch/um/include/asm/tlb.h b/arch/um/include/asm/tlb.h index ff9c62828962..0422467bda5b 100644 --- a/arch/um/include/asm/tlb.h +++ b/arch/um/include/asm/tlb.h @@ -5,7 +5,7 @@ #include <linux/mm.h> #include <asm/tlbflush.h> -#include <asm-generic/cacheflush.h> +#include <asm/cacheflush.h> #include <asm-generic/tlb.h> #endif diff --git a/arch/um/include/asm/xor.h b/arch/um/include/asm/xor.h index 36b33d62a35d..f512704a9ec7 100644 --- a/arch/um/include/asm/xor.h +++ b/arch/um/include/asm/xor.h @@ -1,7 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#include <asm-generic/xor.h> +#ifndef _ASM_UM_XOR_H +#define _ASM_UM_XOR_H + +#ifdef CONFIG_64BIT +#undef CONFIG_X86_32 +#else +#define CONFIG_X86_32 1 +#endif + +#include <asm/cpufeature.h> +#include <../../x86/include/asm/xor.h> #include <linux/time-internal.h> +#ifdef CONFIG_UML_TIME_TRAVEL_SUPPORT +#undef XOR_SELECT_TEMPLATE /* pick an arbitrary one - measuring isn't possible with inf-cpu */ #define XOR_SELECT_TEMPLATE(x) \ (time_travel_mode == TT_MODE_INFCPU ? &xor_block_8regs : NULL) +#endif + +#endif diff --git a/arch/um/include/linux/time-internal.h b/arch/um/include/linux/time-internal.h index 759956ab0108..b22226634ff6 100644 --- a/arch/um/include/linux/time-internal.h +++ b/arch/um/include/linux/time-internal.h @@ -8,17 +8,11 @@ #define __TIMER_INTERNAL_H__ #include <linux/list.h> #include <asm/bug.h> +#include <shared/timetravel.h> #define TIMER_MULTIPLIER 256 #define TIMER_MIN_DELTA 500 -enum time_travel_mode { - TT_MODE_OFF, - TT_MODE_BASIC, - TT_MODE_INFCPU, - TT_MODE_EXTERNAL, -}; - #ifdef CONFIG_UML_TIME_TRAVEL_SUPPORT struct time_travel_event { unsigned long long time; @@ -27,8 +21,6 @@ struct time_travel_event { bool pending, onstack; }; -extern enum time_travel_mode time_travel_mode; - void time_travel_sleep(void); static inline void @@ -62,8 +54,6 @@ bool time_travel_del_event(struct time_travel_event *e); struct time_travel_event { }; -#define time_travel_mode TT_MODE_OFF - static inline void time_travel_sleep(void) { } diff --git a/arch/um/include/linux/virtio-uml.h b/arch/um/include/linux/virtio-uml.h new file mode 100644 index 000000000000..2f652fa90f04 --- /dev/null +++ b/arch/um/include/linux/virtio-uml.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Intel Corporation + * Author: Johannes Berg <johannes@sipsolutions.net> + */ + +#ifndef __VIRTIO_UML_H__ +#define __VIRTIO_UML_H__ + +void virtio_uml_set_no_vq_suspend(struct virtio_device *vdev, + bool no_vq_suspend); + +#endif /* __VIRTIO_UML_H__ */ diff --git a/arch/um/include/shared/irq_user.h b/arch/um/include/shared/irq_user.h index 07239e801a5b..065829f443ae 100644 --- a/arch/um/include/shared/irq_user.h +++ b/arch/um/include/shared/irq_user.h @@ -17,6 +17,7 @@ enum um_irq_type { struct siginfo; extern void sigio_handler(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs); +void sigio_run_timetravel_handlers(void); extern void free_irq_by_fd(int fd); extern void deactivate_fd(int fd, int irqnum); extern int deactivate_all_fds(void); diff --git a/arch/um/include/shared/kern_util.h b/arch/um/include/shared/kern_util.h index 2888ec812f6e..a2cfd42608a0 100644 --- a/arch/um/include/shared/kern_util.h +++ b/arch/um/include/shared/kern_util.h @@ -33,7 +33,6 @@ extern int handle_page_fault(unsigned long address, unsigned long ip, int is_write, int is_user, int *code_out); extern unsigned int do_IRQ(int irq, struct uml_pt_regs *regs); -extern int smp_sigio_handler(void); extern void initial_thread_cb(void (*proc)(void *), void *arg); extern int is_syscall(unsigned long addr); diff --git a/arch/um/include/shared/longjmp.h b/arch/um/include/shared/longjmp.h index 85a1cc290ecb..bdb2869b72b3 100644 --- a/arch/um/include/shared/longjmp.h +++ b/arch/um/include/shared/longjmp.h @@ -5,6 +5,7 @@ #include <sysdep/archsetjmp.h> #include <os.h> +extern int signals_enabled; extern int setjmp(jmp_buf); extern void longjmp(jmp_buf, int); @@ -12,13 +13,12 @@ extern void longjmp(jmp_buf, int); longjmp(*buf, val); \ } while(0) -#define UML_SETJMP(buf) ({ \ - int n; \ - volatile int enable; \ - enable = get_signals(); \ - n = setjmp(*buf); \ - if(n != 0) \ - set_signals_trace(enable); \ +#define UML_SETJMP(buf) ({ \ + int n, enable; \ + enable = *(volatile int *)&signals_enabled; \ + n = setjmp(*buf); \ + if(n != 0) \ + set_signals_trace(enable); \ n; }) #endif diff --git a/arch/um/include/shared/os.h b/arch/um/include/shared/os.h index 13d86f94cf0f..60b84edc8a68 100644 --- a/arch/um/include/shared/os.h +++ b/arch/um/include/shared/os.h @@ -187,6 +187,9 @@ int os_poll(unsigned int n, const int *fds); extern void os_early_checks(void); extern void os_check_bugs(void); extern void check_host_supports_tls(int *supports_tls, int *tls_min); +extern void get_host_cpu_features( + void (*flags_helper_func)(char *line), + void (*cache_helper_func)(char *line)); /* mem.c */ extern int create_mem_file(unsigned long long len); @@ -211,7 +214,6 @@ extern int os_protect_memory(void *addr, unsigned long len, extern int os_unmap_memory(void *addr, int len); extern int os_drop_memory(void *addr, int length); extern int can_drop_memory(void); -extern void os_flush_stdout(void); extern int os_mincore(void *addr, unsigned long len); /* execvp.c */ @@ -237,12 +239,14 @@ extern void send_sigio_to_self(void); extern int change_sig(int signal, int on); extern void block_signals(void); extern void unblock_signals(void); -extern int get_signals(void); extern int set_signals(int enable); extern int set_signals_trace(int enable); extern int os_is_signal_stack(void); extern void deliver_alarm(void); extern void register_pm_wake_signal(void); +extern void block_signals_hard(void); +extern void unblock_signals_hard(void); +extern void mark_sigio_pending(void); /* util.c */ extern void stack_protections(unsigned long address); diff --git a/arch/um/include/shared/timetravel.h b/arch/um/include/shared/timetravel.h new file mode 100644 index 000000000000..e5c3d69f1b69 --- /dev/null +++ b/arch/um/include/shared/timetravel.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019-2021 Intel Corporation + */ +#ifndef _UM_TIME_TRAVEL_H_ +#define _UM_TIME_TRAVEL_H_ + +enum time_travel_mode { + TT_MODE_OFF, + TT_MODE_BASIC, + TT_MODE_INFCPU, + TT_MODE_EXTERNAL, +}; + +#if defined(UML_CONFIG_UML_TIME_TRAVEL_SUPPORT) || \ + defined(CONFIG_UML_TIME_TRAVEL_SUPPORT) +extern enum time_travel_mode time_travel_mode; +#else +#define time_travel_mode TT_MODE_OFF +#endif /* (UML_)CONFIG_UML_TIME_TRAVEL_SUPPORT */ + +#endif /* _UM_TIME_TRAVEL_H_ */ diff --git a/arch/um/kernel/Makefile b/arch/um/kernel/Makefile index e698e0c7dbdc..1d18e4e46989 100644 --- a/arch/um/kernel/Makefile +++ b/arch/um/kernel/Makefile @@ -17,18 +17,19 @@ extra-y := vmlinux.lds obj-y = config.o exec.o exitcode.o irq.o ksyms.o mem.o \ physmem.o process.o ptrace.o reboot.o sigio.o \ signal.o syscall.o sysrq.o time.o tlb.o trap.o \ - um_arch.o umid.o maccess.o kmsg_dump.o skas/ + um_arch.o umid.o maccess.o kmsg_dump.o capflags.o skas/ obj-$(CONFIG_BLK_DEV_INITRD) += initrd.o obj-$(CONFIG_GPROF) += gprof_syms.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_STACKTRACE) += stacktrace.o +obj-$(CONFIG_GENERIC_PCI_IOMAP) += ioport.o USER_OBJS := config.o include arch/um/scripts/Makefile.rules -targets := config.c config.tmp +targets := config.c config.tmp capflags.c # Be careful with the below Sed code - sed is pitfall-rich! # We use sed to lower build requirements, for "embedded" builders for instance. @@ -43,6 +44,15 @@ quiet_cmd_quote1 = QUOTE $@ $(obj)/config.c: $(src)/config.c.in $(obj)/config.tmp FORCE $(call if_changed,quote2) +quiet_cmd_mkcapflags = MKCAP $@ + cmd_mkcapflags = $(CONFIG_SHELL) $(srctree)/$(src)/../../x86/kernel/cpu/mkcapflags.sh $@ $^ + +cpufeature = $(src)/../../x86/include/asm/cpufeatures.h +vmxfeature = $(src)/../../x86/include/asm/vmxfeatures.h + +$(obj)/capflags.c: $(cpufeature) $(vmxfeature) $(src)/../../x86/kernel/cpu/mkcapflags.sh FORCE + $(call if_changed,mkcapflags) + quiet_cmd_quote2 = QUOTE $@ cmd_quote2 = sed -e '/CONFIG/{' \ -e 's/"CONFIG"//' \ diff --git a/arch/um/kernel/ioport.c b/arch/um/kernel/ioport.c new file mode 100644 index 000000000000..7220615b3beb --- /dev/null +++ b/arch/um/kernel/ioport.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Intel Corporation + * Author: Johannes Berg <johannes@sipsolutions.net> + */ +#include <asm/iomap.h> +#include <asm-generic/pci_iomap.h> + +void __iomem *__pci_ioport_map(struct pci_dev *dev, unsigned long port, + unsigned int nr) +{ + return NULL; +} diff --git a/arch/um/kernel/irq.c b/arch/um/kernel/irq.c index 82af5191e73d..a8873d9bc28b 100644 --- a/arch/um/kernel/irq.c +++ b/arch/um/kernel/irq.c @@ -56,7 +56,7 @@ struct irq_entry { static DEFINE_SPINLOCK(irq_lock); static LIST_HEAD(active_fds); -static DECLARE_BITMAP(irqs_allocated, NR_IRQS); +static DECLARE_BITMAP(irqs_allocated, UM_LAST_SIGNAL_IRQ); static bool irqs_suspended; static void irq_io_loop(struct irq_reg *irq, struct uml_pt_regs *regs) @@ -101,10 +101,12 @@ static bool irq_do_timetravel_handler(struct irq_entry *entry, if (!reg->timetravel_handler) return false; - /* prevent nesting - we'll get it again later when we SIGIO ourselves */ - if (reg->pending_on_resume) - return true; - + /* + * Handle all messages - we might get multiple even while + * interrupts are already suspended, due to suspend order + * etc. Note that time_travel_add_irq_event() will not add + * an event twice, if it's pending already "first wins". + */ reg->timetravel_handler(reg->irq, entry->fd, reg->id, ®->event); if (!reg->event.pending) @@ -123,7 +125,8 @@ static bool irq_do_timetravel_handler(struct irq_entry *entry, #endif static void sigio_reg_handler(int idx, struct irq_entry *entry, enum um_irq_type t, - struct uml_pt_regs *regs) + struct uml_pt_regs *regs, + bool timetravel_handlers_only) { struct irq_reg *reg = &entry->reg[t]; @@ -136,18 +139,29 @@ static void sigio_reg_handler(int idx, struct irq_entry *entry, enum um_irq_type if (irq_do_timetravel_handler(entry, t)) return; - if (irqs_suspended) + /* + * If we're called to only run time-travel handlers then don't + * actually proceed but mark sigio as pending (if applicable). + * For suspend/resume, timetravel_handlers_only may be true + * despite time-travel not being configured and used. + */ + if (timetravel_handlers_only) { +#ifdef CONFIG_UML_TIME_TRAVEL_SUPPORT + mark_sigio_pending(); +#endif return; + } irq_io_loop(reg, regs); } -void sigio_handler(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs) +static void _sigio_handler(struct uml_pt_regs *regs, + bool timetravel_handlers_only) { struct irq_entry *irq_entry; int n, i; - if (irqs_suspended && !um_irq_timetravel_handler_used()) + if (timetravel_handlers_only && !um_irq_timetravel_handler_used()) return; while (1) { @@ -172,14 +186,20 @@ void sigio_handler(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs) irq_entry = os_epoll_get_data_pointer(i); for (t = 0; t < NUM_IRQ_TYPES; t++) - sigio_reg_handler(i, irq_entry, t, regs); + sigio_reg_handler(i, irq_entry, t, regs, + timetravel_handlers_only); } } - if (!irqs_suspended) + if (!timetravel_handlers_only) free_irqs(); } +void sigio_handler(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs) +{ + _sigio_handler(regs, irqs_suspended); +} + static struct irq_entry *get_irq_entry_by_fd(int fd) { struct irq_entry *walk; @@ -399,7 +419,8 @@ unsigned int do_IRQ(int irq, struct uml_pt_regs *regs) void um_free_irq(int irq, void *dev) { - if (WARN(irq < 0 || irq > NR_IRQS, "freeing invalid irq %d", irq)) + if (WARN(irq < 0 || irq > UM_LAST_SIGNAL_IRQ, + "freeing invalid irq %d", irq)) return; free_irq_by_irq_and_dev(irq, dev); @@ -467,6 +488,11 @@ int um_request_irq_tt(int irq, int fd, enum um_irq_type type, devname, dev_id, timetravel_handler); } EXPORT_SYMBOL(um_request_irq_tt); + +void sigio_run_timetravel_handlers(void) +{ + _sigio_handler(NULL, true); +} #endif #ifdef CONFIG_PM_SLEEP @@ -623,7 +649,7 @@ void __init init_IRQ(void) irq_set_chip_and_handler(TIMER_IRQ, &alarm_irq_type, handle_edge_irq); - for (i = 1; i < NR_IRQS; i++) + for (i = 1; i < UM_LAST_SIGNAL_IRQ; i++) irq_set_chip_and_handler(i, &normal_irq_type, handle_edge_irq); /* Initialize EPOLL Loop */ os_setup_epoll(); diff --git a/arch/um/kernel/ksyms.c b/arch/um/kernel/ksyms.c index 8ade54a86a7e..b1e5634398d0 100644 --- a/arch/um/kernel/ksyms.c +++ b/arch/um/kernel/ksyms.c @@ -7,7 +7,7 @@ #include <os.h> EXPORT_SYMBOL(set_signals); -EXPORT_SYMBOL(get_signals); +EXPORT_SYMBOL(signals_enabled); EXPORT_SYMBOL(os_stat_fd); EXPORT_SYMBOL(os_stat_file); diff --git a/arch/um/kernel/skas/clone.c b/arch/um/kernel/skas/clone.c index 592cdb138441..5afac0fef24e 100644 --- a/arch/um/kernel/skas/clone.c +++ b/arch/um/kernel/skas/clone.c @@ -29,7 +29,7 @@ stub_clone_handler(void) long err; err = stub_syscall2(__NR_clone, CLONE_PARENT | CLONE_FILES | SIGCHLD, - (unsigned long)data + UM_KERN_PAGE_SIZE / 2 - sizeof(void *)); + (unsigned long)data + UM_KERN_PAGE_SIZE / 2); if (err) { data->parent_err = err; goto done; diff --git a/arch/um/kernel/skas/uaccess.c b/arch/um/kernel/skas/uaccess.c index 2dec915abe6f..6c76df96e858 100644 --- a/arch/um/kernel/skas/uaccess.c +++ b/arch/um/kernel/skas/uaccess.c @@ -11,6 +11,7 @@ #include <asm/current.h> #include <asm/page.h> #include <kern_util.h> +#include <asm/futex.h> #include <os.h> pte_t *virt_to_pte(struct mm_struct *mm, unsigned long addr) @@ -248,3 +249,138 @@ long __strnlen_user(const void __user *str, long len) return 0; } EXPORT_SYMBOL(__strnlen_user); + +/** + * arch_futex_atomic_op_inuser() - Atomic arithmetic operation with constant + * argument and comparison of the previous + * futex value with another constant. + * + * @encoded_op: encoded operation to execute + * @uaddr: pointer to user space address + * + * Return: + * 0 - On success + * -EFAULT - User access resulted in a page fault + * -EAGAIN - Atomic operation was unable to complete due to contention + * -ENOSYS - Operation not supported + */ + +int arch_futex_atomic_op_inuser(int op, u32 oparg, int *oval, u32 __user *uaddr) +{ + int oldval, ret; + struct page *page; + unsigned long addr = (unsigned long) uaddr; + pte_t *pte; + + ret = -EFAULT; + if (!access_ok(uaddr, sizeof(*uaddr))) + return -EFAULT; + preempt_disable(); + pte = maybe_map(addr, 1); + if (pte == NULL) + goto out_inuser; + + page = pte_page(*pte); +#ifdef CONFIG_64BIT + pagefault_disable(); + addr = (unsigned long) page_address(page) + + (((unsigned long) addr) & ~PAGE_MASK); +#else + addr = (unsigned long) kmap_atomic(page) + + ((unsigned long) addr & ~PAGE_MASK); +#endif + uaddr = (u32 *) addr; + oldval = *uaddr; + + ret = 0; + + switch (op) { + case FUTEX_OP_SET: + *uaddr = oparg; + break; + case FUTEX_OP_ADD: + *uaddr += oparg; + break; + case FUTEX_OP_OR: + *uaddr |= oparg; + break; + case FUTEX_OP_ANDN: + *uaddr &= ~oparg; + break; + case FUTEX_OP_XOR: + *uaddr ^= oparg; + break; + default: + ret = -ENOSYS; + } +#ifdef CONFIG_64BIT + pagefault_enable(); +#else + kunmap_atomic((void *)addr); +#endif + +out_inuser: + preempt_enable(); + + if (ret == 0) + *oval = oldval; + + return ret; +} +EXPORT_SYMBOL(arch_futex_atomic_op_inuser); + +/** + * futex_atomic_cmpxchg_inatomic() - Compare and exchange the content of the + * uaddr with newval if the current value is + * oldval. + * @uval: pointer to store content of @uaddr + * @uaddr: pointer to user space address + * @oldval: old value + * @newval: new value to store to @uaddr + * + * Return: + * 0 - On success + * -EFAULT - User access resulted in a page fault + * -EAGAIN - Atomic operation was unable to complete due to contention + * -ENOSYS - Function not implemented (only if !HAVE_FUTEX_CMPXCHG) + */ + +int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, + u32 oldval, u32 newval) +{ + struct page *page; + pte_t *pte; + int ret = -EFAULT; + + if (!access_ok(uaddr, sizeof(*uaddr))) + return -EFAULT; + + preempt_disable(); + pte = maybe_map((unsigned long) uaddr, 1); + if (pte == NULL) + goto out_inatomic; + + page = pte_page(*pte); +#ifdef CONFIG_64BIT + pagefault_disable(); + uaddr = page_address(page) + (((unsigned long) uaddr) & ~PAGE_MASK); +#else + uaddr = kmap_atomic(page) + ((unsigned long) uaddr & ~PAGE_MASK); +#endif + + *uval = *uaddr; + + ret = cmpxchg(uaddr, oldval, newval); + +#ifdef CONFIG_64BIT + pagefault_enable(); +#else + kunmap_atomic(uaddr); +#endif + ret = 0; + +out_inatomic: + preempt_enable(); + return ret; +} +EXPORT_SYMBOL(futex_atomic_cmpxchg_inatomic); diff --git a/arch/um/kernel/time.c b/arch/um/kernel/time.c index e0cdb9694fb8..fddd1dec27e6 100644 --- a/arch/um/kernel/time.c +++ b/arch/um/kernel/time.c @@ -68,23 +68,15 @@ static void time_travel_handle_message(struct um_timetravel_msg *msg, int ret; /* - * Poll outside the locked section (if we're not called to only read - * the response) so we can get interrupts for e.g. virtio while we're - * here, but then we need to lock to not get interrupted between the - * read of the message and write of the ACK. + * We can't unlock here, but interrupt signals with a timetravel_handler + * (see um_request_irq_tt) get to the timetravel_handler anyway. */ if (mode != TTMH_READ) { - bool disabled = irqs_disabled(); + BUG_ON(mode == TTMH_IDLE && !irqs_disabled()); - BUG_ON(mode == TTMH_IDLE && !disabled); - - if (disabled) - local_irq_enable(); while (os_poll(1, &time_travel_ext_fd) != 0) { /* nothing */ } - if (disabled) - local_irq_disable(); } ret = os_read_file(time_travel_ext_fd, msg, sizeof(*msg)); @@ -123,15 +115,15 @@ static u64 time_travel_ext_req(u32 op, u64 time) .time = time, .seq = mseq, }; - unsigned long flags; /* - * We need to save interrupts here and only restore when we - * got the ACK - otherwise we can get interrupted and send - * another request while we're still waiting for an ACK, but - * the peer doesn't know we got interrupted and will send - * the ACKs in the same order as the message, but we'd need - * to see them in the opposite order ... + * We need to block even the timetravel handlers of SIGIO here and + * only restore their use when we got the ACK - otherwise we may + * (will) get interrupted by that, try to queue the IRQ for future + * processing and thus send another request while we're still waiting + * for an ACK, but the peer doesn't know we got interrupted and will + * send the ACKs in the same order as the message, but we'd need to + * see them in the opposite order ... * * This wouldn't matter *too* much, but some ACKs carry the * current time (for UM_TIMETRAVEL_GET) and getting another @@ -140,7 +132,7 @@ static u64 time_travel_ext_req(u32 op, u64 time) * The sequence number assignment that happens here lets us * debug such message handling issues more easily. */ - local_irq_save(flags); + block_signals_hard(); os_write_file(time_travel_ext_fd, &msg, sizeof(msg)); while (msg.op != UM_TIMETRAVEL_ACK) @@ -152,7 +144,7 @@ static u64 time_travel_ext_req(u32 op, u64 time) if (op == UM_TIMETRAVEL_GET) time_travel_set_time(msg.time); - local_irq_restore(flags); + unblock_signals_hard(); return msg.time; } @@ -352,9 +344,6 @@ void deliver_time_travel_irqs(void) while ((e = list_first_entry_or_null(&time_travel_irqs, struct time_travel_event, list))) { - WARN(e->time != time_travel_time, - "time moved from %lld to %lld before IRQ delivery\n", - time_travel_time, e->time); list_del(&e->list); e->pending = false; e->fn(e); diff --git a/arch/um/kernel/um_arch.c b/arch/um/kernel/um_arch.c index 9512253947d5..a149a5e9a16a 100644 --- a/arch/um/kernel/um_arch.c +++ b/arch/um/kernel/um_arch.c @@ -6,6 +6,7 @@ #include <linux/delay.h> #include <linux/init.h> #include <linux/mm.h> +#include <linux/ctype.h> #include <linux/module.h> #include <linux/panic_notifier.h> #include <linux/seq_file.h> @@ -17,6 +18,7 @@ #include <linux/suspend.h> #include <asm/processor.h> +#include <asm/cpufeature.h> #include <asm/sections.h> #include <asm/setup.h> #include <as-layout.h> @@ -51,9 +53,13 @@ static void __init add_arg(char *arg) */ struct cpuinfo_um boot_cpu_data = { .loops_per_jiffy = 0, - .ipi_pipe = { -1, -1 } + .ipi_pipe = { -1, -1 }, + .cache_alignment = L1_CACHE_BYTES, + .x86_capability = { 0 } }; +EXPORT_SYMBOL(boot_cpu_data); + union thread_union cpu0_irqstack __section(".data..init_irqstack") = { .thread_info = INIT_THREAD_INFO(init_task) }; @@ -63,17 +69,25 @@ static char host_info[(__NEW_UTS_LEN + 1) * 5]; static int show_cpuinfo(struct seq_file *m, void *v) { - int index = 0; + int i = 0; - seq_printf(m, "processor\t: %d\n", index); + seq_printf(m, "processor\t: %d\n", i); seq_printf(m, "vendor_id\t: User Mode Linux\n"); seq_printf(m, "model name\t: UML\n"); seq_printf(m, "mode\t\t: skas\n"); seq_printf(m, "host\t\t: %s\n", host_info); - seq_printf(m, "bogomips\t: %lu.%02lu\n\n", + seq_printf(m, "fpu\t\t: %s\n", cpu_has(&boot_cpu_data, X86_FEATURE_FPU) ? "yes" : "no"); + seq_printf(m, "flags\t\t:"); + for (i = 0; i < 32*NCAPINTS; i++) + if (cpu_has(&boot_cpu_data, i) && (x86_cap_flags[i] != NULL)) + seq_printf(m, " %s", x86_cap_flags[i]); + seq_printf(m, "\n"); + seq_printf(m, "cache_alignment\t: %d\n", boot_cpu_data.cache_alignment); + seq_printf(m, "bogomips\t: %lu.%02lu\n", loops_per_jiffy/(500000/HZ), (loops_per_jiffy/(5000/HZ)) % 100); + return 0; } @@ -262,6 +276,30 @@ EXPORT_SYMBOL(end_iomem); #define MIN_VMALLOC (32 * 1024 * 1024) +static void parse_host_cpu_flags(char *line) +{ + int i; + for (i = 0; i < 32*NCAPINTS; i++) { + if ((x86_cap_flags[i] != NULL) && strstr(line, x86_cap_flags[i])) + set_cpu_cap(&boot_cpu_data, i); + } +} +static void parse_cache_line(char *line) +{ + long res; + char *to_parse = strstr(line, ":"); + if (to_parse) { + to_parse++; + while (*to_parse != 0 && isspace(*to_parse)) { + to_parse++; + } + if (kstrtoul(to_parse, 10, &res) == 0 && is_power_of_2(res)) + boot_cpu_data.cache_alignment = res; + else + boot_cpu_data.cache_alignment = L1_CACHE_BYTES; + } +} + int __init linux_main(int argc, char **argv) { unsigned long avail, diff; @@ -298,6 +336,8 @@ int __init linux_main(int argc, char **argv) /* OS sanity checks that need to happen before the kernel runs */ os_early_checks(); + get_host_cpu_features(parse_host_cpu_flags, parse_cache_line); + brk_start = (unsigned long) sbrk(0); /* diff --git a/arch/um/os-Linux/helper.c b/arch/um/os-Linux/helper.c index 9fa6e4187d4f..32e88baf18dd 100644 --- a/arch/um/os-Linux/helper.c +++ b/arch/um/os-Linux/helper.c @@ -64,7 +64,7 @@ int run_helper(void (*pre_exec)(void *), void *pre_data, char **argv) goto out_close; } - sp = stack + UM_KERN_PAGE_SIZE - sizeof(void *); + sp = stack + UM_KERN_PAGE_SIZE; data.pre_exec = pre_exec; data.pre_data = pre_data; data.argv = argv; @@ -120,7 +120,7 @@ int run_helper_thread(int (*proc)(void *), void *arg, unsigned int flags, if (stack == 0) return -ENOMEM; - sp = stack + UM_KERN_PAGE_SIZE - sizeof(void *); + sp = stack + UM_KERN_PAGE_SIZE; pid = clone(proc, (void *) sp, flags, arg); if (pid < 0) { err = -errno; diff --git a/arch/um/os-Linux/signal.c b/arch/um/os-Linux/signal.c index 96f511d1aabe..6de99bb16113 100644 --- a/arch/um/os-Linux/signal.c +++ b/arch/um/os-Linux/signal.c @@ -18,6 +18,7 @@ #include <sysdep/mcontext.h> #include <um_malloc.h> #include <sys/ucontext.h> +#include <timetravel.h> void (*sig_info[NSIG])(int, struct siginfo *, struct uml_pt_regs *) = { [SIGTRAP] = relay_signal, @@ -62,17 +63,30 @@ static void sig_handler_common(int sig, struct siginfo *si, mcontext_t *mc) #define SIGALRM_BIT 1 #define SIGALRM_MASK (1 << SIGALRM_BIT) -static int signals_enabled; +int signals_enabled; +#ifdef UML_CONFIG_UML_TIME_TRAVEL_SUPPORT +static int signals_blocked; +#else +#define signals_blocked false +#endif static unsigned int signals_pending; static unsigned int signals_active = 0; void sig_handler(int sig, struct siginfo *si, mcontext_t *mc) { - int enabled; + int enabled = signals_enabled; - enabled = signals_enabled; - if (!enabled && (sig == SIGIO)) { - signals_pending |= SIGIO_MASK; + if ((signals_blocked || !enabled) && (sig == SIGIO)) { + /* + * In TT_MODE_EXTERNAL, need to still call time-travel + * handlers unless signals are also blocked for the + * external time message processing. This will mark + * signals_pending by itself (only if necessary.) + */ + if (!signals_blocked && time_travel_mode == TT_MODE_EXTERNAL) + sigio_run_timetravel_handlers(); + else + signals_pending |= SIGIO_MASK; return; } @@ -129,7 +143,7 @@ void set_sigstack(void *sig_stack, int size) stack_t stack = { .ss_flags = 0, .ss_sp = sig_stack, - .ss_size = size - sizeof(void *) + .ss_size = size }; if (sigaltstack(&stack, NULL) != 0) @@ -334,11 +348,6 @@ void unblock_signals(void) } } -int get_signals(void) -{ - return signals_enabled; -} - int set_signals(int enable) { int ret; @@ -368,6 +377,39 @@ int set_signals_trace(int enable) return ret; } +#ifdef UML_CONFIG_UML_TIME_TRAVEL_SUPPORT +void mark_sigio_pending(void) +{ + signals_pending |= SIGIO_MASK; +} + +void block_signals_hard(void) +{ + if (signals_blocked) + return; + signals_blocked = 1; + barrier(); +} + +void unblock_signals_hard(void) +{ + if (!signals_blocked) + return; + /* Must be set to 0 before we check the pending bits etc. */ + signals_blocked = 0; + barrier(); + + if (signals_pending && signals_enabled) { + /* this is a bit inefficient, but that's not really important */ + block_signals(); + unblock_signals(); + } else if (signals_pending & SIGIO_MASK) { + /* we need to run time-travel handlers even if not enabled */ + sigio_run_timetravel_handlers(); + } +} +#endif + int os_is_signal_stack(void) { stack_t ss; diff --git a/arch/um/os-Linux/skas/process.c b/arch/um/os-Linux/skas/process.c index fba674fac8b7..87d3129e7362 100644 --- a/arch/um/os-Linux/skas/process.c +++ b/arch/um/os-Linux/skas/process.c @@ -327,7 +327,7 @@ int start_userspace(unsigned long stub_stack) } /* set stack pointer to the end of the stack page, so it can grow downwards */ - sp = (unsigned long) stack + UM_KERN_PAGE_SIZE - sizeof(void *); + sp = (unsigned long)stack + UM_KERN_PAGE_SIZE; flags = CLONE_FILES | SIGCHLD; diff --git a/arch/um/os-Linux/start_up.c b/arch/um/os-Linux/start_up.c index f79dc338279e..8a72c99994eb 100644 --- a/arch/um/os-Linux/start_up.c +++ b/arch/um/os-Linux/start_up.c @@ -321,6 +321,38 @@ static void __init check_coredump_limit(void) os_info("%llu\n", (unsigned long long)lim.rlim_max); } +void __init get_host_cpu_features( + void (*flags_helper_func)(char *line), + void (*cache_helper_func)(char *line)) +{ + FILE *cpuinfo; + char *line = NULL; + size_t len = 0; + int done_parsing = 0; + + cpuinfo = fopen("/proc/cpuinfo", "r"); + if (cpuinfo == NULL) { + os_info("Failed to get host CPU features\n"); + } else { + while ((getline(&line, &len, cpuinfo)) != -1) { + if (strstr(line, "flags")) { + flags_helper_func(line); + done_parsing++; + } + if (strstr(line, "cache_alignment")) { + cache_helper_func(line); + done_parsing++; + } + free(line); + line = NULL; + if (done_parsing > 1) + break; + } + fclose(cpuinfo); + } +} + + void __init os_early_checks(void) { int pid; diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 53eceaf71ab7..307fd0000a83 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -240,9 +240,6 @@ head-y += arch/x86/kernel/platform-quirks.o libs-y += arch/x86/lib/ -# See arch/x86/Kbuild for content of core part of the kernel -core-y += arch/x86/ - # drivers-y are linked after core-y drivers-$(CONFIG_MATH_EMULATION) += arch/x86/math-emu/ drivers-$(CONFIG_PCI) += arch/x86/pci/ diff --git a/arch/x86/Makefile.um b/arch/x86/Makefile.um index 1db7913795f5..b3c1ae084180 100644 --- a/arch/x86/Makefile.um +++ b/arch/x86/Makefile.um @@ -44,7 +44,7 @@ ELF_FORMAT := elf64-x86-64 # Not on all 64-bit distros /lib is a symlink to /lib64. PLD is an example. -LINK-$(CONFIG_LD_SCRIPT_DYN) += -Wl,-rpath,/lib64 +LINK-$(CONFIG_LD_SCRIPT_DYN_RPATH) += -Wl,-rpath,/lib64 LINK-y += -m64 endif diff --git a/arch/x86/entry/syscalls/syscall_32.tbl b/arch/x86/entry/syscalls/syscall_32.tbl index fba2f615119a..ce763a12311c 100644 --- a/arch/x86/entry/syscalls/syscall_32.tbl +++ b/arch/x86/entry/syscalls/syscall_32.tbl @@ -451,3 +451,4 @@ 444 i386 landlock_create_ruleset sys_landlock_create_ruleset 445 i386 landlock_add_rule sys_landlock_add_rule 446 i386 landlock_restrict_self sys_landlock_restrict_self +447 i386 memfd_secret sys_memfd_secret diff --git a/arch/x86/entry/syscalls/syscall_64.tbl b/arch/x86/entry/syscalls/syscall_64.tbl index af973e400053..f6b57799c1ea 100644 --- a/arch/x86/entry/syscalls/syscall_64.tbl +++ b/arch/x86/entry/syscalls/syscall_64.tbl @@ -368,6 +368,7 @@ 444 common landlock_create_ruleset sys_landlock_create_ruleset 445 common landlock_add_rule sys_landlock_add_rule 446 common landlock_restrict_self sys_landlock_restrict_self +447 common memfd_secret sys_memfd_secret # # Due to a historical design error, certain syscalls are numbered differently diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index 433399069e27..c6262b154c3a 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -40,7 +40,7 @@ * Model specific counters: * MSR_CORE_C1_RES: CORE C1 Residency Counter * perf code: 0x00 - * Available model: SLM,AMT,GLM,CNL,TNT,ADL + * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL * Scope: Core (each processor core has a MSR) * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter * perf code: 0x01 @@ -50,8 +50,8 @@ * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter * perf code: 0x02 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, - * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL, - * TNT,RKL,ADL + * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, + * TGL,TNT,RKL,ADL * Scope: Core * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter * perf code: 0x03 @@ -61,7 +61,7 @@ * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. * perf code: 0x00 * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, - * KBL,CML,ICL,TGL,TNT,RKL,ADL + * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL * Scope: Package (physical package) * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. * perf code: 0x01 @@ -72,8 +72,8 @@ * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. * perf code: 0x02 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, - * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL, - * TNT,RKL,ADL + * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, + * TGL,TNT,RKL,ADL * Scope: Package (physical package) * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. * perf code: 0x03 @@ -566,6 +566,14 @@ static const struct cstate_model icl_cstates __initconst = { BIT(PERF_CSTATE_PKG_C10_RES), }; +static const struct cstate_model icx_cstates __initconst = { + .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | + BIT(PERF_CSTATE_CORE_C6_RES), + + .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | + BIT(PERF_CSTATE_PKG_C6_RES), +}; + static const struct cstate_model adl_cstates __initconst = { .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | BIT(PERF_CSTATE_CORE_C6_RES) | @@ -664,6 +672,9 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_cstates), X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &icl_cstates), + X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &icx_cstates), + X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &icx_cstates), + X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &icl_cstates), X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &icl_cstates), X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &icl_cstates), diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index bb6eb1e5569c..609c24aec71a 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -3804,11 +3804,11 @@ pmu_iio_set_mapping(struct intel_uncore_type *type, struct attribute_group *ag) /* One more for NULL. */ attrs = kcalloc((uncore_max_dies() + 1), sizeof(*attrs), GFP_KERNEL); if (!attrs) - goto err; + goto clear_topology; eas = kcalloc(uncore_max_dies(), sizeof(*eas), GFP_KERNEL); if (!eas) - goto err; + goto clear_attrs; for (die = 0; die < uncore_max_dies(); die++) { sprintf(buf, "die%ld", die); @@ -3829,7 +3829,9 @@ err: for (; die >= 0; die--) kfree(eas[die].attr.attr.name); kfree(eas); +clear_attrs: kfree(attrs); +clear_topology: kfree(type->topology); clear_attr_update: type->attr_update = NULL; diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h index ec0d8e106646..448cd01eb3ec 100644 --- a/arch/x86/include/asm/pgtable.h +++ b/arch/x86/include/asm/pgtable.h @@ -836,9 +836,9 @@ static inline int pud_present(pud_t pud) return pud_flags(pud) & _PAGE_PRESENT; } -static inline unsigned long pud_page_vaddr(pud_t pud) +static inline pmd_t *pud_pgtable(pud_t pud) { - return (unsigned long)__va(pud_val(pud) & pud_pfn_mask(pud)); + return (pmd_t *)__va(pud_val(pud) & pud_pfn_mask(pud)); } /* @@ -877,9 +877,9 @@ static inline int p4d_present(p4d_t p4d) return p4d_flags(p4d) & _PAGE_PRESENT; } -static inline unsigned long p4d_page_vaddr(p4d_t p4d) +static inline pud_t *p4d_pgtable(p4d_t p4d) { - return (unsigned long)__va(p4d_val(p4d) & p4d_pfn_mask(p4d)); + return (pud_t *)__va(p4d_val(p4d) & p4d_pfn_mask(p4d)); } /* diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index cc8f1773deca..c890d67a64ad 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -237,7 +237,7 @@ static void __init hv_smp_prepare_cpus(unsigned int max_cpus) for_each_present_cpu(i) { if (i == 0) continue; - ret = hv_call_add_logical_proc(numa_cpu_node(i), i, i); + ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i)); BUG_ON(ret); } diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index 299c20f0a38b..ea4fe192189d 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -69,7 +69,7 @@ static void printk_stack_address(unsigned long address, int reliable, const char *log_lvl) { touch_nmi_watchdog(); - printk("%s %s%pB\n", log_lvl, reliable ? "" : "? ", (void *)address); + printk("%s %s%pBb\n", log_lvl, reliable ? "" : "? ", (void *)address); } static int copy_code(struct pt_regs *regs, u8 *buf, unsigned long src, diff --git a/arch/x86/kernel/jump_label.c b/arch/x86/kernel/jump_label.c index 674906fad43b..68f091ba8443 100644 --- a/arch/x86/kernel/jump_label.c +++ b/arch/x86/kernel/jump_label.c @@ -79,9 +79,10 @@ __jump_label_patch(struct jump_entry *entry, enum jump_label_type type) return (struct jump_label_patch){.code = code, .size = size}; } -static inline void __jump_label_transform(struct jump_entry *entry, - enum jump_label_type type, - int init) +static __always_inline void +__jump_label_transform(struct jump_entry *entry, + enum jump_label_type type, + int init) { const struct jump_label_patch jlp = __jump_label_patch(entry, type); diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 9f1d9215a9fb..bff3a784aec5 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -847,10 +847,7 @@ void __init setup_arch(char **cmdline_p) if (!boot_params.hdr.root_flags) root_mountflags &= ~MS_RDONLY; - init_mm.start_code = (unsigned long) _text; - init_mm.end_code = (unsigned long) _etext; - init_mm.end_data = (unsigned long) _edata; - init_mm.brk = _brk_end; + setup_initial_init_mm(_text, _etext, _edata, (void *)_brk_end); code_resource.start = __pa_symbol(_text); code_resource.end = __pa_symbol(_etext)-1; diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index c42613cfb5ba..739be5da3bca 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -765,7 +765,8 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) edx.split.num_counters_fixed = min(cap.num_counters_fixed, MAX_FIXED_COUNTERS); edx.split.bit_width_fixed = cap.bit_width_fixed; - edx.split.anythread_deprecated = 1; + if (cap.version) + edx.split.anythread_deprecated = 1; edx.split.reserved1 = 0; edx.split.reserved2 = 0; @@ -940,8 +941,21 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); unsigned phys_as = entry->eax & 0xff; - if (!g_phys_as) + /* + * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as + * the guest operates in the same PA space as the host, i.e. + * reductions in MAXPHYADDR for memory encryption affect shadow + * paging, too. + * + * If TDP is enabled but an explicit guest MAXPHYADDR is not + * provided, use the raw bare metal MAXPHYADDR as reductions to + * the HPAs do not affect GPAs. + */ + if (!tdp_enabled) + g_phys_as = boot_cpu_data.x86_phys_bits; + else if (!g_phys_as) g_phys_as = phys_as; + entry->eax = g_phys_as | (virt_as << 8); entry->edx = 0; cpuid_entry_override(entry, CPUID_8000_0008_EBX); @@ -964,12 +978,18 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) case 0x8000001a: case 0x8000001e: break; - /* Support memory encryption cpuid if host supports it */ case 0x8000001F: - if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) + if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { entry->eax = entry->ebx = entry->ecx = entry->edx = 0; - else + } else { cpuid_entry_override(entry, CPUID_8000_001F_EAX); + + /* + * Enumerate '0' for "PA bits reduction", the adjusted + * MAXPHYADDR is enumerated directly (see 0x80000008). + */ + entry->ebx &= ~GENMASK(11, 6); + } break; /*Add support for Centaur's CPUID instruction*/ case 0xC0000000: diff --git a/arch/x86/kvm/ioapic.c b/arch/x86/kvm/ioapic.c index 698969e18fe3..ff005fe738a4 100644 --- a/arch/x86/kvm/ioapic.c +++ b/arch/x86/kvm/ioapic.c @@ -96,7 +96,7 @@ static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic, static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic) { ioapic->rtc_status.pending_eoi = 0; - bitmap_zero(ioapic->rtc_status.dest_map.map, KVM_MAX_VCPU_ID); + bitmap_zero(ioapic->rtc_status.dest_map.map, KVM_MAX_VCPU_ID + 1); } static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic); diff --git a/arch/x86/kvm/ioapic.h b/arch/x86/kvm/ioapic.h index 660401700075..11e4065e1617 100644 --- a/arch/x86/kvm/ioapic.h +++ b/arch/x86/kvm/ioapic.h @@ -43,13 +43,13 @@ struct kvm_vcpu; struct dest_map { /* vcpu bitmap where IRQ has been sent */ - DECLARE_BITMAP(map, KVM_MAX_VCPU_ID); + DECLARE_BITMAP(map, KVM_MAX_VCPU_ID + 1); /* * Vector sent to a given vcpu, only valid when * the vcpu's bit in map is set */ - u8 vectors[KVM_MAX_VCPU_ID]; + u8 vectors[KVM_MAX_VCPU_ID + 1]; }; diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 845d114ae075..66f7f5bc3482 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -53,6 +53,8 @@ #include <asm/kvm_page_track.h> #include "trace.h" +#include "paging.h" + extern bool itlb_multihit_kvm_mitigation; int __read_mostly nx_huge_pages = -1; diff --git a/arch/x86/kvm/mmu/paging.h b/arch/x86/kvm/mmu/paging.h new file mode 100644 index 000000000000..de8ab323bb70 --- /dev/null +++ b/arch/x86/kvm/mmu/paging.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Shadow paging constants/helpers that don't need to be #undef'd. */ +#ifndef __KVM_X86_PAGING_H +#define __KVM_X86_PAGING_H + +#define GUEST_PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) +#define PT64_LVL_ADDR_MASK(level) \ + (GUEST_PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ + * PT64_LEVEL_BITS))) - 1)) +#define PT64_LVL_OFFSET_MASK(level) \ + (GUEST_PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ + * PT64_LEVEL_BITS))) - 1)) +#endif /* __KVM_X86_PAGING_H */ + diff --git a/arch/x86/kvm/mmu/paging_tmpl.h b/arch/x86/kvm/mmu/paging_tmpl.h index 490a028ddabe..ee044d357b5f 100644 --- a/arch/x86/kvm/mmu/paging_tmpl.h +++ b/arch/x86/kvm/mmu/paging_tmpl.h @@ -24,7 +24,7 @@ #define pt_element_t u64 #define guest_walker guest_walker64 #define FNAME(name) paging##64_##name - #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK + #define PT_BASE_ADDR_MASK GUEST_PT64_BASE_ADDR_MASK #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) #define PT_INDEX(addr, level) PT64_INDEX(addr, level) @@ -57,7 +57,7 @@ #define pt_element_t u64 #define guest_walker guest_walkerEPT #define FNAME(name) ept_##name - #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK + #define PT_BASE_ADDR_MASK GUEST_PT64_BASE_ADDR_MASK #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) #define PT_INDEX(addr, level) PT64_INDEX(addr, level) diff --git a/arch/x86/kvm/mmu/spte.h b/arch/x86/kvm/mmu/spte.h index 7a5ce9314107..eb7b227fc6cf 100644 --- a/arch/x86/kvm/mmu/spte.h +++ b/arch/x86/kvm/mmu/spte.h @@ -38,12 +38,6 @@ static_assert(SPTE_TDP_AD_ENABLED_MASK == 0); #else #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) #endif -#define PT64_LVL_ADDR_MASK(level) \ - (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ - * PT64_LEVEL_BITS))) - 1)) -#define PT64_LVL_OFFSET_MASK(level) \ - (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ - * PT64_LEVEL_BITS))) - 1)) #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \ | shadow_x_mask | shadow_nx_mask | shadow_me_mask) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 1d01da64c333..a8ad78a2faa1 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -646,7 +646,7 @@ out: void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm = to_svm(vcpu); - struct vmcb *vmcb = svm->vmcb; + struct vmcb *vmcb = svm->vmcb01.ptr; bool activated = kvm_vcpu_apicv_active(vcpu); if (!enable_apicv) diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index 21d03e3a5dfd..61738ff8ef33 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -154,6 +154,10 @@ void recalc_intercepts(struct vcpu_svm *svm) for (i = 0; i < MAX_INTERCEPT; i++) c->intercepts[i] |= g->intercepts[i]; + + /* If SMI is not intercepted, ignore guest SMI intercept as well */ + if (!intercept_smi) + vmcb_clr_intercept(c, INTERCEPT_SMI); } static void copy_vmcb_control_area(struct vmcb_control_area *dst, @@ -304,8 +308,8 @@ static bool nested_vmcb_valid_sregs(struct kvm_vcpu *vcpu, return true; } -static void nested_load_control_from_vmcb12(struct vcpu_svm *svm, - struct vmcb_control_area *control) +void nested_load_control_from_vmcb12(struct vcpu_svm *svm, + struct vmcb_control_area *control) { copy_vmcb_control_area(&svm->nested.ctl, control); @@ -511,7 +515,7 @@ static void nested_vmcb02_prepare_control(struct vcpu_svm *svm) * Also covers avic_vapic_bar, avic_backing_page, avic_logical_id, * avic_physical_id. */ - WARN_ON(svm->vmcb01.ptr->control.int_ctl & AVIC_ENABLE_MASK); + WARN_ON(kvm_apicv_activated(svm->vcpu.kvm)); /* Copied from vmcb01. msrpm_base can be overwritten later. */ svm->vmcb->control.nested_ctl = svm->vmcb01.ptr->control.nested_ctl; @@ -618,6 +622,11 @@ int nested_svm_vmrun(struct kvm_vcpu *vcpu) struct kvm_host_map map; u64 vmcb12_gpa; + if (!svm->nested.hsave_msr) { + kvm_inject_gp(vcpu, 0); + return 1; + } + if (is_smm(vcpu)) { kvm_queue_exception(vcpu, UD_VECTOR); return 1; @@ -692,7 +701,28 @@ out: return ret; } -void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) +/* Copy state save area fields which are handled by VMRUN */ +void svm_copy_vmrun_state(struct vmcb_save_area *to_save, + struct vmcb_save_area *from_save) +{ + to_save->es = from_save->es; + to_save->cs = from_save->cs; + to_save->ss = from_save->ss; + to_save->ds = from_save->ds; + to_save->gdtr = from_save->gdtr; + to_save->idtr = from_save->idtr; + to_save->rflags = from_save->rflags | X86_EFLAGS_FIXED; + to_save->efer = from_save->efer; + to_save->cr0 = from_save->cr0; + to_save->cr3 = from_save->cr3; + to_save->cr4 = from_save->cr4; + to_save->rax = from_save->rax; + to_save->rsp = from_save->rsp; + to_save->rip = from_save->rip; + to_save->cpl = 0; +} + +void svm_copy_vmloadsave_state(struct vmcb *to_vmcb, struct vmcb *from_vmcb) { to_vmcb->save.fs = from_vmcb->save.fs; to_vmcb->save.gs = from_vmcb->save.gs; @@ -1355,28 +1385,11 @@ static int svm_set_nested_state(struct kvm_vcpu *vcpu, svm->nested.vmcb12_gpa = kvm_state->hdr.svm.vmcb_pa; - svm->vmcb01.ptr->save.es = save->es; - svm->vmcb01.ptr->save.cs = save->cs; - svm->vmcb01.ptr->save.ss = save->ss; - svm->vmcb01.ptr->save.ds = save->ds; - svm->vmcb01.ptr->save.gdtr = save->gdtr; - svm->vmcb01.ptr->save.idtr = save->idtr; - svm->vmcb01.ptr->save.rflags = save->rflags | X86_EFLAGS_FIXED; - svm->vmcb01.ptr->save.efer = save->efer; - svm->vmcb01.ptr->save.cr0 = save->cr0; - svm->vmcb01.ptr->save.cr3 = save->cr3; - svm->vmcb01.ptr->save.cr4 = save->cr4; - svm->vmcb01.ptr->save.rax = save->rax; - svm->vmcb01.ptr->save.rsp = save->rsp; - svm->vmcb01.ptr->save.rip = save->rip; - svm->vmcb01.ptr->save.cpl = 0; - + svm_copy_vmrun_state(&svm->vmcb01.ptr->save, save); nested_load_control_from_vmcb12(svm, ctl); svm_switch_vmcb(svm, &svm->nested.vmcb02); - nested_vmcb02_prepare_control(svm); - kvm_make_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu); ret = 0; out_free: diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 62926f1a5f7b..6710d9ee2e4b 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -1272,8 +1272,8 @@ static int sev_send_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp) /* Pin guest memory */ guest_page = sev_pin_memory(kvm, params.guest_uaddr & PAGE_MASK, PAGE_SIZE, &n, 0); - if (!guest_page) - return -EFAULT; + if (IS_ERR(guest_page)) + return PTR_ERR(guest_page); /* allocate memory for header and transport buffer */ ret = -ENOMEM; @@ -1310,8 +1310,9 @@ static int sev_send_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp) } /* Copy packet header to userspace. */ - ret = copy_to_user((void __user *)(uintptr_t)params.hdr_uaddr, hdr, - params.hdr_len); + if (copy_to_user((void __user *)(uintptr_t)params.hdr_uaddr, hdr, + params.hdr_len)) + ret = -EFAULT; e_free_trans_data: kfree(trans_data); @@ -1463,11 +1464,12 @@ static int sev_receive_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp) data.trans_len = params.trans_len; /* Pin guest memory */ - ret = -EFAULT; guest_page = sev_pin_memory(kvm, params.guest_uaddr & PAGE_MASK, PAGE_SIZE, &n, 0); - if (!guest_page) + if (IS_ERR(guest_page)) { + ret = PTR_ERR(guest_page); goto e_free_trans; + } /* The RECEIVE_UPDATE_DATA command requires C-bit to be always set. */ data.guest_address = (page_to_pfn(guest_page[0]) << PAGE_SHIFT) + offset; diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 8834822c00cd..e8ccab50ebf6 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -198,6 +198,11 @@ module_param(avic, bool, 0444); bool __read_mostly dump_invalid_vmcb; module_param(dump_invalid_vmcb, bool, 0644); + +bool intercept_smi = true; +module_param(intercept_smi, bool, 0444); + + static bool svm_gp_erratum_intercept = true; static u8 rsm_ins_bytes[] = "\x0f\xaa"; @@ -1185,7 +1190,10 @@ static void init_vmcb(struct kvm_vcpu *vcpu) svm_set_intercept(svm, INTERCEPT_INTR); svm_set_intercept(svm, INTERCEPT_NMI); - svm_set_intercept(svm, INTERCEPT_SMI); + + if (intercept_smi) + svm_set_intercept(svm, INTERCEPT_SMI); + svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0); svm_set_intercept(svm, INTERCEPT_RDPMC); svm_set_intercept(svm, INTERCEPT_CPUID); @@ -1398,8 +1406,6 @@ static int svm_create_vcpu(struct kvm_vcpu *vcpu) goto error_free_vmsa_page; } - svm_vcpu_init_msrpm(vcpu, svm->msrpm); - svm->vmcb01.ptr = page_address(vmcb01_page); svm->vmcb01.pa = __sme_set(page_to_pfn(vmcb01_page) << PAGE_SHIFT); @@ -1411,6 +1417,8 @@ static int svm_create_vcpu(struct kvm_vcpu *vcpu) svm_switch_vmcb(svm, &svm->vmcb01); init_vmcb(vcpu); + svm_vcpu_init_msrpm(vcpu, svm->msrpm); + svm_init_osvw(vcpu); vcpu->arch.microcode_version = 0x01000065; @@ -1560,8 +1568,11 @@ static void svm_set_vintr(struct vcpu_svm *svm) { struct vmcb_control_area *control; - /* The following fields are ignored when AVIC is enabled */ - WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu)); + /* + * The following fields are ignored when AVIC is enabled + */ + WARN_ON(kvm_apicv_activated(svm->vcpu.kvm)); + svm_set_intercept(svm, INTERCEPT_VINTR); /* @@ -1923,7 +1934,7 @@ static int npf_interception(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm = to_svm(vcpu); - u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2); + u64 fault_address = svm->vmcb->control.exit_info_2; u64 error_code = svm->vmcb->control.exit_info_1; trace_kvm_page_fault(fault_address, error_code); @@ -2106,6 +2117,11 @@ static int nmi_interception(struct kvm_vcpu *vcpu) return 1; } +static int smi_interception(struct kvm_vcpu *vcpu) +{ + return 1; +} + static int intr_interception(struct kvm_vcpu *vcpu) { ++vcpu->stat.irq_exits; @@ -2134,11 +2150,12 @@ static int vmload_vmsave_interception(struct kvm_vcpu *vcpu, bool vmload) ret = kvm_skip_emulated_instruction(vcpu); if (vmload) { - nested_svm_vmloadsave(vmcb12, svm->vmcb); + svm_copy_vmloadsave_state(svm->vmcb, vmcb12); svm->sysenter_eip_hi = 0; svm->sysenter_esp_hi = 0; - } else - nested_svm_vmloadsave(svm->vmcb, vmcb12); + } else { + svm_copy_vmloadsave_state(vmcb12, svm->vmcb); + } kvm_vcpu_unmap(vcpu, &map, true); @@ -2941,7 +2958,16 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) svm_disable_lbrv(vcpu); break; case MSR_VM_HSAVE_PA: - svm->nested.hsave_msr = data; + /* + * Old kernels did not validate the value written to + * MSR_VM_HSAVE_PA. Allow KVM_SET_MSR to set an invalid + * value to allow live migrating buggy or malicious guests + * originating from those kernels. + */ + if (!msr->host_initiated && !page_address_valid(vcpu, data)) + return 1; + + svm->nested.hsave_msr = data & PAGE_MASK; break; case MSR_VM_CR: return svm_set_vm_cr(vcpu, data); @@ -3080,8 +3106,7 @@ static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = { [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception, [SVM_EXIT_INTR] = intr_interception, [SVM_EXIT_NMI] = nmi_interception, - [SVM_EXIT_SMI] = kvm_emulate_as_nop, - [SVM_EXIT_INIT] = kvm_emulate_as_nop, + [SVM_EXIT_SMI] = smi_interception, [SVM_EXIT_VINTR] = interrupt_window_interception, [SVM_EXIT_RDPMC] = kvm_emulate_rdpmc, [SVM_EXIT_CPUID] = kvm_emulate_cpuid, @@ -4288,6 +4313,7 @@ static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection) static int svm_enter_smm(struct kvm_vcpu *vcpu, char *smstate) { struct vcpu_svm *svm = to_svm(vcpu); + struct kvm_host_map map_save; int ret; if (is_guest_mode(vcpu)) { @@ -4303,6 +4329,29 @@ static int svm_enter_smm(struct kvm_vcpu *vcpu, char *smstate) ret = nested_svm_vmexit(svm); if (ret) return ret; + + /* + * KVM uses VMCB01 to store L1 host state while L2 runs but + * VMCB01 is going to be used during SMM and thus the state will + * be lost. Temporary save non-VMLOAD/VMSAVE state to the host save + * area pointed to by MSR_VM_HSAVE_PA. APM guarantees that the + * format of the area is identical to guest save area offsetted + * by 0x400 (matches the offset of 'struct vmcb_save_area' + * within 'struct vmcb'). Note: HSAVE area may also be used by + * L1 hypervisor to save additional host context (e.g. KVM does + * that, see svm_prepare_guest_switch()) which must be + * preserved. + */ + if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr), + &map_save) == -EINVAL) + return 1; + + BUILD_BUG_ON(offsetof(struct vmcb, save) != 0x400); + + svm_copy_vmrun_state(map_save.hva + 0x400, + &svm->vmcb01.ptr->save); + + kvm_vcpu_unmap(vcpu, &map_save, true); } return 0; } @@ -4310,13 +4359,14 @@ static int svm_enter_smm(struct kvm_vcpu *vcpu, char *smstate) static int svm_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) { struct vcpu_svm *svm = to_svm(vcpu); - struct kvm_host_map map; + struct kvm_host_map map, map_save; int ret = 0; if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) { u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0); u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8); u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0); + struct vmcb *vmcb12; if (guest) { if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM)) @@ -4332,8 +4382,25 @@ static int svm_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) if (svm_allocate_nested(svm)) return 1; - ret = enter_svm_guest_mode(vcpu, vmcb12_gpa, map.hva); + vmcb12 = map.hva; + + nested_load_control_from_vmcb12(svm, &vmcb12->control); + + ret = enter_svm_guest_mode(vcpu, vmcb12_gpa, vmcb12); kvm_vcpu_unmap(vcpu, &map, true); + + /* + * Restore L1 host state from L1 HSAVE area as VMCB01 was + * used during SMM (see svm_enter_smm()) + */ + if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr), + &map_save) == -EINVAL) + return 1; + + svm_copy_vmrun_state(&svm->vmcb01.ptr->save, + map_save.hva + 0x400); + + kvm_vcpu_unmap(vcpu, &map_save, true); } } diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index f89b623bb591..bd0fe94c2920 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -31,6 +31,7 @@ #define MSRPM_OFFSETS 16 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; extern bool npt_enabled; +extern bool intercept_smi; /* * Clean bits in VMCB. @@ -463,7 +464,9 @@ void svm_leave_nested(struct vcpu_svm *svm); void svm_free_nested(struct vcpu_svm *svm); int svm_allocate_nested(struct vcpu_svm *svm); int nested_svm_vmrun(struct kvm_vcpu *vcpu); -void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb); +void svm_copy_vmrun_state(struct vmcb_save_area *to_save, + struct vmcb_save_area *from_save); +void svm_copy_vmloadsave_state(struct vmcb *to_vmcb, struct vmcb *from_vmcb); int nested_svm_vmexit(struct vcpu_svm *svm); static inline int nested_svm_simple_vmexit(struct vcpu_svm *svm, u32 exit_code) @@ -479,6 +482,8 @@ int nested_svm_check_permissions(struct kvm_vcpu *vcpu); int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, bool has_error_code, u32 error_code); int nested_svm_exit_special(struct vcpu_svm *svm); +void nested_load_control_from_vmcb12(struct vcpu_svm *svm, + struct vmcb_control_area *control); void nested_sync_control_from_vmcb02(struct vcpu_svm *svm); void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm); void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb); diff --git a/arch/x86/kvm/svm/svm_onhyperv.h b/arch/x86/kvm/svm/svm_onhyperv.h index 9b9a55abc29f..c53b8bf8d013 100644 --- a/arch/x86/kvm/svm/svm_onhyperv.h +++ b/arch/x86/kvm/svm/svm_onhyperv.h @@ -89,7 +89,7 @@ static inline void svm_hv_vmcb_dirty_nested_enlightenments( * as we mark it dirty unconditionally towards end of vcpu * init phase. */ - if (vmcb && vmcb_is_clean(vmcb, VMCB_HV_NESTED_ENLIGHTENMENTS) && + if (vmcb_is_clean(vmcb, VMCB_HV_NESTED_ENLIGHTENMENTS) && hve->hv_enlightenments_control.msr_bitmap) vmcb_mark_dirty(vmcb, VMCB_HV_NESTED_ENLIGHTENMENTS); } diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 3979a947933a..db88ed4f2121 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -14,8 +14,6 @@ #include "vmx_ops.h" #include "cpuid.h" -extern const u32 vmx_msr_index[]; - #define MSR_TYPE_R 1 #define MSR_TYPE_W 2 #define MSR_TYPE_RW 3 diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index c6dc1b445231..4116567f3d44 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -3407,7 +3407,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) return 1; break; case MSR_KVM_ASYNC_PF_ACK: - if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) + if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) return 1; if (data & 0x1) { vcpu->arch.apf.pageready_pending = false; @@ -3746,7 +3746,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) msr_info->data = vcpu->arch.apf.msr_int_val; break; case MSR_KVM_ASYNC_PF_ACK: - if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) + if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) return 1; msr_info->data = 0; @@ -9601,6 +9601,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) set_debugreg(vcpu->arch.eff_db[3], 3); set_debugreg(vcpu->arch.dr6, 6); vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD; + } else if (unlikely(hw_breakpoint_active())) { + set_debugreg(0, 7); } for (;;) { @@ -10985,9 +10987,6 @@ int kvm_arch_hardware_setup(void *opaque) int r; rdmsrl_safe(MSR_EFER, &host_efer); - if (WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_NX) && - !(host_efer & EFER_NX))) - return -EIO; if (boot_cpu_has(X86_FEATURE_XSAVES)) rdmsrl(MSR_IA32_XSS, host_xss); diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index 65ea58527176..ddeaba947eb3 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -194,8 +194,8 @@ static void sync_global_pgds_l4(unsigned long start, unsigned long end) spin_lock(pgt_lock); if (!p4d_none(*p4d_ref) && !p4d_none(*p4d)) - BUG_ON(p4d_page_vaddr(*p4d) - != p4d_page_vaddr(*p4d_ref)); + BUG_ON(p4d_pgtable(*p4d) + != p4d_pgtable(*p4d_ref)); if (p4d_none(*p4d)) set_p4d(p4d, *p4d_ref); diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c index 156cd235659f..ad8a5c586a35 100644 --- a/arch/x86/mm/pat/set_memory.c +++ b/arch/x86/mm/pat/set_memory.c @@ -1134,7 +1134,7 @@ static void __unmap_pmd_range(pud_t *pud, pmd_t *pmd, unsigned long start, unsigned long end) { if (unmap_pte_range(pmd, start, end)) - if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud))) + if (try_to_free_pmd_page(pud_pgtable(*pud))) pud_clear(pud); } @@ -1178,7 +1178,7 @@ static void unmap_pmd_range(pud_t *pud, unsigned long start, unsigned long end) * Try again to free the PMD page if haven't succeeded above. */ if (!pud_none(*pud)) - if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud))) + if (try_to_free_pmd_page(pud_pgtable(*pud))) pud_clear(pud); } diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index 1303ff6ef7be..3481b35cb4ec 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -682,7 +682,6 @@ int p4d_clear_huge(p4d_t *p4d) } #endif -#if CONFIG_PGTABLE_LEVELS > 3 /** * pud_set_huge - setup kernel PUD mapping * @@ -722,23 +721,6 @@ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) } /** - * pud_clear_huge - clear kernel PUD mapping when it is set - * - * Returns 1 on success and 0 on failure (no PUD map is found). - */ -int pud_clear_huge(pud_t *pud) -{ - if (pud_large(*pud)) { - pud_clear(pud); - return 1; - } - - return 0; -} -#endif - -#if CONFIG_PGTABLE_LEVELS > 2 -/** * pmd_set_huge - setup kernel PMD mapping * * See text over pud_set_huge() above. @@ -769,6 +751,21 @@ int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) } /** + * pud_clear_huge - clear kernel PUD mapping when it is set + * + * Returns 1 on success and 0 on failure (no PUD map is found). + */ +int pud_clear_huge(pud_t *pud) +{ + if (pud_large(*pud)) { + pud_clear(pud); + return 1; + } + + return 0; +} + +/** * pmd_clear_huge - clear kernel PMD mapping when it is set * * Returns 1 on success and 0 on failure (no PMD map is found). @@ -782,7 +779,6 @@ int pmd_clear_huge(pmd_t *pmd) return 0; } -#endif #ifdef CONFIG_X86_64 /** @@ -801,7 +797,7 @@ int pud_free_pmd_page(pud_t *pud, unsigned long addr) pte_t *pte; int i; - pmd = (pmd_t *)pud_page_vaddr(*pud); + pmd = pud_pgtable(*pud); pmd_sv = (pmd_t *)__get_free_page(GFP_KERNEL); if (!pmd_sv) return 0; diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c index e835164189f1..4b951458c9fc 100644 --- a/arch/x86/net/bpf_jit_comp.c +++ b/arch/x86/net/bpf_jit_comp.c @@ -570,6 +570,9 @@ static void bpf_tail_call_direct_fixup(struct bpf_prog *prog) for (i = 0; i < prog->aux->size_poke_tab; i++) { poke = &prog->aux->poke_tab[i]; + if (poke->aux && poke->aux != prog->aux) + continue; + WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable)); if (poke->reason != BPF_POKE_REASON_TAIL_CALL) diff --git a/arch/xtensa/Kbuild b/arch/xtensa/Kbuild new file mode 100644 index 000000000000..a4e40e534e6a --- /dev/null +++ b/arch/xtensa/Kbuild @@ -0,0 +1 @@ +# SPDX-License-Identifier: GPL-2.0-only |