diff options
Diffstat (limited to 'drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h')
| -rw-r--r-- | drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h | 189 |
1 files changed, 189 insertions, 0 deletions
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h new file mode 100644 index 000000000000..5b52b88fee0f --- /dev/null +++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_REGS_H_ +#define ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_REGS_H_ + +/* + ***************************************** + * DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW + * (Prototype: RANGE_REG_LBW) + ***************************************** + */ + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_0 0x4142600 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_1 0x4142604 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_2 0x4142608 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_3 0x414260C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_4 0x4142610 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_5 0x4142614 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_6 0x4142618 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_7 0x414261C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_8 0x4142620 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_9 0x4142624 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_10 0x4142628 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_11 0x414262C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_12 0x4142630 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_SHORT_13 0x4142634 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_0 0x4142638 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_1 0x414263C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_2 0x4142640 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_3 0x4142644 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_4 0x4142648 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_5 0x414264C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_6 0x4142650 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_7 0x4142654 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_8 0x4142658 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_9 0x414265C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_10 0x4142660 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_11 0x4142664 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_12 0x4142668 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_SHORT_13 0x414266C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_0 0x4142670 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_1 0x4142674 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_2 0x4142678 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_3 0x414267C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_4 0x4142680 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_5 0x4142684 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_6 0x4142688 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_7 0x414268C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_8 0x4142690 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_9 0x4142694 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_10 0x4142698 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_11 0x414269C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_12 0x41426A0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_SHORT_13 0x41426A4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_0 0x41426A8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_1 0x41426AC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_2 0x41426B0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_3 0x41426B4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_4 0x41426B8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_5 0x41426BC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_6 0x41426C0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_7 0x41426C4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_8 0x41426C8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_9 0x41426CC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_10 0x41426D0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_11 0x41426D4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_12 0x41426D8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_SHORT_13 0x41426DC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_0 0x41426E0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_1 0x41426E4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_2 0x41426E8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MIN_3 0x41426EC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_0 0x41426F0 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_1 0x41426F4 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_2 0x41426F8 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_RANGE_MAX_3 0x41426FC + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_0 0x4142700 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_1 0x4142704 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_2 0x4142708 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MIN_3 0x414270C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_0 0x4142710 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_1 0x4142714 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_2 0x4142718 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_RANGE_MAX_3 0x414271C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_HIT_AW 0x4142720 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_HIT_AW 0x4142724 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SEC_HIT_AR 0x4142728 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_PRIV_HIT_AR 0x414272C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AW_RAZWI 0x4142730 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AR_RAZWI 0x4142734 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AW_RAZWI_XY 0x4142738 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AR_RAZWI_XY 0x414273C + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AW_RAZWI_HAPPENED 0x4142740 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_AR_RAZWI_HAPPENED 0x4142744 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_RAZWI_ERR_RESP 0x4142748 + +#endif /* ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_REGS_H_ */ |