diff options
Diffstat (limited to 'drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h')
| -rw-r--r-- | drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h | 509 |
1 files changed, 509 insertions, 0 deletions
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h new file mode 100644 index 000000000000..cdecbd0f9d84 --- /dev/null +++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_masks.h @@ -0,0 +1,509 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG + * (Prototype: TPC) + ***************************************** + */ + +/* DCORE0_TPC0_CFG_TPC_COUNT */ +#define DCORE0_TPC0_CFG_TPC_COUNT_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_COUNT_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TPC_ID */ +#define DCORE0_TPC0_CFG_TPC_ID_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_ID_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_STALL_ON_ERR */ +#define DCORE0_TPC0_CFG_STALL_ON_ERR_V_SHIFT 0 +#define DCORE0_TPC0_CFG_STALL_ON_ERR_V_MASK 0x1 + +/* DCORE0_TPC0_CFG_CLK_EN */ +#define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_SHIFT 0 +#define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_MASK 0x1 +#define DCORE0_TPC0_CFG_CLK_EN_DBG_CFG_DIS_SHIFT 4 +#define DCORE0_TPC0_CFG_CLK_EN_DBG_CFG_DIS_MASK 0x10 + +/* DCORE0_TPC0_CFG_IQ_RL_EN */ +#define DCORE0_TPC0_CFG_IQ_RL_EN_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IQ_RL_EN_V_MASK 0x1 + +/* DCORE0_TPC0_CFG_IQ_RL_SAT */ +#define DCORE0_TPC0_CFG_IQ_RL_SAT_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IQ_RL_SAT_V_MASK 0xFF + +/* DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN */ +#define DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IQ_RL_RST_TOKEN_V_MASK 0xFF + +/* DCORE0_TPC0_CFG_IQ_RL_TIMEOUT */ +#define DCORE0_TPC0_CFG_IQ_RL_TIMEOUT_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IQ_RL_TIMEOUT_V_MASK 0xFF + +/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_2 */ +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_2_PHY_BASE_ADD_LO_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_2_PHY_BASE_ADD_LO_MASK 0xFFFFFF + +/* DCORE0_TPC0_CFG_IQ_LBW_CLK_EN */ +#define DCORE0_TPC0_CFG_IQ_LBW_CLK_EN_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IQ_LBW_CLK_EN_V_MASK 0x1 + +/* DCORE0_TPC0_CFG_TPC_LOCK_VALUE */ +#define DCORE0_TPC0_CFG_TPC_LOCK_VALUE_VALUE_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_LOCK_VALUE_VALUE_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TPC_LOCK */ +#define DCORE0_TPC0_CFG_TPC_LOCK_LOCK_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_LOCK_LOCK_MASK 0x1 + +/* DCORE0_TPC0_CFG_CGU_SB */ +#define DCORE0_TPC0_CFG_CGU_SB_TSB_DISABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_CGU_SB_TSB_DISABLE_MASK 0x1 + +/* DCORE0_TPC0_CFG_CGU_CNT */ +#define DCORE0_TPC0_CFG_CGU_CNT_DCACHE_DISABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_CGU_CNT_DCACHE_DISABLE_MASK 0x1 +#define DCORE0_TPC0_CFG_CGU_CNT_WQ_DISABLE_SHIFT 1 +#define DCORE0_TPC0_CFG_CGU_CNT_WQ_DISABLE_MASK 0x2 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_0_DISABLE_SHIFT 2 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_0_DISABLE_MASK 0x4 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_1_DISABLE_SHIFT 3 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_1_DISABLE_MASK 0x8 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_2_DISABLE_SHIFT 4 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_2_DISABLE_MASK 0x10 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_3_DISABLE_SHIFT 5 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_3_DISABLE_MASK 0x20 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_4_DISABLE_SHIFT 6 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_ADDSUB_4_DISABLE_MASK 0x40 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_0_DISABLE_SHIFT 7 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_0_DISABLE_MASK 0x80 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_1_DISABLE_SHIFT 8 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_1_DISABLE_MASK 0x100 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_2_DISABLE_SHIFT 9 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_2_DISABLE_MASK 0x200 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_3_DISABLE_SHIFT 10 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_3_DISABLE_MASK 0x400 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_4_DISABLE_SHIFT 11 +#define DCORE0_TPC0_CFG_CGU_CNT_SPU_AGU_CMP_4_DISABLE_MASK 0x800 +#define DCORE0_TPC0_CFG_CGU_CNT_MSAC_DISABLE_SHIFT 12 +#define DCORE0_TPC0_CFG_CGU_CNT_MSAC_DISABLE_MASK 0x1000 +#define DCORE0_TPC0_CFG_CGU_CNT_CONV_DISABLE_SHIFT 13 +#define DCORE0_TPC0_CFG_CGU_CNT_CONV_DISABLE_MASK 0x2000 +#define DCORE0_TPC0_CFG_CGU_CNT_NEARBYINT_DISABLE_SHIFT 14 +#define DCORE0_TPC0_CFG_CGU_CNT_NEARBYINT_DISABLE_MASK 0x4000 +#define DCORE0_TPC0_CFG_CGU_CNT_CMP_DISABLE_SHIFT 15 +#define DCORE0_TPC0_CFG_CGU_CNT_CMP_DISABLE_MASK 0x8000 +#define DCORE0_TPC0_CFG_CGU_CNT_FP_MAC_DISABLE_SHIFT 16 +#define DCORE0_TPC0_CFG_CGU_CNT_FP_MAC_DISABLE_MASK 0x10000 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_A_D2_DISABLE_SHIFT 17 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_A_D2_DISABLE_MASK 0x20000 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_B_D2_DISABLE_SHIFT 18 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_B_D2_DISABLE_MASK 0x40000 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_E_D2_DISABLE_SHIFT 19 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_SRC_E_D2_DISABLE_MASK 0x80000 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_FMA_SRC_C_E1_DISABLE_SHIFT 20 +#define DCORE0_TPC0_CFG_CGU_CNT_SOPS_FMA_SRC_C_E1_DISABLE_MASK 0x100000 +#define DCORE0_TPC0_CFG_CGU_CNT_LD_SOPS_SRC_A_D2_DISABLE_SHIFT 21 +#define DCORE0_TPC0_CFG_CGU_CNT_LD_SOPS_SRC_A_D2_DISABLE_MASK 0x200000 +#define DCORE0_TPC0_CFG_CGU_CNT_ST_SOPS_SRC_A_D2_DISABLE_SHIFT 22 +#define DCORE0_TPC0_CFG_CGU_CNT_ST_SOPS_SRC_A_D2_DISABLE_MASK 0x400000 +#define DCORE0_TPC0_CFG_CGU_CNT_FP_ADDSUB_DISABLE_SHIFT 23 +#define DCORE0_TPC0_CFG_CGU_CNT_FP_ADDSUB_DISABLE_MASK 0x800000 + +/* DCORE0_TPC0_CFG_CGU_CPE */ +#define DCORE0_TPC0_CFG_CGU_CPE_NEARBYINT_DISABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_CGU_CPE_NEARBYINT_DISABLE_MASK 0x1 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_A_DISABLE_SHIFT 1 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_A_DISABLE_MASK 0x2 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_B_DISABLE_SHIFT 2 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_B_DISABLE_MASK 0x4 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_E_DISABLE_SHIFT 3 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_E_DISABLE_MASK 0x8 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_D_DISABLE_SHIFT 4 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_D_DISABLE_MASK 0x10 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_C_DISABLE_SHIFT 5 +#define DCORE0_TPC0_CFG_CGU_CPE_SOPS_SRC_C_DISABLE_MASK 0x20 +#define DCORE0_TPC0_CFG_CGU_CPE_LD_SOPS_SRC_A_DISABLE_SHIFT 6 +#define DCORE0_TPC0_CFG_CGU_CPE_LD_SOPS_SRC_A_DISABLE_MASK 0x40 +#define DCORE0_TPC0_CFG_CGU_CPE_MSAC_DISABLE_SHIFT 7 +#define DCORE0_TPC0_CFG_CGU_CPE_MSAC_DISABLE_MASK 0x80 +#define DCORE0_TPC0_CFG_CGU_CPE_ADDSUB_DISABLE_SHIFT 8 +#define DCORE0_TPC0_CFG_CGU_CPE_ADDSUB_DISABLE_MASK 0x100 +#define DCORE0_TPC0_CFG_CGU_CPE_SHIFT_DISABLE_SHIFT 9 +#define DCORE0_TPC0_CFG_CGU_CPE_SHIFT_DISABLE_MASK 0x200 +#define DCORE0_TPC0_CFG_CGU_CPE_GLE_DISABLE_SHIFT 10 +#define DCORE0_TPC0_CFG_CGU_CPE_GLE_DISABLE_MASK 0x400 +#define DCORE0_TPC0_CFG_CGU_CPE_CMP_DISABLE_SHIFT 11 +#define DCORE0_TPC0_CFG_CGU_CPE_CMP_DISABLE_MASK 0x800 +#define DCORE0_TPC0_CFG_CGU_CPE_CONV_DISABLE_SHIFT 12 +#define DCORE0_TPC0_CFG_CGU_CPE_CONV_DISABLE_MASK 0x1000 +#define DCORE0_TPC0_CFG_CGU_CPE_SB_DISABLE_SHIFT 13 +#define DCORE0_TPC0_CFG_CGU_CPE_SB_DISABLE_MASK 0x2000 +#define DCORE0_TPC0_CFG_CGU_CPE_TBUF_DISABLE_SHIFT 14 +#define DCORE0_TPC0_CFG_CGU_CPE_TBUF_DISABLE_MASK 0x4000 +#define DCORE0_TPC0_CFG_CGU_CPE_ST_G_DISABLE_SHIFT 15 +#define DCORE0_TPC0_CFG_CGU_CPE_ST_G_DISABLE_MASK 0x8000 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_0_DISABLE_SHIFT 16 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_0_DISABLE_MASK 0x10000 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_1_DISABLE_SHIFT 17 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_MAC_1_DISABLE_MASK 0x20000 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_ADDSUB_DISABLE_SHIFT 18 +#define DCORE0_TPC0_CFG_CGU_CPE_FP_ADDSUB_DISABLE_MASK 0x40000 +#define DCORE0_TPC0_CFG_CGU_CPE_ST_SOPS_SRC_C_DISABLE_SHIFT 19 +#define DCORE0_TPC0_CFG_CGU_CPE_ST_SOPS_SRC_C_DISABLE_MASK 0x80000 + +/* DCORE0_TPC0_CFG_FP16_FTZ_IN */ +#define DCORE0_TPC0_CFG_FP16_FTZ_IN_MODE_SHIFT 0 +#define DCORE0_TPC0_CFG_FP16_FTZ_IN_MODE_MASK 0x1 + +/* DCORE0_TPC0_CFG_DCACHE_CFG */ +#define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_DIS_SHIFT 0 +#define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_DIS_MASK 0x1 +#define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_VLD_CLR_SHIFT 1 +#define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_VLD_CLR_MASK 0x2 +#define DCORE0_TPC0_CFG_DCACHE_CFG_HALT_FLUSH_SHIFT 2 +#define DCORE0_TPC0_CFG_DCACHE_CFG_HALT_FLUSH_MASK 0x4 +#define DCORE0_TPC0_CFG_DCACHE_CFG_DEALIGN_DIS_SHIFT 3 +#define DCORE0_TPC0_CFG_DCACHE_CFG_DEALIGN_DIS_MASK 0x8 + +/* DCORE0_TPC0_CFG_E2E_CRDT_TOP */ +#define DCORE0_TPC0_CFG_E2E_CRDT_TOP_FORCE_EN_SHIFT 0 +#define DCORE0_TPC0_CFG_E2E_CRDT_TOP_FORCE_EN_MASK 0x1 +#define DCORE0_TPC0_CFG_E2E_CRDT_TOP_Y_X_FORCE_SHIFT 4 +#define DCORE0_TPC0_CFG_E2E_CRDT_TOP_Y_X_FORCE_MASK 0x1FF0 + +/* DCORE0_TPC0_CFG_TPC_DCACHE_L0CD */ +#define DCORE0_TPC0_CFG_TPC_DCACHE_L0CD_VAL_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_DCACHE_L0CD_VAL_MASK 0x1 + +/* DCORE0_TPC0_CFG_TPC_SB_L0CD */ +#define DCORE0_TPC0_CFG_TPC_SB_L0CD_VAL_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_SB_L0CD_VAL_MASK 0x1 + +/* DCORE0_TPC0_CFG_CONV_ROUND_CSR */ +#define DCORE0_TPC0_CFG_CONV_ROUND_CSR_MODE_SHIFT 0 +#define DCORE0_TPC0_CFG_CONV_ROUND_CSR_MODE_MASK 0x7 + +/* DCORE0_TPC0_CFG_TSB_OCCUPANCY */ +#define DCORE0_TPC0_CFG_TSB_OCCUPANCY_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_OCCUPANCY_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT */ +#define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AR_SHIFT 0 +#define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AR_MASK 0xFFF +#define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AW_SHIFT 12 +#define DCORE0_TPC0_CFG_ARB_QNT_HBW_WEIGHT_AW_MASK 0xFF000 + +/* DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT */ +#define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AW_SHIFT 0 +#define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AW_MASK 0xFF +#define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AR_SHIFT 8 +#define DCORE0_TPC0_CFG_ARB_QNT_LBW_WEIGHT_AR_MASK 0xFF00 + +/* DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT */ +#define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AR_SHIFT 0 +#define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AR_MASK 0xFFF +#define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AW_SHIFT 12 +#define DCORE0_TPC0_CFG_ARB_CNT_HBW_WEIGHT_AW_MASK 0xFFF000 + +/* DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT */ +#define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AR_SHIFT 0 +#define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AR_MASK 0xFF +#define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AW_SHIFT 8 +#define DCORE0_TPC0_CFG_ARB_CNT_LBW_WEIGHT_AW_MASK 0xFFF00 + +/* DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM */ +#define DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM_V_SHIFT 0 +#define DCORE0_TPC0_CFG_SPE_LFSR_POLYNOM_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL */ +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_EN_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_EN_MASK 0x1 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_DEFAULT_MEMORY_TYPE_SHIFT 4 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_GLBL_DEFAULT_MEMORY_TYPE_MASK 0x10 + +/* DCORE0_TPC0_CFG_TSB_CFG_MTRR */ +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_VALID_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_VALID_MASK 0x1 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MEMORY_TYPE_SHIFT 4 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MEMORY_TYPE_MASK 0x10 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_PHY_BASE_ADD_SHIFT 8 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_PHY_BASE_ADD_MASK 0xFFFF00 + +/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO */ +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI */ +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MTRR_MASK_HI_V_MASK 0xFF + +/* DCORE0_TPC0_CFG_FP8_143_BIAS */ +#define DCORE0_TPC0_CFG_FP8_143_BIAS_BIAS_143_SHIFT 0 +#define DCORE0_TPC0_CFG_FP8_143_BIAS_BIAS_143_MASK 0xF + +/* DCORE0_TPC0_CFG_ROUND_CSR */ +#define DCORE0_TPC0_CFG_ROUND_CSR_MODE_SHIFT 0 +#define DCORE0_TPC0_CFG_ROUND_CSR_MODE_MASK 0x7 + +/* DCORE0_TPC0_CFG_HB_PROT */ +#define DCORE0_TPC0_CFG_HB_PROT_AWPROT_SHIFT 0 +#define DCORE0_TPC0_CFG_HB_PROT_AWPROT_MASK 0x7 +#define DCORE0_TPC0_CFG_HB_PROT_ARPROT_SHIFT 3 +#define DCORE0_TPC0_CFG_HB_PROT_ARPROT_MASK 0x38 + +/* DCORE0_TPC0_CFG_LB_PROT */ +#define DCORE0_TPC0_CFG_LB_PROT_AWPROT_SHIFT 0 +#define DCORE0_TPC0_CFG_LB_PROT_AWPROT_MASK 0x7 +#define DCORE0_TPC0_CFG_LB_PROT_ARPROT_SHIFT 3 +#define DCORE0_TPC0_CFG_LB_PROT_ARPROT_MASK 0x38 + +/* DCORE0_TPC0_CFG_SEMAPHORE */ +#define DCORE0_TPC0_CFG_SEMAPHORE_V_SHIFT 0 +#define DCORE0_TPC0_CFG_SEMAPHORE_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_VFLAGS */ +#define DCORE0_TPC0_CFG_VFLAGS_V_SHIFT 0 +#define DCORE0_TPC0_CFG_VFLAGS_V_MASK 0x7F + +/* DCORE0_TPC0_CFG_SFLAGS */ +#define DCORE0_TPC0_CFG_SFLAGS_V_SHIFT 0 +#define DCORE0_TPC0_CFG_SFLAGS_V_MASK 0x7F + +/* DCORE0_TPC0_CFG_LFSR_POLYNOM */ +#define DCORE0_TPC0_CFG_LFSR_POLYNOM_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LFSR_POLYNOM_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_STATUS */ +#define DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT 1 +#define DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK 0x2 +#define DCORE0_TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT 2 +#define DCORE0_TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK 0x4 +#define DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_SHIFT 3 +#define DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_MASK 0x8 +#define DCORE0_TPC0_CFG_STATUS_SB_EMPTY_SHIFT 5 +#define DCORE0_TPC0_CFG_STATUS_SB_EMPTY_MASK 0x20 +#define DCORE0_TPC0_CFG_STATUS_QM_IDLE_SHIFT 6 +#define DCORE0_TPC0_CFG_STATUS_QM_IDLE_MASK 0x40 +#define DCORE0_TPC0_CFG_STATUS_QM_RDY_SHIFT 7 +#define DCORE0_TPC0_CFG_STATUS_QM_RDY_MASK 0x80 + +/* DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH */ +#define DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define DCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE */ +#define DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT 0 +#define DCORE0_TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH */ +#define DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define DCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TPC_CMD */ +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK 0x1 +#define DCORE0_TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT 1 +#define DCORE0_TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK 0x2 +#define DCORE0_TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT 2 +#define DCORE0_TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK 0x4 +#define DCORE0_TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT 3 +#define DCORE0_TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK 0x8 +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT 4 +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK 0x10 +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT 5 +#define DCORE0_TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK 0x20 +#define DCORE0_TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT 6 +#define DCORE0_TPC0_CFG_TPC_CMD_QMAN_STOP_MASK 0x40 + +/* DCORE0_TPC0_CFG_TPC_EXECUTE */ +#define DCORE0_TPC0_CFG_TPC_EXECUTE_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_EXECUTE_V_MASK 0x1 + +/* DCORE0_TPC0_CFG_TPC_STALL */ +#define DCORE0_TPC0_CFG_TPC_STALL_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_STALL_V_MASK 0x1 + +/* DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */ +#define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT 0 +#define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */ +#define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT 0 +#define DCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_RD_RATE_LIMIT */ +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_ENABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_ENABLE_MASK 0x1 +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_SATURATION_SHIFT 1 +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_SATURATION_MASK 0x1FE +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_SHIFT 9 +#define DCORE0_TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 + +/* DCORE0_TPC0_CFG_WR_RATE_LIMIT */ +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_ENABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_ENABLE_MASK 0x1 +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_SATURATION_SHIFT 1 +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_SATURATION_MASK 0x1FE +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_SHIFT 9 +#define DCORE0_TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 + +/* DCORE0_TPC0_CFG_MSS_CONFIG */ +#define DCORE0_TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT 0 +#define DCORE0_TPC0_CFG_MSS_CONFIG_AWCACHE_MASK 0xF +#define DCORE0_TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT 4 +#define DCORE0_TPC0_CFG_MSS_CONFIG_ARCACHE_MASK 0xF0 +#define DCORE0_TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT 8 +#define DCORE0_TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK 0x300 +#define DCORE0_TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT 10 +#define DCORE0_TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK 0x400 +#define DCORE0_TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_SHIFT 11 +#define DCORE0_TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_MASK 0x800 + +/* DCORE0_TPC0_CFG_TPC_INTR_CAUSE */ +#define DCORE0_TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TPC_INTR_MASK */ +#define DCORE0_TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT 0 +#define DCORE0_TPC0_CFG_TPC_INTR_MASK_MASK_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_WQ_CREDITS */ +#define DCORE0_TPC0_CFG_WQ_CREDITS_ST_G_SHIFT 0 +#define DCORE0_TPC0_CFG_WQ_CREDITS_ST_G_MASK 0xF +#define DCORE0_TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_SHIFT 4 +#define DCORE0_TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_MASK 0x70 + +/* DCORE0_TPC0_CFG_OPCODE_EXEC */ +#define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_OP_SHIFT 0 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_OP_MASK 0x7F +#define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_EN_SHIFT 7 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_SPU_EN_MASK 0x80 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_OP_SHIFT 8 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_OP_MASK 0x7F00 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_EN_SHIFT 15 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_VPU_EN_MASK 0x8000 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_OP_SHIFT 16 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_OP_MASK 0x7F0000 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_EN_SHIFT 23 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_LD_EN_MASK 0x800000 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_OP_SHIFT 24 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_OP_MASK 0x7F000000 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_EN_SHIFT 31 +#define DCORE0_TPC0_CFG_OPCODE_EXEC_ST_EN_MASK 0x80000000 + +/* DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO */ +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI */ +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_SHIFT 0 +#define DCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE */ +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_MASK 0xFFFF +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_MD_SHIFT 16 +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_SIZE_MD_MASK 0xFFFF0000 + +/* DCORE0_TPC0_CFG_TSB_CFG */ +#define DCORE0_TPC0_CFG_TSB_CFG_CACHE_DISABLE_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_CFG_CACHE_DISABLE_MASK 0x1 +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_OS_SHIFT 1 +#define DCORE0_TPC0_CFG_TSB_CFG_MAX_OS_MASK 0x1FFFE +#define DCORE0_TPC0_CFG_TSB_CFG_ENABLE_CGATE_SHIFT 17 +#define DCORE0_TPC0_CFG_TSB_CFG_ENABLE_CGATE_MASK 0x20000 + +/* DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR */ +#define DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR_V_SHIFT 0 +#define DCORE0_TPC0_CFG_TSB_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR */ +#define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_SHIFT 0 +#define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_MASK 0xFFFF +#define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_SHIFT 16 +#define DCORE0_TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_MASK 0x1FF0000 + +/* DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR */ +#define DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_SHIFT 0 +#define DCORE0_TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR */ +#define DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_SHIFT 0 +#define DCORE0_TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF + +/* DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR */ +#define DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR_V_SHIFT 0 +#define DCORE0_TPC0_CFG_IRQ_OCCOUPY_CNTR_V_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_MASKS_H_ */ |