1 files changed, 151 insertions, 0 deletions
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_spmu_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_spmu_regs.h
new file mode 100644
index 000000000000..580ae57476bd
--- /dev/null
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_eml_spmu_regs.h
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright 2016-2020 HabanaLabs, Ltd.
+ * All Rights Reserved.
+ *
+ */
+
+/************************************
+ ** This is an auto-generated file **
+ **       DO NOT EDIT BELOW        **
+ ************************************/
+
+#ifndef ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_
+#define ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_
+
+/*
+ *****************************************
+ *   DCORE0_TPC0_EML_SPMU
+ *   (Prototype: SPMU)
+ *****************************************
+ */
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 0x1000
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 0x1008
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 0x1010
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 0x1018
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 0x1020
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 0x1028
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 0x10F8
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 0x10FC
+
+#define mmDCORE0_TPC0_EML_SPMU_PMTRC 0x1200
+
+#define mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST 0x1204
+
+#define mmDCORE0_TPC0_EML_SPMU_TRC_STAT_HOST 0x1208
+
+#define mmDCORE0_TPC0_EML_SPMU_TRC_EN_HOST 0x120C
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER0_EL0 0x1400
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER1_EL0 0x1404
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER2_EL0 0x1408
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER3_EL0 0x140C
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER4_EL0 0x1410
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER5_EL0 0x1414
+
+#define mmDCORE0_TPC0_EML_SPMU_PMSSR 0x1610
+
+#define mmDCORE0_TPC0_EML_SPMU_PMOVSSR 0x1614
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_L 0x1618
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_H 0x161C
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR0 0x1620
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR1 0x1624
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR2 0x1628
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR3 0x162C
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR4 0x1630
+
+#define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR5 0x1634
+
+#define mmDCORE0_TPC0_EML_SPMU_PMSCR 0x16F0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMSRR 0x16F4
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCNTENSET_EL0 0x1C00
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCNTENCLR_EL0 0x1C20
+
+#define mmDCORE0_TPC0_EML_SPMU_PMINTENSET_EL1 0x1C40
+
+#define mmDCORE0_TPC0_EML_SPMU_PMINTENCLR_EL1 0x1C60
+
+#define mmDCORE0_TPC0_EML_SPMU_PMOVSCLR_EL0 0x1C80
+
+#define mmDCORE0_TPC0_EML_SPMU_PMSWINC_EL0 0x1CA0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMOVSSET_EL0 0x1CC0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCFGR 0x1E00
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCR_EL0 0x1E04
+
+#define mmDCORE0_TPC0_EML_SPMU_PMITCTRL 0x1F00
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCLAIMSET 0x1FA0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCLAIMCLR 0x1FA4
+
+#define mmDCORE0_TPC0_EML_SPMU_PMDEVAFF0 0x1FA8
+
+#define mmDCORE0_TPC0_EML_SPMU_PMDEVAFF1 0x1FAC
+
+#define mmDCORE0_TPC0_EML_SPMU_PMLAR 0x1FB0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMLSR 0x1FB4
+
+#define mmDCORE0_TPC0_EML_SPMU_PMAUTHSTATUS 0x1FB8
+
+#define mmDCORE0_TPC0_EML_SPMU_PMDEVARCH 0x1FBC
+
+#define mmDCORE0_TPC0_EML_SPMU_PMDEVID2 0x1FC0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMDEVID1 0x1FC4
+
+#define mmDCORE0_TPC0_EML_SPMU_PMDEVID 0x1FC8
+
+#define mmDCORE0_TPC0_EML_SPMU_PMDEVTYPE 0x1FCC
+
+#define mmDCORE0_TPC0_EML_SPMU_PMPIDR4 0x1FD0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMPIDR5 0x1FD4
+
+#define mmDCORE0_TPC0_EML_SPMU_PMPIDR6 0x1FD8
+
+#define mmDCORE0_TPC0_EML_SPMU_PMPIDR7 0x1FDC
+
+#define mmDCORE0_TPC0_EML_SPMU_PMPIDR0 0x1FE0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMPIDR1 0x1FE4
+
+#define mmDCORE0_TPC0_EML_SPMU_PMPIDR2 0x1FE8
+
+#define mmDCORE0_TPC0_EML_SPMU_PMPIDR3 0x1FEC
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCIDR0 0x1FF0
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCIDR1 0x1FF4
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCIDR2 0x1FF8
+
+#define mmDCORE0_TPC0_EML_SPMU_PMCIDR3 0x1FFC
+
+#endif /* ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_ */