diff options
Diffstat (limited to 'drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_arc_aux_regs.h')
| -rw-r--r-- | drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_arc_aux_regs.h | 591 |
1 files changed, 591 insertions, 0 deletions
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_arc_aux_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_arc_aux_regs.h new file mode 100644 index 000000000000..9b1cb609d134 --- /dev/null +++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pdma0_qm_arc_aux_regs.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PDMA0_QM_ARC_AUX_REGS_H_ +#define ASIC_REG_PDMA0_QM_ARC_AUX_REGS_H_ + +/* + ***************************************** + * PDMA0_QM_ARC_AUX + * (Prototype: QMAN_ARC_AUX) + ***************************************** + */ + +#define mmPDMA0_QM_ARC_AUX_RUN_HALT_REQ 0x4C88100 + +#define mmPDMA0_QM_ARC_AUX_RUN_HALT_ACK 0x4C88104 + +#define mmPDMA0_QM_ARC_AUX_RST_VEC_ADDR 0x4C88108 + +#define mmPDMA0_QM_ARC_AUX_DBG_MODE 0x4C8810C + +#define mmPDMA0_QM_ARC_AUX_CLUSTER_NUM 0x4C88110 + +#define mmPDMA0_QM_ARC_AUX_ARC_NUM 0x4C88114 + +#define mmPDMA0_QM_ARC_AUX_WAKE_UP_EVENT 0x4C88118 + +#define mmPDMA0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x4C8811C + +#define mmPDMA0_QM_ARC_AUX_CTI_AP_STS 0x4C88120 + +#define mmPDMA0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4C88124 + +#define mmPDMA0_QM_ARC_AUX_ARC_RST 0x4C88128 + +#define mmPDMA0_QM_ARC_AUX_ARC_RST_REQ 0x4C8812C + +#define mmPDMA0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4C88130 + +#define mmPDMA0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4C88134 + +#define mmPDMA0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4C88138 + +#define mmPDMA0_QM_ARC_AUX_PCIE_MSB_ADDR 0x4C8813C + +#define mmPDMA0_QM_ARC_AUX_CFG_LSB_ADDR 0x4C88140 + +#define mmPDMA0_QM_ARC_AUX_CFG_MSB_ADDR 0x4C88144 + +#define mmPDMA0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4C88150 + +#define mmPDMA0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4C88154 + +#define mmPDMA0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4C88158 + +#define mmPDMA0_QM_ARC_AUX_HBM1_MSB_ADDR 0x4C8815C + +#define mmPDMA0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4C88160 + +#define mmPDMA0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4C88164 + +#define mmPDMA0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4C88168 + +#define mmPDMA0_QM_ARC_AUX_HBM3_MSB_ADDR 0x4C8816C + +#define mmPDMA0_QM_ARC_AUX_HBM0_OFFSET 0x4C88170 + +#define mmPDMA0_QM_ARC_AUX_HBM1_OFFSET 0x4C88174 + +#define mmPDMA0_QM_ARC_AUX_HBM2_OFFSET 0x4C88178 + +#define mmPDMA0_QM_ARC_AUX_HBM3_OFFSET 0x4C8817C + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4C88180 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4C88184 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4C88188 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x4C8818C + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4C88190 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4C88194 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4C88198 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x4C8819C + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x4C881A0 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x4C881A4 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x4C881A8 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x4C881AC + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x4C881B0 + +#define mmPDMA0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x4C881B4 + +#define mmPDMA0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x4C881B8 + +#define mmPDMA0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x4C881BC + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_0 0x4C881C0 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_1 0x4C881C4 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_2 0x4C881C8 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_3 0x4C881CC + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_4 0x4C881D0 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_5 0x4C881D4 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_6 0x4C881D8 + +#define mmPDMA0_QM_ARC_AUX_CONTEXT_ID_7 0x4C881DC + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_0 0x4C881E0 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_1 0x4C881E4 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_2 0x4C881E8 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_3 0x4C881EC + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_4 0x4C881F0 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_5 0x4C881F4 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_6 0x4C881F8 + +#define mmPDMA0_QM_ARC_AUX_CID_OFFSET_7 0x4C881FC + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_0 0x4C88200 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_1 0x4C88204 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_2 0x4C88208 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_3 0x4C8820C + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_4 0x4C88210 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_5 0x4C88214 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_6 0x4C88218 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_7 0x4C8821C + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_8 0x4C88220 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_9 0x4C88224 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_10 0x4C88228 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_11 0x4C8822C + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_12 0x4C88230 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_13 0x4C88234 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_14 0x4C88238 + +#define mmPDMA0_QM_ARC_AUX_SW_INTR_15 0x4C8823C + +#define mmPDMA0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x4C88280 + +#define mmPDMA0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x4C88284 + +#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x4C88290 + +#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x4C88294 + +#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x4C88298 + +#define mmPDMA0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x4C8829C + +#define mmPDMA0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x4C882A0 + +#define mmPDMA0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x4C882A4 + +#define mmPDMA0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x4C882A8 + +#define mmPDMA0_QM_ARC_AUX_ARC_REI_INTR_STS 0x4C882B0 + +#define mmPDMA0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x4C882B4 + +#define mmPDMA0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x4C882B8 + +#define mmPDMA0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x4C882BC + +#define mmPDMA0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x4C882C0 + +#define mmPDMA0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x4C882C4 + +#define mmPDMA0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x4C882C8 + +#define mmPDMA0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x4C882CC + +#define mmPDMA0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x4C882D0 + +#define mmPDMA0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x4C882E0 + +#define mmPDMA0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x4C882E4 + +#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x4C882E8 + +#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x4C882EC + +#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x4C882F0 + +#define mmPDMA0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x4C882F4 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_0 0x4C88300 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_1 0x4C88304 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_2 0x4C88308 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_3 0x4C8830C + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_4 0x4C88310 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_5 0x4C88314 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_6 0x4C88318 + +#define mmPDMA0_QM_ARC_AUX_SCRATCHPAD_7 0x4C8831C + +#define mmPDMA0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x4C88320 + +#define mmPDMA0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x4C88324 + +#define mmPDMA0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x4C88328 + +#define mmPDMA0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x4C8832C + +#define mmPDMA0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x4C88330 + +#define mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x4C88334 + +#define mmPDMA0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x4C88338 + +#define mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x4C8833C + +#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_OVR 0x4C88350 + +#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x4C88354 + +#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_OVR 0x4C88358 + +#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x4C8835C + +#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x4C88360 + +#define mmPDMA0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x4C88364 + +#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x4C88368 + +#define mmPDMA0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x4C8836C + +#define mmPDMA0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x4C88370 + +#define mmPDMA0_QM_ARC_AUX_CBU_LOCK_OVR 0x4C88374 + +#define mmPDMA0_QM_ARC_AUX_CBU_PROT_OVR 0x4C88378 + +#define mmPDMA0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x4C8837C + +#define mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x4C88380 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x4C88384 + +#define mmPDMA0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x4C8838C + +#define mmPDMA0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x4C88390 + +#define mmPDMA0_QM_ARC_AUX_LBU_ARUSER_OVR 0x4C88400 + +#define mmPDMA0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x4C88404 + +#define mmPDMA0_QM_ARC_AUX_LBU_AWUSER_OVR 0x4C88408 + +#define mmPDMA0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x4C8840C + +#define mmPDMA0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x4C88420 + +#define mmPDMA0_QM_ARC_AUX_LBU_LOCK_OVR 0x4C88424 + +#define mmPDMA0_QM_ARC_AUX_LBU_PROT_OVR 0x4C88428 + +#define mmPDMA0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x4C8842C + +#define mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x4C88430 + +#define mmPDMA0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x4C88434 + +#define mmPDMA0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x4C8843C + +#define mmPDMA0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x4C88440 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4C88500 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4C88504 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4C88508 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x4C8850C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4C88510 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4C88514 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4C88518 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x4C8851C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x4C88520 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x4C88524 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x4C88528 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x4C8852C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x4C88530 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x4C88534 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x4C88538 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x4C8853C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x4C88540 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x4C88544 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x4C88548 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x4C8854C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x4C88550 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x4C88554 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x4C88558 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x4C8855C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x4C88560 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x4C88564 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x4C88568 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x4C8856C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x4C88570 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x4C88574 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x4C88578 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x4C8857C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x4C88580 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x4C88584 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x4C88588 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x4C8858C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x4C88590 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x4C88594 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x4C88598 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x4C8859C + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x4C885A0 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x4C885A4 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x4C885A8 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x4C885AC + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x4C885B0 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x4C885B4 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x4C885B8 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x4C885BC + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x4C885C0 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x4C885C4 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x4C885C8 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x4C885CC + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x4C885D0 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x4C885D4 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x4C885D8 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x4C885DC + +#define mmPDMA0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x4C885E0 + +#define mmPDMA0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x4C885E4 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x4C88620 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x4C88624 + +#define mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x4C88628 + +#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x4C88630 + +#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x4C88634 + +#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x4C88638 + +#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x4C8863C + +#define mmPDMA0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x4C88640 + +#define mmPDMA0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x4C88644 + +#define mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4C88648 + +#define mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x4C8864C + +#define mmPDMA0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4C88650 + +#define mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4C88654 + +#define mmPDMA0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x4C88658 + +#define mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x4C8865C + +#define mmPDMA0_QM_ARC_AUX_AUX2APB_PROT 0x4C88700 + +#define mmPDMA0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x4C88704 + +#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4C88708 + +#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x4C8870C + +#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4C88710 + +#define mmPDMA0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4C88714 + +#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4C88718 + +#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x4C8871C + +#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4C88720 + +#define mmPDMA0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4C88724 + +#define mmPDMA0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x4C88728 + +#define mmPDMA0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x4C8872C + +#define mmPDMA0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4C88730 + +#define mmPDMA0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4C88734 + +#define mmPDMA0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4C88738 + +#define mmPDMA0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x4C8873C + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x4C88740 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4C88750 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4C88754 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4C88758 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x4C8875C + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4C88760 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4C88764 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4C88768 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x4C8876C + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4C88770 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4C88774 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4C88778 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x4C8877C + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4C88780 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4C88784 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4C88788 + +#define mmPDMA0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x4C8878C + +#define mmPDMA0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x4C88790 + +#define mmPDMA0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x4C88794 + +#define mmPDMA0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x4C88798 + +#define mmPDMA0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x4C8879C + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_0 0x4C88800 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_1 0x4C88804 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_2 0x4C88808 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_3 0x4C8880C + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_4 0x4C88810 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_5 0x4C88814 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_6 0x4C88818 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_7 0x4C8881C + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_8 0x4C88820 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_9 0x4C88824 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_10 0x4C88828 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_11 0x4C8882C + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_12 0x4C88830 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_13 0x4C88834 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_14 0x4C88838 + +#define mmPDMA0_QM_ARC_AUX_ARC_REGION_CFG_15 0x4C8883C + +#define mmPDMA0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4C88840 + +#define mmPDMA0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4C88844 + +#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x4C88848 + +#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x4C8884C + +#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x4C88850 + +#define mmPDMA0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x4C88854 + +#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4C88900 + +#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x4C88904 + +#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4C88908 + +#define mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x4C8890C + +#define mmPDMA0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x4C88910 + +#define mmPDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x4C88920 + +#endif /* ASIC_REG_PDMA0_QM_ARC_AUX_REGS_H_ */ |