diff options
Diffstat (limited to 'drivers/acpi/spcr.c')
-rw-r--r-- | drivers/acpi/spcr.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/drivers/acpi/spcr.c b/drivers/acpi/spcr.c index 1eabfcd122ee..cd36a97b0ea2 100644 --- a/drivers/acpi/spcr.c +++ b/drivers/acpi/spcr.c @@ -71,7 +71,6 @@ static bool xgene_8250_erratum_present(struct acpi_table_spcr *tb) /** * acpi_parse_spcr() - parse ACPI SPCR table and add preferred console - * * @enable_earlycon: set up earlycon for the console specified by the table * @enable_console: setup the console specified by the table. * @@ -82,7 +81,6 @@ static bool xgene_8250_erratum_present(struct acpi_table_spcr *tb) * * When CONFIG_ACPI_SPCR_TABLE is defined, this function should be called * from arch initialization code as soon as the DT/ACPI decision is made. - * */ int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console) { @@ -97,9 +95,7 @@ int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console) if (acpi_disabled) return -ENODEV; - status = acpi_get_table(ACPI_SIG_SPCR, 0, - (struct acpi_table_header **)&table); - + status = acpi_get_table(ACPI_SIG_SPCR, 0, (struct acpi_table_header **)&table); if (ACPI_FAILURE(status)) return -ENOENT; @@ -110,12 +106,12 @@ int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console) u32 bit_width = table->serial_port.access_width; if (bit_width > ACPI_ACCESS_BIT_MAX) { - pr_err("Unacceptable wide SPCR Access Width. Defaulting to byte size\n"); + pr_err(FW_BUG "Unacceptable wide SPCR Access Width. Defaulting to byte size\n"); bit_width = ACPI_ACCESS_BIT_DEFAULT; } switch (ACPI_ACCESS_BIT_WIDTH((bit_width))) { default: - pr_err("Unexpected SPCR Access Width. Defaulting to byte size\n"); + pr_err(FW_BUG "Unexpected SPCR Access Width. Defaulting to byte size\n"); fallthrough; case 8: iotype = "mmio"; @@ -202,7 +198,8 @@ int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console) if (xgene_8250_erratum_present(table)) { iotype = "mmio32"; - /* for xgene v1 and v2 we don't know the clock rate of the + /* + * For xgene v1 and v2 we don't know the clock rate of the * UART so don't attempt to change to the baud rate state * in the table because driver cannot calculate the dividers */ |