diff options
Diffstat (limited to 'drivers/clk/mvebu')
| -rw-r--r-- | drivers/clk/mvebu/armada-37xx-periph.c | 6 | ||||
| -rw-r--r-- | drivers/clk/mvebu/armada-xp.c | 26 |
2 files changed, 4 insertions, 28 deletions
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c index 5fc6d486a381..f5746f9ea929 100644 --- a/drivers/clk/mvebu/armada-37xx-periph.c +++ b/drivers/clk/mvebu/armada-37xx-periph.c @@ -303,6 +303,7 @@ PERIPH_CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, clk_table1); PERIPH_CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6); PERIPH_CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12); PERIPH_CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18); +static PERIPH_GATE(pcie, 14); static struct clk_periph_data data_sb[] = { REF_CLK_MUX_DD(gbe_50), @@ -318,6 +319,7 @@ static struct clk_periph_data data_sb[] = { REF_CLK_FULL_DD(sdio), REF_CLK_FULL_DD(usb32_usb2_sys), REF_CLK_FULL_DD(usb32_ss_sys), + REF_CLK_GATE(pcie, "gbe_core"), { }, }; @@ -712,8 +714,8 @@ static int __maybe_unused armada_3700_periph_clock_resume(struct device *dev) } static const struct dev_pm_ops armada_3700_periph_clock_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(armada_3700_periph_clock_suspend, - armada_3700_periph_clock_resume) + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(armada_3700_periph_clock_suspend, + armada_3700_periph_clock_resume) }; static int armada_3700_periph_clock_probe(struct platform_device *pdev) diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c index fa1568279c23..45665655a258 100644 --- a/drivers/clk/mvebu/armada-xp.c +++ b/drivers/clk/mvebu/armada-xp.c @@ -50,12 +50,6 @@ static u32 __init axp_get_tclk_freq(void __iomem *sar) return 250000000; } -/* MV98DX3236 TCLK frequency is fixed to 200MHz */ -static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar) -{ - return 200000000; -} - static const u32 axp_cpu_freqs[] __initconst = { 1000000000, 1066000000, @@ -93,12 +87,6 @@ static u32 __init axp_get_cpu_freq(void __iomem *sar) return cpu_freq; } -/* MV98DX3236 CLK frequency is fixed to 800MHz */ -static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar) -{ - return 800000000; -} - static const int axp_nbclk_ratios[32][2] __initconst = { {0, 1}, {1, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 1}, {2, 3}, @@ -168,11 +156,6 @@ static const struct coreclk_soc_desc axp_coreclks = { .num_ratios = ARRAY_SIZE(axp_coreclk_ratios), }; -static const struct coreclk_soc_desc mv98dx3236_coreclks = { - .get_tclk_freq = mv98dx3236_get_tclk_freq, - .get_cpu_freq = mv98dx3236_get_cpu_freq, -}; - /* * Clock Gating Control */ @@ -210,15 +193,6 @@ static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = { { } }; -static const struct clk_gating_soc_desc mv98dx3236_gating_desc[] __initconst = { - { "ge1", NULL, 3, 0 }, - { "ge0", NULL, 4, 0 }, - { "pex00", NULL, 5, 0 }, - { "sdio", NULL, 17, 0 }, - { "xor0", NULL, 22, 0 }, - { } -}; - static void __init axp_clk_init(struct device_node *np) { struct device_node *cgnp = |