diff options
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/clk-si5351.c | 47 | ||||
| -rw-r--r-- | drivers/clk/clk-versaclock3.c | 88 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-cpu.h | 30 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk.h | 157 | ||||
| -rw-r--r-- | drivers/clk/starfive/clk-starfive-jh7100-audio.c | 2 | ||||
| -rw-r--r-- | drivers/clk/starfive/clk-starfive-jh7100.c | 32 | ||||
| -rw-r--r-- | drivers/clk/starfive/clk-starfive-jh7110-aon.c | 6 | ||||
| -rw-r--r-- | drivers/clk/starfive/clk-starfive-jh7110-isp.c | 2 | ||||
| -rw-r--r-- | drivers/clk/starfive/clk-starfive-jh7110-sys.c | 26 | ||||
| -rw-r--r-- | drivers/clk/starfive/clk-starfive-jh71x0.h | 4 |
10 files changed, 221 insertions, 173 deletions
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index a9a0bc448a4b..4ce83c5265b8 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -506,6 +506,8 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, { struct si5351_hw_data *hwdata = container_of(hw, struct si5351_hw_data, hw); + struct si5351_platform_data *pdata = + hwdata->drvdata->client->dev.platform_data; u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : SI5351_PLLB_PARAMETERS; @@ -518,9 +520,10 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); /* Do a pll soft reset on the affected pll */ - si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, - hwdata->num == 0 ? SI5351_PLL_RESET_A : - SI5351_PLL_RESET_B); + if (pdata->pll_reset[hwdata->num]) + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, + hwdata->num == 0 ? SI5351_PLL_RESET_A : + SI5351_PLL_RESET_B); dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", @@ -1222,6 +1225,44 @@ static int si5351_dt_parse(struct i2c_client *client, } } + /* + * Parse PLL reset mode. For compatibility with older device trees, the + * default is to always reset a PLL after setting its rate. + */ + pdata->pll_reset[0] = true; + pdata->pll_reset[1] = true; + + of_property_for_each_u32(np, "silabs,pll-reset-mode", prop, p, num) { + if (num >= 2) { + dev_err(&client->dev, + "invalid pll %d on pll-reset-mode prop\n", num); + return -EINVAL; + } + + p = of_prop_next_u32(prop, p, &val); + if (!p) { + dev_err(&client->dev, + "missing pll-reset-mode for pll %d\n", num); + return -EINVAL; + } + + switch (val) { + case 0: + /* Reset PLL whenever its rate is adjusted */ + pdata->pll_reset[num] = true; + break; + case 1: + /* Don't reset PLL whenever its rate is adjusted */ + pdata->pll_reset[num] = false; + break; + default: + dev_err(&client->dev, + "invalid pll-reset-mode %d for pll %d\n", val, + num); + return -EINVAL; + } + } + /* per clkout properties */ for_each_child_of_node(np, child) { if (of_property_read_u32(child, "reg", &num)) { diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c index 00930d7bca77..76d7ea1964c3 100644 --- a/drivers/clk/clk-versaclock3.c +++ b/drivers/clk/clk-versaclock3.c @@ -37,7 +37,7 @@ #define VC3_PLL1_M_DIV(n) ((n) & GENMASK(5, 0)) #define VC3_PLL1_VCO_N_DIVIDER 0x9 -#define VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0x0a +#define VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0xa #define VC3_OUT_DIV1_DIV2_CTRL 0xf @@ -148,16 +148,16 @@ struct vc3_pfd_data { }; struct vc3_pll_data { + unsigned long vco_min; + unsigned long vco_max; u8 num; u8 int_div_msb_offs; u8 int_div_lsb_offs; - unsigned long vco_min; - unsigned long vco_max; }; struct vc3_div_data { - u8 offs; const struct clk_div_table *table; + u8 offs; u8 shift; u8 width; u8 flags; @@ -210,7 +210,7 @@ static const struct clk_div_table div3_divs[] = { static struct clk_hw *clk_out[6]; -static unsigned char vc3_pfd_mux_get_parent(struct clk_hw *hw) +static u8 vc3_pfd_mux_get_parent(struct clk_hw *hw) { struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *pfd_mux = vc3->data; @@ -226,9 +226,8 @@ static int vc3_pfd_mux_set_parent(struct clk_hw *hw, u8 index) struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *pfd_mux = vc3->data; - regmap_update_bits(vc3->regmap, pfd_mux->offs, pfd_mux->bitmsk, - index ? pfd_mux->bitmsk : 0); - return 0; + return regmap_update_bits(vc3->regmap, pfd_mux->offs, pfd_mux->bitmsk, + index ? pfd_mux->bitmsk : 0); } static const struct clk_ops vc3_pfd_mux_ops = { @@ -440,7 +439,7 @@ static const struct clk_ops vc3_pll_ops = { .set_rate = vc3_pll_set_rate, }; -static unsigned char vc3_div_mux_get_parent(struct clk_hw *hw) +static u8 vc3_div_mux_get_parent(struct clk_hw *hw) { struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *div_mux = vc3->data; @@ -456,10 +455,8 @@ static int vc3_div_mux_set_parent(struct clk_hw *hw, u8 index) struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *div_mux = vc3->data; - regmap_update_bits(vc3->regmap, div_mux->offs, div_mux->bitmsk, - index ? div_mux->bitmsk : 0); - - return 0; + return regmap_update_bits(vc3->regmap, div_mux->offs, div_mux->bitmsk, + index ? div_mux->bitmsk : 0); } static const struct clk_ops vc3_div_mux_ops = { @@ -477,7 +474,7 @@ static unsigned int vc3_get_div(const struct clk_div_table *table, if (clkt->val == val) return clkt->div; - return 0; + return 1; } static unsigned long vc3_div_recalc_rate(struct clk_hw *hw, @@ -524,10 +521,9 @@ static int vc3_div_set_rate(struct clk_hw *hw, unsigned long rate, value = divider_get_val(rate, parent_rate, div_data->table, div_data->width, div_data->flags); - regmap_update_bits(vc3->regmap, div_data->offs, - VC3_DIV_MASK(div_data->width) << div_data->shift, - value << div_data->shift); - return 0; + return regmap_update_bits(vc3->regmap, div_data->offs, + VC3_DIV_MASK(div_data->width) << div_data->shift, + value << div_data->shift); } static const struct clk_ops vc3_div_ops = { @@ -539,11 +535,9 @@ static const struct clk_ops vc3_div_ops = { static int vc3_clk_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - int ret; int frc; - ret = clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT); - if (ret) { + if (clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT)) { /* The below check is equivalent to (best_parent_rate/rate) */ if (req->best_parent_rate >= req->rate) { frc = DIV_ROUND_CLOSEST_ULL(req->best_parent_rate, @@ -552,13 +546,12 @@ static int vc3_clk_mux_determine_rate(struct clk_hw *hw, return clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT); } - ret = 0; } - return ret; + return 0; } -static unsigned char vc3_clk_mux_get_parent(struct clk_hw *hw) +static u8 vc3_clk_mux_get_parent(struct clk_hw *hw) { struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *clk_mux = vc3->data; @@ -574,9 +567,8 @@ static int vc3_clk_mux_set_parent(struct clk_hw *hw, u8 index) struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *clk_mux = vc3->data; - regmap_update_bits(vc3->regmap, clk_mux->offs, - clk_mux->bitmsk, index ? clk_mux->bitmsk : 0); - return 0; + return regmap_update_bits(vc3->regmap, clk_mux->offs, clk_mux->bitmsk, + index ? clk_mux->bitmsk : 0); } static const struct clk_ops vc3_clk_mux_ops = { @@ -605,7 +597,7 @@ static struct vc3_hw_data clk_pfd_mux[] = { .offs = VC3_PLL_OP_CTRL, .bitmsk = BIT(VC3_PLL_OP_CTRL_PLL2_REFIN_SEL) }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pfd2_mux", .ops = &vc3_pfd_mux_ops, .parent_data = pfd_mux_parent_data, @@ -618,7 +610,7 @@ static struct vc3_hw_data clk_pfd_mux[] = { .offs = VC3_GENERAL_CTR, .bitmsk = BIT(VC3_GENERAL_CTR_PLL3_REFIN_SEL) }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pfd3_mux", .ops = &vc3_pfd_mux_ops, .parent_data = pfd_mux_parent_data, @@ -636,7 +628,7 @@ static struct vc3_hw_data clk_pfd[] = { .mdiv1_bitmsk = VC3_PLL1_M_DIV1, .mdiv2_bitmsk = VC3_PLL1_M_DIV2 }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pfd1", .ops = &vc3_pfd_ops, .parent_data = &(const struct clk_parent_data) { @@ -653,7 +645,7 @@ static struct vc3_hw_data clk_pfd[] = { .mdiv1_bitmsk = VC3_PLL2_M_DIV1, .mdiv2_bitmsk = VC3_PLL2_M_DIV2 }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pfd2", .ops = &vc3_pfd_ops, .parent_hws = (const struct clk_hw *[]) { @@ -670,7 +662,7 @@ static struct vc3_hw_data clk_pfd[] = { .mdiv1_bitmsk = VC3_PLL3_M_DIV1, .mdiv2_bitmsk = VC3_PLL3_M_DIV2 }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pfd3", .ops = &vc3_pfd_ops, .parent_hws = (const struct clk_hw *[]) { @@ -691,7 +683,7 @@ static struct vc3_hw_data clk_pll[] = { .vco_min = VC3_PLL1_VCO_MIN, .vco_max = VC3_PLL1_VCO_MAX }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pll1", .ops = &vc3_pll_ops, .parent_hws = (const struct clk_hw *[]) { @@ -709,7 +701,7 @@ static struct vc3_hw_data clk_pll[] = { .vco_min = VC3_PLL2_VCO_MIN, .vco_max = VC3_PLL2_VCO_MAX }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pll2", .ops = &vc3_pll_ops, .parent_hws = (const struct clk_hw *[]) { @@ -727,7 +719,7 @@ static struct vc3_hw_data clk_pll[] = { .vco_min = VC3_PLL3_VCO_MIN, .vco_max = VC3_PLL3_VCO_MAX }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pll3", .ops = &vc3_pll_ops, .parent_hws = (const struct clk_hw *[]) { @@ -760,7 +752,7 @@ static struct vc3_hw_data clk_div_mux[] = { .offs = VC3_GENERAL_CTR, .bitmsk = VC3_GENERAL_CTR_DIV1_SRC_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div1_mux", .ops = &vc3_div_mux_ops, .parent_data = div_mux_parent_data[VC3_DIV1_MUX], @@ -773,7 +765,7 @@ static struct vc3_hw_data clk_div_mux[] = { .offs = VC3_PLL3_CHARGE_PUMP_CTRL, .bitmsk = VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div3_mux", .ops = &vc3_div_mux_ops, .parent_data = div_mux_parent_data[VC3_DIV3_MUX], @@ -786,7 +778,7 @@ static struct vc3_hw_data clk_div_mux[] = { .offs = VC3_OUTPUT_CTR, .bitmsk = VC3_OUTPUT_CTR_DIV4_SRC_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div4_mux", .ops = &vc3_div_mux_ops, .parent_data = div_mux_parent_data[VC3_DIV4_MUX], @@ -805,7 +797,7 @@ static struct vc3_hw_data clk_div[] = { .width = 4, .flags = CLK_DIVIDER_READ_ONLY }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div1", .ops = &vc3_div_ops, .parent_hws = (const struct clk_hw *[]) { @@ -823,7 +815,7 @@ static struct vc3_hw_data clk_div[] = { .width = 4, .flags = CLK_DIVIDER_READ_ONLY }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div2", .ops = &vc3_div_ops, .parent_hws = (const struct clk_hw *[]) { @@ -841,7 +833,7 @@ static struct vc3_hw_data clk_div[] = { .width = 4, .flags = CLK_DIVIDER_READ_ONLY }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div3", .ops = &vc3_div_ops, .parent_hws = (const struct clk_hw *[]) { @@ -859,7 +851,7 @@ static struct vc3_hw_data clk_div[] = { .width = 4, .flags = CLK_DIVIDER_READ_ONLY }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div4", .ops = &vc3_div_ops, .parent_hws = (const struct clk_hw *[]) { @@ -877,7 +869,7 @@ static struct vc3_hw_data clk_div[] = { .width = 4, .flags = CLK_DIVIDER_READ_ONLY }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div5", .ops = &vc3_div_ops, .parent_hws = (const struct clk_hw *[]) { @@ -895,7 +887,7 @@ static struct vc3_hw_data clk_mux[] = { .offs = VC3_SE1_DIV4_CTRL, .bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "se1_mux", .ops = &vc3_clk_mux_ops, .parent_hws = (const struct clk_hw *[]) { @@ -911,7 +903,7 @@ static struct vc3_hw_data clk_mux[] = { .offs = VC3_SE2_CTRL_REG0, .bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "se2_mux", .ops = &vc3_clk_mux_ops, .parent_hws = (const struct clk_hw *[]) { @@ -927,7 +919,7 @@ static struct vc3_hw_data clk_mux[] = { .offs = VC3_SE3_DIFF1_CTRL_REG, .bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "se3_mux", .ops = &vc3_clk_mux_ops, .parent_hws = (const struct clk_hw *[]) { @@ -943,7 +935,7 @@ static struct vc3_hw_data clk_mux[] = { .offs = VC3_DIFF1_CTRL_REG, .bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "diff1_mux", .ops = &vc3_clk_mux_ops, .parent_hws = (const struct clk_hw *[]) { @@ -959,7 +951,7 @@ static struct vc3_hw_data clk_mux[] = { .offs = VC3_DIFF2_CTRL_REG, .bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "diff2_mux", .ops = &vc3_clk_mux_ops, .parent_hws = (const struct clk_hw *[]) { diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h index fc9f67a3b22e..0164bd9ad021 100644 --- a/drivers/clk/samsung/clk-cpu.h +++ b/drivers/clk/samsung/clk-cpu.h @@ -11,10 +11,10 @@ #include "clk.h" /** - * struct exynos_cpuclk_data: config data to setup cpu clocks. - * @prate: frequency of the primary parent clock (in KHz). - * @div0: value to be programmed in the div_cpu0 register. - * @div1: value to be programmed in the div_cpu1 register. + * struct exynos_cpuclk_cfg_data - config data to setup cpu clocks + * @prate: frequency of the primary parent clock (in KHz) + * @div0: value to be programmed in the div_cpu0 register + * @div1: value to be programmed in the div_cpu1 register * * This structure holds the divider configuration data for dividers in the CPU * clock domain. The parent frequency at which these divider values are valid is @@ -29,17 +29,17 @@ struct exynos_cpuclk_cfg_data { }; /** - * struct exynos_cpuclk: information about clock supplied to a CPU core. - * @hw: handle between CCF and CPU clock. - * @alt_parent: alternate parent clock to use when switching the speed - * of the primary parent clock. - * @ctrl_base: base address of the clock controller. - * @lock: cpu clock domain register access lock. - * @cfg: cpu clock rate configuration data. - * @num_cfgs: number of array elements in @cfg array. - * @clk_nb: clock notifier registered for changes in clock speed of the - * primary parent clock. - * @flags: configuration flags for the CPU clock. + * struct exynos_cpuclk - information about clock supplied to a CPU core + * @hw: handle between CCF and CPU clock + * @alt_parent: alternate parent clock to use when switching the speed + * of the primary parent clock + * @ctrl_base: base address of the clock controller + * @lock: cpu clock domain register access lock + * @cfg: cpu clock rate configuration data + * @num_cfgs: number of array elements in @cfg array + * @clk_nb: clock notifier registered for changes in clock speed of the + * primary parent clock + * @flags: configuration flags for the CPU clock * * This structure holds information required for programming the CPU clock for * various clock speeds. diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index ab9c3d7a25b3..516b716407e5 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -14,11 +14,11 @@ #include "clk-pll.h" /** - * struct samsung_clk_provider: information about clock provider - * @reg_base: virtual address for the register base. - * @dev: clock provider device needed for runtime PM. - * @lock: maintains exclusion between callbacks for a given clock-provider. - * @clk_data: holds clock related data like clk_hw* and number of clocks. + * struct samsung_clk_provider - information about clock provider + * @reg_base: virtual address for the register base + * @dev: clock provider device needed for runtime PM + * @lock: maintains exclusion between callbacks for a given clock-provider + * @clk_data: holds clock related data like clk_hw* and number of clocks */ struct samsung_clk_provider { void __iomem *reg_base; @@ -29,10 +29,10 @@ struct samsung_clk_provider { }; /** - * struct samsung_clock_alias: information about mux clock - * @id: platform specific id of the clock. - * @dev_name: name of the device to which this clock belongs. - * @alias: optional clock alias name to be assigned to this clock. + * struct samsung_clock_alias - information about mux clock + * @id: platform specific id of the clock + * @dev_name: name of the device to which this clock belongs + * @alias: optional clock alias name to be assigned to this clock */ struct samsung_clock_alias { unsigned int id; @@ -50,12 +50,12 @@ struct samsung_clock_alias { #define MHZ (1000 * 1000) /** - * struct samsung_fixed_rate_clock: information about fixed-rate clock - * @id: platform specific id of the clock. - * @name: name of this fixed-rate clock. - * @parent_name: optional parent clock name. - * @flags: optional fixed-rate clock flags. - * @fixed-rate: fixed clock rate of this clock. + * struct samsung_fixed_rate_clock - information about fixed-rate clock + * @id: platform specific id of the clock + * @name: name of this fixed-rate clock + * @parent_name: optional parent clock name + * @flags: optional fixed-rate clock flags + * @fixed_rate: fixed clock rate of this clock */ struct samsung_fixed_rate_clock { unsigned int id; @@ -74,14 +74,14 @@ struct samsung_fixed_rate_clock { .fixed_rate = frate, \ } -/* - * struct samsung_fixed_factor_clock: information about fixed-factor clock - * @id: platform specific id of the clock. - * @name: name of this fixed-factor clock. - * @parent_name: parent clock name. - * @mult: fixed multiplication factor. - * @div: fixed division factor. - * @flags: optional fixed-factor clock flags. +/** + * struct samsung_fixed_factor_clock - information about fixed-factor clock + * @id: platform specific id of the clock + * @name: name of this fixed-factor clock + * @parent_name: parent clock name + * @mult: fixed multiplication factor + * @div: fixed division factor + * @flags: optional fixed-factor clock flags */ struct samsung_fixed_factor_clock { unsigned int id; @@ -103,16 +103,16 @@ struct samsung_fixed_factor_clock { } /** - * struct samsung_mux_clock: information about mux clock - * @id: platform specific id of the clock. - * @name: name of this mux clock. - * @parent_names: array of pointer to parent clock names. - * @num_parents: number of parents listed in @parent_names. - * @flags: optional flags for basic clock. - * @offset: offset of the register for configuring the mux. - * @shift: starting bit location of the mux control bit-field in @reg. - * @width: width of the mux control bit-field in @reg. - * @mux_flags: flags for mux-type clock. + * struct samsung_mux_clock - information about mux clock + * @id: platform specific id of the clock + * @name: name of this mux clock + * @parent_names: array of pointer to parent clock names + * @num_parents: number of parents listed in @parent_names + * @flags: optional flags for basic clock + * @offset: offset of the register for configuring the mux + * @shift: starting bit location of the mux control bit-field in @reg + * @width: width of the mux control bit-field in @reg + * @mux_flags: flags for mux-type clock */ struct samsung_mux_clock { unsigned int id; @@ -146,14 +146,16 @@ struct samsung_mux_clock { __MUX(_id, cname, pnames, o, s, w, f, mf) /** - * @id: platform specific id of the clock. - * struct samsung_div_clock: information about div clock - * @name: name of this div clock. - * @parent_name: name of the parent clock. - * @flags: optional flags for basic clock. - * @offset: offset of the register for configuring the div. - * @shift: starting bit location of the div control bit-field in @reg. - * @div_flags: flags for div-type clock. + * struct samsung_div_clock - information about div clock + * @id: platform specific id of the clock + * @name: name of this div clock + * @parent_name: name of the parent clock + * @flags: optional flags for basic clock + * @offset: offset of the register for configuring the div + * @shift: starting bit location of the div control bit-field in @reg + * @width: width of the bitfield + * @div_flags: flags for div-type clock + * @table: array of divider/value pairs ending with a div set to 0 */ struct samsung_div_clock { unsigned int id; @@ -190,14 +192,14 @@ struct samsung_div_clock { __DIV(_id, cname, pname, o, s, w, 0, 0, t) /** - * struct samsung_gate_clock: information about gate clock - * @id: platform specific id of the clock. - * @name: name of this gate clock. - * @parent_name: name of the parent clock. - * @flags: optional flags for basic clock. - * @offset: offset of the register for configuring the gate. - * @bit_idx: bit index of the gate control bit-field in @reg. - * @gate_flags: flags for gate-type clock. + * struct samsung_gate_clock - information about gate clock + * @id: platform specific id of the clock + * @name: name of this gate clock + * @parent_name: name of the parent clock + * @flags: optional flags for basic clock + * @offset: offset of the register for configuring the gate + * @bit_idx: bit index of the gate control bit-field in @reg + * @gate_flags: flags for gate-type clock */ struct samsung_gate_clock { unsigned int id; @@ -226,9 +228,9 @@ struct samsung_gate_clock { #define PNAME(x) static const char * const x[] __initconst /** - * struct samsung_clk_reg_dump: register dump of clock controller registers. - * @offset: clock register offset from the controller base address. - * @value: the value to be register at offset. + * struct samsung_clk_reg_dump - register dump of clock controller registers + * @offset: clock register offset from the controller base address + * @value: the value to be register at offset */ struct samsung_clk_reg_dump { u32 offset; @@ -236,14 +238,15 @@ struct samsung_clk_reg_dump { }; /** - * struct samsung_pll_clock: information about pll clock - * @id: platform specific id of the clock. - * @name: name of this pll clock. - * @parent_name: name of the parent clock. - * @flags: optional flags for basic clock. - * @con_offset: offset of the register for configuring the PLL. - * @lock_offset: offset of the register for locking the PLL. - * @type: Type of PLL to be registered. + * struct samsung_pll_clock - information about pll clock + * @id: platform specific id of the clock + * @name: name of this pll clock + * @parent_name: name of the parent clock + * @flags: optional flags for basic clock + * @con_offset: offset of the register for configuring the PLL + * @lock_offset: offset of the register for locking the PLL + * @type: type of PLL to be registered + * @rate_table: array of PLL settings for possible PLL rates */ struct samsung_pll_clock { unsigned int id; @@ -302,39 +305,51 @@ struct samsung_clock_reg_cache { unsigned int rsuspend_num; }; +/** + * struct samsung_cmu_info - all clocks information needed for CMU registration + * @pll_clks: list of PLL clocks + * @nr_pll_clks: count of clocks in @pll_clks + * @mux_clks: list of mux clocks + * @nr_mux_clks: count of clocks in @mux_clks + * @div_clks: list of div clocks + * @nr_div_clks: count of clocks in @div_clks + * @gate_clks: list of gate clocks + * @nr_gate_clks: count of clocks in @gate_clks + * @fixed_clks: list of fixed clocks + * @nr_fixed_clks: count clocks in @fixed_clks + * @fixed_factor_clks: list of fixed factor clocks + * @nr_fixed_factor_clks: count of clocks in @fixed_factor_clks + * @nr_clk_ids: total number of clocks with IDs assigned + * @cpu_clks: list of CPU clocks + * @nr_cpu_clks: count of clocks in @cpu_clks + * @clk_regs: list of clock registers + * @nr_clk_regs: count of clock registers in @clk_regs + * @suspend_regs: list of clock registers to set before suspend + * @nr_suspend_regs: count of clock registers in @suspend_regs + * @clk_name: name of the parent clock needed for CMU register access + */ struct samsung_cmu_info { - /* list of pll clocks and respective count */ const struct samsung_pll_clock *pll_clks; unsigned int nr_pll_clks; - /* list of mux clocks and respective count */ const struct samsung_mux_clock *mux_clks; unsigned int nr_mux_clks; - /* list of div clocks and respective count */ const struct samsung_div_clock *div_clks; unsigned int nr_div_clks; - /* list of gate clocks and respective count */ const struct samsung_gate_clock *gate_clks; unsigned int nr_gate_clks; - /* list of fixed clocks and respective count */ const struct samsung_fixed_rate_clock *fixed_clks; unsigned int nr_fixed_clks; - /* list of fixed factor clocks and respective count */ const struct samsung_fixed_factor_clock *fixed_factor_clks; unsigned int nr_fixed_factor_clks; - /* total number of clocks with IDs assigned*/ unsigned int nr_clk_ids; - /* list of cpu clocks and respective count */ const struct samsung_cpu_clock *cpu_clks; unsigned int nr_cpu_clks; - /* list and number of clocks registers */ const unsigned long *clk_regs; unsigned int nr_clk_regs; - /* list and number of clocks registers to set before suspend */ const struct samsung_clk_reg_dump *suspend_regs; unsigned int nr_suspend_regs; - /* name of the parent clock needed for CMU register access */ const char *clk_name; }; diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c index ee4bda14a40e..1fcf4e62f347 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c +++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c @@ -79,7 +79,7 @@ static const struct jh71x0_clk_data jh7100_audclk_data[] = { JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB), JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB), JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS), - JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2, + JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 0, 2, JH7100_AUDCLK_VAD_INTMEM, JH7100_AUDCLK_AUDIO_12288), }; diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c index 69cc11ea7e33..03f6f26a15d8 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100.c +++ b/drivers/clk/starfive/clk-starfive-jh7100.c @@ -24,48 +24,48 @@ #define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3) static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = { - JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4, + JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 0, 4, JH7100_CLK_OSC_SYS, JH7100_CLK_PLL0_OUT, JH7100_CLK_PLL1_OUT, JH7100_CLK_PLL2_OUT), - JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3, + JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 0, 3, JH7100_CLK_OSC_SYS, JH7100_CLK_PLL1_OUT, JH7100_CLK_PLL2_OUT), - JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4, + JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 0, 4, JH7100_CLK_OSC_SYS, JH7100_CLK_PLL0_OUT, JH7100_CLK_PLL1_OUT, JH7100_CLK_PLL2_OUT), - JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3, + JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 0, 3, JH7100_CLK_OSC_SYS, JH7100_CLK_PLL0_OUT, JH7100_CLK_PLL2_OUT), - JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2, + JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 0, 2, JH7100_CLK_OSC_SYS, JH7100_CLK_PLL0_OUT), - JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2, + JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 0, 2, JH7100_CLK_OSC_SYS, JH7100_CLK_PLL2_OUT), - JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3, + JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 0, 3, JH7100_CLK_OSC_SYS, JH7100_CLK_PLL1_OUT, JH7100_CLK_PLL2_OUT), - JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3, + JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 0, 3, JH7100_CLK_OSC_AUD, JH7100_CLK_PLL0_OUT, JH7100_CLK_PLL2_OUT), JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT), - JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3, + JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 0, 3, JH7100_CLK_OSC_SYS, JH7100_CLK_PLL1_OUT, JH7100_CLK_PLL2_OUT), - JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3, + JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 0, 3, JH7100_CLK_OSC_SYS, JH7100_CLK_PLL0_OUT, JH7100_CLK_PLL1_OUT), - JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3, + JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 0, 3, JH7100_CLK_OSC_AUD, JH7100_CLK_PLL0_OUT, JH7100_CLK_PLL2_OUT), @@ -76,7 +76,7 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = { JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC), JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT), JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC), - JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2, + JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 0, 2, JH7100_CLK_OSC_SYS, JH7100_CLK_OSC_AUD), JH71X0__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), @@ -142,7 +142,7 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = { JH71X0__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT), JH71X0_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS), JH71X0__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT), - JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2, + JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 0, 2, JH7100_CLK_CPU_AXI, JH7100_CLK_NNEBUS_SRC1), JH71X0_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS), @@ -166,7 +166,7 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = { JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV), JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, JH7100_CLK_USBPHY_ROOTDIV), - JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2, + JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 0, 2, JH7100_CLK_OSC_SYS, JH7100_CLK_USBPHY_PLLDIV25M), JH71X0_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT), @@ -200,12 +200,12 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = { JH71X0_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV), JH71X0_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF), JH71X0_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF), - JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3, + JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 3, JH7100_CLK_GMAC_GTX, JH7100_CLK_GMAC_TX_INV, JH7100_CLK_GMAC_RMII_TX), JH71X0__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX), - JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2, + JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 0, 2, JH7100_CLK_GMAC_GR_MII_RX, JH7100_CLK_GMAC_RMII_RX), JH71X0__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE), diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c index 62954eb7b50a..418efdad719b 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-aon.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c @@ -26,7 +26,7 @@ static const struct jh71x0_clk_data jh7110_aonclk_data[] = { /* source */ JH71X0__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC), - JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2, + JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 0, 2, JH7110_AONCLK_OSC_DIV4, JH7110_AONCLK_OSC), /* gmac0 */ @@ -39,7 +39,7 @@ static const struct jh71x0_clk_data jh7110_aonclk_data[] = { JH7110_AONCLK_GMAC0_GTXCLK, JH7110_AONCLK_GMAC0_RMII_RTX), JH71X0__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX), - JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2, + JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 0, 2, JH7110_AONCLK_GMAC0_RGMII_RXIN, JH7110_AONCLK_GMAC0_RMII_RTX), JH71X0__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX), @@ -48,7 +48,7 @@ static const struct jh71x0_clk_data jh7110_aonclk_data[] = { /* rtc */ JH71X0_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", 0, JH7110_AONCLK_APB_BUS), JH71X0__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC), - JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2, + JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 0, 2, JH7110_AONCLK_RTC_OSC, JH7110_AONCLK_RTC_INTERNAL), JH71X0_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC), diff --git a/drivers/clk/starfive/clk-starfive-jh7110-isp.c b/drivers/clk/starfive/clk-starfive-jh7110-isp.c index ce034ed28532..929b8788279e 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-isp.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-isp.c @@ -53,7 +53,7 @@ static const struct jh71x0_clk_data jh7110_ispclk_data[] = { JH7110_ISPCLK_MIPI_RX0_PXL), JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0, JH7110_ISPCLK_MIPI_RX0_PXL), - JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2, + JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 0, 2, JH7110_ISPCLK_MIPI_RX0_PXL, JH7110_ISPCLK_DVP_INV), /* ispv2_top_wrapper */ diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c index 3884eff9fe93..8f5e5abfa178 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -36,18 +36,18 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = { /* root */ - JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2, + JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 0, 2, JH7110_SYSCLK_OSC, JH7110_SYSCLK_PLL0_OUT), JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT), JH71X0__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE), - JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2, + JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 0, 2, JH7110_SYSCLK_PLL2_OUT, JH7110_SYSCLK_PLL1_OUT), JH71X0_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2, JH7110_SYSCLK_PLL0_OUT, JH7110_SYSCLK_PLL2_OUT), - JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2, + JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 0, 2, JH7110_SYSCLK_OSC, JH7110_SYSCLK_PLL2_OUT), JH71X0__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT), @@ -62,7 +62,7 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = { JH71X0__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT), JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT), JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT), - JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2, + JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 0, 2, JH7110_SYSCLK_MCLK_INNER, JH7110_SYSCLK_MCLK_EXT), JH71X0_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER), @@ -96,7 +96,7 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = { JH71X0__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC), JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2), JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4), - JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4, + JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 0, 4, JH7110_SYSCLK_OSC_DIV2, JH7110_SYSCLK_PLL1_DIV2, JH7110_SYSCLK_PLL1_DIV4, @@ -186,7 +186,7 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = { JH71X0__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30, JH7110_SYSCLK_GMAC1_RMII_REFIN), JH71X0_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC), - JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2, + JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 0, 2, JH7110_SYSCLK_GMAC1_RGMII_RXIN, JH7110_SYSCLK_GMAC1_RMII_RTX), JH71X0__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX), @@ -270,11 +270,11 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = { JH71X0_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2, JH7110_SYSCLK_I2STX0_BCLK_MST_INV, JH7110_SYSCLK_I2STX0_BCLK_MST), - JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2, + JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 0, 2, JH7110_SYSCLK_I2STX0_BCLK_MST, JH7110_SYSCLK_I2STX_BCLK_EXT), JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK), - JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2, + JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 0, 2, JH7110_SYSCLK_I2STX0_LRCK_MST, JH7110_SYSCLK_I2STX_LRCK_EXT), /* i2stx1 */ @@ -285,11 +285,11 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = { JH71X0_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2, JH7110_SYSCLK_I2STX1_BCLK_MST_INV, JH7110_SYSCLK_I2STX1_BCLK_MST), - JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2, + JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 0, 2, JH7110_SYSCLK_I2STX1_BCLK_MST, JH7110_SYSCLK_I2STX_BCLK_EXT), JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK), - JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2, + JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 0, 2, JH7110_SYSCLK_I2STX1_LRCK_MST, JH7110_SYSCLK_I2STX_LRCK_EXT), /* i2srx */ @@ -300,11 +300,11 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = { JH71X0_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2, JH7110_SYSCLK_I2SRX_BCLK_MST_INV, JH7110_SYSCLK_I2SRX_BCLK_MST), - JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2, + JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 0, 2, JH7110_SYSCLK_I2SRX_BCLK_MST, JH7110_SYSCLK_I2SRX_BCLK_EXT), JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK), - JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2, + JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 0, 2, JH7110_SYSCLK_I2SRX_LRCK_MST, JH7110_SYSCLK_I2SRX_LRCK_EXT), /* pdm */ @@ -314,7 +314,7 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = { JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0), JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0), JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK), - JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2, + JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 0, 2, JH7110_SYSCLK_TDM_INTERNAL, JH7110_SYSCLK_TDM_EXT), JH71X0__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM), diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-jh71x0.h index 34bb11c72eb7..23e052fc1549 100644 --- a/drivers/clk/starfive/clk-starfive-jh71x0.h +++ b/drivers/clk/starfive/clk-starfive-jh71x0.h @@ -61,10 +61,10 @@ struct jh71x0_clk_data { .parents = { [0] = _parent }, \ } -#define JH71X0__MUX(_idx, _name, _nparents, ...) \ +#define JH71X0__MUX(_idx, _name, _flags, _nparents, ...) \ [_idx] = { \ .name = _name, \ - .flags = 0, \ + .flags = _flags, \ .max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT, \ .parents = { __VA_ARGS__ }, \ } |