diff options
Diffstat (limited to 'drivers/clk')
251 files changed, 2931 insertions, 712 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 93f38a8178ba..fc6fe6baf80e 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -360,13 +360,6 @@ config COMMON_CLK_PXA help Support for the Marvell PXA SoC. -config COMMON_CLK_OXNAS - bool "Clock driver for the OXNAS SoC Family" - depends on ARCH_OXNAS || COMPILE_TEST - select MFD_SYSCON - help - Support for the OXNAS SoC Family clocks. - config COMMON_CLK_RS9_PCIE tristate "Clock driver for Renesas 9-series PCIe clock generators" depends on I2C @@ -385,6 +378,15 @@ config COMMON_CLK_SI521XX This driver supports the SkyWorks Si521xx PCIe clock generator models Si52144/Si52146/Si52147. +config COMMON_CLK_VC3 + tristate "Clock driver for Renesas VersaClock 3 devices" + depends on I2C + depends on OF + select REGMAP_I2C + help + This driver supports the Renesas VersaClock 3 programmable clock + generators. + config COMMON_CLK_VC5 tristate "Clock driver for IDT VersaClock 5,6 devices" depends on I2C diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 7cb000549b61..18969cbd4bb1 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -52,7 +52,6 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o -obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o obj-$(CONFIG_CLK_LS1028A_PLLDIG) += clk-plldig.o obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o @@ -76,6 +75,7 @@ obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o obj-$(CONFIG_COMMON_CLK_SI521XX) += clk-si521xx.o +obj-$(CONFIG_COMMON_CLK_VC3) += clk-versaclock3.o obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_VC7) += clk-versaclock7.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o diff --git a/drivers/clk/actions/owl-common.c b/drivers/clk/actions/owl-common.c index 4de97cc7cb54..c62024b7c737 100644 --- a/drivers/clk/actions/owl-common.c +++ b/drivers/clk/actions/owl-common.c @@ -8,8 +8,6 @@ // Copyright (c) 2018 Linaro Ltd. // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> -#include <linux/of_address.h> -#include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/regmap.h> @@ -43,10 +41,8 @@ int owl_clk_regmap_init(struct platform_device *pdev, { void __iomem *base; struct regmap *regmap; - struct resource *res; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); diff --git a/drivers/clk/actions/owl-common.h b/drivers/clk/actions/owl-common.h index c000a431471e..8fb65f3e82d7 100644 --- a/drivers/clk/actions/owl-common.h +++ b/drivers/clk/actions/owl-common.h @@ -12,10 +12,10 @@ #define _OWL_COMMON_H_ #include <linux/clk-provider.h> -#include <linux/of_platform.h> #include <linux/regmap.h> struct device_node; +struct platform_device; struct owl_clk_common { struct regmap *regmap; diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c index 242bf5d75bab..6c7a2b62b406 100644 --- a/drivers/clk/axs10x/pll_clock.c +++ b/drivers/clk/axs10x/pll_clock.c @@ -12,10 +12,9 @@ #include <linux/err.h> #include <linux/device.h> #include <linux/io.h> +#include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/slab.h> -#include <linux/of.h> /* PLL registers addresses */ #define PLL_REG_IDIV 0x0 diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c index 0e772e034812..84555a00f950 100644 --- a/drivers/clk/baikal-t1/clk-ccu-div.c +++ b/drivers/clk/baikal-t1/clk-ccu-div.c @@ -20,7 +20,6 @@ #include <linux/mfd/syscon.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_platform.h> #include <linux/ioport.h> #include <linux/regmap.h> diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 8dc476ef5bf9..fb04734afc80 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -32,7 +32,7 @@ #include <linux/io.h> #include <linux/math.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <dt-bindings/clock/bcm2835.h> diff --git a/drivers/clk/bcm/clk-bcm63xx-gate.c b/drivers/clk/bcm/clk-bcm63xx-gate.c index 0769f98767da..36c7b302e396 100644 --- a/drivers/clk/bcm/clk-bcm63xx-gate.c +++ b/drivers/clk/bcm/clk-bcm63xx-gate.c @@ -3,7 +3,6 @@ #include <linux/clk-provider.h> #include <linux/init.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <dt-bindings/clock/bcm3368-clock.h> diff --git a/drivers/clk/bcm/clk-sr.c b/drivers/clk/bcm/clk-sr.c index 5db021685d6d..3b2cf397b789 100644 --- a/drivers/clk/bcm/clk-sr.c +++ b/drivers/clk/bcm/clk-sr.c @@ -5,7 +5,7 @@ #include <linux/err.h> #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <dt-bindings/clock/bcm-sr.h> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 411ff5fb2c07..284710adaef5 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -4,8 +4,8 @@ #define pr_fmt(fmt) "clk-aspeed: " fmt #include <linux/mfd/syscon.h> +#include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/slab.h> diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c index a094a2601a37..f9e27f95a967 100644 --- a/drivers/clk/clk-ast2600.c +++ b/drivers/clk/clk-ast2600.c @@ -5,8 +5,8 @@ #define pr_fmt(fmt) "clk-ast2600: " fmt #include <linux/mfd/syscon.h> +#include <linux/mod_devicetable.h> #include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/slab.h> diff --git a/drivers/clk/clk-axm5516.c b/drivers/clk/clk-axm5516.c index 1afcfdf2e6f9..4a3462ee8f3e 100644 --- a/drivers/clk/clk-axm5516.c +++ b/drivers/clk/clk-axm5516.c @@ -541,14 +541,12 @@ MODULE_DEVICE_TABLE(of, axmclk_match_table); static int axmclk_probe(struct platform_device *pdev) { void __iomem *base; - struct resource *res; int i, ret; struct device *dev = &pdev->dev; struct regmap *regmap; size_t num_clks; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(dev, res); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); diff --git a/drivers/clk/clk-bm1880.c b/drivers/clk/clk-bm1880.c index 2a19e50fff68..002f7360b1c6 100644 --- a/drivers/clk/clk-bm1880.c +++ b/drivers/clk/clk-bm1880.c @@ -7,10 +7,10 @@ */ #include <linux/clk-provider.h> +#include <linux/io.h> #include <linux/kernel.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/slab.h> @@ -876,16 +876,13 @@ static int bm1880_clk_probe(struct platform_device *pdev) struct bm1880_clock_data *clk_data; void __iomem *pll_base, *sys_base; struct device *dev = &pdev->dev; - struct resource *res; int num_clks, i; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pll_base = devm_ioremap_resource(&pdev->dev, res); + pll_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pll_base)) return PTR_ERR(pll_base); - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - sys_base = devm_ioremap_resource(&pdev->dev, res); + sys_base = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(sys_base)) return PTR_ERR(sys_base); diff --git a/drivers/clk/clk-cdce925.c b/drivers/clk/clk-cdce925.c index 96ac90364847..cdee4958f26d 100644 --- a/drivers/clk/clk-cdce925.c +++ b/drivers/clk/clk-cdce925.c @@ -834,7 +834,7 @@ MODULE_DEVICE_TABLE(of, clk_cdce925_of_match); static struct i2c_driver cdce925_driver = { .driver = { .name = "cdce925", - .of_match_table = of_match_ptr(clk_cdce925_of_match), + .of_match_table = clk_cdce925_of_match, }, .probe = cdce925_probe, .id_table = cdce925_id, diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c index b82fee6a3d6f..35cb93ad298a 100644 --- a/drivers/clk/clk-cs2000-cp.c +++ b/drivers/clk/clk-cs2000-cp.c @@ -9,7 +9,7 @@ #include <linux/delay.h> #include <linux/clk.h> #include <linux/i2c.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/module.h> #include <linux/regmap.h> diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 29f0126cbd05..7cde328495e2 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -2,9 +2,8 @@ #include <linux/delay.h> #include <linux/clk-provider.h> +#include <linux/io.h> #include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <dt-bindings/clock/en7523-clk.h> diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c index ee5baf993ff2..cba45e07562d 100644 --- a/drivers/clk/clk-fsl-sai.c +++ b/drivers/clk/clk-fsl-sai.c @@ -33,14 +33,12 @@ static int fsl_sai_clk_probe(struct platform_device *pdev) struct clk_parent_data pdata = { .index = 0 }; void __iomem *base; struct clk_hw *hw; - struct resource *res; sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), GFP_KERNEL); if (!sai_clk) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(dev, res); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); diff --git a/drivers/clk/clk-gemini.c b/drivers/clk/clk-gemini.c index a23fa6d47ef1..4a085b042d22 100644 --- a/drivers/clk/clk-gemini.c +++ b/drivers/clk/clk-gemini.c @@ -276,7 +276,6 @@ static int gemini_clk_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; unsigned int mult, div; - struct resource *res; u32 val; int ret; int i; @@ -286,8 +285,7 @@ static int gemini_clk_probe(struct platform_device *pdev) return -ENOMEM; /* Remap the system controller for the exclusive register */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(dev, res); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c index 38755a241ab7..5b114043771d 100644 --- a/drivers/clk/clk-gpio.c +++ b/drivers/clk/clk-gpio.c @@ -15,8 +15,8 @@ #include <linux/gpio/consumer.h> #include <linux/err.h> #include <linux/device.h> +#include <linux/of.h> #include <linux/platform_device.h> -#include <linux/of_device.h> /** * DOC: basic gpio gated clock which can be enabled and disabled diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c index 33b48ea5ea3d..5d2a90addf1a 100644 --- a/drivers/clk/clk-hsdk-pll.c +++ b/drivers/clk/clk-hsdk-pll.c @@ -12,7 +12,6 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/slab.h> @@ -304,7 +303,6 @@ static const struct clk_ops hsdk_pll_ops = { static int hsdk_pll_clk_probe(struct platform_device *pdev) { int ret; - struct resource *mem; const char *parent_name; unsigned int num_parents; struct hsdk_pll_clk *pll_clk; @@ -315,8 +313,7 @@ static int hsdk_pll_clk_probe(struct platform_device *pdev) if (!pll_clk) return -ENOMEM; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pll_clk->regs = devm_ioremap_resource(dev, mem); + pll_clk->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pll_clk->regs)) return PTR_ERR(pll_clk->regs); diff --git a/drivers/clk/clk-k210.c b/drivers/clk/clk-k210.c index 870adac5cdee..7b7329a907ab 100644 --- a/drivers/clk/clk-k210.c +++ b/drivers/clk/clk-k210.c @@ -11,7 +11,6 @@ #include <linux/platform_device.h> #include <linux/of.h> #include <linux/of_clk.h> -#include <linux/of_platform.h> #include <linux/of_address.h> #include <linux/clk-provider.h> #include <linux/bitfield.h> diff --git a/drivers/clk/clk-oxnas.c b/drivers/clk/clk-oxnas.c deleted file mode 100644 index 584e293156ad..000000000000 --- a/drivers/clk/clk-oxnas.c +++ /dev/null @@ -1,251 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Broadcom - * Copyright (C) 2012 Stephen Warren - * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> - */ - -#include <linux/clk-provider.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/of.h> -#include <linux/of_device.h> -#include <linux/platform_device.h> -#include <linux/stringify.h> -#include <linux/regmap.h> -#include <linux/mfd/syscon.h> - -#include <dt-bindings/clock/oxsemi,ox810se.h> -#include <dt-bindings/clock/oxsemi,ox820.h> - -/* Standard regmap gate clocks */ -struct clk_oxnas_gate { - struct clk_hw hw; - unsigned int bit; - struct regmap *regmap; -}; - -struct oxnas_stdclk_data { - struct clk_hw_onecell_data *onecell_data; - struct clk_oxnas_gate **gates; - unsigned int ngates; - struct clk_oxnas_pll **plls; - unsigned int nplls; -}; - -/* Regmap offsets */ -#define CLK_STAT_REGOFFSET 0x24 -#define CLK_SET_REGOFFSET 0x2c -#define CLK_CLR_REGOFFSET 0x30 - -static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw) -{ - return container_of(hw, struct clk_oxnas_gate, hw); -} - -static int oxnas_clk_gate_is_enabled(struct clk_hw *hw) -{ - struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw); - int ret; - unsigned int val; - - ret = regmap_read(std->regmap, CLK_STAT_REGOFFSET, &val); - if (ret < 0) - return ret; - - return val & BIT(std->bit); -} - -static int oxnas_clk_gate_enable(struct clk_hw *hw) -{ - struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw); - - regmap_write(std->regmap, CLK_SET_REGOFFSET, BIT(std->bit)); - - return 0; -} - -static void oxnas_clk_gate_disable(struct clk_hw *hw) -{ - struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw); - - regmap_write(std->regmap, CLK_CLR_REGOFFSET, BIT(std->bit)); -} - -static const struct clk_ops oxnas_clk_gate_ops = { - .enable = oxnas_clk_gate_enable, - .disable = oxnas_clk_gate_disable, - .is_enabled = oxnas_clk_gate_is_enabled, -}; - -static const char *const osc_parents[] = { - "oscillator", -}; - -static const char *const eth_parents[] = { - "gmacclk", -}; - -#define OXNAS_GATE(_name, _bit, _parents) \ -struct clk_oxnas_gate _name = { \ - .bit = (_bit), \ - .hw.init = &(struct clk_init_data) { \ - .name = #_name, \ - .ops = &oxnas_clk_gate_ops, \ - .parent_names = _parents, \ - .num_parents = ARRAY_SIZE(_parents), \ - .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ - }, \ -} - -static OXNAS_GATE(ox810se_leon, 0, osc_parents); -static OXNAS_GATE(ox810se_dma_sgdma, 1, osc_parents); -static OXNAS_GATE(ox810se_cipher, 2, osc_parents); -static OXNAS_GATE(ox810se_sata, 4, osc_parents); -static OXNAS_GATE(ox810se_audio, 5, osc_parents); -static OXNAS_GATE(ox810se_usbmph, 6, osc_parents); -static OXNAS_GATE(ox810se_etha, 7, eth_parents); -static OXNAS_GATE(ox810se_pciea, 8, osc_parents); -static OXNAS_GATE(ox810se_nand, 9, osc_parents); - -static struct clk_oxnas_gate *ox810se_gates[] = { - &ox810se_leon, - &ox810se_dma_sgdma, - &ox810se_cipher, - &ox810se_sata, - &ox810se_audio, - &ox810se_usbmph, - &ox810se_etha, - &ox810se_pciea, - &ox810se_nand, -}; - -static OXNAS_GATE(ox820_leon, 0, osc_parents); -static OXNAS_GATE(ox820_dma_sgdma, 1, osc_parents); -static OXNAS_GATE(ox820_cipher, 2, osc_parents); -static OXNAS_GATE(ox820_sd, 3, osc_parents); -static OXNAS_GATE(ox820_sata, 4, osc_parents); -static OXNAS_GATE(ox820_audio, 5, osc_parents); -static OXNAS_GATE(ox820_usbmph, 6, osc_parents); -static OXNAS_GATE(ox820_etha, 7, eth_parents); -static OXNAS_GATE(ox820_pciea, 8, osc_parents); -static OXNAS_GATE(ox820_nand, 9, osc_parents); -static OXNAS_GATE(ox820_ethb, 10, eth_parents); -static OXNAS_GATE(ox820_pcieb, 11, osc_parents); -static OXNAS_GATE(ox820_ref600, 12, osc_parents); -static OXNAS_GATE(ox820_usbdev, 13, osc_parents); - -static struct clk_oxnas_gate *ox820_gates[] = { - &ox820_leon, - &ox820_dma_sgdma, - &ox820_cipher, - &ox820_sd, - &ox820_sata, - &ox820_audio, - &ox820_usbmph, - &ox820_etha, - &ox820_pciea, - &ox820_nand, - &ox820_etha, - &ox820_pciea, - &ox820_ref600, - &ox820_usbdev, -}; - -static struct clk_hw_onecell_data ox810se_hw_onecell_data = { - .hws = { - [CLK_810_LEON] = &ox810se_leon.hw, - [CLK_810_DMA_SGDMA] = &ox810se_dma_sgdma.hw, - [CLK_810_CIPHER] = &ox810se_cipher.hw, - [CLK_810_SATA] = &ox810se_sata.hw, - [CLK_810_AUDIO] = &ox810se_audio.hw, - [CLK_810_USBMPH] = &ox810se_usbmph.hw, - [CLK_810_ETHA] = &ox810se_etha.hw, - [CLK_810_PCIEA] = &ox810se_pciea.hw, - [CLK_810_NAND] = &ox810se_nand.hw, - }, - .num = ARRAY_SIZE(ox810se_gates), -}; - -static struct clk_hw_onecell_data ox820_hw_onecell_data = { - .hws = { - [CLK_820_LEON] = &ox820_leon.hw, - [CLK_820_DMA_SGDMA] = &ox820_dma_sgdma.hw, - [CLK_820_CIPHER] = &ox820_cipher.hw, - [CLK_820_SD] = &ox820_sd.hw, - [CLK_820_SATA] = &ox820_sata.hw, - [CLK_820_AUDIO] = &ox820_audio.hw, - [CLK_820_USBMPH] = &ox820_usbmph.hw, - [CLK_820_ETHA] = &ox820_etha.hw, - [CLK_820_PCIEA] = &ox820_pciea.hw, - [CLK_820_NAND] = &ox820_nand.hw, - [CLK_820_ETHB] = &ox820_ethb.hw, - [CLK_820_PCIEB] = &ox820_pcieb.hw, - [CLK_820_REF600] = &ox820_ref600.hw, - [CLK_820_USBDEV] = &ox820_usbdev.hw, - }, - .num = ARRAY_SIZE(ox820_gates), -}; - -static struct oxnas_stdclk_data ox810se_stdclk_data = { - .onecell_data = &ox810se_hw_onecell_data, - .gates = ox810se_gates, - .ngates = ARRAY_SIZE(ox810se_gates), -}; - -static struct oxnas_stdclk_data ox820_stdclk_data = { - .onecell_data = &ox820_hw_onecell_data, - .gates = ox820_gates, - .ngates = ARRAY_SIZE(ox820_gates), -}; - -static const struct of_device_id oxnas_stdclk_dt_ids[] = { - { .compatible = "oxsemi,ox810se-stdclk", &ox810se_stdclk_data }, - { .compatible = "oxsemi,ox820-stdclk", &ox820_stdclk_data }, - { } -}; - -static int oxnas_stdclk_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node, *parent_np; - const struct oxnas_stdclk_data *data; - struct regmap *regmap; - int ret; - int i; - - data = of_device_get_match_data(&pdev->dev); - - parent_np = of_get_parent(np); - regmap = syscon_node_to_regmap(parent_np); - of_node_put(parent_np); - if (IS_ERR(regmap)) { - dev_err(&pdev->dev, "failed to have parent regmap\n"); - return PTR_ERR(regmap); - } - - for (i = 0 ; i < data->ngates ; ++i) - data->gates[i]->regmap = regmap; - - for (i = 0; i < data->onecell_data->num; i++) { - if (!data->onecell_data->hws[i]) - continue; - - ret = devm_clk_hw_register(&pdev->dev, - data->onecell_data->hws[i]); - if (ret) - return ret; - } - - return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, - data->onecell_data); -} - -static struct platform_driver oxnas_stdclk_driver = { - .probe = oxnas_stdclk_probe, - .driver = { - .name = "oxnas-stdclk", - .suppress_bind_attrs = true, - .of_match_table = oxnas_stdclk_dt_ids, - }, -}; -builtin_platform_driver(oxnas_stdclk_driver); diff --git a/drivers/clk/clk-palmas.c b/drivers/clk/clk-palmas.c index 74a241b1e1f4..5efb10776ae5 100644 --- a/drivers/clk/clk-palmas.c +++ b/drivers/clk/clk-palmas.c @@ -14,7 +14,6 @@ #include <linux/mfd/palmas.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/slab.h> diff --git a/drivers/clk/clk-plldig.c b/drivers/clk/clk-plldig.c index 25020164b89e..14357f3e4561 100644 --- a/drivers/clk/clk-plldig.c +++ b/drivers/clk/clk-plldig.c @@ -12,8 +12,6 @@ #include <linux/io.h> #include <linux/iopoll.h> #include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/bitfield.h> diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index e3386fd98c5e..4dcde305944c 100644 --- a/drivers/clk/clk-qoriq.c +++ b/drivers/clk/clk-qoriq.c @@ -17,8 +17,8 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/of_address.h> -#include <linux/of_platform.h> #include <linux/of.h> +#include <linux/platform_device.h> #include <linux/slab.h> #define PLL_DIV1 0 diff --git a/drivers/clk/clk-scpi.c b/drivers/clk/clk-scpi.c index 3fb4003453ee..108b697bd317 100644 --- a/drivers/clk/clk-scpi.c +++ b/drivers/clk/clk-scpi.c @@ -10,7 +10,6 @@ #include <linux/err.h> #include <linux/of.h> #include <linux/module.h> -#include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/scpi_protocol.h> diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index 31c3c8a71f12..00fb9b09e030 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -21,7 +21,7 @@ #include <linux/errno.h> #include <linux/rational.h> #include <linux/i2c.h> -#include <linux/of_platform.h> +#include <linux/of.h> #include <linux/platform_data/si5351.h> #include <linux/regmap.h> #include <linux/slab.h> diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c new file mode 100644 index 000000000000..7ab2447bd203 --- /dev/null +++ b/drivers/clk/clk-versaclock3.c @@ -0,0 +1,1143 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for Renesas Versaclock 3 + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include <linux/clk-provider.h> +#include <linux/i2c.h> +#include <linux/limits.h> +#include <linux/module.h> +#include <linux/regmap.h> + +#define NUM_CONFIG_REGISTERS 37 + +#define VC3_GENERAL_CTR 0x0 +#define VC3_GENERAL_CTR_DIV1_SRC_SEL BIT(3) +#define VC3_GENERAL_CTR_PLL3_REFIN_SEL BIT(2) + +#define VC3_PLL3_M_DIVIDER 0x3 +#define VC3_PLL3_M_DIV1 BIT(7) +#define VC3_PLL3_M_DIV2 BIT(6) +#define VC3_PLL3_M_DIV(n) ((n) & GENMASK(5, 0)) + +#define VC3_PLL3_N_DIVIDER 0x4 +#define VC3_PLL3_LOOP_FILTER_N_DIV_MSB 0x5 + +#define VC3_PLL3_CHARGE_PUMP_CTRL 0x6 +#define VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL BIT(7) + +#define VC3_PLL1_CTRL_OUTDIV5 0x7 +#define VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER BIT(7) + +#define VC3_PLL1_M_DIVIDER 0x8 +#define VC3_PLL1_M_DIV1 BIT(7) +#define VC3_PLL1_M_DIV2 BIT(6) +#define VC3_PLL1_M_DIV(n) ((n) & GENMASK(5, 0)) + +#define VC3_PLL1_VCO_N_DIVIDER 0x9 +#define VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0x0a + +#define VC3_OUT_DIV1_DIV2_CTRL 0xf + +#define VC3_PLL2_FB_INT_DIV_MSB 0x10 +#define VC3_PLL2_FB_INT_DIV_LSB 0x11 +#define VC3_PLL2_FB_FRC_DIV_MSB 0x12 +#define VC3_PLL2_FB_FRC_DIV_LSB 0x13 + +#define VC3_PLL2_M_DIVIDER 0x1a +#define VC3_PLL2_MDIV_DOUBLER BIT(7) +#define VC3_PLL2_M_DIV1 BIT(6) +#define VC3_PLL2_M_DIV2 BIT(5) +#define VC3_PLL2_M_DIV(n) ((n) & GENMASK(4, 0)) + +#define VC3_OUT_DIV3_DIV4_CTRL 0x1b + +#define VC3_PLL_OP_CTRL 0x1c +#define VC3_PLL_OP_CTRL_PLL2_REFIN_SEL 6 + +#define VC3_OUTPUT_CTR 0x1d +#define VC3_OUTPUT_CTR_DIV4_SRC_SEL BIT(3) + +#define VC3_SE2_CTRL_REG0 0x1f +#define VC3_SE2_CTRL_REG0_SE2_CLK_SEL BIT(6) + +#define VC3_SE3_DIFF1_CTRL_REG 0x21 +#define VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL BIT(6) + +#define VC3_DIFF1_CTRL_REG 0x22 +#define VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL BIT(7) + +#define VC3_DIFF2_CTRL_REG 0x23 +#define VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL BIT(7) + +#define VC3_SE1_DIV4_CTRL 0x24 +#define VC3_SE1_DIV4_CTRL_SE1_CLK_SEL BIT(3) + +#define VC3_PLL1_VCO_MIN 300000000UL +#define VC3_PLL1_VCO_MAX 600000000UL + +#define VC3_PLL2_VCO_MIN 400000000UL +#define VC3_PLL2_VCO_MAX 1200000000UL + +#define VC3_PLL3_VCO_MIN 300000000UL +#define VC3_PLL3_VCO_MAX 800000000UL + +#define VC3_2_POW_16 (U16_MAX + 1) +#define VC3_DIV_MASK(width) ((1 << (width)) - 1) + +enum vc3_pfd_mux { + VC3_PFD2_MUX, + VC3_PFD3_MUX, +}; + +enum vc3_pfd { + VC3_PFD1, + VC3_PFD2, + VC3_PFD3, +}; + +enum vc3_pll { + VC3_PLL1, + VC3_PLL2, + VC3_PLL3, +}; + +enum vc3_div_mux { + VC3_DIV1_MUX, + VC3_DIV3_MUX, + VC3_DIV4_MUX, +}; + +enum vc3_div { + VC3_DIV1, + VC3_DIV2, + VC3_DIV3, + VC3_DIV4, + VC3_DIV5, +}; + +enum vc3_clk_mux { + VC3_DIFF2_MUX, + VC3_DIFF1_MUX, + VC3_SE3_MUX, + VC3_SE2_MUX, + VC3_SE1_MUX, +}; + +enum vc3_clk { + VC3_DIFF2, + VC3_DIFF1, + VC3_SE3, + VC3_SE2, + VC3_SE1, + VC3_REF, +}; + +struct vc3_clk_data { + u8 offs; + u8 bitmsk; +}; + +struct vc3_pfd_data { + u8 num; + u8 offs; + u8 mdiv1_bitmsk; + u8 mdiv2_bitmsk; +}; + +struct vc3_pll_data { + u8 num; + u8 int_div_msb_offs; + u8 int_div_lsb_offs; + unsigned long vco_min; + unsigned long vco_max; +}; + +struct vc3_div_data { + u8 offs; + const struct clk_div_table *table; + u8 shift; + u8 width; + u8 flags; +}; + +struct vc3_hw_data { + struct clk_hw hw; + struct regmap *regmap; + const void *data; + + u32 div_int; + u32 div_frc; +}; + +static const struct clk_div_table div1_divs[] = { + { .val = 0, .div = 1, }, { .val = 1, .div = 4, }, + { .val = 2, .div = 5, }, { .val = 3, .div = 6, }, + { .val = 4, .div = 2, }, { .val = 5, .div = 8, }, + { .val = 6, .div = 10, }, { .val = 7, .div = 12, }, + { .val = 8, .div = 4, }, { .val = 9, .div = 16, }, + { .val = 10, .div = 20, }, { .val = 11, .div = 24, }, + { .val = 12, .div = 8, }, { .val = 13, .div = 32, }, + { .val = 14, .div = 40, }, { .val = 15, .div = 48, }, + {} +}; + +static const struct clk_div_table div245_divs[] = { + { .val = 0, .div = 1, }, { .val = 1, .div = 3, }, + { .val = 2, .div = 5, }, { .val = 3, .div = 10, }, + { .val = 4, .div = 2, }, { .val = 5, .div = 6, }, + { .val = 6, .div = 10, }, { .val = 7, .div = 20, }, + { .val = 8, .div = 4, }, { .val = 9, .div = 12, }, + { .val = 10, .div = 20, }, { .val = 11, .div = 40, }, + { .val = 12, .div = 5, }, { .val = 13, .div = 15, }, + { .val = 14, .div = 25, }, { .val = 15, .div = 50, }, + {} +}; + +static const struct clk_div_table div3_divs[] = { + { .val = 0, .div = 1, }, { .val = 1, .div = 3, }, + { .val = 2, .div = 5, }, { .val = 3, .div = 10, }, + { .val = 4, .div = 2, }, { .val = 5, .div = 6, }, + { .val = 6, .div = 10, }, { .val = 7, .div = 20, }, + { .val = 8, .div = 4, }, { .val = 9, .div = 12, }, + { .val = 10, .div = 20, }, { .val = 11, .div = 40, }, + { .val = 12, .div = 8, }, { .val = 13, .div = 24, }, + { .val = 14, .div = 40, }, { .val = 15, .div = 80, }, + {} +}; + +static struct clk_hw *clk_out[6]; + +static unsigned char vc3_pfd_mux_get_parent(struct clk_hw *hw) +{ + struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); + const struct vc3_clk_data *pfd_mux = vc3->data; + u32 src; + + regmap_read(vc3->regmap, pfd_mux->offs, &src); + + return !!(src & pfd_mux->bitmsk); +} + +static int vc3_pfd_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); + const struct vc3_clk_data *pfd_mux = vc3->data; + + regmap_update_bits(vc3->regmap, pfd_mux->offs, pfd_mux->bitmsk, + index ? pfd_mux->bitmsk : 0); + return 0; +} + +static const struct clk_ops vc3_pfd_mux_ops = { + .determine_rate = clk_hw_determine_rate_no_reparent, + .set_parent = vc3_pfd_mux_set_parent, + .get_parent = vc3_pfd_mux_get_parent, +}; + +static unsigned long vc3_pfd_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); + const struct vc3_pfd_data *pfd = vc3->data; + unsigned int prediv, premul; + unsigned long rate; + u8 mdiv; + + regmap_read(vc3->regmap, pfd->offs, &prediv); + if (pfd->num == VC3_PFD1) { + /* The bypass_prediv is set, PLL fed from Ref_in directly. */ + if (prediv & pfd->mdiv1_bitmsk) { + /* check doubler is set or not */ + regmap_read(vc3->regmap, VC3_PLL1_CTRL_OUTDIV5, &premul); + if (premul & VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER) + parent_rate *= 2; + return parent_rate; + } + mdiv = VC3_PLL1_M_DIV(prediv); + } else if (pfd->num == VC3_PFD2) { + /* The bypass_prediv is set, PLL fed from Ref_in directly. */ + if (prediv & pfd->mdiv1_bitmsk) { + regmap_read(vc3->regmap, VC3_PLL2_M_DIVIDER, &premul); + /* check doubler is set or not */ + if (premul & VC3_PLL2_MDIV_DOUBLER) + parent_rate *= 2; + return parent_rate; + } + + mdiv = VC3_PLL2_M_DIV(prediv); + } else { + /* The bypass_prediv is set, PLL fed from Ref_in directly. */ + if (prediv & pfd->mdiv1_bitmsk) + return parent_rate; + + mdiv = VC3_PLL3_M_DIV(prediv); + } + + if (prediv & pfd->mdiv2_bitmsk) + rate = parent_rate / 2; + else + rate = parent_rate / mdiv; + + return rate; +} + +static long vc3_pfd_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); + const struct vc3_pfd_data *pfd = vc3->data; + unsigned long idiv; + + /* PLL cannot operate with input clock above 50 MHz. */ + if (rate > 50000000) + return -EINVAL; + + /* CLKIN within range of PLL input, feed directly to PLL. */ + if (*parent_rate <= 50000000) + return *parent_rate; + + idiv = DIV_ROUND_UP(*parent_rate, rate); + if (pfd->num == VC3_PFD1 || pfd->num == VC3_PFD3) { + if (idiv > 63) + return -EINVAL; + } else { + if (idiv > 31) + return -EINVAL; + } + + return *parent_rate / idiv; +} + +static int vc3_pfd_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); + const struct vc3_pfd_data *pfd = vc3->data; + unsigned long idiv; + u8 div; + + /* CLKIN within range of PLL input, feed directly to PLL. */ + if (parent_rate <= 50000000) { + regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk, + pfd->mdiv1_bitmsk); + regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv2_bitmsk, 0); + return 0; + } + + idiv = DIV_ROUND_UP(parent_rate, rate); + /* We have dedicated div-2 predivider. */ + if (idiv == 2) { + regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv2_bitmsk, + pfd->mdiv2_bitmsk); + regmap_update_bits(vc3->regmap, pfd->offs, pfd->mdiv1_bitmsk, 0); + } else { + if (pfd->num == VC3_PFD1) + div = VC3_PLL1_M_DIV(idiv); + else if (pfd->num == VC3_PFD2) + div = VC3_PLL2_M_DIV(idiv); + else + div = VC3_PLL3_M_DIV(idiv); + + regmap_write(vc3->regmap, pfd->offs, div); + } + + return 0; +} + +static const struct clk_ops vc3_pfd_ops = { + .recalc_rate = vc3_pfd_recalc_rate, + .round_rate = vc3_pfd_round_rate, + .set_rate = vc3_pfd_set_rate, +}; + +static unsigned long vc3_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); + const struct vc3_pll_data *pll = vc3->data; + u32 div_int, div_frc, val; + unsigned long rate; + + regmap_read(vc3->regmap, pll->int_div_msb_offs, &val); + div_int = (val & GENMASK(2, 0)) << 8; + regmap_read(vc3->regmap, pll->int_div_lsb_offs, &val); + div_int |= val; + + if (pll->num == VC3_PLL2) { + regmap_read(vc3->regmap, VC3_PLL2_FB_FRC_DIV_MSB, &val); + div_frc = val << 8; + regmap_read(vc3->regmap, VC3_PLL2_FB_FRC_DIV_LSB, &val); + div_frc |= val; + rate = (parent_rate * + (div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16); + } else { + rate = parent_rate * div_int; + } + + return rate; +} + +static long vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); + const struct vc3_pll_data *pll = vc3->data; + u64 div_frc; + + if (rate < pll->vco_min) + rate = pll->vco_min; + if (rate > pll->vco_max) + rate = pll->vco_max; + + vc3->div_int = rate / *parent_rate; + + if (pll->num == VC3_PLL2) { + if (vc3->div_int > 0x7ff) + rate = *parent_rate * 0x7ff; + + /* Determine best fractional part, which is 16 bit wide */ + div_frc = rate % *parent_rate; + div_frc *= BIT(16) - 1; + do_div(div_frc, *parent_rate); + + vc3->div_frc = (u32)div_frc; + rate = (*parent_rate * + (vc3->div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16); + } else { + rate = *parent_rate * vc3->div_int; + } + + return rate; +} + +static int vc3_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); + const struct vc3_pll_data *pll = vc3->data; + u32 val; + + regmap_read(vc3->regmap, pll->int_div_msb_offs, &val); + val = (val & 0xf8) | ((vc3->div_int >> 8) & 0x7); + regmap_write(vc3->regmap, pll->int_div_msb_offs, val); + regmap_write(vc3->regmap, pll->int_div_lsb_offs, vc3->div_int & 0xff); + + if (pll->num == VC3_PLL2) { + regmap_write(vc3->regmap, VC3_PLL2_FB_FRC_DIV_MSB, + vc3->div_frc >> 8); + regmap_write(vc3->regmap, VC3_PLL2_FB_FRC_DIV_LSB, + vc3->div_frc & 0xff); + } + + return 0; +} + +static const struct clk_ops vc3_pll_ops = { + .recalc_rate = vc3_pll_recalc_rate, + .round_rate = vc3_pll_round_rate, + .set_rate = vc3_pll_set_rate, +}; + +static unsigned char vc3_div_mux_get_parent(struct clk_hw *hw) +{ + struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); + const struct vc3_clk_data *div_mux = vc3->data; + u32 src; + + regmap_read(vc3->regmap, div_mux->offs, &src); + + return !!(src & div_mux->bitmsk); +} + +static int vc3_div_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); + const struct vc3_clk_data *div_mux = vc3->data; + + regmap_update_bits(vc3->regmap, div_mux->offs, div_mux->bitmsk, + index ? div_mux->bitmsk : 0); + + return 0; +} + +static const struct clk_ops vc3_div_mux_ops = { + .determine_rate = clk_hw_determine_rate_no_reparent, + .set_parent = vc3_div_mux_set_parent, + .get_parent = vc3_div_mux_get_parent, +}; + +static unsigned int vc3_get_div(const struct clk_div_table *table, + unsigned int val, unsigned long flag) +{ + const struct clk_div_table *clkt; + + for (clkt = table; clkt->div; clkt++) + if (clkt->val == val) + return clkt->div; + + return 0; +} + +static unsigned long vc3_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); + const struct vc3_div_data *div_data = vc3->data; + unsigned int val; + + regmap_read(vc3->regmap, div_data->offs, &val); + val >>= div_data->shift; + val &= VC3_DIV_MASK(div_data->width); + + return divider_recalc_rate(hw, parent_rate, val, div_data->table, + div_data->flags, div_data->width); +} + +static long vc3_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); + const struct vc3_div_data *div_data = vc3->data; + unsigned int bestdiv; + + /* if read only, just return current value */ + if (div_data->flags & CLK_DIVIDER_READ_ONLY) { + regmap_read(vc3->regmap, div_data->offs, &bestdiv); + bestdiv >>= div_data->shift; + bestdiv &= VC3_DIV_MASK(div_data->width); + bestdiv = vc3_get_div(div_data->table, bestdiv, div_data->flags); + return DIV_ROUND_UP(*parent_rate, bestdiv); + } + + return divider_round_rate(hw, rate, parent_rate, div_data->table, + div_data->width, div_data->flags); +} + +static int vc3_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); + const struct vc3_div_data *div_data = vc3->data; + unsigned int value; + + value = divider_get_val(rate, parent_rate, div_data->table, + div_data->width, div_data->flags); + regmap_update_bits(vc3->regmap, div_data->offs, + VC3_DIV_MASK(div_data->width) << div_data->shift, + value << div_data->shift); + return 0; +} + +static const struct clk_ops vc3_div_ops = { + .recalc_rate = vc3_div_recalc_rate, + .round_rate = vc3_div_round_rate, + .set_rate = vc3_div_set_rate, +}; + +static int vc3_clk_mux_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + int ret; + int frc; + + ret = clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT); + if (ret) { + /* The below check is equivalent to (best_parent_rate/rate) */ + if (req->best_parent_rate >= req->rate) { + frc = DIV_ROUND_CLOSEST_ULL(req->best_parent_rate, + req->rate); + req->rate *= frc; + return clk_mux_determine_rate_flags(hw, req, + CLK_SET_RATE_PARENT); + } + ret = 0; + } + + return ret; +} + +static unsigned char vc3_clk_mux_get_parent(struct clk_hw *hw) +{ + struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); + const struct vc3_clk_data *clk_mux = vc3->data; + u32 val; + + regmap_read(vc3->regmap, clk_mux->offs, &val); + + return !!(val & clk_mux->bitmsk); +} + +static int vc3_clk_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); + const struct vc3_clk_data *clk_mux = vc3->data; + + regmap_update_bits(vc3->regmap, clk_mux->offs, + clk_mux->bitmsk, index ? clk_mux->bitmsk : 0); + return 0; +} + +static const struct clk_ops vc3_clk_mux_ops = { + .determine_rate = vc3_clk_mux_determine_rate, + .set_parent = vc3_clk_mux_set_parent, + .get_parent = vc3_clk_mux_get_parent, +}; + +static bool vc3_regmap_is_writeable(struct device *dev, unsigned int reg) +{ + return true; +} + +static const struct regmap_config vc3_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .cache_type = REGCACHE_RBTREE, + .max_register = 0x24, + .writeable_reg = vc3_regmap_is_writeable, +}; + +static struct vc3_hw_data clk_div[5]; + +static const struct clk_parent_data pfd_mux_parent_data[] = { + { .index = 0, }, + { .hw = &clk_div[VC3_DIV2].hw } +}; + +static struct vc3_hw_data clk_pfd_mux[] = { + [VC3_PFD2_MUX] = { + .data = &(struct vc3_clk_data) { + .offs = VC3_PLL_OP_CTRL, + .bitmsk = BIT(VC3_PLL_OP_CTRL_PLL2_REFIN_SEL) + }, + .hw.init = &(struct clk_init_data){ + .name = "pfd2_mux", + .ops = &vc3_pfd_mux_ops, + .parent_data = pfd_mux_parent_data, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT + } + }, + [VC3_PFD3_MUX] = { + .data = &(struct vc3_clk_data) { + .offs = VC3_GENERAL_CTR, + .bitmsk = BIT(VC3_GENERAL_CTR_PLL3_REFIN_SEL) + }, + .hw.init = &(struct clk_init_data){ + .name = "pfd3_mux", + .ops = &vc3_pfd_mux_ops, + .parent_data = pfd_mux_parent_data, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT + } + } +}; + +static struct vc3_hw_data clk_pfd[] = { + [VC3_PFD1] = { + .data = &(struct vc3_pfd_data) { + .num = VC3_PFD1, + .offs = VC3_PLL1_M_DIVIDER, + .mdiv1_bitmsk = VC3_PLL1_M_DIV1, + .mdiv2_bitmsk = VC3_PLL1_M_DIV2 + }, + .hw.init = &(struct clk_init_data){ + .name = "pfd1", + .ops = &vc3_pfd_ops, + .parent_data = &(const struct clk_parent_data) { + .index = 0 + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT + } + }, + [VC3_PFD2] = { + .data = &(struct vc3_pfd_data) { + .num = VC3_PFD2, + .offs = VC3_PLL2_M_DIVIDER, + .mdiv1_bitmsk = VC3_PLL2_M_DIV1, + .mdiv2_bitmsk = VC3_PLL2_M_DIV2 + }, + .hw.init = &(struct clk_init_data){ + .name = "pfd2", + .ops = &vc3_pfd_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_pfd_mux[VC3_PFD2_MUX].hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT + } + }, + [VC3_PFD3] = { + .data = &(struct vc3_pfd_data) { + .num = VC3_PFD3, + .offs = VC3_PLL3_M_DIVIDER, + .mdiv1_bitmsk = VC3_PLL3_M_DIV1, + .mdiv2_bitmsk = VC3_PLL3_M_DIV2 + }, + .hw.init = &(struct clk_init_data){ + .name = "pfd3", + .ops = &vc3_pfd_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_pfd_mux[VC3_PFD3_MUX].hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT + } + } +}; + +static struct vc3_hw_data clk_pll[] = { + [VC3_PLL1] = { + .data = &(struct vc3_pll_data) { + .num = VC3_PLL1, + .int_div_msb_offs = VC3_PLL1_LOOP_FILTER_N_DIV_MSB, + .int_div_lsb_offs = VC3_PLL1_VCO_N_DIVIDER, + .vco_min = VC3_PLL1_VCO_MIN, + .vco_max = VC3_PLL1_VCO_MAX + }, + .hw.init = &(struct clk_init_data){ + .name = "pll1", + .ops = &vc3_pll_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_pfd[VC3_PFD1].hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT + } + }, + [VC3_PLL2] = { + .data = &(struct vc3_pll_data) { + .num = VC3_PLL2, + .int_div_msb_offs = VC3_PLL2_FB_INT_DIV_MSB, + .int_div_lsb_offs = VC3_PLL2_FB_INT_DIV_LSB, + .vco_min = VC3_PLL2_VCO_MIN, + .vco_max = VC3_PLL2_VCO_MAX + }, + .hw.init = &(struct clk_init_data){ + .name = "pll2", + .ops = &vc3_pll_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_pfd[VC3_PFD2].hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT + } + }, + [VC3_PLL3] = { + .data = &(struct vc3_pll_data) { + .num = VC3_PLL3, + .int_div_msb_offs = VC3_PLL3_LOOP_FILTER_N_DIV_MSB, + .int_div_lsb_offs = VC3_PLL3_N_DIVIDER, + .vco_min = VC3_PLL3_VCO_MIN, + .vco_max = VC3_PLL3_VCO_MAX + }, + .hw.init = &(struct clk_init_data){ + .name = "pll3", + .ops = &vc3_pll_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_pfd[VC3_PFD3].hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT + } + } +}; + +static const struct clk_parent_data div_mux_parent_data[][2] = { + [VC3_DIV1_MUX] = { + { .hw = &clk_pll[VC3_PLL1].hw }, + { .index = 0 } + }, + [VC3_DIV3_MUX] = { + { .hw = &clk_pll[VC3_PLL2].hw }, + { .hw = &clk_pll[VC3_PLL3].hw } + }, + [VC3_DIV4_MUX] = { + { .hw = &clk_pll[VC3_PLL2].hw }, + { .index = 0 } + } +}; + +static struct vc3_hw_data clk_div_mux[] = { + [VC3_DIV1_MUX] = { + .data = &(struct vc3_clk_data) { + .offs = VC3_GENERAL_CTR, + .bitmsk = VC3_GENERAL_CTR_DIV1_SRC_SEL + }, + .hw.init = &(struct clk_init_data){ + .name = "div1_mux", + .ops = &vc3_div_mux_ops, + .parent_data = div_mux_parent_data[VC3_DIV1_MUX], + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT + } + }, + [VC3_DIV3_MUX] = { + .data = &(struct vc3_clk_data) { + .offs = VC3_PLL3_CHARGE_PUMP_CTRL, + .bitmsk = VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL + }, + .hw.init = &(struct clk_init_data){ + .name = "div3_mux", + .ops = &vc3_div_mux_ops, + .parent_data = div_mux_parent_data[VC3_DIV3_MUX], + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT + } + }, + [VC3_DIV4_MUX] = { + .data = &(struct vc3_clk_data) { + .offs = VC3_OUTPUT_CTR, + .bitmsk = VC3_OUTPUT_CTR_DIV4_SRC_SEL + }, + .hw.init = &(struct clk_init_data){ + .name = "div4_mux", + .ops = &vc3_div_mux_ops, + .parent_data = div_mux_parent_data[VC3_DIV4_MUX], + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT + } + } +}; + +static struct vc3_hw_data clk_div[] = { + [VC3_DIV1] = { + .data = &(struct vc3_div_data) { + .offs = VC3_OUT_DIV1_DIV2_CTRL, + .table = div1_divs, + .shift = 4, + .width = 4, + .flags = CLK_DIVIDER_READ_ONLY + }, + .hw.init = &(struct clk_init_data){ + .name = "div1", + .ops = &vc3_div_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_div_mux[VC3_DIV1_MUX].hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT + } + }, + [VC3_DIV2] = { + .data = &(struct vc3_div_data) { + .offs = VC3_OUT_DIV1_DIV2_CTRL, + .table = div245_divs, + .shift = 0, + .width = 4, + .flags = CLK_DIVIDER_READ_ONLY + }, + .hw.init = &(struct clk_init_data){ + .name = "div2", + .ops = &vc3_div_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_pll[VC3_PLL1].hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT + } + }, + [VC3_DIV3] = { + .data = &(struct vc3_div_data) { + .offs = VC3_OUT_DIV3_DIV4_CTRL, + .table = div3_divs, + .shift = 4, + .width = 4, + .flags = CLK_DIVIDER_READ_ONLY + }, + .hw.init = &(struct clk_init_data){ + .name = "div3", + .ops = &vc3_div_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_div_mux[VC3_DIV3_MUX].hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT + } + }, + [VC3_DIV4] = { + .data = &(struct vc3_div_data) { + .offs = VC3_OUT_DIV3_DIV4_CTRL, + .table = div245_divs, + .shift = 0, + .width = 4, + .flags = CLK_DIVIDER_READ_ONLY + }, + .hw.init = &(struct clk_init_data){ + .name = "div4", + .ops = &vc3_div_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_div_mux[VC3_DIV4_MUX].hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT + } + }, + [VC3_DIV5] = { + .data = &(struct vc3_div_data) { + .offs = VC3_PLL1_CTRL_OUTDIV5, + .table = div245_divs, + .shift = 0, + .width = 4, + .flags = CLK_DIVIDER_READ_ONLY + }, + .hw.init = &(struct clk_init_data){ + .name = "div5", + .ops = &vc3_div_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_pll[VC3_PLL3].hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT + } + } +}; + +static struct vc3_hw_data clk_mux[] = { + [VC3_DIFF2_MUX] = { + .data = &(struct vc3_clk_data) { + .offs = VC3_DIFF2_CTRL_REG, + .bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL + }, + .hw.init = &(struct clk_init_data){ + .name = "diff2_mux", + .ops = &vc3_clk_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_div[VC3_DIV1].hw, + &clk_div[VC3_DIV3].hw + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT + } + }, + [VC3_DIFF1_MUX] = { + .data = &(struct vc3_clk_data) { + .offs = VC3_DIFF1_CTRL_REG, + .bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL + }, + .hw.init = &(struct clk_init_data){ + .name = "diff1_mux", + .ops = &vc3_clk_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_div[VC3_DIV1].hw, + &clk_div[VC3_DIV3].hw + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT + } + }, + [VC3_SE3_MUX] = { + .data = &(struct vc3_clk_data) { + .offs = VC3_SE3_DIFF1_CTRL_REG, + .bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL + }, + .hw.init = &(struct clk_init_data){ + .name = "se3_mux", + .ops = &vc3_clk_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_div[VC3_DIV2].hw, + &clk_div[VC3_DIV4].hw + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT + } + }, + [VC3_SE2_MUX] = { + .data = &(struct vc3_clk_data) { + .offs = VC3_SE2_CTRL_REG0, + .bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL + }, + .hw.init = &(struct clk_init_data){ + .name = "se2_mux", + .ops = &vc3_clk_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_div[VC3_DIV5].hw, + &clk_div[VC3_DIV4].hw + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT + } + }, + [VC3_SE1_MUX] = { + .data = &(struct vc3_clk_data) { + .offs = VC3_SE1_DIV4_CTRL, + .bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL + }, + .hw.init = &(struct clk_init_data){ + .name = "se1_mux", + .ops = &vc3_clk_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_div[VC3_DIV5].hw, + &clk_div[VC3_DIV4].hw + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT + } + } +}; + +static struct clk_hw *vc3_of_clk_get(struct of_phandle_args *clkspec, + void *data) +{ + unsigned int idx = clkspec->args[0]; + struct clk_hw **clkout_hw = data; + + if (idx >= ARRAY_SIZE(clk_out)) { + pr_err("invalid clk index %u for provider %pOF\n", idx, clkspec->np); + return ERR_PTR(-EINVAL); + } + + return clkout_hw[idx]; +} + +static int vc3_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + u8 settings[NUM_CONFIG_REGISTERS]; + struct regmap *regmap; + const char *name; + int ret, i; + + regmap = devm_regmap_init_i2c(client, &vc3_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "failed to allocate register map\n"); + + ret = of_property_read_u8_array(dev->of_node, "renesas,settings", + settings, ARRAY_SIZE(settings)); + if (!ret) { + /* + * A raw settings array was specified in the DT. Write the + * settings to the device immediately. + */ + for (i = 0; i < NUM_CONFIG_REGISTERS; i++) { + ret = regmap_write(regmap, i, settings[i]); + if (ret) { + dev_err(dev, "error writing to chip (%i)\n", ret); + return ret; + } + } + } else if (ret == -EOVERFLOW) { + dev_err(&client->dev, "EOVERFLOW reg settings. ARRAY_SIZE: %zu\n", + ARRAY_SIZE(settings)); + return ret; + } + + /* Register pfd muxes */ + for (i = 0; i < ARRAY_SIZE(clk_pfd_mux); i++) { + clk_pfd_mux[i].regmap = regmap; + ret = devm_clk_hw_register(dev, &clk_pfd_mux[i].hw); + if (ret) + return dev_err_probe(dev, ret, "%s failed\n", + clk_pfd_mux[i].hw.init->name); + } + + /* Register pfd's */ + for (i = 0; i < ARRAY_SIZE(clk_pfd); i++) { + clk_pfd[i].regmap = regmap; + ret = devm_clk_hw_register(dev, &clk_pfd[i].hw); + if (ret) + return dev_err_probe(dev, ret, "%s failed\n", + clk_pfd[i].hw.init->name); + } + + /* Register pll's */ + for (i = 0; i < ARRAY_SIZE(clk_pll); i++) { + clk_pll[i].regmap = regmap; + ret = devm_clk_hw_register(dev, &clk_pll[i].hw); + if (ret) + return dev_err_probe(dev, ret, "%s failed\n", + clk_pll[i].hw.init->name); + } + + /* Register divider muxes */ + for (i = 0; i < ARRAY_SIZE(clk_div_mux); i++) { + clk_div_mux[i].regmap = regmap; + ret = devm_clk_hw_register(dev, &clk_div_mux[i].hw); + if (ret) + return dev_err_probe(dev, ret, "%s failed\n", + clk_div_mux[i].hw.init->name); + } + + /* Register dividers */ + for (i = 0; i < ARRAY_SIZE(clk_div); i++) { + clk_div[i].regmap = regmap; + ret = devm_clk_hw_register(dev, &clk_div[i].hw); + if (ret) + return dev_err_probe(dev, ret, "%s failed\n", + clk_div[i].hw.init->name); + } + + /* Register clk muxes */ + for (i = 0; i < ARRAY_SIZE(clk_mux); i++) { + clk_mux[i].regmap = regmap; + ret = devm_clk_hw_register(dev, &clk_mux[i].hw); + if (ret) + return dev_err_probe(dev, ret, "%s failed\n", + clk_mux[i].hw.init->name); + } + + /* Register clk outputs */ + for (i = 0; i < ARRAY_SIZE(clk_out); i++) { + switch (i) { + case VC3_DIFF2: + name = "diff2"; + break; + case VC3_DIFF1: + name = "diff1"; + break; + case VC3_SE3: + name = "se3"; + break; + case VC3_SE2: + name = "se2"; + break; + case VC3_SE1: + name = "se1"; + break; + case VC3_REF: + name = "ref"; + break; + default: + return dev_err_probe(dev, -EINVAL, "invalid clk output %d\n", i); + } + + if (i == VC3_REF) + clk_out[i] = devm_clk_hw_register_fixed_factor_index(dev, + name, 0, CLK_SET_RATE_PARENT, 1, 1); + else + clk_out[i] = devm_clk_hw_register_fixed_factor_parent_hw(dev, + name, &clk_mux[i].hw, CLK_SET_RATE_PARENT, 1, 1); + + if (IS_ERR(clk_out[i])) + return PTR_ERR(clk_out[i]); + } + + ret = devm_of_clk_add_hw_provider(dev, vc3_of_clk_get, clk_out); + if (ret) + return dev_err_probe(dev, ret, "unable to add clk provider\n"); + + return ret; +} + +static const struct of_device_id dev_ids[] = { + { .compatible = "renesas,5p35023" }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, dev_ids); + +static struct i2c_driver vc3_driver = { + .driver = { + .name = "vc3", + .of_match_table = of_match_ptr(dev_ids), + }, + .probe = vc3_probe, +}; +module_i2c_driver(vc3_driver); + +MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>"); +MODULE_DESCRIPTION("Renesas VersaClock 3 driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c index 8bc54176f325..17cbb30d20ad 100644 --- a/drivers/clk/clk-versaclock5.c +++ b/drivers/clk/clk-versaclock5.c @@ -19,7 +19,6 @@ #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_platform.h> #include <linux/property.h> #include <linux/regmap.h> #include <linux/slab.h> @@ -956,7 +955,7 @@ static int vc5_probe(struct i2c_client *client) i2c_set_clientdata(client, vc5); vc5->client = client; - vc5->chip_info = device_get_match_data(&client->dev); + vc5->chip_info = i2c_get_match_data(client); vc5->pin_xin = devm_clk_get(&client->dev, "xin"); if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER) diff --git a/drivers/clk/clk-versaclock7.c b/drivers/clk/clk-versaclock7.c index 9babb7913c1c..9ab35c1af0ff 100644 --- a/drivers/clk/clk-versaclock7.c +++ b/drivers/clk/clk-versaclock7.c @@ -14,7 +14,6 @@ #include <linux/math64.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_platform.h> #include <linux/property.h> #include <linux/regmap.h> #include <linux/swab.h> @@ -1109,7 +1108,7 @@ static int vc7_probe(struct i2c_client *client) i2c_set_clientdata(client, vc7); vc7->client = client; - vc7->chip_info = device_get_match_data(&client->dev); + vc7->chip_info = i2c_get_match_data(client); vc7->pin_xin = devm_clk_get(&client->dev, "xin"); if (PTR_ERR(vc7->pin_xin) == -EPROBE_DEFER) { diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c index ce4028102bc2..ff4ca0edce06 100644 --- a/drivers/clk/hisilicon/clk-hi3559a.c +++ b/drivers/clk/hisilicon/clk-hi3559a.c @@ -9,7 +9,7 @@ #include <linux/clk-provider.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c index a3d04c7c3da8..2d7186905abd 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c @@ -14,7 +14,6 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/slab.h> #include <dt-bindings/clock/hi3620-clock.h> diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index 41f61726ab19..50f13dbb0e48 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -6,7 +6,7 @@ #include <dt-bindings/clock/hi3660-clock.h> #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include "clk.h" diff --git a/drivers/clk/hisilicon/clk-hi3670.c b/drivers/clk/hisilicon/clk-hi3670.c index 4d05a71683a5..fa20ad144c8e 100644 --- a/drivers/clk/hisilicon/clk-hi3670.c +++ b/drivers/clk/hisilicon/clk-hi3670.c @@ -9,7 +9,7 @@ #include <dt-bindings/clock/hi3670-clock.h> #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include "clk.h" diff --git a/drivers/clk/hisilicon/clk-hi6220-stub.c b/drivers/clk/hisilicon/clk-hi6220-stub.c index 4fdee4424d82..a8319795ed1c 100644 --- a/drivers/clk/hisilicon/clk-hi6220-stub.c +++ b/drivers/clk/hisilicon/clk-hi6220-stub.c @@ -14,7 +14,7 @@ #include <linux/mfd/syscon.h> #include <linux/mailbox_client.h> #include <linux/of.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/regmap.h> /* Stub clocks id */ diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index e7cdf72d4b06..c9d5a88da053 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -11,9 +11,6 @@ #include <linux/clk-provider.h> #include <linux/clkdev.h> #include <linux/io.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/slab.h> #include <dt-bindings/clock/hi6220-clock.h> diff --git a/drivers/clk/hisilicon/clk-hip04.c b/drivers/clk/hisilicon/clk-hip04.c index 785b9faf3ea5..feb34e98af8c 100644 --- a/drivers/clk/hisilicon/clk-hip04.c +++ b/drivers/clk/hisilicon/clk-hip04.c @@ -11,9 +11,6 @@ #include <linux/kernel.h> #include <linux/clk-provider.h> #include <linux/io.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/slab.h> #include <dt-bindings/clock/hip04-clock.h> diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index 54d9fdc93599..09368fd32bef 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -16,7 +16,7 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/slab.h> #include "clk.h" diff --git a/drivers/clk/hisilicon/crg-hi3516cv300.c b/drivers/clk/hisilicon/crg-hi3516cv300.c index fe1bd3e3f988..e602e65fbc38 100644 --- a/drivers/clk/hisilicon/crg-hi3516cv300.c +++ b/drivers/clk/hisilicon/crg-hi3516cv300.c @@ -8,7 +8,7 @@ #include <dt-bindings/clock/hi3516cv300-clock.h> #include <linux/clk-provider.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include "clk.h" #include "crg.h" diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c index a0b16be1e25d..f651b197e45a 100644 --- a/drivers/clk/hisilicon/crg-hi3798cv200.c +++ b/drivers/clk/hisilicon/crg-hi3798cv200.c @@ -8,7 +8,7 @@ #include <dt-bindings/clock/histb-clock.h> #include <linux/clk-provider.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include "clk.h" #include "crg.h" diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c index 5e31a6a24b3a..5ce2c34e8f0c 100644 --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c @@ -9,8 +9,6 @@ #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/slab.h> diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 546a3703bfeb..cadcbb318f5c 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -9,7 +9,6 @@ #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/slab.h> diff --git a/drivers/clk/imx/clk-imx8ulp.c b/drivers/clk/imx/clk-imx8ulp.c index e308c88cb801..6636a1921b46 100644 --- a/drivers/clk/imx/clk-imx8ulp.c +++ b/drivers/clk/imx/clk-imx8ulp.c @@ -7,7 +7,7 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/reset-controller.h> #include <linux/slab.h> diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index 85041e339515..cd83c52e9952 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -9,7 +9,7 @@ #include <linux/bsearch.h> #include <linux/clk-provider.h> #include <linux/err.h> -#include <linux/of_platform.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_domain.h> #include <linux/pm_runtime.h> diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c index d59a7621bb20..ee5c72369334 100644 --- a/drivers/clk/keystone/pll.c +++ b/drivers/clk/keystone/pll.c @@ -209,7 +209,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) } clk = clk_register_pll(NULL, node->name, parent_name, pll_data); - if (clk) { + if (!IS_ERR_OR_NULL(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); return; } diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c index 6c1df4f11536..35fe197dd303 100644 --- a/drivers/clk/keystone/sci-clk.c +++ b/drivers/clk/keystone/sci-clk.c @@ -9,8 +9,7 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/module.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/soc/ti/ti_sci_protocol.h> diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/clk-mt2701-aud.c index 3ce7e71196fd..27eecb6d3a53 100644 --- a/drivers/clk/mediatek/clk-mt2701-aud.c +++ b/drivers/clk/mediatek/clk-mt2701-aud.c @@ -7,7 +7,7 @@ #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/of_platform.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index e03ac76279ba..d25687f6c9b4 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -6,9 +6,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 4a154da8a543..c81f3e33ce56 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -5,9 +5,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-cpumux.h" @@ -663,9 +661,8 @@ static int mtk_topckgen_init(struct platform_device *pdev) struct clk_hw_onecell_data *clk_data; void __iomem *base; struct device_node *node = pdev->dev.of_node; - struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); @@ -887,9 +884,8 @@ static int mtk_pericfg_init(struct platform_device *pdev) void __iomem *base; int r; struct device_node *node = pdev->dev.of_node; - struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index c4cc68c47af9..a8d12a1210fc 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -7,9 +7,7 @@ #include <linux/clk.h> #include <linux/delay.h> #include <linux/mfd/syscon.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/slab.h> diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c index 0377e6dd3206..1f4c8d0c041a 100644 --- a/drivers/clk/mediatek/clk-mt6765.c +++ b/drivers/clk/mediatek/clk-mt6765.c @@ -9,7 +9,7 @@ #include <linux/of_address.h> #include <linux/slab.h> #include <linux/mfd/syscon.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-gate.h" @@ -731,13 +731,10 @@ static int clk_mt6765_apmixed_probe(struct platform_device *pdev) int r; struct device_node *node = pdev->dev.of_node; void __iomem *base; - struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(base)) { - pr_err("%s(): ioremap failed\n", __func__); + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) return PTR_ERR(base); - } clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); @@ -766,13 +763,10 @@ static int clk_mt6765_top_probe(struct platform_device *pdev) struct device_node *node = pdev->dev.of_node; void __iomem *base; struct clk_hw_onecell_data *clk_data; - struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(base)) { - pr_err("%s(): ioremap failed\n", __func__); + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) return PTR_ERR(base); - } clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); @@ -807,13 +801,10 @@ static int clk_mt6765_ifr_probe(struct platform_device *pdev) int r; struct device_node *node = pdev->dev.of_node; void __iomem *base; - struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(base)) { - pr_err("%s(): ioremap failed\n", __func__); + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) return PTR_ERR(base); - } clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK); diff --git a/drivers/clk/mediatek/clk-mt6779-aud.c b/drivers/clk/mediatek/clk-mt6779-aud.c index a97e1117d30b..66ae6421e27e 100644 --- a/drivers/clk/mediatek/clk-mt6779-aud.c +++ b/drivers/clk/mediatek/clk-mt6779-aud.c @@ -6,9 +6,7 @@ #include <linux/module.h> #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index f33fbaee1404..3ee2f5a2319a 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -6,8 +6,6 @@ #include <linux/module.h> #include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include "clk-gate.h" diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c index 4c87c0348e5f..2ebd25f0ce71 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -5,8 +5,6 @@ */ #include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include "clk-gate.h" diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/clk-mt7622-aud.c index c3ce65ced902..42bade71e2f8 100644 --- a/drivers/clk/mediatek/clk-mt7622-aud.c +++ b/drivers/clk/mediatek/clk-mt7622-aud.c @@ -8,7 +8,7 @@ #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/of_platform.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index df81e445026a..62fdf127e77d 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -6,9 +6,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index 9c738d730a7b..b4a520ce362c 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -6,9 +6,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index fa5fb5891a09..27781a62a131 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -6,9 +6,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-cpumux.h" diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c index 1e1c77cc14ba..fe714debdc9e 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -7,8 +7,6 @@ #include <linux/clk-provider.h> #include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index ec3a71ebb766..dd1be946a8f0 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -6,9 +6,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 0893fbbb68cc..2882107d0f24 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -8,8 +8,6 @@ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include "clk-cpumux.h" diff --git a/drivers/clk/mediatek/clk-mt7981-apmixed.c b/drivers/clk/mediatek/clk-mt7981-apmixed.c index 875813d8b4a9..98739877f430 100644 --- a/drivers/clk/mediatek/clk-mt7981-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c @@ -8,9 +8,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-gate.h" diff --git a/drivers/clk/mediatek/clk-mt7981-eth.c b/drivers/clk/mediatek/clk-mt7981-eth.c index 6bc509a54e14..fb1a8c9242ef 100644 --- a/drivers/clk/mediatek/clk-mt7981-eth.c +++ b/drivers/clk/mediatek/clk-mt7981-eth.c @@ -8,9 +8,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt7981-infracfg.c b/drivers/clk/mediatek/clk-mt7981-infracfg.c index 7e9d3d309151..18bf4e8be457 100644 --- a/drivers/clk/mediatek/clk-mt7981-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c @@ -8,9 +8,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" #include "clk-gate.h" diff --git a/drivers/clk/mediatek/clk-mt7981-topckgen.c b/drivers/clk/mediatek/clk-mt7981-topckgen.c index 4740776e7aab..682f4ca9e89a 100644 --- a/drivers/clk/mediatek/clk-mt7981-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c @@ -8,9 +8,7 @@ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" #include "clk-gate.h" diff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediatek/clk-mt7986-apmixed.c index 6767e9c43886..7f807fbdfcb9 100644 --- a/drivers/clk/mediatek/clk-mt7986-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c @@ -6,9 +6,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-gate.h" diff --git a/drivers/clk/mediatek/clk-mt7986-eth.c b/drivers/clk/mediatek/clk-mt7986-eth.c index 854e2c565041..7ab78e0f49a1 100644 --- a/drivers/clk/mediatek/clk-mt7986-eth.c +++ b/drivers/clk/mediatek/clk-mt7986-eth.c @@ -6,9 +6,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt7986-infracfg.c b/drivers/clk/mediatek/clk-mt7986-infracfg.c index c576e9fb986c..cb8ab3e53abf 100644 --- a/drivers/clk/mediatek/clk-mt7986-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c @@ -6,9 +6,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" #include "clk-gate.h" diff --git a/drivers/clk/mediatek/clk-mt7986-topckgen.c b/drivers/clk/mediatek/clk-mt7986-topckgen.c index af151b016872..84bc24511504 100644 --- a/drivers/clk/mediatek/clk-mt7986-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c @@ -6,9 +6,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" #include "clk-gate.h" diff --git a/drivers/clk/mediatek/clk-mt8167-aud.c b/drivers/clk/mediatek/clk-mt8167-aud.c index b73058edf3d6..a5181f4eb34a 100644 --- a/drivers/clk/mediatek/clk-mt8167-aud.c +++ b/drivers/clk/mediatek/clk-mt8167-aud.c @@ -7,9 +7,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt8167-img.c b/drivers/clk/mediatek/clk-mt8167-img.c index ba07d20f14b3..02fa52d8aabb 100644 --- a/drivers/clk/mediatek/clk-mt8167-img.c +++ b/drivers/clk/mediatek/clk-mt8167-img.c @@ -7,9 +7,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c index 5f7dbaf97e96..a5b5ee7ac805 100644 --- a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c @@ -7,9 +7,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt8167-mm.c b/drivers/clk/mediatek/clk-mt8167-mm.c index 6472e76567a5..9b0c6b3343b9 100644 --- a/drivers/clk/mediatek/clk-mt8167-mm.c +++ b/drivers/clk/mediatek/clk-mt8167-mm.c @@ -7,9 +7,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt8167-vdec.c b/drivers/clk/mediatek/clk-mt8167-vdec.c index 2f662b3f16a9..1e1e76743180 100644 --- a/drivers/clk/mediatek/clk-mt8167-vdec.c +++ b/drivers/clk/mediatek/clk-mt8167-vdec.c @@ -7,9 +7,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt8173-mm.c b/drivers/clk/mediatek/clk-mt8173-mm.c index ffed6c5bfde2..fd903bee328f 100644 --- a/drivers/clk/mediatek/clk-mt8173-mm.c +++ b/drivers/clk/mediatek/clk-mt8173-mm.c @@ -5,7 +5,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-gate.h" diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 1ba421b38ec5..3155c65b15dc 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -5,9 +5,7 @@ #include <linux/delay.h> #include <linux/mfd/syscon.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/slab.h> diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c index 3c1ace87796b..41ab4d6896a4 100644 --- a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c @@ -5,7 +5,7 @@ */ #include <dt-bindings/clock/mediatek,mt8188-clk.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-gate.h" diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c b/drivers/clk/mediatek/clk-mt8188-topckgen.c index d2eba2d6af8d..e330a4f9a0c3 100644 --- a/drivers/clk/mediatek/clk-mt8188-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8188-topckgen.c @@ -5,7 +5,7 @@ */ #include <dt-bindings/clock/mediatek,mt8188-clk.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-gate.h" diff --git a/drivers/clk/mediatek/clk-mt8192-cam.c b/drivers/clk/mediatek/clk-mt8192-cam.c index 7b9327eba924..a2c0142273a8 100644 --- a/drivers/clk/mediatek/clk-mt8192-cam.c +++ b/drivers/clk/mediatek/clk-mt8192-cam.c @@ -4,7 +4,7 @@ // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt8192-img.c b/drivers/clk/mediatek/clk-mt8192-img.c index 0208030c31a0..ee52b5b748e7 100644 --- a/drivers/clk/mediatek/clk-mt8192-img.c +++ b/drivers/clk/mediatek/clk-mt8192-img.c @@ -4,7 +4,7 @@ // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c index 275581f8c710..a97b6e8d97ac 100644 --- a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c @@ -4,7 +4,7 @@ // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt8192-ipe.c b/drivers/clk/mediatek/clk-mt8192-ipe.c index f3656c3b9573..56ce58ac01ad 100644 --- a/drivers/clk/mediatek/clk-mt8192-ipe.c +++ b/drivers/clk/mediatek/clk-mt8192-ipe.c @@ -4,7 +4,7 @@ // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt8192-mdp.c b/drivers/clk/mediatek/clk-mt8192-mdp.c index 5385ac95533a..bad2f3d439f5 100644 --- a/drivers/clk/mediatek/clk-mt8192-mdp.c +++ b/drivers/clk/mediatek/clk-mt8192-mdp.c @@ -4,7 +4,7 @@ // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt8192-mfg.c b/drivers/clk/mediatek/clk-mt8192-mfg.c index 0ac7045cf5d1..666b401e778c 100644 --- a/drivers/clk/mediatek/clk-mt8192-mfg.c +++ b/drivers/clk/mediatek/clk-mt8192-mfg.c @@ -4,7 +4,7 @@ // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt8192-msdc.c b/drivers/clk/mediatek/clk-mt8192-msdc.c index 9da647c5b8b3..52d6f0babf12 100644 --- a/drivers/clk/mediatek/clk-mt8192-msdc.c +++ b/drivers/clk/mediatek/clk-mt8192-msdc.c @@ -4,7 +4,7 @@ // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c index 44091147c813..72c8a8722b11 100644 --- a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c +++ b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c @@ -4,7 +4,7 @@ // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt8192-vdec.c b/drivers/clk/mediatek/clk-mt8192-vdec.c index d82dee8317b2..cc514068bcdb 100644 --- a/drivers/clk/mediatek/clk-mt8192-vdec.c +++ b/drivers/clk/mediatek/clk-mt8192-vdec.c @@ -4,7 +4,7 @@ // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt8192-venc.c b/drivers/clk/mediatek/clk-mt8192-venc.c index b0ef242991e5..9f6fff2dd753 100644 --- a/drivers/clk/mediatek/clk-mt8192-venc.c +++ b/drivers/clk/mediatek/clk-mt8192-venc.c @@ -4,7 +4,7 @@ // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index 462ec4465b50..e395c04632bc 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -6,9 +6,7 @@ #include <linux/clk.h> #include <linux/delay.h> #include <linux/mfd/syscon.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/slab.h> diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c index 502a9dc1fdb8..44a4c85a67ef 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -10,7 +10,7 @@ #include "clk-pllfh.h" #include <dt-bindings/clock/mt8195-clk.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> static const struct mtk_gate_regs apmixed_cg_regs = { diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c index 81daa24cadde..5c426a1c94c7 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -8,7 +8,7 @@ #include "clk-mux.h" #include <dt-bindings/clock/mt8195-clk.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> static DEFINE_SPINLOCK(mt8195_clk_lock); diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index 1dca18f99134..ac45e4cc9bcd 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -10,9 +10,7 @@ #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/mfd/syscon.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/slab.h> diff --git a/drivers/clk/mediatek/clk-mt8516-aud.c b/drivers/clk/mediatek/clk-mt8516-aud.c index d1e848e78fd5..53e1866fb8e2 100644 --- a/drivers/clk/mediatek/clk-mt8516-aud.c +++ b/drivers/clk/mediatek/clk-mt8516-aud.c @@ -7,9 +7,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-mtk.h" diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peripherals.c index dde2912671b8..e2a1f12f9175 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -8,7 +8,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "a1-peripherals.h" #include "clk-dualdiv.h" diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c index 7de7d78c3813..4325e8a6a3ef 100644 --- a/drivers/clk/meson/a1-pll.c +++ b/drivers/clk/meson/a1-pll.c @@ -8,7 +8,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "a1-pll.h" #include "clk-regmap.h" diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c index 6aca231b1d81..ac3482960903 100644 --- a/drivers/clk/meson/axg-audio.c +++ b/drivers/clk/meson/axg-audio.c @@ -7,8 +7,8 @@ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/init.h> -#include <linux/of_device.h> #include <linux/module.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/reset.h> diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index f132439a33a4..c12f81dfa674 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -11,7 +11,7 @@ #include <linux/clk-provider.h> #include <linux/init.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/module.h> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index ceabd5f4b2ac..f373a8d48b1d 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -12,7 +12,7 @@ #include <linux/clk-provider.h> #include <linux/init.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/module.h> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 1ee0774a9827..1b1279d94781 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -6,7 +6,7 @@ #include <linux/clk-provider.h> #include <linux/init.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/module.h> diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c index e7a72bdd0db0..bf466fef263c 100644 --- a/drivers/clk/meson/meson-aoclk.c +++ b/drivers/clk/meson/meson-aoclk.c @@ -13,7 +13,7 @@ #include <linux/platform_device.h> #include <linux/reset-controller.h> #include <linux/mfd/syscon.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/module.h> #include <linux/slab.h> diff --git a/drivers/clk/meson/meson-eeclk.c b/drivers/clk/meson/meson-eeclk.c index 3ce9f702e63d..845ca8bfa346 100644 --- a/drivers/clk/meson/meson-eeclk.c +++ b/drivers/clk/meson/meson-eeclk.c @@ -5,7 +5,7 @@ */ #include <linux/clk-provider.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> diff --git a/drivers/clk/microchip/clk-pic32mzda.c b/drivers/clk/microchip/clk-pic32mzda.c index eabfc4931fe9..27599829ea40 100644 --- a/drivers/clk/microchip/clk-pic32mzda.c +++ b/drivers/clk/microchip/clk-pic32mzda.c @@ -9,8 +9,8 @@ #include <linux/clkdev.h> #include <linux/io.h> #include <linux/module.h> +#include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_platform.h> #include <linux/platform_device.h> #include <asm/traps.h> diff --git a/drivers/clk/mvebu/ap-cpu-clk.c b/drivers/clk/mvebu/ap-cpu-clk.c index d8a7a4c90d54..677cc3514849 100644 --- a/drivers/clk/mvebu/ap-cpu-clk.c +++ b/drivers/clk/mvebu/ap-cpu-clk.c @@ -15,7 +15,6 @@ #include <linux/mfd/syscon.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include "armada_ap_cp_helper.h" diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c index 3ae6078f6ff7..8701a58a5804 100644 --- a/drivers/clk/mvebu/armada-37xx-periph.c +++ b/drivers/clk/mvebu/armada-37xx-periph.c @@ -21,7 +21,6 @@ #include <linux/io.h> #include <linux/mfd/syscon.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/slab.h> @@ -733,7 +732,6 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev) const struct clk_periph_data *data; struct device *dev = &pdev->dev; int num_periph = 0, i, ret; - struct resource *res; data = of_device_get_match_data(dev); if (!data) @@ -754,8 +752,7 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev) return -ENOMEM; driver_data->hw_data->num = num_periph; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - driver_data->reg = devm_ioremap_resource(dev, res); + driver_data->reg = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(driver_data->reg)) return PTR_ERR(driver_data->reg); diff --git a/drivers/clk/mvebu/armada-37xx-tbg.c b/drivers/clk/mvebu/armada-37xx-tbg.c index eccc1aeefbaf..e94c336e0f1c 100644 --- a/drivers/clk/mvebu/armada-37xx-tbg.c +++ b/drivers/clk/mvebu/armada-37xx-tbg.c @@ -84,7 +84,6 @@ static int armada_3700_tbg_clock_probe(struct platform_device *pdev) struct clk_hw_onecell_data *hw_tbg_data; struct device *dev = &pdev->dev; const char *parent_name; - struct resource *res; struct clk *parent; void __iomem *reg; int i; @@ -105,8 +104,7 @@ static int armada_3700_tbg_clock_probe(struct platform_device *pdev) parent_name = __clk_get_name(parent); clk_put(parent); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - reg = devm_ioremap_resource(dev, res); + reg = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(reg)) return PTR_ERR(reg); diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c index f1fe7edd21b5..9f65d0623517 100644 --- a/drivers/clk/nuvoton/clk-ma35d1.c +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -460,7 +460,6 @@ static int ma35d1_clocks_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *clk_node = pdev->dev.of_node; - struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); void __iomem *clk_base; static struct clk_hw **hws; static struct clk_hw_onecell_data *ma35d1_hw_data; @@ -476,7 +475,7 @@ static int ma35d1_clocks_probe(struct platform_device *pdev) ma35d1_hw_data->num = CLK_MAX_IDX; hws = ma35d1_hw_data->hws; - clk_base = devm_ioremap_resource(dev, res); + clk_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(clk_base)) return PTR_ERR(clk_base); diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c index ce28d882ee78..e170331858cc 100644 --- a/drivers/clk/qcom/apss-ipq-pll.c +++ b/drivers/clk/qcom/apss-ipq-pll.c @@ -2,7 +2,7 @@ // Copyright (c) 2018, The Linux Foundation. All rights reserved. #include <linux/clk-provider.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/regmap.h> diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c index 8a4ba7a19ed1..cbffc44c4d32 100644 --- a/drivers/clk/qcom/camcc-sc7180.c +++ b/drivers/clk/qcom/camcc-sc7180.c @@ -7,7 +7,7 @@ #include <linux/err.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/pm_clock.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> diff --git a/drivers/clk/qcom/camcc-sc7280.c b/drivers/clk/qcom/camcc-sc7280.c index 4396fddba7a6..49f046ea857c 100644 --- a/drivers/clk/qcom/camcc-sc7280.c +++ b/drivers/clk/qcom/camcc-sc7280.c @@ -7,8 +7,8 @@ #include <linux/err.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_device.h> #include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,camcc-sc7280.h> diff --git a/drivers/clk/qcom/clk-rpm.c b/drivers/clk/qcom/clk-rpm.c index cac623e27b0e..745026ef4d9c 100644 --- a/drivers/clk/qcom/clk-rpm.c +++ b/drivers/clk/qcom/clk-rpm.c @@ -13,7 +13,6 @@ #include <linux/mutex.h> #include <linux/mfd/qcom_rpm.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <dt-bindings/mfd/qcom-rpm.h> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 86572570bc54..4c5b552b47b6 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -8,7 +8,6 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <soc/qcom/cmd-db.h> #include <soc/qcom/rpmh.h> diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index e4de74b68797..4bcf2e949877 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -12,7 +12,6 @@ #include <linux/module.h> #include <linux/mutex.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/soc/qcom/smd-rpm.h> diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c index 44dd5cfcc150..9206f0eed446 100644 --- a/drivers/clk/qcom/dispcc-qcm2290.c +++ b/drivers/clk/qcom/dispcc-qcm2290.c @@ -7,8 +7,8 @@ #include <linux/err.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_device.h> #include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,dispcc-qcm2290.h> diff --git a/drivers/clk/qcom/dispcc-sm6115.c b/drivers/clk/qcom/dispcc-sm6115.c index 1937edf23f21..1fab43f08e73 100644 --- a/drivers/clk/qcom/dispcc-sm6115.c +++ b/drivers/clk/qcom/dispcc-sm6115.c @@ -8,8 +8,8 @@ #include <linux/err.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_device.h> #include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,sm6115-dispcc.h> diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c index adbfd30bfc96..3643af36d755 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -9,8 +9,8 @@ #include <linux/err.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_device.h> #include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/pm_runtime.h> diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index 1e5a11081860..2a74be35452f 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -9,8 +9,8 @@ #include <linux/err.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_device.h> #include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/pm_runtime.h> diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c index 7085d2ccae49..c7ca93ef0d53 100644 --- a/drivers/clk/qcom/gcc-apq8084.c +++ b/drivers/clk/qcom/gcc-apq8084.c @@ -9,7 +9,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c index 5657e29464ad..9c75682a3915 100644 --- a/drivers/clk/qcom/gcc-ipq4019.c +++ b/drivers/clk/qcom/gcc-ipq4019.c @@ -8,7 +8,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index a75ab88ed14c..ce6dc6e99a29 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -4,8 +4,9 @@ */ #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,ipq5332-gcc.h> diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c index 86b43175b042..6120fbbc5de0 100644 --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c @@ -8,7 +8,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 6447f3e81b55..974d01fd4381 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -9,7 +9,7 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> +#include <linux/of_platform.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 6541d98c0348..63ac2ced76bb 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -8,7 +8,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> diff --git a/drivers/clk/qcom/gcc-mdm9607.c b/drivers/clk/qcom/gcc-mdm9607.c index 4c9078e99bb3..fb290e73ce94 100644 --- a/drivers/clk/qcom/gcc-mdm9607.c +++ b/drivers/clk/qcom/gcc-mdm9607.c @@ -9,7 +9,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c index 8bed02a748ab..8513cb5af7c6 100644 --- a/drivers/clk/qcom/gcc-mdm9615.c +++ b/drivers/clk/qcom/gcc-mdm9615.c @@ -11,7 +11,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c index a9eb6a9ac445..67870c899ab9 100644 --- a/drivers/clk/qcom/gcc-msm8660.c +++ b/drivers/clk/qcom/gcc-msm8660.c @@ -9,7 +9,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-msm8909.c b/drivers/clk/qcom/gcc-msm8909.c index 2a00b11ce2cd..cc36e81bca7d 100644 --- a/drivers/clk/qcom/gcc-msm8909.c +++ b/drivers/clk/qcom/gcc-msm8909.c @@ -14,7 +14,6 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c index 0c8fe19387a7..9c7c6b23ce32 100644 --- a/drivers/clk/qcom/gcc-msm8916.c +++ b/drivers/clk/qcom/gcc-msm8916.c @@ -9,7 +9,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-msm8917.c b/drivers/clk/qcom/gcc-msm8917.c index a4c33a2ce61c..5ec14480e068 100644 --- a/drivers/clk/qcom/gcc-msm8917.c +++ b/drivers/clk/qcom/gcc-msm8917.c @@ -18,7 +18,6 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c index 7f8969a77974..b45f97c07eeb 100644 --- a/drivers/clk/qcom/gcc-msm8939.c +++ b/drivers/clk/qcom/gcc-msm8939.c @@ -9,7 +9,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-msm8953.c b/drivers/clk/qcom/gcc-msm8953.c index 8aafa6591e84..3e5a8cb14d4d 100644 --- a/drivers/clk/qcom/gcc-msm8953.c +++ b/drivers/clk/qcom/gcc-msm8953.c @@ -7,7 +7,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-msm8976.c b/drivers/clk/qcom/gcc-msm8976.c index 8beb923c0e19..f60a8171972b 100644 --- a/drivers/clk/qcom/gcc-msm8976.c +++ b/drivers/clk/qcom/gcc-msm8976.c @@ -15,8 +15,8 @@ #include <linux/err.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_device.h> #include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,gcc-msm8976.h> diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index 0f52c48e89d8..80170a805c3b 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -9,7 +9,6 @@ #include <linux/ctype.h> #include <linux/io.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/module.h> #include <linux/regmap.h> diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index 5e44d1bcca9e..14dcc3f03668 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -9,7 +9,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index be024f8093c5..1ba516a0c0f3 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -9,7 +9,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 5051769ad90c..328b306297ef 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -5,7 +5,8 @@ #include <linux/clk-provider.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,qdu1000-gcc.h> diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c index bb94ff367abd..8171d23c96e6 100644 --- a/drivers/clk/qcom/gcc-sa8775p.c +++ b/drivers/clk/qcom/gcc-sa8775p.c @@ -9,8 +9,8 @@ #include <linux/err.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_device.h> #include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,sa8775p-gcc.h> diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c index cef3c77564cf..ede83c644716 100644 --- a/drivers/clk/qcom/gcc-sc7180.c +++ b/drivers/clk/qcom/gcc-sc7180.c @@ -8,7 +8,7 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,gcc-sc7180.h> diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index 1dc804154031..2b661df5de26 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -6,8 +6,8 @@ #include <linux/clk-provider.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_device.h> #include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,gcc-sc7280.h> diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c index c41b9f010585..ae2147381559 100644 --- a/drivers/clk/qcom/gcc-sc8180x.c +++ b/drivers/clk/qcom/gcc-sc8180x.c @@ -10,7 +10,6 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index b90c71637814..1ab119b3702a 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -8,9 +8,9 @@ #include <linux/err.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_device.h> #include <linux/pm_runtime.h> #include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c index 6afce8e42ede..c4fe70871b6d 100644 --- a/drivers/clk/qcom/gcc-sdm660.c +++ b/drivers/clk/qcom/gcc-sdm660.c @@ -10,7 +10,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index 6af08e0ca847..725cd52d2398 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -9,7 +9,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-sdx65.c b/drivers/clk/qcom/gcc-sdx65.c index b0c17043551d..ffddbed5a6db 100644 --- a/drivers/clk/qcom/gcc-sdx65.c +++ b/drivers/clk/qcom/gcc-sdx65.c @@ -7,8 +7,8 @@ #include <linux/err.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_device.h> #include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,gcc-sdx65.h> diff --git a/drivers/clk/qcom/gcc-sdx75.c b/drivers/clk/qcom/gcc-sdx75.c index b6772abdcec5..573af17bd24c 100644 --- a/drivers/clk/qcom/gcc-sdx75.c +++ b/drivers/clk/qcom/gcc-sdx75.c @@ -4,8 +4,9 @@ */ #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,sdx75-gcc.h> diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c index 033e308ff865..13e521cd4259 100644 --- a/drivers/clk/qcom/gcc-sm6115.c +++ b/drivers/clk/qcom/gcc-sm6115.c @@ -6,7 +6,8 @@ #include <linux/err.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-sm6125.c b/drivers/clk/qcom/gcc-sm6125.c index 40ad062d1bf7..da554efee2ce 100644 --- a/drivers/clk/qcom/gcc-sm6125.c +++ b/drivers/clk/qcom/gcc-sm6125.c @@ -8,7 +8,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c index 417a0fd242ec..3dd15d765b22 100644 --- a/drivers/clk/qcom/gcc-sm6375.c +++ b/drivers/clk/qcom/gcc-sm6375.c @@ -6,7 +6,8 @@ #include <linux/clk-provider.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,sm6375-gcc.h> diff --git a/drivers/clk/qcom/gcc-sm7150.c b/drivers/clk/qcom/gcc-sm7150.c index 6b628178f62c..973142a1b404 100644 --- a/drivers/clk/qcom/gcc-sm7150.c +++ b/drivers/clk/qcom/gcc-sm7150.c @@ -8,9 +8,9 @@ #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/kernel.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,sm7150-gcc.h> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c index 70b067f3618c..41ab210875fb 100644 --- a/drivers/clk/qcom/gcc-sm8150.c +++ b/drivers/clk/qcom/gcc-sm8150.c @@ -7,7 +7,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c index b6cf4bc88d4d..ee0ce6582e85 100644 --- a/drivers/clk/qcom/gcc-sm8250.c +++ b/drivers/clk/qcom/gcc-sm8250.c @@ -7,8 +7,8 @@ #include <linux/err.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_device.h> #include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,gcc-sm8250.h> diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index 75635d40a12d..86ad085260db 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -6,7 +6,8 @@ #include <linux/clk-provider.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,gcc-sm8450.h> diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index 277cd4f020ff..586126c4dd90 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -7,7 +7,8 @@ #include <linux/clk-provider.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,sm8550-gcc.h> diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c index f929e0f2333f..0b6e1d6d884e 100644 --- a/drivers/clk/qcom/gpucc-msm8998.c +++ b/drivers/clk/qcom/gpucc-msm8998.c @@ -9,7 +9,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c index 18d23be8d435..26ecfa63be19 100644 --- a/drivers/clk/qcom/gpucc-sa8775p.c +++ b/drivers/clk/qcom/gpucc-sa8775p.c @@ -7,9 +7,9 @@ #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/kernel.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> -#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,sa8775p-gpucc.h> diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c index d6b38a0b063d..459f123a6720 100644 --- a/drivers/clk/qcom/gpucc-sdm660.c +++ b/drivers/clk/qcom/gpucc-sdm660.c @@ -13,7 +13,6 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/regmap.h> #include <linux/reset-controller.h> #include <dt-bindings/clock/qcom,gpucc-sdm660.h> diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c index c84727e8352d..fb71c21c9a89 100644 --- a/drivers/clk/qcom/gpucc-sm6115.c +++ b/drivers/clk/qcom/gpucc-sm6115.c @@ -5,8 +5,9 @@ */ #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,sm6115-gpucc.h> diff --git a/drivers/clk/qcom/gpucc-sm6125.c b/drivers/clk/qcom/gpucc-sm6125.c index d4f1296a48ef..61959ba02f9a 100644 --- a/drivers/clk/qcom/gpucc-sm6125.c +++ b/drivers/clk/qcom/gpucc-sm6125.c @@ -5,8 +5,9 @@ */ #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,sm6125-gpucc.h> diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c index 2d863dc3d83b..da24276a018e 100644 --- a/drivers/clk/qcom/gpucc-sm6375.c +++ b/drivers/clk/qcom/gpucc-sm6375.c @@ -5,8 +5,9 @@ */ #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c index 5367ce654ac9..8dc54dff983f 100644 --- a/drivers/clk/qcom/gpucc-sm8350.c +++ b/drivers/clk/qcom/gpucc-sm8350.c @@ -8,8 +8,8 @@ #include <linux/err.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_device.h> #include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,gpucc-sm8350.h> diff --git a/drivers/clk/qcom/gpucc-sm8450.c b/drivers/clk/qcom/gpucc-sm8450.c index 16c0381b3087..1c4769b646b0 100644 --- a/drivers/clk/qcom/gpucc-sm8450.c +++ b/drivers/clk/qcom/gpucc-sm8450.c @@ -4,8 +4,9 @@ */ #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,sm8450-gpucc.h> diff --git a/drivers/clk/qcom/gpucc-sm8550.c b/drivers/clk/qcom/gpucc-sm8550.c index 8a2e3522af51..775e0b931923 100644 --- a/drivers/clk/qcom/gpucc-sm8550.c +++ b/drivers/clk/qcom/gpucc-sm8550.c @@ -4,8 +4,9 @@ */ #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,sm8550-gpucc.h> diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c index 81a44a9a9abc..fa8cda63cf20 100644 --- a/drivers/clk/qcom/lcc-ipq806x.c +++ b/drivers/clk/qcom/lcc-ipq806x.c @@ -9,7 +9,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> diff --git a/drivers/clk/qcom/lcc-mdm9615.c b/drivers/clk/qcom/lcc-mdm9615.c index 8d243e880d95..396f7a804cfe 100644 --- a/drivers/clk/qcom/lcc-mdm9615.c +++ b/drivers/clk/qcom/lcc-mdm9615.c @@ -11,7 +11,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c index 3926184cc91b..35a30c793f92 100644 --- a/drivers/clk/qcom/lcc-msm8960.c +++ b/drivers/clk/qcom/lcc-msm8960.c @@ -9,7 +9,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> diff --git a/drivers/clk/qcom/lpass-gfm-sm8250.c b/drivers/clk/qcom/lpass-gfm-sm8250.c index 96f476f24eb2..8a1ee52cbcc3 100644 --- a/drivers/clk/qcom/lpass-gfm-sm8250.c +++ b/drivers/clk/qcom/lpass-gfm-sm8250.c @@ -15,8 +15,8 @@ #include <linux/pm_clock.h> #include <linux/pm_runtime.h> #include <linux/device.h> +#include <linux/of.h> #include <linux/platform_device.h> -#include <linux/of_device.h> #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h> #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c index 134eb1529ede..c43d0b1af7f7 100644 --- a/drivers/clk/qcom/lpassaudiocc-sc7280.c +++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c @@ -7,7 +7,8 @@ #include <linux/err.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/pm_clock.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> diff --git a/drivers/clk/qcom/lpasscc-sc8280xp.c b/drivers/clk/qcom/lpasscc-sc8280xp.c index 43b37ce397cf..3693e47d548e 100644 --- a/drivers/clk/qcom/lpasscc-sc8280xp.c +++ b/drivers/clk/qcom/lpasscc-sc8280xp.c @@ -6,8 +6,10 @@ #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/kernel.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c b/drivers/clk/qcom/lpasscorecc-sc7180.c index 010867dcc2ef..9051fd567112 100644 --- a/drivers/clk/qcom/lpasscorecc-sc7180.c +++ b/drivers/clk/qcom/lpasscorecc-sc7180.c @@ -6,7 +6,7 @@ #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/pm_clock.h> #include <linux/pm_runtime.h> #include <linux/of.h> diff --git a/drivers/clk/qcom/lpasscorecc-sc7280.c b/drivers/clk/qcom/lpasscorecc-sc7280.c index 6ad19b06b1ce..a2f1e6ad6da4 100644 --- a/drivers/clk/qcom/lpasscorecc-sc7280.c +++ b/drivers/clk/qcom/lpasscorecc-sc7280.c @@ -6,7 +6,8 @@ #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/pm_clock.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c index 82f6bad144a9..a7acdef5a14e 100644 --- a/drivers/clk/qcom/mmcc-msm8974.c +++ b/drivers/clk/qcom/mmcc-msm8974.c @@ -9,7 +9,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/mmcc-msm8994.c b/drivers/clk/qcom/mmcc-msm8994.c index 89c5f5fa7d9a..3229ff77372f 100644 --- a/drivers/clk/qcom/mmcc-msm8994.c +++ b/drivers/clk/qcom/mmcc-msm8994.c @@ -9,7 +9,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c index 80330dab4d81..d3f2dc798567 100644 --- a/drivers/clk/qcom/mmcc-msm8996.c +++ b/drivers/clk/qcom/mmcc-msm8996.c @@ -9,7 +9,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c index 4490594bde69..c62aa270af1c 100644 --- a/drivers/clk/qcom/mmcc-msm8998.c +++ b/drivers/clk/qcom/mmcc-msm8998.c @@ -9,7 +9,6 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> diff --git a/drivers/clk/qcom/tcsrcc-sm8550.c b/drivers/clk/qcom/tcsrcc-sm8550.c index 2c67ee71c196..552a3eb1fd91 100644 --- a/drivers/clk/qcom/tcsrcc-sm8550.c +++ b/drivers/clk/qcom/tcsrcc-sm8550.c @@ -7,7 +7,8 @@ #include <linux/clk-provider.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,sm8550-tcsr.h> diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c index 7d0029b8b799..16a61146e619 100644 --- a/drivers/clk/qcom/videocc-sm8450.c +++ b/drivers/clk/qcom/videocc-sm8450.c @@ -4,8 +4,9 @@ */ #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index e2400fe23e60..3bb136ec31b1 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -4,8 +4,9 @@ */ #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> diff --git a/drivers/clk/renesas/clk-emev2.c b/drivers/clk/renesas/clk-emev2.c index 7807b30a5bbb..37c6f9be5e5b 100644 --- a/drivers/clk/renesas/clk-emev2.c +++ b/drivers/clk/renesas/clk-emev2.c @@ -6,7 +6,6 @@ * Copyright (C) 2012 Magnus Damm */ #include <linux/clk-provider.h> -#include <linux/clkdev.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> @@ -74,7 +73,6 @@ static void __init emev2_smu_clkdiv_init(struct device_node *np) clk = clk_register_divider(NULL, np->name, parent_name, 0, smu_base + reg[0], reg[1], 8, 0, &lock); of_clk_add_provider(np, of_clk_src_simple_get, clk); - clk_register_clkdev(clk, np->full_name, NULL); pr_debug("## %s %pOFn %p\n", __func__, np, clk); } CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv", @@ -92,7 +90,6 @@ static void __init emev2_smu_gclk_init(struct device_node *np) clk = clk_register_gate(NULL, np->name, parent_name, 0, smu_base + reg[0], reg[1], 0, &lock); of_clk_add_provider(np, of_clk_src_simple_get, clk); - clk_register_clkdev(clk, np->full_name, NULL); pr_debug("## %s %pOFn %p\n", __func__, np, clk); } CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init); diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index ad03c09ebc1f..aba043f999eb 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), + DEF_GEN3_Z("zg", R8A774A1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24), DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), @@ -123,6 +124,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { + DEF_MOD("3dge", 112, R8A774A1_CLK_ZG), DEF_MOD("tmu4", 121, R8A774A1_CLK_S0D6), DEF_MOD("tmu3", 122, R8A774A1_CLK_S3D2), DEF_MOD("tmu2", 123, R8A774A1_CLK_S3D2), @@ -213,6 +215,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { DEF_MOD("rpc-if", 917, R8A774A1_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6), DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6), + DEF_MOD("adg", 922, R8A774A1_CLK_S0D4), DEF_MOD("iic-pmic", 926, R8A774A1_CLK_CP), DEF_MOD("i2c4", 927, R8A774A1_CLK_S0D6), DEF_MOD("i2c3", 928, R8A774A1_CLK_S0D6), diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c index ab087b02ef90..a3244e76f779 100644 --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c @@ -73,6 +73,7 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_GEN3_Z("z", R8A774B1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), + DEF_GEN3_Z("zg", R8A774B1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24), DEF_FIXED("ztr", R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774B1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), @@ -120,6 +121,7 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = { + DEF_MOD("3dge", 112, R8A774B1_CLK_ZG), DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6), DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2), DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2), @@ -209,6 +211,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = { DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6), DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6), + DEF_MOD("adg", 922, R8A774B1_CLK_S0D4), DEF_MOD("iic-pmic", 926, R8A774B1_CLK_CP), DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6), DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6), diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c index c9c8fde0f0a6..870f8c55eb28 100644 --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c @@ -211,6 +211,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = { DEF_MOD("rpc-if", 917, R8A774C0_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2), DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2), + DEF_MOD("adg", 922, R8A774C0_CLK_ZA2), DEF_MOD("iic-pmic", 926, R8A774C0_CLK_CP), DEF_MOD("i2c4", 927, R8A774C0_CLK_S3D2), DEF_MOD("i2c3", 928, R8A774C0_CLK_S3D2), diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c b/drivers/clk/renesas/r8a774e1-cpg-mssr.c index a790061db877..7158464c80d8 100644 --- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c @@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_GEN3_Z("z", R8A774E1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), + DEF_GEN3_Z("zg", R8A774E1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24), DEF_FIXED("ztr", R8A774E1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774E1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774E1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), @@ -124,6 +125,7 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = { + DEF_MOD("3dge", 112, R8A774E1_CLK_ZG), DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1), DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1), DEF_MOD("tmu4", 121, R8A774E1_CLK_S0D6), @@ -221,7 +223,7 @@ static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = { DEF_MOD("rpc-if", 917, R8A774E1_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774E1_CLK_S0D6), DEF_MOD("i2c5", 919, R8A774E1_CLK_S0D6), - DEF_MOD("adg", 922, R8A774E1_CLK_S0D1), + DEF_MOD("adg", 922, R8A774E1_CLK_S0D4), DEF_MOD("iic-pmic", 926, R8A774E1_CLK_CP), DEF_MOD("i2c4", 927, R8A774E1_CLK_S0D6), DEF_MOD("i2c3", 928, R8A774E1_CLK_S0D6), diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 7a585a777d38..ad20b3301ef6 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -79,6 +79,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { /* Core Clock Outputs */ DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), + DEF_GEN3_Z("zg", R8A7795_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24), DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), @@ -128,6 +129,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { }; static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { + DEF_MOD("3dge", 112, R8A7795_CLK_ZG), DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1), DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1), DEF_MOD("tmu4", 121, R8A7795_CLK_S0D6), @@ -251,6 +253,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { DEF_MOD("rpc-if", 917, R8A7795_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6), DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6), + DEF_MOD("adg", 922, R8A7795_CLK_S0D4), DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP), DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6), DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6), diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index c4969318508e..e5f9e3e74229 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -81,6 +81,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), + DEF_GEN3_Z("zg", R8A7796_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24), DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), @@ -130,6 +131,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { }; static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = { + DEF_MOD("3dge", 112, R8A7796_CLK_ZG), DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1), DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6), DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2), @@ -236,6 +238,7 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = { DEF_MOD("rpc-if", 917, R8A7796_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6), DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6), + DEF_MOD("adg", 922, R8A7796_CLK_S0D4), DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP), DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6), DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6), diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index 78f6e530848e..219e41abb5df 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), + DEF_GEN3_Z("zg", R8A77965_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24), DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1), @@ -125,6 +126,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { + DEF_MOD("3dge", 112, R8A77965_CLK_ZG), DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1), DEF_MOD("tmu4", 121, R8A77965_CLK_S0D6), DEF_MOD("tmu3", 122, R8A77965_CLK_S3D2), @@ -236,6 +238,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { DEF_MOD("rpc-if", 917, R8A77965_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6), DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6), + DEF_MOD("adg", 922, R8A77965_CLK_S0D4), DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP), DEF_MOD("i2c4", 927, R8A77965_CLK_S0D6), DEF_MOD("i2c3", 928, R8A77965_CLK_S0D6), diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index b666d099365e..b2f82c594925 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -224,6 +224,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = { DEF_MOD("rpc-if", 917, R8A77990_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2), DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2), + DEF_MOD("adg", 922, R8A77990_CLK_ZA2), DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP), DEF_MOD("i2c4", 927, R8A77990_CLK_S3D2), DEF_MOD("i2c3", 928, R8A77990_CLK_S3D2), diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index 3a73f6f911dd..162fa86c81ff 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -181,6 +181,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4), DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4), DEF_MOD("rpc-if", 917, R8A77995_CLK_RPCD2), + DEF_MOD("adg", 922, R8A77995_CLK_ZA2), DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2), DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2), DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2), diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 99f72bf590fa..1a7a6d60aca4 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -154,6 +154,8 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x534, 1), DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, 0x534, 2), + DEF_MOD("mtu_x_mck", R9A07G043_MTU_X_MCK_MTU3, R9A07G043_CLK_P0, + 0x538, 0), DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0, 0x548, 0), DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK, @@ -264,6 +266,7 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1), DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), + DEF_RST(R9A07G043_MTU_X_PRESET_MTU3, 0x838, 0), DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0), DEF_RST(R9A07G043_SPI_RST, 0x850, 0), DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index 3d06baf5061d..dda9f29dff33 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -28,6 +28,8 @@ #define DIV_W DDIV_PACK(0x328, 0, 3) #define SEL_B SEL_PLL_PACK(0x214, 0, 1) +#define SEL_CSI0 SEL_PLL_PACK(0x330, 0, 1) +#define SEL_CSI4 SEL_PLL_PACK(0x330, 4, 1) #define SEL_D SEL_PLL_PACK(0x214, 1, 1) #define SEL_E SEL_PLL_PACK(0x214, 2, 1) #define SEL_SDI SEL_PLL_PACK(0x300, 0, 1) @@ -58,6 +60,8 @@ enum clk_ids { CLK_DIV_W, CLK_SEL_B, CLK_SEL_B_D2, + CLK_SEL_CSI0, + CLK_SEL_CSI4, CLK_SEL_D, CLK_SEL_E, CLK_SEL_SDI, @@ -108,6 +112,7 @@ static const struct clk_div_table dtable_divw[] = { /* Mux clock tables */ static const char * const sel_b[] = { ".main", ".divb" }; +static const char * const sel_csi[] = { ".main_24", ".main" }; static const char * const sel_d[] = { ".main", ".divd" }; static const char * const sel_e[] = { ".main", ".dive" }; static const char * const sel_w[] = { ".main", ".divw" }; @@ -139,6 +144,8 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { DEF_MUX_RO(".seld", CLK_SEL_D, SEL_D, sel_d), DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e), DEF_MUX(".selsdi", CLK_SEL_SDI, SEL_SDI, sel_sdi), + DEF_MUX(".selcsi0", CLK_SEL_CSI0, SEL_CSI0, sel_csi), + DEF_MUX(".selcsi4", CLK_SEL_CSI4, SEL_CSI4, sel_csi), DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w), DEF_FIXED(".selb_d2", CLK_SEL_B_D2, CLK_SEL_B, 1, 2), @@ -196,8 +203,12 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8), DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9), DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10), + DEF_MOD("cperi_grpg", R9A09G011_CPERI_GRPG_PCLK, CLK_SEL_E, 0x438, 0), + DEF_MOD("cperi_grph", R9A09G011_CPERI_GRPH_PCLK, CLK_SEL_E, 0x438, 1), DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4), DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5), + DEF_MOD("csi0_clk", R9A09G011_CSI0_CLK, CLK_SEL_CSI0, 0x438, 8), + DEF_MOD("csi4_clk", R9A09G011_CSI4_CLK, CLK_SEL_CSI4, 0x438, 12), DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0), }; @@ -215,6 +226,8 @@ static const struct rzg2l_reset r9a09g011_resets[] = { DEF_RST(R9A09G011_TIM_GPB_PRESETN, 0x614, 1), DEF_RST(R9A09G011_TIM_GPC_PRESETN, 0x614, 2), DEF_RST_MON(R9A09G011_PWM_GPF_PRESETN, 0x614, 5, 23), + DEF_RST_MON(R9A09G011_CSI_GPG_PRESETN, 0x614, 6, 22), + DEF_RST_MON(R9A09G011_CSI_GPH_PRESETN, 0x614, 7, 23), DEF_RST(R9A09G011_IIC_GPA_PRESETN, 0x614, 8), DEF_RST(R9A09G011_IIC_GPB_PRESETN, 0x614, 9), DEF_RST_MON(R9A09G011_WDT0_PRESETN, 0x614, 12, 19), @@ -225,6 +238,8 @@ static const unsigned int r9a09g011_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A09G011_CPERI_GRPB_PCLK, MOD_CLK_BASE + R9A09G011_CPERI_GRPC_PCLK, MOD_CLK_BASE + R9A09G011_CPERI_GRPF_PCLK, + MOD_CLK_BASE + R9A09G011_CPERI_GRPG_PCLK, + MOD_CLK_BASE + R9A09G011_CPERI_GRPH_PCLK, MOD_CLK_BASE + R9A09G011_GIC_CLK, MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK, MOD_CLK_BASE + R9A09G011_URT_PCLK, diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index b3ef62fa612e..d0129a650941 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -264,11 +264,13 @@ static const struct clk_ops cpg_z_clk_ops = { .set_rate = cpg_z_clk_set_rate, }; -static struct clk * __init cpg_z_clk_register(const char *name, +static struct clk * __init __cpg_z_clk_register(const char *name, const char *parent_name, void __iomem *reg, unsigned int div, - unsigned int offset) + unsigned int offset, + unsigned int fcr, + unsigned int flags) { struct clk_init_data init = {}; struct cpg_z_clk *zclk; @@ -280,11 +282,11 @@ static struct clk * __init cpg_z_clk_register(const char *name, init.name = name; init.ops = &cpg_z_clk_ops; - init.flags = CLK_SET_RATE_PARENT; + init.flags = flags; init.parent_names = &parent_name; init.num_parents = 1; - zclk->reg = reg + CPG_FRQCRC; + zclk->reg = reg + fcr; zclk->kick_reg = reg + CPG_FRQCRB; zclk->hw.init = &init; zclk->mask = GENMASK(offset + 4, offset); @@ -301,6 +303,27 @@ static struct clk * __init cpg_z_clk_register(const char *name, return clk; } +static struct clk * __init cpg_z_clk_register(const char *name, + const char *parent_name, + void __iomem *reg, + unsigned int div, + unsigned int offset) +{ + return __cpg_z_clk_register(name, parent_name, reg, div, offset, + CPG_FRQCRC, CLK_SET_RATE_PARENT); +} + +static struct clk * __init cpg_zg_clk_register(const char *name, + const char *parent_name, + void __iomem *reg, + unsigned int div, + unsigned int offset) +{ + return __cpg_z_clk_register(name, parent_name, reg, div, offset, + CPG_FRQCRB, 0); + +} + static const struct clk_div_table cpg_rpcsrc_div_table[] = { { 2, 5 }, { 3, 6 }, { 0, 0 }, }; @@ -438,6 +461,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, return cpg_z_clk_register(core->name, __clk_get_name(parent), base, core->div, core->offset); + case CLK_TYPE_GEN3_ZG: + return cpg_zg_clk_register(core->name, __clk_get_name(parent), + base, core->div, core->offset); + case CLK_TYPE_GEN3_OSC: /* * Clock combining OSC EXTAL predivider and a fixed divider diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 9028bf4295ce..bfdc649bdf12 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -22,6 +22,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_R, CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ CLK_TYPE_GEN3_Z, + CLK_TYPE_GEN3_ZG, CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ CLK_TYPE_GEN3_RPCSRC, diff --git a/drivers/clk/renesas/rcar-usb2-clock-sel.c b/drivers/clk/renesas/rcar-usb2-clock-sel.c index 17c110978e33..de4896cf5f40 100644 --- a/drivers/clk/renesas/rcar-usb2-clock-sel.c +++ b/drivers/clk/renesas/rcar-usb2-clock-sel.c @@ -15,7 +15,6 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/module.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pm.h> #include <linux/pm_runtime.h> diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 2772499d2016..cb80d1bf6c7c 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -21,7 +21,6 @@ #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pm_clock.h> #include <linux/pm_domain.h> diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index bc623515ad84..47f488387f33 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -20,8 +20,7 @@ #include <linux/iopoll.h> #include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_clock.h> #include <linux/pm_domain.h> @@ -182,12 +181,6 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core, return clk_hw->clk; } -static int rzg2l_cpg_sd_clk_mux_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST); -} - static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) { struct sd_hw_data *hwdata = to_sd_hw_data(hw); @@ -250,7 +243,7 @@ static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw) } static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = { - .determine_rate = rzg2l_cpg_sd_clk_mux_determine_rate, + .determine_rate = __clk_mux_determine_rate_closest, .set_parent = rzg2l_cpg_sd_clk_mux_set_parent, .get_parent = rzg2l_cpg_sd_clk_mux_get_parent, }; diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index f85902e2590c..16dabe2b9c47 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -7,8 +7,8 @@ #include <linux/clk-provider.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/of_address.h> +#include <linux/platform_device.h> #include <linux/syscore_ops.h> #include <dt-bindings/clock/rk3568-cru.h> #include "clk.h" @@ -79,9 +79,10 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0), + RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0), RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), - RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0), + RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0), RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), { /* sentinel */ }, }; diff --git a/drivers/clk/rockchip/clk-rv1126.c b/drivers/clk/rockchip/clk-rv1126.c index c18790f5d05b..fc19c5522490 100644 --- a/drivers/clk/rockchip/clk-rv1126.c +++ b/drivers/clk/rockchip/clk-rv1126.c @@ -8,7 +8,7 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> #include <linux/syscore_ops.h> #include <dt-bindings/clock/rockchip,rv1126-cru.h> #include "clk.h" @@ -175,6 +175,7 @@ PNAME(mux_i2s2_p) = { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xi PNAME(mux_i2s2_out2io_p) = { "mclk_i2s2", "xin12m" }; PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" }; PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" }; +PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" }; PNAME(mux_usb480m_gpll_p) = { "usb480m", "gpll" }; PNAME(clk_gmac_src_m0_p) = { "clk_gmac_div", "clk_gmac_rgmii_m0" }; PNAME(clk_gmac_src_m1_p) = { "clk_gmac_div", "clk_gmac_rgmii_m1" }; @@ -259,6 +260,10 @@ static struct rockchip_clk_branch rv1126_audpwm_fracmux __initdata = MUX(SCLK_AUDPWM_MUX, "mclk_audpwm_mux", mux_audpwm_p, CLK_SET_RATE_PARENT, RV1126_CLKSEL_CON(36), 8, 2, MFLAGS); +static struct rockchip_clk_branch rv1126_dclk_vop_fracmux __initdata = + MUX(DCLK_VOP_MUX, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT, + RV1126_CLKSEL_CON(47), 10, 2, MFLAGS); + static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = { /* * Clock-Architecture Diagram 2 @@ -715,6 +720,49 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = { RV1126_CLKGATE_CON(11), 1, GFLAGS), /* + * Clock-Architecture Diagram 9 + */ + /* PD_VO */ + COMPOSITE(ACLK_PDVO, "aclk_pdvo", mux_gpll_cpll_p, 0, + RV1126_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 5, DFLAGS, + RV1126_CLKGATE_CON(14), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_PDVO, "hclk_pdvo", "aclk_pdvo", 0, + RV1126_CLKSEL_CON(45), 8, 5, DFLAGS, + RV1126_CLKGATE_CON(14), 1, GFLAGS), + COMPOSITE_NOMUX(PCLK_PDVO, "pclk_pdvo", "aclk_pdvo", 0, + RV1126_CLKSEL_CON(46), 8, 5, DFLAGS, + RV1126_CLKGATE_CON(14), 2, GFLAGS), + GATE(ACLK_RGA, "aclk_rga", "aclk_pdvo", 0, + RV1126_CLKGATE_CON(14), 6, GFLAGS), + GATE(HCLK_RGA, "hclk_rga", "hclk_pdvo", 0, + RV1126_CLKGATE_CON(14), 7, GFLAGS), + COMPOSITE(CLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_p, 0, + RV1126_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 5, DFLAGS, + RV1126_CLKGATE_CON(14), 8, GFLAGS), + GATE(ACLK_VOP, "aclk_vop", "aclk_pdvo", 0, + RV1126_CLKGATE_CON(14), 9, GFLAGS), + GATE(HCLK_VOP, "hclk_vop", "hclk_pdvo", 0, + RV1126_CLKGATE_CON(14), 10, GFLAGS), + COMPOSITE(DCLK_VOP_DIV, "dclk_vop_div", mux_gpll_cpll_p, 0, + RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS, + RV1126_CLKGATE_CON(14), 11, GFLAGS), + COMPOSITE_FRACMUX(DCLK_VOP_FRACDIV, "dclk_vop_fracdiv", "dclk_vop_div", + CLK_SET_RATE_PARENT, RV1126_CLKSEL_CON(48), 0, + RV1126_CLKGATE_CON(14), 12, GFLAGS, + &rv1126_dclk_vop_fracmux), + GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0, + RV1126_CLKGATE_CON(14), 13, GFLAGS), + GATE(PCLK_DSIHOST, "pclk_dsihost", "pclk_pdvo", 0, + RV1126_CLKGATE_CON(14), 14, GFLAGS), + GATE(ACLK_IEP, "aclk_iep", "aclk_pdvo", 0, + RV1126_CLKGATE_CON(12), 7, GFLAGS), + GATE(HCLK_IEP, "hclk_iep", "hclk_pdvo", 0, + RV1126_CLKGATE_CON(12), 8, GFLAGS), + COMPOSITE(CLK_IEP_CORE, "clk_iep_core", mux_gpll_cpll_p, 0, + RV1126_CLKSEL_CON(54), 7, 1, MFLAGS, 0, 5, DFLAGS, + RV1126_CLKGATE_CON(12), 9, GFLAGS), + + /* * Clock-Architecture Diagram 12 */ /* PD_PHP */ @@ -906,6 +954,17 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = { RV1126_CLKGATE_CON(9), 3, GFLAGS), /* + * Clock-Architecture Diagram 9 + */ + /* PD_VO */ + GATE(0, "aclk_pdvo_niu", "aclk_pdvo", CLK_IGNORE_UNUSED, + RV1126_CLKGATE_CON(14), 3, GFLAGS), + GATE(0, "hclk_pdvo_niu", "hclk_pdvo", CLK_IGNORE_UNUSED, + RV1126_CLKGATE_CON(14), 4, GFLAGS), + GATE(0, "pclk_pdvo_niu", "pclk_pdvo", CLK_IGNORE_UNUSED, + RV1126_CLKGATE_CON(14), 5, GFLAGS), + + /* * Clock-Architecture Diagram 12 */ /* PD_PHP */ diff --git a/drivers/clk/samsung/clk-exynos-arm64.c b/drivers/clk/samsung/clk-exynos-arm64.c index 7d8937caf22a..6fb7194df7ab 100644 --- a/drivers/clk/samsung/clk-exynos-arm64.c +++ b/drivers/clk/samsung/clk-exynos-arm64.c @@ -10,7 +10,8 @@ */ #include <linux/clk.h> #include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/slab.h> diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 7626dff41f6f..e44b172d7255 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -10,8 +10,7 @@ #include <linux/io.h> #include <linux/clk.h> #include <linux/clk-provider.h> -#include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> diff --git a/drivers/clk/samsung/clk-exynos5-subcmu.c b/drivers/clk/samsung/clk-exynos5-subcmu.c index 96d74bc250e5..373129847301 100644 --- a/drivers/clk/samsung/clk-exynos5-subcmu.c +++ b/drivers/clk/samsung/clk-exynos5-subcmu.c @@ -5,7 +5,7 @@ // Common Clock Framework support for Exynos5 power-domain dependent clocks #include <linux/io.h> -#include <linux/of_platform.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_domain.h> #include <linux/pm_runtime.h> diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c index 0d2a950ed184..0c6a84764f7a 100644 --- a/drivers/clk/samsung/clk-exynos7885.c +++ b/drivers/clk/samsung/clk-exynos7885.c @@ -9,7 +9,6 @@ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <dt-bindings/clock/exynos7885.h> diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c index 98b23af7324d..c32b2e6451a0 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -9,7 +9,6 @@ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <dt-bindings/clock/exynos850.h> diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c index 7b16320bba66..ddef546be545 100644 --- a/drivers/clk/samsung/clk-exynosautov9.c +++ b/drivers/clk/samsung/clk-exynosautov9.c @@ -9,8 +9,6 @@ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <dt-bindings/clock/samsung,exynosautov9.h> diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c index 5d009c70e97d..6f984cfcd33c 100644 --- a/drivers/clk/samsung/clk-fsd.c +++ b/drivers/clk/samsung/clk-fsd.c @@ -13,8 +13,6 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <dt-bindings/clock/fsd-clk.h> diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index e317f3454e93..af81eb835bc2 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -7,7 +7,7 @@ #include <linux/clkdev.h> #include <linux/delay.h> #include <linux/io.h> -#include <linux/of_device.h> +#include <linux/of.h> #include "sifive-prci.h" #include "fu540-prci.h" #include "fu740-prci.h" diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c index 74d21bd82710..6b65a74aefa6 100644 --- a/drivers/clk/socfpga/clk-agilex.c +++ b/drivers/clk/socfpga/clk-agilex.c @@ -4,8 +4,7 @@ */ #include <linux/slab.h> #include <linux/clk-provider.h> -#include <linux/of_device.h> -#include <linux/of_address.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <dt-bindings/clock/agilex-clock.h> @@ -458,12 +457,10 @@ static int agilex_clkmgr_init(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct device *dev = &pdev->dev; struct stratix10_clock_data *clk_data; - struct resource *res; void __iomem *base; int i, num_clks; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(dev, res); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c index 9b2e0275fbf7..3752bd9c103c 100644 --- a/drivers/clk/socfpga/clk-s10.c +++ b/drivers/clk/socfpga/clk-s10.c @@ -4,8 +4,7 @@ */ #include <linux/slab.h> #include <linux/clk-provider.h> -#include <linux/of_device.h> -#include <linux/of_address.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <dt-bindings/clock/stratix10-clock.h> diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c index 9d5959a4251a..0847f5452489 100644 --- a/drivers/clk/spear/spear1310_clock.c +++ b/drivers/clk/spear/spear1310_clock.c @@ -12,7 +12,6 @@ #include <linux/clk/spear.h> #include <linux/err.h> #include <linux/io.h> -#include <linux/of_platform.h> #include <linux/spinlock_types.h> #include "clk.h" diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c index 8b51229d0471..361d344bfaf0 100644 --- a/drivers/clk/spear/spear1340_clock.c +++ b/drivers/clk/spear/spear1340_clock.c @@ -12,7 +12,6 @@ #include <linux/clk/spear.h> #include <linux/err.h> #include <linux/io.h> -#include <linux/of_platform.h> #include <linux/spinlock_types.h> #include "clk.h" diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c index ba8791303156..6c0af99b0578 100644 --- a/drivers/clk/spear/spear3xx_clock.c +++ b/drivers/clk/spear/spear3xx_clock.c @@ -11,7 +11,7 @@ #include <linux/clk/spear.h> #include <linux/err.h> #include <linux/io.h> -#include <linux/of_platform.h> +#include <linux/of.h> #include <linux/spinlock_types.h> #include "clk.h" diff --git a/drivers/clk/sprd/common.c b/drivers/clk/sprd/common.c index 16142fbb7a47..762f0961f17f 100644 --- a/drivers/clk/sprd/common.c +++ b/drivers/clk/sprd/common.c @@ -8,7 +8,7 @@ #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of_address.h> -#include <linux/of_platform.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include "common.h" diff --git a/drivers/clk/sprd/sc9860-clk.c b/drivers/clk/sprd/sc9860-clk.c index f76305b4bc8d..cc5ed2dd8267 100644 --- a/drivers/clk/sprd/sc9860-clk.c +++ b/drivers/clk/sprd/sc9860-clk.c @@ -9,7 +9,7 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> diff --git a/drivers/clk/sprd/ums512-clk.c b/drivers/clk/sprd/ums512-clk.c index fc25bdd85e4e..8f4441dd572b 100644 --- a/drivers/clk/sprd/ums512-clk.c +++ b/drivers/clk/sprd/ums512-clk.c @@ -9,8 +9,8 @@ #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/io.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/slab.h> diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index 5d2333106f13..bd29358ffeec 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -21,12 +21,21 @@ config CLK_STARFIVE_JH7100_AUDIO Say Y or M here to support the audio clocks on the StarFive JH7100 SoC. +config CLK_STARFIVE_JH7110_PLL + bool "StarFive JH7110 PLL clock support" + depends on ARCH_STARFIVE || COMPILE_TEST + default ARCH_STARFIVE + help + Say yes here to support the PLL clock controller on the + StarFive JH7110 SoC. + config CLK_STARFIVE_JH7110_SYS bool "StarFive JH7110 system clock support" depends on ARCH_STARFIVE || COMPILE_TEST select AUXILIARY_BUS select CLK_STARFIVE_JH71X0 select RESET_STARFIVE_JH7110 if RESET_CONTROLLER + select CLK_STARFIVE_JH7110_PLL default ARCH_STARFIVE help Say yes here to support the system clock controller on the @@ -39,3 +48,27 @@ config CLK_STARFIVE_JH7110_AON help Say yes here to support the always-on clock controller on the StarFive JH7110 SoC. + +config CLK_STARFIVE_JH7110_STG + tristate "StarFive JH7110 System-Top-Group clock support" + depends on CLK_STARFIVE_JH7110_SYS + default m if ARCH_STARFIVE + help + Say yes here to support the System-Top-Group clock controller + on the StarFive JH7110 SoC. + +config CLK_STARFIVE_JH7110_ISP + tristate "StarFive JH7110 Image-Signal-Process clock support" + depends on CLK_STARFIVE_JH7110_SYS && JH71XX_PMU + default m if ARCH_STARFIVE + help + Say yes here to support the Image-Signal-Process clock controller + on the StarFive JH7110 SoC. + +config CLK_STARFIVE_JH7110_VOUT + tristate "StarFive JH7110 Video-Output clock support" + depends on CLK_STARFIVE_JH7110_SYS && JH71XX_PMU + default m if ARCH_STARFIVE + help + Say yes here to support the Video-Output clock controller + on the StarFive JH7110 SoC. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index f3df7d957b1e..199ac0f37a2f 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -4,5 +4,9 @@ obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o +obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL) += clk-starfive-jh7110-pll.o obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o +obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o +obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o +obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c index 02aefb7264f8..ee4bda14a40e 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c +++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c @@ -11,7 +11,6 @@ #include <linux/kernel.h> #include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <dt-bindings/clock/starfive-jh7100-audio.h> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-isp.c b/drivers/clk/starfive/clk-starfive-jh7110-isp.c new file mode 100644 index 000000000000..ce034ed28532 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jh7110-isp.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JH7110 Image-Signal-Process Clock Driver + * + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/reset.h> + +#include <dt-bindings/clock/starfive,jh7110-crg.h> + +#include "clk-starfive-jh7110.h" + +/* external clocks */ +#define JH7110_ISPCLK_ISP_TOP_CORE (JH7110_ISPCLK_END + 0) +#define JH7110_ISPCLK_ISP_TOP_AXI (JH7110_ISPCLK_END + 1) +#define JH7110_ISPCLK_NOC_BUS_ISP_AXI (JH7110_ISPCLK_END + 2) +#define JH7110_ISPCLK_DVP_CLK (JH7110_ISPCLK_END + 3) +#define JH7110_ISPCLK_EXT_END (JH7110_ISPCLK_END + 4) + +static struct clk_bulk_data jh7110_isp_top_clks[] = { + { .id = "isp_top_core" }, + { .id = "isp_top_axi" } +}; + +static const struct jh71x0_clk_data jh7110_ispclk_data[] = { + /* syscon */ + JH71X0__DIV(JH7110_ISPCLK_DOM4_APB_FUNC, "dom4_apb_func", 15, + JH7110_ISPCLK_ISP_TOP_AXI), + JH71X0__DIV(JH7110_ISPCLK_MIPI_RX0_PXL, "mipi_rx0_pxl", 8, + JH7110_ISPCLK_ISP_TOP_CORE), + JH71X0__INV(JH7110_ISPCLK_DVP_INV, "dvp_inv", JH7110_ISPCLK_DVP_CLK), + /* vin */ + JH71X0__DIV(JH7110_ISPCLK_M31DPHY_CFG_IN, "m31dphy_cfg_in", 16, + JH7110_ISPCLK_ISP_TOP_CORE), + JH71X0__DIV(JH7110_ISPCLK_M31DPHY_REF_IN, "m31dphy_ref_in", 16, + JH7110_ISPCLK_ISP_TOP_CORE), + JH71X0__DIV(JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0, "m31dphy_tx_esc_lan0", 60, + JH7110_ISPCLK_ISP_TOP_CORE), + JH71X0_GATE(JH7110_ISPCLK_VIN_APB, "vin_apb", 0, + JH7110_ISPCLK_DOM4_APB_FUNC), + JH71X0__DIV(JH7110_ISPCLK_VIN_SYS, "vin_sys", 8, JH7110_ISPCLK_ISP_TOP_CORE), + JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF0, "vin_pixel_if0", 0, + JH7110_ISPCLK_MIPI_RX0_PXL), + JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF1, "vin_pixel_if1", 0, + JH7110_ISPCLK_MIPI_RX0_PXL), + JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF2, "vin_pixel_if2", 0, + JH7110_ISPCLK_MIPI_RX0_PXL), + JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0, + JH7110_ISPCLK_MIPI_RX0_PXL), + JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2, + JH7110_ISPCLK_MIPI_RX0_PXL, + JH7110_ISPCLK_DVP_INV), + /* ispv2_top_wrapper */ + JH71X0_GMUX(JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C, "ispv2_top_wrapper_c", 0, 2, + JH7110_ISPCLK_MIPI_RX0_PXL, + JH7110_ISPCLK_DVP_INV), +}; + +static inline int jh7110_isp_top_rst_init(struct jh71x0_clk_priv *priv) +{ + struct reset_control *top_rsts; + + /* The resets should be shared and other ISP modules will use its. */ + top_rsts = devm_reset_control_array_get_shared(priv->dev); + if (IS_ERR(top_rsts)) + return dev_err_probe(priv->dev, PTR_ERR(top_rsts), + "failed to get top resets\n"); + + return reset_control_deassert(top_rsts); +} + +static struct clk_hw *jh7110_ispclk_get(struct of_phandle_args *clkspec, void *data) +{ + struct jh71x0_clk_priv *priv = data; + unsigned int idx = clkspec->args[0]; + + if (idx < JH7110_ISPCLK_END) + return &priv->reg[idx].hw; + + return ERR_PTR(-EINVAL); +} + +#ifdef CONFIG_PM +static int jh7110_ispcrg_suspend(struct device *dev) +{ + struct jh7110_top_sysclk *top = dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks); + + return 0; +} + +static int jh7110_ispcrg_resume(struct device *dev) +{ + struct jh7110_top_sysclk *top = dev_get_drvdata(dev); + + return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks); +} + +static const struct dev_pm_ops jh7110_ispcrg_pm_ops = { + RUNTIME_PM_OPS(jh7110_ispcrg_suspend, jh7110_ispcrg_resume, NULL) +}; +#endif + +static int jh7110_ispcrg_probe(struct platform_device *pdev) +{ + struct jh71x0_clk_priv *priv; + struct jh7110_top_sysclk *top; + unsigned int idx; + int ret; + + priv = devm_kzalloc(&pdev->dev, + struct_size(priv, reg, JH7110_ISPCLK_END), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL); + if (!top) + return -ENOMEM; + + spin_lock_init(&priv->rmw_lock); + priv->dev = &pdev->dev; + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + top->top_clks = jh7110_isp_top_clks; + top->top_clks_num = ARRAY_SIZE(jh7110_isp_top_clks); + ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks); + if (ret) + return dev_err_probe(priv->dev, ret, "failed to get main clocks\n"); + dev_set_drvdata(priv->dev, top); + + /* enable power domain and clocks */ + pm_runtime_enable(priv->dev); + ret = pm_runtime_get_sync(priv->dev); + if (ret < 0) + return dev_err_probe(priv->dev, ret, "failed to turn on power\n"); + + ret = jh7110_isp_top_rst_init(priv); + if (ret) + goto err_exit; + + for (idx = 0; idx < JH7110_ISPCLK_END; idx++) { + u32 max = jh7110_ispclk_data[idx].max; + struct clk_parent_data parents[4] = {}; + struct clk_init_data init = { + .name = jh7110_ispclk_data[idx].name, + .ops = starfive_jh71x0_clk_ops(max), + .parent_data = parents, + .num_parents = + ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, + .flags = jh7110_ispclk_data[idx].flags, + }; + struct jh71x0_clk *clk = &priv->reg[idx]; + unsigned int i; + const char *fw_name[JH7110_ISPCLK_EXT_END - JH7110_ISPCLK_END] = { + "isp_top_core", + "isp_top_axi", + "noc_bus_isp_axi", + "dvp_clk" + }; + + for (i = 0; i < init.num_parents; i++) { + unsigned int pidx = jh7110_ispclk_data[idx].parents[i]; + + if (pidx < JH7110_ISPCLK_END) + parents[i].hw = &priv->reg[pidx].hw; + else + parents[i].fw_name = fw_name[pidx - JH7110_ISPCLK_END]; + } + + clk->hw.init = &init; + clk->idx = idx; + clk->max_div = max & JH71X0_CLK_DIV_MASK; + + ret = devm_clk_hw_register(&pdev->dev, &clk->hw); + if (ret) + goto err_exit; + } + + ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_ispclk_get, priv); + if (ret) + goto err_exit; + + ret = jh7110_reset_controller_register(priv, "rst-isp", 3); + if (ret) + goto err_exit; + + return 0; + +err_exit: + pm_runtime_put_sync(priv->dev); + pm_runtime_disable(priv->dev); + return ret; +} + +static int jh7110_ispcrg_remove(struct platform_device *pdev) +{ + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct of_device_id jh7110_ispcrg_match[] = { + { .compatible = "starfive,jh7110-ispcrg" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh7110_ispcrg_match); + +static struct platform_driver jh7110_ispcrg_driver = { + .probe = jh7110_ispcrg_probe, + .remove = jh7110_ispcrg_remove, + .driver = { + .name = "clk-starfive-jh7110-isp", + .of_match_table = jh7110_ispcrg_match, + .pm = pm_ptr(&jh7110_ispcrg_pm_ops), + }, +}; +module_platform_driver(jh7110_ispcrg_driver); + +MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>"); +MODULE_DESCRIPTION("StarFive JH7110 Image-Signal-Process clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.c b/drivers/clk/starfive/clk-starfive-jh7110-pll.c new file mode 100644 index 000000000000..3598390e8fd0 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.c @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JH7110 PLL Clock Generator Driver + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * Copyright (C) 2023 Emil Renner Berthing <emil.renner.berthing@canonical.com> + * + * This driver is about to register JH7110 PLL clock generator and support ops. + * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2. + * Each PLL clocks work in integer mode or fraction mode by some dividers, + * and the configuration registers and dividers are set in several syscon registers. + * The formula for calculating frequency is: + * Fvco = Fref * (NI + NF) / M / Q1 + * Fref: OSC source clock rate + * NI: integer frequency dividing ratio of feedback divider, set by fbdiv[11:0]. + * NF: fractional frequency dividing ratio, set by frac[23:0]. NF = frac[23:0] / 2^24 = 0 ~ 0.999. + * M: frequency dividing ratio of pre-divider, set by prediv[5:0]. + * Q1: frequency dividing ratio of post divider, set by 2^postdiv1[1:0], eg. 1, 2, 4 or 8. + */ + +#include <linux/bits.h> +#include <linux/clk-provider.h> +#include <linux/debugfs.h> +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/starfive,jh7110-crg.h> + +/* this driver expects a 24MHz input frequency from the oscillator */ +#define JH7110_PLL_OSC_RATE 24000000UL + +#define JH7110_PLL0_PD_OFFSET 0x18 +#define JH7110_PLL0_DACPD_SHIFT 24 +#define JH7110_PLL0_DACPD_MASK BIT(24) +#define JH7110_PLL0_DSMPD_SHIFT 25 +#define JH7110_PLL0_DSMPD_MASK BIT(25) +#define JH7110_PLL0_FBDIV_OFFSET 0x1c +#define JH7110_PLL0_FBDIV_SHIFT 0 +#define JH7110_PLL0_FBDIV_MASK GENMASK(11, 0) +#define JH7110_PLL0_FRAC_OFFSET 0x20 +#define JH7110_PLL0_PREDIV_OFFSET 0x24 + +#define JH7110_PLL1_PD_OFFSET 0x24 +#define JH7110_PLL1_DACPD_SHIFT 15 +#define JH7110_PLL1_DACPD_MASK BIT(15) +#define JH7110_PLL1_DSMPD_SHIFT 16 +#define JH7110_PLL1_DSMPD_MASK BIT(16) +#define JH7110_PLL1_FBDIV_OFFSET 0x24 +#define JH7110_PLL1_FBDIV_SHIFT 17 +#define JH7110_PLL1_FBDIV_MASK GENMASK(28, 17) +#define JH7110_PLL1_FRAC_OFFSET 0x28 +#define JH7110_PLL1_PREDIV_OFFSET 0x2c + +#define JH7110_PLL2_PD_OFFSET 0x2c +#define JH7110_PLL2_DACPD_SHIFT 15 +#define JH7110_PLL2_DACPD_MASK BIT(15) +#define JH7110_PLL2_DSMPD_SHIFT 16 +#define JH7110_PLL2_DSMPD_MASK BIT(16) +#define JH7110_PLL2_FBDIV_OFFSET 0x2c +#define JH7110_PLL2_FBDIV_SHIFT 17 +#define JH7110_PLL2_FBDIV_MASK GENMASK(28, 17) +#define JH7110_PLL2_FRAC_OFFSET 0x30 +#define JH7110_PLL2_PREDIV_OFFSET 0x34 + +#define JH7110_PLL_FRAC_SHIFT 0 +#define JH7110_PLL_FRAC_MASK GENMASK(23, 0) +#define JH7110_PLL_POSTDIV1_SHIFT 28 +#define JH7110_PLL_POSTDIV1_MASK GENMASK(29, 28) +#define JH7110_PLL_PREDIV_SHIFT 0 +#define JH7110_PLL_PREDIV_MASK GENMASK(5, 0) + +enum jh7110_pll_mode { + JH7110_PLL_MODE_FRACTION, + JH7110_PLL_MODE_INTEGER, +}; + +struct jh7110_pll_preset { + unsigned long freq; + u32 frac; /* frac value should be decimals multiplied by 2^24 */ + unsigned fbdiv : 12; /* fbdiv value should be 8 to 4095 */ + unsigned prediv : 6; + unsigned postdiv1 : 2; + unsigned mode : 1; +}; + +struct jh7110_pll_info { + char *name; + const struct jh7110_pll_preset *presets; + unsigned int npresets; + struct { + unsigned int pd; + unsigned int fbdiv; + unsigned int frac; + unsigned int prediv; + } offsets; + struct { + u32 dacpd; + u32 dsmpd; + u32 fbdiv; + } masks; + struct { + char dacpd; + char dsmpd; + char fbdiv; + } shifts; +}; + +#define _JH7110_PLL(_idx, _name, _presets) \ + [_idx] = { \ + .name = _name, \ + .presets = _presets, \ + .npresets = ARRAY_SIZE(_presets), \ + .offsets = { \ + .pd = JH7110_PLL##_idx##_PD_OFFSET, \ + .fbdiv = JH7110_PLL##_idx##_FBDIV_OFFSET, \ + .frac = JH7110_PLL##_idx##_FRAC_OFFSET, \ + .prediv = JH7110_PLL##_idx##_PREDIV_OFFSET, \ + }, \ + .masks = { \ + .dacpd = JH7110_PLL##_idx##_DACPD_MASK, \ + .dsmpd = JH7110_PLL##_idx##_DSMPD_MASK, \ + .fbdiv = JH7110_PLL##_idx##_FBDIV_MASK, \ + }, \ + .shifts = { \ + .dacpd = JH7110_PLL##_idx##_DACPD_SHIFT, \ + .dsmpd = JH7110_PLL##_idx##_DSMPD_SHIFT, \ + .fbdiv = JH7110_PLL##_idx##_FBDIV_SHIFT, \ + }, \ + } +#define JH7110_PLL(idx, name, presets) _JH7110_PLL(idx, name, presets) + +struct jh7110_pll_data { + struct clk_hw hw; + unsigned int idx; +}; + +struct jh7110_pll_priv { + struct device *dev; + struct regmap *regmap; + struct jh7110_pll_data pll[JH7110_PLLCLK_END]; +}; + +struct jh7110_pll_regvals { + u32 dacpd; + u32 dsmpd; + u32 fbdiv; + u32 frac; + u32 postdiv1; + u32 prediv; +}; + +/* + * Because the pll frequency is relatively fixed, + * it cannot be set arbitrarily, so it needs a specific configuration. + * PLL0 frequency should be multiple of 125MHz (USB frequency). + */ +static const struct jh7110_pll_preset jh7110_pll0_presets[] = { + { + .freq = 375000000, + .fbdiv = 125, + .prediv = 8, + .postdiv1 = 0, + .mode = JH7110_PLL_MODE_INTEGER, + }, { + .freq = 500000000, + .fbdiv = 125, + .prediv = 6, + .postdiv1 = 0, + .mode = JH7110_PLL_MODE_INTEGER, + }, { + .freq = 625000000, + .fbdiv = 625, + .prediv = 24, + .postdiv1 = 0, + .mode = JH7110_PLL_MODE_INTEGER, + }, { + .freq = 750000000, + .fbdiv = 125, + .prediv = 4, + .postdiv1 = 0, + .mode = JH7110_PLL_MODE_INTEGER, + }, { + .freq = 875000000, + .fbdiv = 875, + .prediv = 24, + .postdiv1 = 0, + .mode = JH7110_PLL_MODE_INTEGER, + }, { + .freq = 1000000000, + .fbdiv = 125, + .prediv = 3, + .postdiv1 = 0, + .mode = JH7110_PLL_MODE_INTEGER, + }, { + .freq = 1250000000, + .fbdiv = 625, + .prediv = 12, + .postdiv1 = 0, + .mode = JH7110_PLL_MODE_INTEGER, + }, { + .freq = 1375000000, + .fbdiv = 1375, + .prediv = 24, + .postdiv1 = 0, + .mode = JH7110_PLL_MODE_INTEGER, + }, { + .freq = 1500000000, + .fbdiv = 125, + .prediv = 2, + .postdiv1 = 0, + .mode = JH7110_PLL_MODE_INTEGER, + }, +}; + +static const struct jh7110_pll_preset jh7110_pll1_presets[] = { + { + .freq = 1066000000, + .fbdiv = 533, + .prediv = 12, + .postdiv1 = 0, + .mode = JH7110_PLL_MODE_INTEGER, + }, { + .freq = 1200000000, + .fbdiv = 50, + .prediv = 1, + .postdiv1 = 0, + .mode = JH7110_PLL_MODE_INTEGER, + }, { + .freq = 1400000000, + .fbdiv = 350, + .prediv = 6, + .postdiv1 = 0, + .mode = JH7110_PLL_MODE_INTEGER, + }, { + .freq = 1600000000, + .fbdiv = 200, + .prediv = 3, + .postdiv1 = 0, + .mode = JH7110_PLL_MODE_INTEGER, + }, +}; + +static const struct jh7110_pll_preset jh7110_pll2_presets[] = { + { + .freq = 1188000000, + .fbdiv = 99, + .prediv = 2, + .postdiv1 = 0, + .mode = JH7110_PLL_MODE_INTEGER, + }, { + .freq = 1228800000, + .fbdiv = 256, + .prediv = 5, + .postdiv1 = 0, + .mode = JH7110_PLL_MODE_INTEGER, + }, +}; + +static const struct jh7110_pll_info jh7110_plls[JH7110_PLLCLK_END] = { + JH7110_PLL(JH7110_PLLCLK_PLL0_OUT, "pll0_out", jh7110_pll0_presets), + JH7110_PLL(JH7110_PLLCLK_PLL1_OUT, "pll1_out", jh7110_pll1_presets), + JH7110_PLL(JH7110_PLLCLK_PLL2_OUT, "pll2_out", jh7110_pll2_presets), +}; + +static struct jh7110_pll_data *jh7110_pll_data_from(struct clk_hw *hw) +{ + return container_of(hw, struct jh7110_pll_data, hw); +} + +static struct jh7110_pll_priv *jh7110_pll_priv_from(struct jh7110_pll_data *pll) +{ + return container_of(pll, struct jh7110_pll_priv, pll[pll->idx]); +} + +static void jh7110_pll_regvals_get(struct regmap *regmap, + const struct jh7110_pll_info *info, + struct jh7110_pll_regvals *ret) +{ + u32 val; + + regmap_read(regmap, info->offsets.pd, &val); + ret->dacpd = (val & info->masks.dacpd) >> info->shifts.dacpd; + ret->dsmpd = (val & info->masks.dsmpd) >> info->shifts.dsmpd; + + regmap_read(regmap, info->offsets.fbdiv, &val); + ret->fbdiv = (val & info->masks.fbdiv) >> info->shifts.fbdiv; + + regmap_read(regmap, info->offsets.frac, &val); + ret->frac = (val & JH7110_PLL_FRAC_MASK) >> JH7110_PLL_FRAC_SHIFT; + ret->postdiv1 = (val & JH7110_PLL_POSTDIV1_MASK) >> JH7110_PLL_POSTDIV1_SHIFT; + + regmap_read(regmap, info->offsets.prediv, &val); + ret->prediv = (val & JH7110_PLL_PREDIV_MASK) >> JH7110_PLL_PREDIV_SHIFT; +} + +static unsigned long jh7110_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct jh7110_pll_data *pll = jh7110_pll_data_from(hw); + struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll); + struct jh7110_pll_regvals val; + unsigned long rate; + + jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val); + + /* + * dacpd = dsmpd = 0: fraction mode + * dacpd = dsmpd = 1: integer mode, frac value ignored + * + * rate = parent * (fbdiv + frac/2^24) / prediv / 2^postdiv1 + * = (parent * fbdiv + parent * frac / 2^24) / (prediv * 2^postdiv1) + */ + if (val.dacpd == 0 && val.dsmpd == 0) + rate = parent_rate * val.frac / (1UL << 24); + else if (val.dacpd == 1 && val.dsmpd == 1) + rate = 0; + else + return 0; + + rate += parent_rate * val.fbdiv; + rate /= val.prediv << val.postdiv1; + + return rate; +} + +static int jh7110_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) +{ + struct jh7110_pll_data *pll = jh7110_pll_data_from(hw); + const struct jh7110_pll_info *info = &jh7110_plls[pll->idx]; + const struct jh7110_pll_preset *selected = &info->presets[0]; + unsigned int idx; + + /* if the parent rate doesn't match our expectations the presets won't work */ + if (req->best_parent_rate != JH7110_PLL_OSC_RATE) { + req->rate = jh7110_pll_recalc_rate(hw, req->best_parent_rate); + return 0; + } + + /* find highest rate lower or equal to the requested rate */ + for (idx = 1; idx < info->npresets; idx++) { + const struct jh7110_pll_preset *val = &info->presets[idx]; + + if (req->rate < val->freq) + break; + + selected = val; + } + + req->rate = selected->freq; + return 0; +} + +static int jh7110_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct jh7110_pll_data *pll = jh7110_pll_data_from(hw); + struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll); + const struct jh7110_pll_info *info = &jh7110_plls[pll->idx]; + const struct jh7110_pll_preset *val; + unsigned int idx; + + /* if the parent rate doesn't match our expectations the presets won't work */ + if (parent_rate != JH7110_PLL_OSC_RATE) + return -EINVAL; + + for (idx = 0, val = &info->presets[0]; idx < info->npresets; idx++, val++) { + if (val->freq == rate) + goto found; + } + return -EINVAL; + +found: + if (val->mode == JH7110_PLL_MODE_FRACTION) + regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_FRAC_MASK, + val->frac << JH7110_PLL_FRAC_SHIFT); + + regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dacpd, + (u32)val->mode << info->shifts.dacpd); + regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dsmpd, + (u32)val->mode << info->shifts.dsmpd); + regmap_update_bits(priv->regmap, info->offsets.prediv, JH7110_PLL_PREDIV_MASK, + (u32)val->prediv << JH7110_PLL_PREDIV_SHIFT); + regmap_update_bits(priv->regmap, info->offsets.fbdiv, info->masks.fbdiv, + val->fbdiv << info->shifts.fbdiv); + regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_POSTDIV1_MASK, + (u32)val->postdiv1 << JH7110_PLL_POSTDIV1_SHIFT); + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static int jh7110_pll_registers_read(struct seq_file *s, void *unused) +{ + struct jh7110_pll_data *pll = s->private; + struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll); + struct jh7110_pll_regvals val; + + jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val); + + seq_printf(s, "fbdiv=%u\n" + "frac=%u\n" + "prediv=%u\n" + "postdiv1=%u\n" + "dacpd=%u\n" + "dsmpd=%u\n", + val.fbdiv, val.frac, val.prediv, val.postdiv1, + val.dacpd, val.dsmpd); + + return 0; +} + +static int jh7110_pll_registers_open(struct inode *inode, struct file *f) +{ + return single_open(f, jh7110_pll_registers_read, inode->i_private); +} + +static const struct file_operations jh7110_pll_registers_ops = { + .owner = THIS_MODULE, + .open = jh7110_pll_registers_open, + .release = single_release, + .read = seq_read, + .llseek = seq_lseek +}; + +static void jh7110_pll_debug_init(struct clk_hw *hw, struct dentry *dentry) +{ + struct jh7110_pll_data *pll = jh7110_pll_data_from(hw); + + debugfs_create_file("registers", 0400, dentry, pll, + &jh7110_pll_registers_ops); +} +#else +#define jh7110_pll_debug_init NULL +#endif + +static const struct clk_ops jh7110_pll_ops = { + .recalc_rate = jh7110_pll_recalc_rate, + .determine_rate = jh7110_pll_determine_rate, + .set_rate = jh7110_pll_set_rate, + .debug_init = jh7110_pll_debug_init, +}; + +static struct clk_hw *jh7110_pll_get(struct of_phandle_args *clkspec, void *data) +{ + struct jh7110_pll_priv *priv = data; + unsigned int idx = clkspec->args[0]; + + if (idx < JH7110_PLLCLK_END) + return &priv->pll[idx].hw; + + return ERR_PTR(-EINVAL); +} + +static int jh7110_pll_probe(struct platform_device *pdev) +{ + struct jh7110_pll_priv *priv; + unsigned int idx; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + priv->regmap = syscon_node_to_regmap(priv->dev->of_node->parent); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + for (idx = 0; idx < JH7110_PLLCLK_END; idx++) { + struct clk_parent_data parents = { + .index = 0, + }; + struct clk_init_data init = { + .name = jh7110_plls[idx].name, + .ops = &jh7110_pll_ops, + .parent_data = &parents, + .num_parents = 1, + .flags = 0, + }; + struct jh7110_pll_data *pll = &priv->pll[idx]; + + pll->hw.init = &init; + pll->idx = idx; + + ret = devm_clk_hw_register(&pdev->dev, &pll->hw); + if (ret) + return ret; + } + + return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_pll_get, priv); +} + +static const struct of_device_id jh7110_pll_match[] = { + { .compatible = "starfive,jh7110-pll" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh7110_pll_match); + +static struct platform_driver jh7110_pll_driver = { + .driver = { + .name = "clk-starfive-jh7110-pll", + .of_match_table = jh7110_pll_match, + }, +}; +builtin_platform_driver_probe(jh7110_pll_driver, jh7110_pll_probe); diff --git a/drivers/clk/starfive/clk-starfive-jh7110-stg.c b/drivers/clk/starfive/clk-starfive-jh7110-stg.c new file mode 100644 index 000000000000..dafcb7190592 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JH7110 System-Top-Group Clock Driver + * + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#include <linux/clk-provider.h> +#include <linux/io.h> +#include <linux/platform_device.h> + +#include <dt-bindings/clock/starfive,jh7110-crg.h> + +#include "clk-starfive-jh7110.h" + +/* external clocks */ +#define JH7110_STGCLK_OSC (JH7110_STGCLK_END + 0) +#define JH7110_STGCLK_HIFI4_CORE (JH7110_STGCLK_END + 1) +#define JH7110_STGCLK_STG_AXIAHB (JH7110_STGCLK_END + 2) +#define JH7110_STGCLK_USB_125M (JH7110_STGCLK_END + 3) +#define JH7110_STGCLK_CPU_BUS (JH7110_STGCLK_END + 4) +#define JH7110_STGCLK_HIFI4_AXI (JH7110_STGCLK_END + 5) +#define JH7110_STGCLK_NOCSTG_BUS (JH7110_STGCLK_END + 6) +#define JH7110_STGCLK_APB_BUS (JH7110_STGCLK_END + 7) +#define JH7110_STGCLK_EXT_END (JH7110_STGCLK_END + 8) + +static const struct jh71x0_clk_data jh7110_stgclk_data[] = { + /* hifi4 */ + JH71X0_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", 0, + JH7110_STGCLK_HIFI4_CORE), + /* usb */ + JH71X0_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", 0, JH7110_STGCLK_APB_BUS), + JH71X0_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", 0, JH7110_STGCLK_APB_BUS), + JH71X0_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", 0, JH7110_STGCLK_STG_AXIAHB), + JH71X0_GDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 0, 2, JH7110_STGCLK_OSC), + JH71X0_GDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 0, 4, JH7110_STGCLK_OSC), + JH71X0_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", 0, JH7110_STGCLK_USB_125M), + JH71X0__DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, JH7110_STGCLK_OSC), + /* pci-e */ + JH71X0_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0, + JH7110_STGCLK_STG_AXIAHB), + JH71X0_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", 0, JH7110_STGCLK_APB_BUS), + JH71X0_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", 0, JH7110_STGCLK_STG_AXIAHB), + JH71X0_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", 0, + JH7110_STGCLK_STG_AXIAHB), + JH71X0_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", 0, JH7110_STGCLK_APB_BUS), + JH71X0_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", 0, JH7110_STGCLK_STG_AXIAHB), + JH71X0_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", CLK_IS_CRITICAL, + JH7110_STGCLK_STG_AXIAHB), + /* security */ + JH71X0_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", 0, JH7110_STGCLK_STG_AXIAHB), + JH71X0_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", 0, JH7110_STGCLK_STG_AXIAHB), + /* stg mtrx */ + JH71X0_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", CLK_IS_CRITICAL, + JH7110_STGCLK_CPU_BUS), + JH71X0_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", CLK_IS_CRITICAL, + JH7110_STGCLK_NOCSTG_BUS), + JH71X0_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", CLK_IS_CRITICAL, + JH7110_STGCLK_STG_AXIAHB), + JH71X0_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", CLK_IS_CRITICAL, + JH7110_STGCLK_CPU_BUS), + JH71X0_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", CLK_IS_CRITICAL, + JH7110_STGCLK_NOCSTG_BUS), + JH71X0_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", CLK_IS_CRITICAL, + JH7110_STGCLK_STG_AXIAHB), + JH71X0_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", CLK_IS_CRITICAL, + JH7110_STGCLK_HIFI4_AXI), + /* e24_rvpi */ + JH71X0_GDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 0, 24, JH7110_STGCLK_OSC), + JH71X0_GATE(JH7110_STGCLK_E2_CORE, "e2_core", 0, JH7110_STGCLK_STG_AXIAHB), + JH71X0_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", 0, JH7110_STGCLK_STG_AXIAHB), + /* dw_sgdma1p */ + JH71X0_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", 0, JH7110_STGCLK_STG_AXIAHB), + JH71X0_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7110_STGCLK_STG_AXIAHB), +}; + +static struct clk_hw *jh7110_stgclk_get(struct of_phandle_args *clkspec, void *data) +{ + struct jh71x0_clk_priv *priv = data; + unsigned int idx = clkspec->args[0]; + + if (idx < JH7110_STGCLK_END) + return &priv->reg[idx].hw; + + return ERR_PTR(-EINVAL); +} + +static int jh7110_stgcrg_probe(struct platform_device *pdev) +{ + struct jh71x0_clk_priv *priv; + unsigned int idx; + int ret; + + priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7110_STGCLK_END), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + spin_lock_init(&priv->rmw_lock); + priv->dev = &pdev->dev; + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + for (idx = 0; idx < JH7110_STGCLK_END; idx++) { + u32 max = jh7110_stgclk_data[idx].max; + struct clk_parent_data parents[4] = {}; + struct clk_init_data init = { + .name = jh7110_stgclk_data[idx].name, + .ops = starfive_jh71x0_clk_ops(max), + .parent_data = parents, + .num_parents = + ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, + .flags = jh7110_stgclk_data[idx].flags, + }; + struct jh71x0_clk *clk = &priv->reg[idx]; + const char *fw_name[JH7110_STGCLK_EXT_END - JH7110_STGCLK_END] = { + "osc", + "hifi4_core", + "stg_axiahb", + "usb_125m", + "cpu_bus", + "hifi4_axi", + "nocstg_bus", + "apb_bus" + }; + unsigned int i; + + for (i = 0; i < init.num_parents; i++) { + unsigned int pidx = jh7110_stgclk_data[idx].parents[i]; + + if (pidx < JH7110_STGCLK_END) + parents[i].hw = &priv->reg[pidx].hw; + else if (pidx < JH7110_STGCLK_EXT_END) + parents[i].fw_name = fw_name[pidx - JH7110_STGCLK_END]; + } + + clk->hw.init = &init; + clk->idx = idx; + clk->max_div = max & JH71X0_CLK_DIV_MASK; + + ret = devm_clk_hw_register(&pdev->dev, &clk->hw); + if (ret) + return ret; + } + + ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_stgclk_get, priv); + if (ret) + return ret; + + return jh7110_reset_controller_register(priv, "rst-stg", 2); +} + +static const struct of_device_id jh7110_stgcrg_match[] = { + { .compatible = "starfive,jh7110-stgcrg" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh7110_stgcrg_match); + +static struct platform_driver jh7110_stgcrg_driver = { + .probe = jh7110_stgcrg_probe, + .driver = { + .name = "clk-starfive-jh7110-stg", + .of_match_table = jh7110_stgcrg_match, + }, +}; +module_platform_driver(jh7110_stgcrg_driver); + +MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>"); +MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>"); +MODULE_DESCRIPTION("StarFive JH7110 System-Top-Group clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c index e6031345ef05..3884eff9fe93 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -7,6 +7,7 @@ */ #include <linux/auxiliary_bus.h> +#include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/init.h> #include <linux/io.h> @@ -389,6 +390,7 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) struct jh71x0_clk_priv *priv; unsigned int idx; int ret; + struct clk *pllclk; priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7110_SYSCLK_END), @@ -402,28 +404,42 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) if (IS_ERR(priv->base)) return PTR_ERR(priv->base); - /* - * These PLL clocks are not actually fixed factor clocks and can be - * controlled by the syscon registers of JH7110. They will be dropped - * and registered in the PLL clock driver instead. - */ - /* 24MHz -> 1000.0MHz */ - priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out", - "osc", 0, 125, 3); - if (IS_ERR(priv->pll[0])) - return PTR_ERR(priv->pll[0]); - - /* 24MHz -> 1066.0MHz */ - priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out", - "osc", 0, 533, 12); - if (IS_ERR(priv->pll[1])) - return PTR_ERR(priv->pll[1]); - - /* 24MHz -> 1188.0MHz */ - priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out", - "osc", 0, 99, 2); - if (IS_ERR(priv->pll[2])) - return PTR_ERR(priv->pll[2]); + /* Use fixed factor clocks if can not get the PLL clocks from DTS */ + pllclk = clk_get(priv->dev, "pll0_out"); + if (IS_ERR(pllclk)) { + /* 24MHz -> 1000.0MHz */ + priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out", + "osc", 0, 125, 3); + if (IS_ERR(priv->pll[0])) + return PTR_ERR(priv->pll[0]); + } else { + clk_put(pllclk); + priv->pll[0] = NULL; + } + + pllclk = clk_get(priv->dev, "pll1_out"); + if (IS_ERR(pllclk)) { + /* 24MHz -> 1066.0MHz */ + priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out", + "osc", 0, 533, 12); + if (IS_ERR(priv->pll[1])) + return PTR_ERR(priv->pll[1]); + } else { + clk_put(pllclk); + priv->pll[1] = NULL; + } + + pllclk = clk_get(priv->dev, "pll2_out"); + if (IS_ERR(pllclk)) { + /* 24MHz -> 1188.0MHz */ + priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out", + "osc", 0, 99, 2); + if (IS_ERR(priv->pll[2])) + return PTR_ERR(priv->pll[2]); + } else { + clk_put(pllclk); + priv->pll[2] = NULL; + } for (idx = 0; idx < JH7110_SYSCLK_END; idx++) { u32 max = jh7110_sysclk_data[idx].max; @@ -462,6 +478,12 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) parents[i].fw_name = "tdm_ext"; else if (pidx == JH7110_SYSCLK_MCLK_EXT) parents[i].fw_name = "mclk_ext"; + else if (pidx == JH7110_SYSCLK_PLL0_OUT && !priv->pll[0]) + parents[i].fw_name = "pll0_out"; + else if (pidx == JH7110_SYSCLK_PLL1_OUT && !priv->pll[1]) + parents[i].fw_name = "pll1_out"; + else if (pidx == JH7110_SYSCLK_PLL2_OUT && !priv->pll[2]) + parents[i].fw_name = "pll2_out"; else parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT]; } diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c new file mode 100644 index 000000000000..10cc1ec43925 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JH7110 Video-Output Clock Driver + * + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/reset.h> + +#include <dt-bindings/clock/starfive,jh7110-crg.h> + +#include "clk-starfive-jh7110.h" + +/* external clocks */ +#define JH7110_VOUTCLK_VOUT_SRC (JH7110_VOUTCLK_END + 0) +#define JH7110_VOUTCLK_VOUT_TOP_AHB (JH7110_VOUTCLK_END + 1) +#define JH7110_VOUTCLK_VOUT_TOP_AXI (JH7110_VOUTCLK_END + 2) +#define JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK (JH7110_VOUTCLK_END + 3) +#define JH7110_VOUTCLK_I2STX0_BCLK (JH7110_VOUTCLK_END + 4) +#define JH7110_VOUTCLK_HDMITX0_PIXELCLK (JH7110_VOUTCLK_END + 5) +#define JH7110_VOUTCLK_EXT_END (JH7110_VOUTCLK_END + 6) + +static struct clk_bulk_data jh7110_vout_top_clks[] = { + { .id = "vout_src" }, + { .id = "vout_top_ahb" } +}; + +static const struct jh71x0_clk_data jh7110_voutclk_data[] = { + /* divider */ + JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB), + JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC), + JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC), + JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB), + /* dc8200 */ + JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI), + JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI), + JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB), + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2, + JH7110_VOUTCLK_DC8200_PIX, + JH7110_VOUTCLK_HDMITX0_PIXELCLK), + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2, + JH7110_VOUTCLK_DC8200_PIX, + JH7110_VOUTCLK_HDMITX0_PIXELCLK), + /* LCD */ + JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2, + JH7110_VOUTCLK_DC8200_PIX0, + JH7110_VOUTCLK_DC8200_PIX1), + /* dsiTx */ + JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS), + JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS), + JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2, + JH7110_VOUTCLK_DC8200_PIX, + JH7110_VOUTCLK_HDMITX0_PIXELCLK), + JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC), + /* mipitx DPHY */ + JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0, + JH7110_VOUTCLK_TX_ESC), + /* hdmi */ + JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0, + JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK), + JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0, + JH7110_VOUTCLK_I2STX0_BCLK), + JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB), +}; + +static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv) +{ + struct reset_control *top_rst; + + /* The reset should be shared and other Vout modules will use its. */ + top_rst = devm_reset_control_get_shared(priv->dev, NULL); + if (IS_ERR(top_rst)) + return dev_err_probe(priv->dev, PTR_ERR(top_rst), "failed to get top reset\n"); + + return reset_control_deassert(top_rst); +} + +static struct clk_hw *jh7110_voutclk_get(struct of_phandle_args *clkspec, void *data) +{ + struct jh71x0_clk_priv *priv = data; + unsigned int idx = clkspec->args[0]; + + if (idx < JH7110_VOUTCLK_END) + return &priv->reg[idx].hw; + + return ERR_PTR(-EINVAL); +} + +#ifdef CONFIG_PM +static int jh7110_voutcrg_suspend(struct device *dev) +{ + struct jh7110_top_sysclk *top = dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks); + + return 0; +} + +static int jh7110_voutcrg_resume(struct device *dev) +{ + struct jh7110_top_sysclk *top = dev_get_drvdata(dev); + + return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks); +} + +static const struct dev_pm_ops jh7110_voutcrg_pm_ops = { + RUNTIME_PM_OPS(jh7110_voutcrg_suspend, jh7110_voutcrg_resume, NULL) +}; +#endif + +static int jh7110_voutcrg_probe(struct platform_device *pdev) +{ + struct jh71x0_clk_priv *priv; + struct jh7110_top_sysclk *top; + unsigned int idx; + int ret; + + priv = devm_kzalloc(&pdev->dev, + struct_size(priv, reg, JH7110_VOUTCLK_END), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL); + if (!top) + return -ENOMEM; + + spin_lock_init(&priv->rmw_lock); + priv->dev = &pdev->dev; + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + top->top_clks = jh7110_vout_top_clks; + top->top_clks_num = ARRAY_SIZE(jh7110_vout_top_clks); + ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks); + if (ret) + return dev_err_probe(priv->dev, ret, "failed to get top clocks\n"); + dev_set_drvdata(priv->dev, top); + + /* enable power domain and clocks */ + pm_runtime_enable(priv->dev); + ret = pm_runtime_get_sync(priv->dev); + if (ret < 0) + return dev_err_probe(priv->dev, ret, "failed to turn on power\n"); + + ret = jh7110_vout_top_rst_init(priv); + if (ret) + goto err_exit; + + for (idx = 0; idx < JH7110_VOUTCLK_END; idx++) { + u32 max = jh7110_voutclk_data[idx].max; + struct clk_parent_data parents[4] = {}; + struct clk_init_data init = { + .name = jh7110_voutclk_data[idx].name, + .ops = starfive_jh71x0_clk_ops(max), + .parent_data = parents, + .num_parents = + ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, + .flags = jh7110_voutclk_data[idx].flags, + }; + struct jh71x0_clk *clk = &priv->reg[idx]; + unsigned int i; + const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = { + "vout_src", + "vout_top_ahb", + "vout_top_axi", + "vout_top_hdmitx0_mclk", + "i2stx0_bclk", + "hdmitx0_pixelclk" + }; + + for (i = 0; i < init.num_parents; i++) { + unsigned int pidx = jh7110_voutclk_data[idx].parents[i]; + + if (pidx < JH7110_VOUTCLK_END) + parents[i].hw = &priv->reg[pidx].hw; + else if (pidx < JH7110_VOUTCLK_EXT_END) + parents[i].fw_name = fw_name[pidx - JH7110_VOUTCLK_END]; + } + + clk->hw.init = &init; + clk->idx = idx; + clk->max_div = max & JH71X0_CLK_DIV_MASK; + + ret = devm_clk_hw_register(&pdev->dev, &clk->hw); + if (ret) + goto err_exit; + } + + ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_voutclk_get, priv); + if (ret) + goto err_exit; + + ret = jh7110_reset_controller_register(priv, "rst-vo", 4); + if (ret) + goto err_exit; + + return 0; + +err_exit: + pm_runtime_put_sync(priv->dev); + pm_runtime_disable(priv->dev); + return ret; +} + +static int jh7110_voutcrg_remove(struct platform_device *pdev) +{ + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct of_device_id jh7110_voutcrg_match[] = { + { .compatible = "starfive,jh7110-voutcrg" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh7110_voutcrg_match); + +static struct platform_driver jh7110_voutcrg_driver = { + .probe = jh7110_voutcrg_probe, + .remove = jh7110_voutcrg_remove, + .driver = { + .name = "clk-starfive-jh7110-vout", + .of_match_table = jh7110_voutcrg_match, + .pm = pm_ptr(&jh7110_voutcrg_pm_ops), + }, +}; +module_platform_driver(jh7110_voutcrg_driver); + +MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>"); +MODULE_DESCRIPTION("StarFive JH7110 Video-Output clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/starfive/clk-starfive-jh7110.h b/drivers/clk/starfive/clk-starfive-jh7110.h index f29682b8d400..0659adae4d76 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110.h +++ b/drivers/clk/starfive/clk-starfive-jh7110.h @@ -4,6 +4,12 @@ #include "clk-starfive-jh71x0.h" +/* top clocks of ISP/VOUT domain from JH7110 SYSCRG */ +struct jh7110_top_sysclk { + struct clk_bulk_data *top_clks; + int top_clks_num; +}; + int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, const char *adev_name, u32 adev_id); diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c index b372083d11c3..aebc99264a0b 100644 --- a/drivers/clk/starfive/clk-starfive-jh71x0.c +++ b/drivers/clk/starfive/clk-starfive-jh71x0.c @@ -174,12 +174,6 @@ static int jh71x0_clk_set_parent(struct clk_hw *hw, u8 index) return 0; } -static int jh71x0_clk_mux_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - return clk_mux_determine_rate_flags(hw, req, 0); -} - static int jh71x0_clk_get_phase(struct clk_hw *hw) { struct jh71x0_clk *clk = jh71x0_clk_from(hw); @@ -261,7 +255,7 @@ static const struct clk_ops jh71x0_clk_gdiv_ops = { }; static const struct clk_ops jh71x0_clk_mux_ops = { - .determine_rate = jh71x0_clk_mux_determine_rate, + .determine_rate = __clk_mux_determine_rate, .set_parent = jh71x0_clk_set_parent, .get_parent = jh71x0_clk_get_parent, .debug_init = jh71x0_clk_debug_init, @@ -271,7 +265,7 @@ static const struct clk_ops jh71x0_clk_gmux_ops = { .enable = jh71x0_clk_enable, .disable = jh71x0_clk_disable, .is_enabled = jh71x0_clk_is_enabled, - .determine_rate = jh71x0_clk_mux_determine_rate, + .determine_rate = __clk_mux_determine_rate, .set_parent = jh71x0_clk_set_parent, .get_parent = jh71x0_clk_get_parent, .debug_init = jh71x0_clk_debug_init, diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c index c19828f1aa0f..451ebb7c99a3 100644 --- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c +++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c @@ -8,7 +8,7 @@ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include "ccu_common.h" diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index eb36f8f77d55..8951ffc14ff5 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -68,7 +68,7 @@ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", BIT(28), /* lock */ CLK_SET_RATE_UNGATE); -static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0", +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(pll_video0_clk, "pll-video0", "osc24M", 0x010, 192000000, /* Minimum rate */ 1008000000, /* Maximum rate */ @@ -179,7 +179,9 @@ static struct ccu_nkm pll_mipi_clk = { .common = { .reg = 0x040, .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0", - &ccu_nkm_ops, CLK_SET_RATE_UNGATE), + &ccu_nkm_ops, + CLK_SET_RATE_UNGATE | CLK_SET_RATE_PARENT), + .features = CCU_FEATURE_CLOSEST_RATE, }, }; @@ -536,25 +538,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" }; static const u8 tcon0_table[] = { 0, 2, }; -static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents, - tcon0_table, 0x118, 24, 3, BIT(31), - CLK_SET_RATE_PARENT | - CLK_SET_RATE_NO_REPARENT); +static SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(tcon0_clk, "tcon0", tcon0_parents, + tcon0_table, 0x118, 24, 3, BIT(31), + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT); static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" }; static const u8 tcon1_table[] = { 0, 2, }; -static struct ccu_div tcon1_clk = { - .enable = BIT(31), - .div = _SUNXI_CCU_DIV(0, 4), - .mux = _SUNXI_CCU_MUX_TABLE(24, 2, tcon1_table), - .common = { - .reg = 0x11c, - .hw.init = CLK_HW_INIT_PARENTS("tcon1", - tcon1_parents, - &ccu_div_ops, - CLK_SET_RATE_PARENT), - }, -}; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(tcon1_clk, "tcon1", tcon1_parents, + tcon1_table, 0x11c, + 0, 4, /* M */ + 24, 2, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" }; static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents, @@ -584,8 +579,8 @@ static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0); static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" }; -static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, - 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); +static SUNXI_CCU_M_WITH_MUX_GATE_CLOSEST(hdmi_clk, "hdmi", hdmi_parents, + 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x154, BIT(31), 0); @@ -597,9 +592,9 @@ static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" }; static const u8 dsi_dphy_table[] = { 0, 2, }; -static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy", - dsi_dphy_parents, dsi_dphy_table, - 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT); +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(dsi_dphy_clk, "dsi-dphy", + dsi_dphy_parents, dsi_dphy_table, + 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c index 001582ea71ba..02b28cfc5525 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c @@ -5,7 +5,7 @@ #include <linux/clk-provider.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include "ccu_common.h" diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c index d65398497d5f..fdc8ccc586c9 100644 --- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c +++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c @@ -5,8 +5,10 @@ #include <linux/clk.h> #include <linux/clk-provider.h> +#include <linux/device.h> #include <linux/io.h> #include <linux/module.h> +#include <linux/of.h> #include <linux/of_device.h> #include <linux/clk/sunxi-ng.h> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index b70b312e7483..6a043a0a9dd6 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -6,7 +6,7 @@ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/reset.h> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index bfebe8dbbe65..74274c17efb3 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c @@ -6,7 +6,7 @@ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include "ccu_common.h" diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c index 4221649b311f..4890a976b1a0 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-r.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c @@ -5,7 +5,7 @@ #include <linux/clk-provider.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include "ccu_common.h" diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c index fbb3529f0d3e..f3ce8664b288 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c @@ -9,7 +9,7 @@ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include "ccu_common.h" diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c index 8d28a7a079d0..8babce55302f 100644 --- a/drivers/clk/sunxi-ng/ccu_common.c +++ b/drivers/clk/sunxi-ng/ccu_common.c @@ -39,6 +39,18 @@ void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock) } EXPORT_SYMBOL_NS_GPL(ccu_helper_wait_for_lock, SUNXI_CCU); +bool ccu_is_better_rate(struct ccu_common *common, + unsigned long target_rate, + unsigned long current_rate, + unsigned long best_rate) +{ + if (common->features & CCU_FEATURE_CLOSEST_RATE) + return abs(current_rate - target_rate) < abs(best_rate - target_rate); + + return current_rate <= target_rate && current_rate > best_rate; +} +EXPORT_SYMBOL_NS_GPL(ccu_is_better_rate, SUNXI_CCU); + /* * This clock notifier is called when the frequency of a PLL clock is * changed. In common PLL designs, changes to the dividers take effect diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h index fbf16c6b896d..942a72c09437 100644 --- a/drivers/clk/sunxi-ng/ccu_common.h +++ b/drivers/clk/sunxi-ng/ccu_common.h @@ -18,6 +18,7 @@ #define CCU_FEATURE_MMC_TIMING_SWITCH BIT(6) #define CCU_FEATURE_SIGMA_DELTA_MOD BIT(7) #define CCU_FEATURE_KEY_FIELD BIT(8) +#define CCU_FEATURE_CLOSEST_RATE BIT(9) /* MMC timing mode switch bit */ #define CCU_MMC_NEW_TIMING_MODE BIT(30) @@ -52,6 +53,11 @@ struct sunxi_ccu_desc { void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock); +bool ccu_is_better_rate(struct ccu_common *common, + unsigned long target_rate, + unsigned long current_rate, + unsigned long best_rate); + struct ccu_pll_nb { struct notifier_block clk_nb; struct ccu_common *common; diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h index 948e2b0c0c3b..90d49ee8e0cc 100644 --- a/drivers/clk/sunxi-ng/ccu_div.h +++ b/drivers/clk/sunxi-ng/ccu_div.h @@ -143,6 +143,26 @@ struct ccu_div { }, \ } +#define SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(_struct, _name, \ + _parents, _table, \ + _reg, \ + _mshift, _mwidth, \ + _muxshift, _muxwidth, \ + _gate, _flags) \ + struct ccu_div _struct = { \ + .enable = _gate, \ + .div = _SUNXI_CCU_DIV_FLAGS(_mshift, _mwidth, CLK_DIVIDER_ROUND_CLOSEST), \ + .mux = _SUNXI_CCU_MUX_TABLE(_muxshift, _muxwidth, _table), \ + .common = { \ + .reg = _reg, \ + .hw.init = CLK_HW_INIT_PARENTS(_name, \ + _parents, \ + &ccu_div_ops, \ + _flags), \ + .features = CCU_FEATURE_CLOSEST_RATE, \ + }, \ + } + #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ _mshift, _mwidth, _muxshift, _muxwidth, \ _gate, _flags) \ @@ -152,6 +172,16 @@ struct ccu_div { _muxshift, _muxwidth, \ _gate, _flags) +#define SUNXI_CCU_M_WITH_MUX_GATE_CLOSEST(_struct, _name, _parents, \ + _reg, _mshift, _mwidth, \ + _muxshift, _muxwidth, \ + _gate, _flags) \ + SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(_struct, _name, \ + _parents, NULL, \ + _reg, _mshift, _mwidth, \ + _muxshift, _muxwidth, \ + _gate, _flags) + #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ _mshift, _mwidth, _muxshift, _muxwidth, \ _flags) \ diff --git a/drivers/clk/sunxi-ng/ccu_mmc_timing.c b/drivers/clk/sunxi-ng/ccu_mmc_timing.c index 23a8d44e2449..78919d7843be 100644 --- a/drivers/clk/sunxi-ng/ccu_mmc_timing.c +++ b/drivers/clk/sunxi-ng/ccu_mmc_timing.c @@ -43,7 +43,7 @@ int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode) EXPORT_SYMBOL_GPL(sunxi_ccu_set_mmc_timing_mode); /** - * sunxi_ccu_set_mmc_timing_mode: Get the current MMC clock timing mode + * sunxi_ccu_get_mmc_timing_mode: Get the current MMC clock timing mode * @clk: clock to query * * Return: %0 if the clock is in old timing mode, > %0 if it is in diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c index 1d557e323169..5edc63b46651 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.c +++ b/drivers/clk/sunxi-ng/ccu_mux.c @@ -139,7 +139,7 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common, goto out; } - if ((req->rate - tmp_rate) < (req->rate - best_rate)) { + if (ccu_is_better_rate(common, req->rate, tmp_rate, best_rate)) { best_rate = tmp_rate; best_parent_rate = parent_rate; best_parent = parent; @@ -242,6 +242,17 @@ static int ccu_mux_set_parent(struct clk_hw *hw, u8 index) return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index); } +static int ccu_mux_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct ccu_mux *cm = hw_to_ccu_mux(hw); + + if (cm->common.features & CCU_FEATURE_CLOSEST_RATE) + return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST); + + return clk_mux_determine_rate_flags(hw, req, 0); +} + static unsigned long ccu_mux_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -259,7 +270,7 @@ const struct clk_ops ccu_mux_ops = { .get_parent = ccu_mux_get_parent, .set_parent = ccu_mux_set_parent, - .determine_rate = __clk_mux_determine_rate, + .determine_rate = ccu_mux_determine_rate, .recalc_rate = ccu_mux_recalc_rate, }; EXPORT_SYMBOL_NS_GPL(ccu_mux_ops, SUNXI_CCU); diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h index 2c1811a445b0..eb1172ebbd94 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.h +++ b/drivers/clk/sunxi-ng/ccu_mux.h @@ -46,20 +46,36 @@ struct ccu_mux { struct ccu_common common; }; +#define SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, _table, \ + _reg, _shift, _width, _gate, \ + _flags, _features) \ + struct ccu_mux _struct = { \ + .enable = _gate, \ + .mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \ + .common = { \ + .reg = _reg, \ + .hw.init = CLK_HW_INIT_PARENTS(_name, \ + _parents, \ + &ccu_mux_ops, \ + _flags), \ + .features = _features, \ + } \ + } + +#define SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(_struct, _name, _parents, \ + _table, _reg, _shift, \ + _width, _gate, _flags) \ + SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, \ + _table, _reg, _shift, \ + _width, _gate, _flags, \ + CCU_FEATURE_CLOSEST_RATE) + #define SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, _table, \ _reg, _shift, _width, _gate, \ _flags) \ - struct ccu_mux _struct = { \ - .enable = _gate, \ - .mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \ - .common = { \ - .reg = _reg, \ - .hw.init = CLK_HW_INIT_PARENTS(_name, \ - _parents, \ - &ccu_mux_ops, \ - _flags), \ - } \ - } + SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, \ + _table, _reg, _shift, \ + _width, _gate, _flags, 0) #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ _shift, _width, _gate, _flags) \ diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c index a0978a50edae..eed64547ad42 100644 --- a/drivers/clk/sunxi-ng/ccu_nkm.c +++ b/drivers/clk/sunxi-ng/ccu_nkm.c @@ -16,8 +16,47 @@ struct _ccu_nkm { unsigned long m, min_m, max_m; }; +static unsigned long ccu_nkm_find_best_with_parent_adj(struct ccu_common *common, + struct clk_hw *parent_hw, + unsigned long *parent, unsigned long rate, + struct _ccu_nkm *nkm) +{ + unsigned long best_rate = 0, best_parent_rate = *parent, tmp_parent = *parent; + unsigned long best_n = 0, best_k = 0, best_m = 0; + unsigned long _n, _k, _m; + + for (_k = nkm->min_k; _k <= nkm->max_k; _k++) { + for (_n = nkm->min_n; _n <= nkm->max_n; _n++) { + for (_m = nkm->min_m; _m <= nkm->max_m; _m++) { + unsigned long tmp_rate; + + tmp_parent = clk_hw_round_rate(parent_hw, rate * _m / (_n * _k)); + + tmp_rate = tmp_parent * _n * _k / _m; + + if (ccu_is_better_rate(common, rate, tmp_rate, best_rate) || + (tmp_parent == *parent && tmp_rate == best_rate)) { + best_rate = tmp_rate; + best_parent_rate = tmp_parent; + best_n = _n; + best_k = _k; + best_m = _m; + } + } + } + } + + nkm->n = best_n; + nkm->k = best_k; + nkm->m = best_m; + + *parent = best_parent_rate; + + return best_rate; +} + static unsigned long ccu_nkm_find_best(unsigned long parent, unsigned long rate, - struct _ccu_nkm *nkm) + struct _ccu_nkm *nkm, struct ccu_common *common) { unsigned long best_rate = 0; unsigned long best_n = 0, best_k = 0, best_m = 0; @@ -30,9 +69,7 @@ static unsigned long ccu_nkm_find_best(unsigned long parent, unsigned long rate, tmp_rate = parent * _n * _k / _m; - if (tmp_rate > rate) - continue; - if ((rate - tmp_rate) < (rate - best_rate)) { + if (ccu_is_better_rate(common, rate, tmp_rate, best_rate)) { best_rate = tmp_rate; best_n = _n; best_k = _k; @@ -106,7 +143,7 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw, } static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux, - struct clk_hw *hw, + struct clk_hw *parent_hw, unsigned long *parent_rate, unsigned long rate, void *data) @@ -124,7 +161,11 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux, if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV) rate *= nkm->fixed_post_div; - rate = ccu_nkm_find_best(*parent_rate, rate, &_nkm); + if (!clk_hw_can_set_rate_parent(&nkm->common.hw)) + rate = ccu_nkm_find_best(*parent_rate, rate, &_nkm, &nkm->common); + else + rate = ccu_nkm_find_best_with_parent_adj(&nkm->common, parent_hw, parent_rate, rate, + &_nkm); if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV) rate /= nkm->fixed_post_div; @@ -159,7 +200,7 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate, _nkm.min_m = 1; _nkm.max_m = nkm->m.max ?: 1 << nkm->m.width; - ccu_nkm_find_best(parent_rate, rate, &_nkm); + ccu_nkm_find_best(parent_rate, rate, &_nkm, &nkm->common); spin_lock_irqsave(nkm->common.lock, flags); diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c index c1fd11542c45..ffac3deb89d6 100644 --- a/drivers/clk/sunxi-ng/ccu_nm.c +++ b/drivers/clk/sunxi-ng/ccu_nm.c @@ -27,8 +27,8 @@ static unsigned long ccu_nm_calc_rate(unsigned long parent, return rate; } -static unsigned long ccu_nm_find_best(unsigned long parent, unsigned long rate, - struct _ccu_nm *nm) +static unsigned long ccu_nm_find_best(struct ccu_common *common, unsigned long parent, + unsigned long rate, struct _ccu_nm *nm) { unsigned long best_rate = 0; unsigned long best_n = 0, best_m = 0; @@ -39,10 +39,7 @@ static unsigned long ccu_nm_find_best(unsigned long parent, unsigned long rate, unsigned long tmp_rate = ccu_nm_calc_rate(parent, _n, _m); - if (tmp_rate > rate) - continue; - - if ((rate - tmp_rate) < (rate - best_rate)) { + if (ccu_is_better_rate(common, rate, tmp_rate, best_rate)) { best_rate = tmp_rate; best_n = _n; best_m = _m; @@ -159,7 +156,7 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate, _nm.min_m = 1; _nm.max_m = nm->m.max ?: 1 << nm->m.width; - rate = ccu_nm_find_best(*parent_rate, rate, &_nm); + rate = ccu_nm_find_best(&nm->common, *parent_rate, rate, &_nm); if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) rate /= nm->fixed_post_div; @@ -210,7 +207,7 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate, &_nm.m, &_nm.n); } else { ccu_sdm_helper_disable(&nm->common, &nm->sdm); - ccu_nm_find_best(parent_rate, rate, &_nm); + ccu_nm_find_best(&nm->common, parent_rate, rate, &_nm); } spin_lock_irqsave(nm->common.lock, flags); diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h index 2904e67f05a8..93c11693574f 100644 --- a/drivers/clk/sunxi-ng/ccu_nm.h +++ b/drivers/clk/sunxi-ng/ccu_nm.h @@ -108,7 +108,7 @@ struct ccu_nm { }, \ } -#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name, \ +#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT(_struct, _name, \ _parent, _reg, \ _min_rate, _max_rate, \ _nshift, _nwidth, \ @@ -116,7 +116,8 @@ struct ccu_nm { _frac_en, _frac_sel, \ _frac_rate_0, \ _frac_rate_1, \ - _gate, _lock, _flags) \ + _gate, _lock, _flags, \ + _features) \ struct ccu_nm _struct = { \ .enable = _gate, \ .lock = _lock, \ @@ -129,7 +130,7 @@ struct ccu_nm { .max_rate = _max_rate, \ .common = { \ .reg = _reg, \ - .features = CCU_FEATURE_FRACTIONAL, \ + .features = _features, \ .hw.init = CLK_HW_INIT(_name, \ _parent, \ &ccu_nm_ops, \ @@ -137,6 +138,47 @@ struct ccu_nm { }, \ } +#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name, \ + _parent, _reg, \ + _min_rate, _max_rate, \ + _nshift, _nwidth, \ + _mshift, _mwidth, \ + _frac_en, _frac_sel, \ + _frac_rate_0, \ + _frac_rate_1, \ + _gate, _lock, _flags) \ + SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT(_struct, _name, \ + _parent, _reg, \ + _min_rate, _max_rate, \ + _nshift, _nwidth, \ + _mshift, _mwidth, \ + _frac_en, _frac_sel, \ + _frac_rate_0, \ + _frac_rate_1, \ + _gate, _lock, _flags, \ + CCU_FEATURE_FRACTIONAL) + +#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(_struct, _name, \ + _parent, _reg, \ + _min_rate, _max_rate, \ + _nshift, _nwidth, \ + _mshift, _mwidth, \ + _frac_en, _frac_sel, \ + _frac_rate_0, \ + _frac_rate_1, \ + _gate, _lock, _flags) \ + SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT(_struct, _name, \ + _parent, _reg, \ + _min_rate, _max_rate, \ + _nshift, _nwidth, \ + _mshift, _mwidth, \ + _frac_en, _frac_sel, \ + _frac_rate_0, \ + _frac_rate_1, \ + _gate, _lock, _flags, \ + CCU_FEATURE_FRACTIONAL |\ + CCU_FEATURE_CLOSEST_RATE) + #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ _nshift, _nwidth, \ _mshift, _mwidth, \ diff --git a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c index e4cf1180b088..b0a93b4fb051 100644 --- a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c +++ b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c @@ -10,7 +10,6 @@ #include <linux/clk-provider.h> #include <linux/init.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #define SUN6I_APB0_GATES_MAX_SIZE 32 diff --git a/drivers/clk/sunxi/clk-sun9i-mmc.c b/drivers/clk/sunxi/clk-sun9i-mmc.c index 636bcf2439ef..91074017c04f 100644 --- a/drivers/clk/sunxi/clk-sun9i-mmc.c +++ b/drivers/clk/sunxi/clk-sun9i-mmc.c @@ -11,7 +11,6 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/reset.h> #include <linux/platform_device.h> #include <linux/reset-controller.h> @@ -108,15 +107,13 @@ static int sun9i_a80_mmc_config_clk_probe(struct platform_device *pdev) spin_lock_init(&data->lock); - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!r) - return -EINVAL; - /* one clock/reset pair per word */ - count = DIV_ROUND_UP((resource_size(r)), SUN9I_MMC_WIDTH); - data->membase = devm_ioremap_resource(&pdev->dev, r); + data->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r); if (IS_ERR(data->membase)) return PTR_ERR(data->membase); + /* one clock/reset pair per word */ + count = DIV_ROUND_UP((resource_size(r)), SUN9I_MMC_WIDTH); + clk_data = &data->clk_data; clk_data->clk_num = count; clk_data->clks = devm_kcalloc(&pdev->dev, count, sizeof(struct clk *), diff --git a/drivers/clk/tegra/clk-device.c b/drivers/clk/tegra/clk-device.c index c58beaf8afbc..8c8e2b853a99 100644 --- a/drivers/clk/tegra/clk-device.c +++ b/drivers/clk/tegra/clk-device.c @@ -2,8 +2,8 @@ #include <linux/clk.h> #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/mutex.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pm_domain.h> #include <linux/pm_opp.h> diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index 2a164e565c86..a9be4b56b2b7 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -12,7 +12,7 @@ #include <linux/err.h> #include <linux/kernel.h> #include <linux/init.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> #include <soc/tegra/fuse.h> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index dcacc5064d33..2c58ce25af75 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -9,7 +9,6 @@ #include <linux/init.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/clk/tegra.h> #include <linux/delay.h> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 60f1534711f1..82a8cb9545eb 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -10,7 +10,6 @@ #include <linux/init.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/clk/tegra.h> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index 26bda45813c0..19037346f522 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -9,12 +9,12 @@ #include <linux/delay.h> #include <linux/io.h> #include <linux/of.h> -#include <linux/of_device.h> +#include <linux/of_platform.h> #include <linux/clk/tegra.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/reset-controller.h> -#include <linux/string.h> +#include <linux/string_helpers.h> #include <soc/tegra/fuse.h> @@ -384,12 +384,10 @@ static struct device_node *tegra_clk_get_of_node(struct clk_hw *hw) struct device_node *np; char *node_name; - node_name = kstrdup(hw->init->name, GFP_KERNEL); + node_name = kstrdup_and_replace(hw->init->name, '_', '-', GFP_KERNEL); if (!node_name) return NULL; - strreplace(node_name, '_', '-'); - for_each_child_of_node(tegra_car_np, np) { if (!strcmp(np->name, node_name)) break; diff --git a/drivers/clk/ti/adpll.c b/drivers/clk/ti/adpll.c index 6ecbba4342c5..ff42ea75cb43 100644 --- a/drivers/clk/ti/adpll.c +++ b/drivers/clk/ti/adpll.c @@ -881,14 +881,10 @@ static int ti_adpll_probe(struct platform_device *pdev) dev_set_drvdata(d->dev, d); spin_lock_init(&d->lock); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -ENODEV; - d->pa = res->start; - - d->iobase = devm_ioremap_resource(dev, res); + d->iobase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(d->iobase)) return PTR_ERR(d->iobase); + d->pa = res->start; err = ti_adpll_init_registers(d); if (err) diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index 3d636938a739..1862958ab412 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -16,6 +16,7 @@ #include <linux/of_address.h> #include <linux/list.h> #include <linux/regmap.h> +#include <linux/string_helpers.h> #include <linux/memblock.h> #include <linux/device.h> @@ -123,10 +124,9 @@ static struct device_node *ti_find_clock_provider(struct device_node *from, const char *n; char *tmp; - tmp = kstrdup(name, GFP_KERNEL); + tmp = kstrdup_and_replace(name, '-', '_', GFP_KERNEL); if (!tmp) return NULL; - strreplace(tmp, '-', '_'); /* Node named "clock" with "clock-output-names" */ for_each_of_allnodes_from(from, np) { diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index 8c40f10280b7..607e34d8e289 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -13,6 +13,7 @@ #include <linux/of_address.h> #include <linux/clk/ti.h> #include <linux/delay.h> +#include <linux/string_helpers.h> #include <linux/timekeeping.h> #include "clock.h" @@ -473,11 +474,11 @@ static const char * __init clkctrl_get_name(struct device_node *np) const int prefix_len = 11; const char *compat; const char *output; + const char *end; char *name; if (!of_property_read_string_index(np, "clock-output-names", 0, &output)) { - const char *end; int len; len = strlen(output); @@ -491,13 +492,13 @@ static const char * __init clkctrl_get_name(struct device_node *np) of_property_for_each_string(np, "compatible", prop, compat) { if (!strncmp("ti,clkctrl-", compat, prefix_len)) { + end = compat + prefix_len; /* Two letter minimum name length for l3, l4 etc */ - if (strnlen(compat + prefix_len, 16) < 2) + if (strnlen(end, 16) < 2) continue; - name = kasprintf(GFP_KERNEL, "%s", compat + prefix_len); + name = kstrdup_and_replace(end, '-', '_', GFP_KERNEL); if (!name) continue; - strreplace(name, '-', '_'); return name; } diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index a61213311d6c..37b495e68107 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -8,7 +8,6 @@ #include <linux/init.h> #include <linux/mfd/syscon.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include "clk-uniphier.h" diff --git a/drivers/clk/xilinx/xlnx_vcu.c b/drivers/clk/xilinx/xlnx_vcu.c index 0786f15ebbe8..60a3ed7c7263 100644 --- a/drivers/clk/xilinx/xlnx_vcu.c +++ b/drivers/clk/xilinx/xlnx_vcu.c @@ -15,7 +15,7 @@ #include <linux/mfd/syscon.h> #include <linux/mfd/syscon/xlnx-vcu.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/regmap.h> diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c index 5636ff1ce552..a91d98e238c2 100644 --- a/drivers/clk/zynqmp/clkc.c +++ b/drivers/clk/zynqmp/clkc.c @@ -11,7 +11,8 @@ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/slab.h> #include <linux/string.h> |