diff options
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/mediatek/clk-pll.c | 5 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-pll.h | 1 |
2 files changed, 4 insertions, 2 deletions
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 513ab6b1b322..ce453e1718e5 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -23,7 +23,7 @@ #define CON0_BASE_EN BIT(0) #define CON0_PWR_ON BIT(0) #define CON0_ISO_EN BIT(1) -#define PCW_CHG_MASK BIT(31) +#define PCW_CHG_BIT 31 #define AUDPLL_TUNER_EN BIT(31) @@ -114,7 +114,8 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, pll->data->pcw_shift); val |= pcw << pll->data->pcw_shift; writel(val, pll->pcw_addr); - chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; + chg = readl(pll->pcw_chg_addr) | + BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT); writel(chg, pll->pcw_chg_addr); if (pll->tuner_addr) writel(val + 1, pll->tuner_addr); diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index f17278ff15d7..285c8db958b3 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -48,6 +48,7 @@ struct mtk_pll_data { const char *parent_name; u32 en_reg; u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ + u8 pcw_chg_bit; }; /* |