diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core/dc.c')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc.c | 127 |
1 files changed, 89 insertions, 38 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 45ad05f6e03b..58eb0d69873a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -70,6 +70,8 @@ #include "dce/dmub_hw_lock_mgr.h" +#include "dc_trace.h" + #define CTX \ dc->ctx @@ -147,6 +149,20 @@ static void destroy_links(struct dc *dc) } } +static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links) +{ + int i; + uint32_t count = 0; + + for (i = 0; i < num_links; i++) { + if (links[i]->connector_signal == SIGNAL_TYPE_EDP || + links[i]->is_internal_display) + count++; + } + + return count; +} + static bool create_links( struct dc *dc, uint32_t num_virtual_links) @@ -248,6 +264,8 @@ static bool create_links( virtual_link_encoder_construct(link->link_enc, &enc_init); } + dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count); + return true; failed_alloc: @@ -344,7 +362,7 @@ bool dc_stream_get_crtc_position(struct dc *dc, * calculate the crc. */ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, - bool enable, bool continuous) + struct crc_params *crc_window, bool enable, bool continuous) { int i; struct pipe_ctx *pipe; @@ -360,7 +378,7 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, if (i == MAX_PIPES) return false; - /* Always capture the full frame */ + /* By default, capture the full frame */ param.windowa_x_start = 0; param.windowa_y_start = 0; param.windowa_x_end = pipe->stream->timing.h_addressable; @@ -370,6 +388,17 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, param.windowb_x_end = pipe->stream->timing.h_addressable; param.windowb_y_end = pipe->stream->timing.v_addressable; + if (crc_window) { + param.windowa_x_start = crc_window->windowa_x_start; + param.windowa_y_start = crc_window->windowa_y_start; + param.windowa_x_end = crc_window->windowa_x_end; + param.windowa_y_end = crc_window->windowa_y_end; + param.windowb_x_start = crc_window->windowb_x_start; + param.windowb_y_start = crc_window->windowb_y_start; + param.windowb_x_end = crc_window->windowb_x_end; + param.windowb_y_end = crc_window->windowb_y_end; + } + param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0; param.odm_mode = pipe->next_odm_pipe ? 1:0; @@ -731,7 +760,7 @@ static bool dc_construct(struct dc *dc, dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); if (!dc->clk_mgr) goto fail; -#ifdef CONFIG_DRM_AMD_DC_DCN3_0 +#ifdef CONFIG_DRM_AMD_DC_DCN dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present; #endif @@ -763,7 +792,7 @@ fail: return false; } -static bool disable_all_writeback_pipes_for_stream( +static void disable_all_writeback_pipes_for_stream( const struct dc *dc, struct dc_stream_state *stream, struct dc_state *context) @@ -772,8 +801,6 @@ static bool disable_all_writeback_pipes_for_stream( for (i = 0; i < stream->num_wb_info; i++) stream->writeback_info[i].wb_enabled = false; - - return true; } void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context, struct dc_stream_state *stream, bool lock) @@ -861,12 +888,16 @@ static void disable_vbios_mode_if_required( if (stream == NULL) continue; + // only looking for first odm pipe + if (pipe->prev_odm_pipe) + continue; + if (stream->link->local_sink && stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { link = stream->link; } - if (link != NULL) { + if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) { unsigned int enc_inst, tg_inst = 0; unsigned int pix_clk_100hz; @@ -1266,16 +1297,19 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc, return false; } + if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) { + return false; + } + return true; } -bool dc_enable_stereo( +void dc_enable_stereo( struct dc *dc, struct dc_state *context, struct dc_stream_state *streams[], uint8_t stream_count) { - bool ret = true; int i, j; struct pipe_ctx *pipe; @@ -1290,8 +1324,6 @@ bool dc_enable_stereo( dc->hwss.setup_stereo(pipe, dc); } } - - return ret; } void dc_trigger_sync(struct dc *dc, struct dc_state *context) @@ -1327,7 +1359,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c int i, k, l; struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#if defined(CONFIG_DRM_AMD_DC_DCN) dc_allow_idle_optimizations(dc, false); #endif @@ -1434,6 +1466,11 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c dc->hwss.optimize_bandwidth(dc, context); } + if (dc->ctx->dce_version >= DCE_VERSION_MAX) + TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk); + else + TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); + context->stream_mask = get_stream_mask(dc, context); if (context->stream_mask != dc->current_state->stream_mask) @@ -1473,7 +1510,7 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context) return (result == DC_OK); } -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#if defined(CONFIG_DRM_AMD_DC_DCN) bool dc_acquire_release_mpc_3dlut( struct dc *dc, bool acquire, struct dc_stream_state *stream, @@ -1530,18 +1567,18 @@ static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context) return false; } -bool dc_post_update_surfaces_to_stream(struct dc *dc) +void dc_post_update_surfaces_to_stream(struct dc *dc) { int i; struct dc_state *context = dc->current_state; if ((!dc->optimized_required) || dc->optimize_seamless_boot_streams > 0) - return true; + return; post_surface_trace(dc); if (is_flip_pending_in_pipes(dc, context)) - return true; + return; for (i = 0; i < dc->res_pool->pipe_count; i++) if (context->res_ctx.pipe_ctx[i].stream == NULL || @@ -1554,8 +1591,6 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) dc->optimized_required = false; dc->wm_optimized_required = false; - - return true; } static void init_state(struct dc *dc, struct dc_state *context) @@ -1929,7 +1964,7 @@ static enum surface_update_type check_update_surfaces_for_stream( int i; enum surface_update_type overall_type = UPDATE_TYPE_FAST; -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#if defined(CONFIG_DRM_AMD_DC_DCN) if (dc->idle_optimizations_allowed) overall_type = UPDATE_TYPE_FULL; @@ -2383,7 +2418,6 @@ static void commit_planes_for_stream(struct dc *dc, enum surface_update_type update_type, struct dc_state *context) { - bool mpcc_disconnected = false; int i, j; struct pipe_ctx *top_pipe_to_program = NULL; @@ -2404,7 +2438,7 @@ static void commit_planes_for_stream(struct dc *dc, } if (update_type == UPDATE_TYPE_FULL) { -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#if defined(CONFIG_DRM_AMD_DC_DCN) dc_allow_idle_optimizations(dc, false); #endif @@ -2414,15 +2448,6 @@ static void commit_planes_for_stream(struct dc *dc, context_clock_trace(dc, context); } - if (update_type != UPDATE_TYPE_FAST && dc->hwss.interdependent_update_lock && - dc->hwss.disconnect_pipes && dc->hwss.wait_for_pending_cleared){ - dc->hwss.interdependent_update_lock(dc, context, true); - mpcc_disconnected = dc->hwss.disconnect_pipes(dc, context); - dc->hwss.interdependent_update_lock(dc, context, false); - if (mpcc_disconnected) - dc->hwss.wait_for_pending_cleared(dc, context); - } - for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; @@ -2461,7 +2486,6 @@ static void commit_planes_for_stream(struct dc *dc, */ dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true); - // Stream updates if (stream_update) commit_planes_do_stream_update(dc, stream, stream_update, update_type, context); @@ -2641,9 +2665,8 @@ static void commit_planes_for_stream(struct dc *dc, for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (pipe_ctx->bottom_pipe || - !pipe_ctx->stream || - pipe_ctx->stream != stream || + if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe || + !pipe_ctx->stream || pipe_ctx->stream != stream || !pipe_ctx->plane_state->update_flags.bits.addr_update) continue; @@ -2724,6 +2747,8 @@ void dc_commit_updates_for_stream(struct dc *dc, } } + TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES); + commit_planes_for_stream( dc, srf_updates, @@ -2748,9 +2773,15 @@ void dc_commit_updates_for_stream(struct dc *dc, } } /*let's use current_state to update watermark etc*/ - if (update_type >= UPDATE_TYPE_FULL) + if (update_type >= UPDATE_TYPE_FULL) { dc_post_update_surfaces_to_stream(dc); + if (dc_ctx->dce_version >= DCE_VERSION_MAX) + TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk); + else + TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); + } + return; } @@ -2767,6 +2798,19 @@ struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i) return NULL; } +struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link) +{ + uint8_t i; + struct dc_context *ctx = link->ctx; + + for (i = 0; i < ctx->dc->current_state->stream_count; i++) { + if (ctx->dc->current_state->streams[i]->link == link) + return ctx->dc->current_state->streams[i]; + } + + return NULL; +} + enum dc_irq_source dc_interrupt_to_irq_source( struct dc *dc, uint32_t src_id, @@ -3043,16 +3087,16 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable) if (link->psr_settings.psr_feature_enabled) { if (enable && !link->psr_settings.psr_allow_active) - return dc_link_set_psr_allow_active(link, true, false); + return dc_link_set_psr_allow_active(link, true, false, false); else if (!enable && link->psr_settings.psr_allow_active) - return dc_link_set_psr_allow_active(link, false, true); + return dc_link_set_psr_allow_active(link, false, true, false); } } return true; } -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#if defined(CONFIG_DRM_AMD_DC_DCN) void dc_allow_idle_optimizations(struct dc *dc, bool allow) { @@ -3104,4 +3148,11 @@ bool dc_is_plane_eligible_for_idle_optimizaitons(struct dc *dc, { return false; } + +/* cleanup on driver unload */ +void dc_hardware_release(struct dc *dc) +{ + if (dc->hwss.hardware_release) + dc->hwss.hardware_release(dc); +} #endif |