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path: root/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 2a8007928210..7c2e3b8dc26a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -402,6 +402,44 @@ void get_hdr_visual_confirm_color(
}
}
+void get_subvp_visual_confirm_color(
+ struct dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ struct tg_color *color)
+{
+ uint32_t color_value = MAX_TG_COLOR_VALUE;
+ bool enable_subvp = false;
+ int i;
+
+ if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx)
+ return;
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+
+ if (pipe->stream && pipe->stream->mall_stream_config.paired_stream &&
+ pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
+ /* SubVP enable - red */
+ color->color_r_cr = color_value;
+ enable_subvp = true;
+
+ if (pipe_ctx->stream == pipe->stream)
+ return;
+ break;
+ }
+ }
+
+ if (enable_subvp && pipe_ctx->stream->mall_stream_config.type == SUBVP_NONE) {
+ color->color_r_cr = 0;
+ if (pipe_ctx->stream->ignore_msa_timing_param == 1)
+ /* SubVP enable and DRR on - green */
+ color->color_g_y = color_value;
+ else
+ /* SubVP enable and No DRR - blue */
+ color->color_b_cb = color_value;
+ }
+}
+
void get_surface_tile_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
struct tg_color *color)