diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc.c | 140 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 59 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link.c | 43 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 42 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 268 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 24 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 79 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 67 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c | 3 |
9 files changed, 544 insertions, 181 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index d016f50e187c..ef0b5941bc50 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -68,6 +68,8 @@ #include "dmub/dmub_srv.h" +#include "dce/dmub_hw_lock_mgr.h" + #define CTX \ dc->ctx @@ -186,9 +188,10 @@ static bool create_links( bool should_destory_link = false; if (link->connector_signal == SIGNAL_TYPE_EDP) { - if (dc->config.edp_not_connected) - should_destory_link = true; - else if (dc->debug.remove_disconnect_edp) { + if (dc->config.edp_not_connected) { + if (!IS_DIAG_DC(dc->ctx->dce_environment)) + should_destory_link = true; + } else { enum dc_connection_type type; dc_link_detect_sink(link, &type); if (type == dc_connection_none) @@ -728,6 +731,9 @@ static bool dc_construct(struct dc *dc, dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); if (!dc->clk_mgr) goto fail; +#ifdef CONFIG_DRM_AMD_DC_DCN3_0 + dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present; +#endif if (dc->res_pool->funcs->update_bw_bounding_box) dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); @@ -1244,7 +1250,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c int i, k, l; struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; - disable_dangling_plane(dc, context); for (i = 0; i < context->stream_count; i++) dc_streams[i] = context->streams[i]; @@ -1260,6 +1265,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c if (dc->optimize_seamless_boot_streams == 0) dc->hwss.prepare_bandwidth(dc, context); + disable_dangling_plane(dc, context); /* re-program planes for existing stream, in case we need to * free up plane resource for later use */ @@ -1382,6 +1388,43 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context) return (result == DC_OK); } +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +bool dc_acquire_release_mpc_3dlut( + struct dc *dc, bool acquire, + struct dc_stream_state *stream, + struct dc_3dlut **lut, + struct dc_transfer_func **shaper) +{ + int pipe_idx; + bool ret = false; + bool found_pipe_idx = false; + const struct resource_pool *pool = dc->res_pool; + struct resource_context *res_ctx = &dc->current_state->res_ctx; + int mpcc_id = 0; + + if (pool && res_ctx) { + if (acquire) { + /*find pipe idx for the given stream*/ + for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) { + if (res_ctx->pipe_ctx[pipe_idx].stream == stream) { + found_pipe_idx = true; + mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst; + break; + } + } + } else + found_pipe_idx = true;/*for release pipe_idx is not required*/ + + if (found_pipe_idx) { + if (acquire && pool->funcs->acquire_post_bldn_3dlut) + ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper); + else if (acquire == false && pool->funcs->release_post_bldn_3dlut) + ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper); + } + } + return ret; +} +#endif static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context) { int i; @@ -2280,9 +2323,22 @@ static void commit_planes_for_stream(struct dc *dc, } if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) - if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) - top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable( - top_pipe_to_program->stream_res.tg); + if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) { + if (should_use_dmub_lock(stream->link)) { + union dmub_hw_lock_flags hw_locks = { 0 }; + struct dmub_hw_lock_inst_flags inst_flags = { 0 }; + + hw_locks.bits.lock_dig = 1; + inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst; + + dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, + true, + &hw_locks, + &inst_flags); + } else + top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable( + top_pipe_to_program->stream_res.tg); + } if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock) dc->hwss.interdependent_update_lock(dc, context, true); @@ -2452,7 +2508,20 @@ static void commit_planes_for_stream(struct dc *dc, top_pipe_to_program->stream_res.tg->funcs->wait_for_state( top_pipe_to_program->stream_res.tg, CRTC_STATE_VACTIVE); - top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable( + + if (stream && should_use_dmub_lock(stream->link)) { + union dmub_hw_lock_flags hw_locks = { 0 }; + struct dmub_hw_lock_inst_flags inst_flags = { 0 }; + + hw_locks.bits.lock_dig = 1; + inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst; + + dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, + false, + &hw_locks, + &inst_flags); + } else + top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable( top_pipe_to_program->stream_res.tg); } @@ -2614,6 +2683,13 @@ void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src) dal_irq_service_ack(dc->res_pool->irqs, src); } +void dc_power_down_on_boot(struct dc *dc) +{ + if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW && + dc->hwss.power_down_on_boot) + dc->hwss.power_down_on_boot(dc); +} + void dc_set_power_state( struct dc *dc, enum dc_acpi_cm_power_state power_state) @@ -2842,3 +2918,51 @@ void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_ if (dc->hwss.get_clock) dc->hwss.get_clock(dc, clock_type, clock_cfg); } + +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + +void dc_allow_idle_optimizations(struct dc *dc, bool allow) +{ + if (dc->debug.disable_idle_power_optimizations) + return; + + if (allow == dc->idle_optimizations_allowed) + return; + + if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow)) + dc->idle_optimizations_allowed = allow; +} + +/* + * blank all streams, and set min and max memory clock to + * lowest and highest DPM level, respectively + */ +void dc_unlock_memory_clock_frequency(struct dc *dc) +{ + unsigned int i; + + for (i = 0; i < MAX_PIPES; i++) + if (dc->current_state->res_ctx.pipe_ctx[i].plane_state) + core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]); + + dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false); + dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); +} + +/* + * set min memory clock to the min required for current mode, + * max to maxDPM, and unblank streams + */ +void dc_lock_memory_clock_frequency(struct dc *dc) +{ + unsigned int i; + + dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr); + dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true); + dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); + + for (i = 0; i < MAX_PIPES; i++) + if (dc->current_state->res_ctx.pipe_ctx[i].plane_state) + core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]); +} +#endif diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 502ed3c7959d..87d89449b9af 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -365,3 +365,62 @@ void context_clock_trace( context->bw_ctx.bw.dcn.clk.socclk_khz); #endif } + +/** + * dc_status_to_str - convert dc_status to a human readable string + * @status: dc_status to be converted + * + * Return: + * A string describing the DC status. + */ +char *dc_status_to_str(enum dc_status status) +{ + switch (status) { + case DC_OK: + return "DC OK"; + case DC_NO_CONTROLLER_RESOURCE: + return "No controller resource"; + case DC_NO_STREAM_ENC_RESOURCE: + return "No stream encoder"; + case DC_NO_CLOCK_SOURCE_RESOURCE: + return "No clock source"; + case DC_FAIL_CONTROLLER_VALIDATE: + return "Controller validation failure"; + case DC_FAIL_ENC_VALIDATE: + return "Encoder validation failure"; + case DC_FAIL_ATTACH_SURFACES: + return "Surfaces attachment failure"; + case DC_FAIL_DETACH_SURFACES: + return "Surfaces detachment failure"; + case DC_FAIL_SURFACE_VALIDATE: + return "Surface validation failure"; + case DC_NO_DP_LINK_BANDWIDTH: + return "No DP link bandwidth"; + case DC_EXCEED_DONGLE_CAP: + return "Exceed dongle capability"; + case DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED: + return "Unsupported pixel format"; + case DC_FAIL_BANDWIDTH_VALIDATE: + return "Bandwidth validation failure (BW and Watermark)"; + case DC_FAIL_SCALING: + return "Scaling failure"; + case DC_FAIL_DP_LINK_TRAINING: + return "DP link training failure"; + case DC_FAIL_DSC_VALIDATE: + return "DSC validation failure"; + case DC_NO_DSC_RESOURCE: + return "No DSC resource"; + case DC_FAIL_UNSUPPORTED_1: + return "Unsupported"; + case DC_FAIL_CLK_EXCEED_MAX: + return "Clk exceed max failure"; + case DC_FAIL_CLK_BELOW_MIN: + return "Fail clk below minimum"; + case DC_FAIL_CLK_BELOW_CFG_REQUIRED: + return "Fail clk below required CFG (hard_min in PPLIB)"; + case DC_ERROR_UNEXPECTED: + return "Unexpected error"; + } + + return "Unexpected status error"; +} diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 48ab51533d5d..02742cca4d84 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -521,11 +521,11 @@ static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *lin } #if defined(CONFIG_DRM_AMD_DC_HDCP) -bool dc_link_is_hdcp14(struct dc_link *link) +bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal) { bool ret = false; - switch (link->connector_signal) { + switch (signal) { case SIGNAL_TYPE_DISPLAY_PORT: case SIGNAL_TYPE_DISPLAY_PORT_MST: ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE; @@ -545,11 +545,11 @@ bool dc_link_is_hdcp14(struct dc_link *link) return ret; } -bool dc_link_is_hdcp22(struct dc_link *link) +bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal) { bool ret = false; - switch (link->connector_signal) { + switch (signal) { case SIGNAL_TYPE_DISPLAY_PORT: case SIGNAL_TYPE_DISPLAY_PORT_MST: ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE && @@ -690,12 +690,8 @@ static bool detect_dp(struct dc_link *link, if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) { sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT; - - dpcd_set_source_specific_data(link); - if (!detect_dp_sink_caps(link)) return false; - if (is_mst_supported(link)) { sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST; link->type = dc_connection_mst_branch; @@ -858,6 +854,7 @@ static bool dc_link_detect_helper(struct dc_link *link, bool same_dpcd = true; enum dc_connection_type new_connection_type = dc_connection_none; bool perform_dp_seamless_boot = false; + const uint32_t post_oui_delay = 30; // 30ms DC_LOGGER_INIT(link->ctx->logger); @@ -870,6 +867,7 @@ static bool dc_link_detect_helper(struct dc_link *link, // need to re-write OUI and brightness in resume case if (link->connector_signal == SIGNAL_TYPE_EDP) { dpcd_set_source_specific_data(link); + msleep(post_oui_delay); dc_link_set_default_brightness_aux(link); //TODO: use cached } @@ -925,8 +923,6 @@ static bool dc_link_detect_helper(struct dc_link *link, case SIGNAL_TYPE_EDP: { read_current_link_settings_on_detect(link); - dpcd_set_source_specific_data(link); - detect_edp_sink_caps(link); read_current_link_settings_on_detect(link); sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; @@ -1636,6 +1632,7 @@ static enum dc_status enable_link_dp(struct dc_state *state, int i; bool apply_seamless_boot_optimization = false; uint32_t bl_oled_enable_delay = 50; // in ms + const uint32_t post_oui_delay = 30; // 30ms // check for seamless boot for (i = 0; i < state->stream_count; i++) { @@ -1662,6 +1659,8 @@ static enum dc_status enable_link_dp(struct dc_state *state, // during mode switch we do DP_SET_POWER off then on, and OUI is lost dpcd_set_source_specific_data(link); + if (link->dpcd_sink_ext_caps.raw != 0) + msleep(post_oui_delay); skip_video_pattern = true; @@ -2560,12 +2559,14 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool struct dmcu *dmcu = dc->res_pool->dmcu; struct dmub_psr *psr = dc->res_pool->psr; + link->psr_settings.psr_allow_active = allow_active; + if (psr != NULL && link->psr_settings.psr_feature_enabled) psr->funcs->psr_enable(psr, allow_active); else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled) dmcu->funcs->set_psr_enable(dmcu, allow_active, wait); - - link->psr_settings.psr_allow_active = allow_active; + else + return false; return true; } @@ -3134,6 +3135,11 @@ void core_link_enable_stream( pipe_ctx->stream->link->link_state_valid = true; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + if (pipe_ctx->stream_res.tg->funcs->set_out_mux) + pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); +#endif + if (dc_is_dvi_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute( pipe_ctx->stream_res.stream_enc, @@ -3216,6 +3222,15 @@ void core_link_enable_stream( CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, COLOR_DEPTH_UNDEFINED); + /* This second call is needed to reconfigure the DIG + * as a workaround for the incorrect value being applied + * from transmitter control. + */ + if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) + stream->link->link_enc->funcs->setup( + stream->link->link_enc, + pipe_ctx->stream->signal); + dc->hwss.enable_stream(pipe_ctx); /* Set DPS PPS SDP (AKA "info frames") */ @@ -3298,9 +3313,11 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx) write_i2c_redriver_setting(pipe_ctx, false); } } - dc->hwss.disable_stream(pipe_ctx); disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal); + + dc->hwss.disable_stream(pipe_ctx); + if (pipe_ctx->stream->timing.flags.DSC) { if (dc_is_dp_signal(pipe_ctx->stream->signal)) dp_set_dsc_enable(pipe_ctx, false); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c index aefd29a440b5..b984eecca58b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c @@ -503,7 +503,7 @@ bool dal_ddc_service_query_ddc_data( uint8_t *read_buf, uint32_t read_size) { - bool ret = false; + bool success = true; uint32_t payload_size = dal_ddc_service_is_in_aux_transaction_mode(ddc) ? DEFAULT_AUX_MAX_DATA_SIZE : EDID_SEGMENT_SIZE; @@ -527,7 +527,6 @@ bool dal_ddc_service_query_ddc_data( * but we want to read 256 over i2c!!!!*/ if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) { struct aux_payload payload; - bool read_available = true; payload.i2c_over_aux = true; payload.address = address; @@ -536,21 +535,26 @@ bool dal_ddc_service_query_ddc_data( if (write_size != 0) { payload.write = true; - payload.mot = false; + /* should not set mot (middle of transaction) to 0 + * if there are pending read payloads + */ + payload.mot = read_size == 0 ? false : true; payload.length = write_size; payload.data = write_buf; - ret = dal_ddc_submit_aux_command(ddc, &payload); - read_available = ret; + success = dal_ddc_submit_aux_command(ddc, &payload); } - if (read_size != 0 && read_available) { + if (read_size != 0 && success) { payload.write = false; + /* should set mot (middle of transaction) to 0 + * since it is the last payload to send + */ payload.mot = false; payload.length = read_size; payload.data = read_buf; - ret = dal_ddc_submit_aux_command(ddc, &payload); + success = dal_ddc_submit_aux_command(ddc, &payload); } } else { struct i2c_command command = {0}; @@ -573,7 +577,7 @@ bool dal_ddc_service_query_ddc_data( command.number_of_payloads = dal_ddc_i2c_payloads_get_count(&payloads); - ret = dm_helpers_submit_i2c( + success = dm_helpers_submit_i2c( ddc->ctx, ddc->link, &command); @@ -581,7 +585,7 @@ bool dal_ddc_service_query_ddc_data( dal_ddc_i2c_payloads_destroy(&payloads); } - return ret; + return success; } bool dal_ddc_submit_aux_command(struct ddc_service *ddc, @@ -598,7 +602,7 @@ bool dal_ddc_submit_aux_command(struct ddc_service *ddc, do { struct aux_payload current_payload; - bool is_end_of_payload = (retrieved + DEFAULT_AUX_MAX_DATA_SIZE) > + bool is_end_of_payload = (retrieved + DEFAULT_AUX_MAX_DATA_SIZE) >= payload->length; current_payload.address = payload->address; @@ -607,7 +611,10 @@ bool dal_ddc_submit_aux_command(struct ddc_service *ddc, current_payload.i2c_over_aux = payload->i2c_over_aux; current_payload.length = is_end_of_payload ? payload->length - retrieved : DEFAULT_AUX_MAX_DATA_SIZE; - current_payload.mot = !is_end_of_payload; + /* set mot (middle of transaction) to false + * if it is the last payload + */ + current_payload.mot = is_end_of_payload ? payload->mot:true; current_payload.reply = payload->reply; current_payload.write = payload->write; @@ -648,16 +655,17 @@ bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc, } -uint32_t dc_link_aux_configure_timeout(struct ddc_service *ddc, +bool dc_link_aux_try_to_configure_timeout(struct ddc_service *ddc, uint32_t timeout) { - uint32_t prev_timeout = 0; + bool result = false; struct ddc *ddc_pin = ddc->ddc_pin; - if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) - prev_timeout = - ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout); - return prev_timeout; + if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) { + ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout); + result = true; + } + return result; } /*test only function*/ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 91cd884d6f25..5cb7b834e459 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -12,6 +12,8 @@ #include "dc_link_ddc.h" #include "core_status.h" #include "dpcd_defs.h" +#include "dc_dmub_srv.h" +#include "dce/dmub_hw_lock_mgr.h" #define DC_LOGGER \ link->ctx->logger @@ -245,7 +247,7 @@ static uint8_t dc_dp_initialize_scrambling_data_symbols( static inline bool is_repeater(struct dc_link *link, uint32_t offset) { - return (!link->is_lttpr_mode_transparent && offset != 0); + return (link->lttpr_non_transparent_mode && offset != 0); } static void dpcd_set_lt_pattern_and_lane_settings( @@ -1038,7 +1040,7 @@ static enum link_training_result perform_clock_recovery_sequence( /* 3. wait receiver to lock-on*/ wait_time_microsec = lt_settings->cr_pattern_time; - if (!link->is_lttpr_mode_transparent) + if (link->lttpr_non_transparent_mode) wait_time_microsec = TRAINING_AUX_RD_INTERVAL; wait_for_training_aux_rd_interval( @@ -1268,7 +1270,7 @@ static void configure_lttpr_mode(struct dc_link *link) link->dpcd_caps.lttpr_caps.mode = repeater_mode; } - if (!link->is_lttpr_mode_transparent) { + if (link->lttpr_non_transparent_mode) { DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__); @@ -1473,7 +1475,7 @@ enum link_training_result dc_link_dp_perform_link_training( <_settings); /* Configure lttpr mode */ - if (!link->is_lttpr_mode_transparent) + if (link->lttpr_non_transparent_mode) configure_lttpr_mode(link); if (link->ctx->dc->work_arounds.lt_early_cr_pattern) @@ -1489,7 +1491,7 @@ enum link_training_result dc_link_dp_perform_link_training( dp_set_fec_ready(link, fec_enable); - if (!link->is_lttpr_mode_transparent) { + if (link->lttpr_non_transparent_mode) { /* 2. perform link training (set link training done * to false is done as well) @@ -1551,6 +1553,12 @@ bool perform_link_training_with_retries( struct dc_link *link = stream->link; enum dp_panel_mode panel_mode = dp_get_panel_mode(link); + /* We need to do this before the link training to ensure the idle pattern in SST + * mode will be sent right after the link training + */ + link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, + pipe_ctx->stream_res.stream_enc->id, true); + for (j = 0; j < attempts; ++j) { dp_enable_link_phy( @@ -1567,12 +1575,6 @@ bool perform_link_training_with_retries( dp_set_panel_mode(link, panel_mode); - /* We need to do this before the link training to ensure the idle pattern in SST - * mode will be sent right after the link training - */ - link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, - pipe_ctx->stream_res.stream_enc->id, true); - if (link->aux_access_disabled) { dc_link_dp_perform_link_training_skip_aux(link, link_setting); return true; @@ -1756,7 +1758,7 @@ static struct dc_link_settings get_max_link_cap(struct dc_link *link) * account for lttpr repeaters cap * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3). */ - if (!link->is_lttpr_mode_transparent) { + if (link->lttpr_non_transparent_mode) { if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count) max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count; @@ -1914,7 +1916,7 @@ bool dp_verify_link_cap( max_link_cap = get_max_link_cap(link); /* Grant extended timeout request */ - if (!link->is_lttpr_mode_transparent && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) { + if (link->lttpr_non_transparent_mode && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) { uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80; core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant)); @@ -2849,7 +2851,6 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd enum dc_status result; bool status = false; struct pipe_ctx *pipe_ctx; - struct dc_link_settings previous_link_settings; int i; if (out_link_loss) @@ -2928,32 +2929,25 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd for (i = 0; i < MAX_PIPES; i++) { pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link) - link->dc->hwss.blank_stream(pipe_ctx); - } - - for (i = 0; i < MAX_PIPES; i++) { - pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; - if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link) break; } if (pipe_ctx == NULL || pipe_ctx->stream == NULL) return false; - previous_link_settings = link->cur_link_settings; - - perform_link_training_with_retries(&previous_link_settings, - true, LINK_TRAINING_ATTEMPTS, - pipe_ctx, - pipe_ctx->stream->signal); - if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) - dc_link_reallocate_mst_payload(link); + for (i = 0; i < MAX_PIPES; i++) { + pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; + if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off && + pipe_ctx->stream->link == link) + core_link_disable_stream(pipe_ctx); + } for (i = 0; i < MAX_PIPES; i++) { pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; - if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link) - link->dc->hwss.unblank_stream(pipe_ctx, &previous_link_settings); + if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off && + pipe_ctx->stream->link == link) + core_link_enable_stream(link->dc->current_state, pipe_ctx); } status = false; @@ -3099,62 +3093,63 @@ static void get_active_converter_info( uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/ union dwnstream_port_caps_byte0 *port_caps = (union dwnstream_port_caps_byte0 *)det_caps; - core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0, - det_caps, sizeof(det_caps)); + if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0, + det_caps, sizeof(det_caps)) == DC_OK) { - switch (port_caps->bits.DWN_STRM_PORTX_TYPE) { - /*Handle DP case as DONGLE_NONE*/ - case DOWN_STREAM_DETAILED_DP: - link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; - break; - case DOWN_STREAM_DETAILED_VGA: - link->dpcd_caps.dongle_type = - DISPLAY_DONGLE_DP_VGA_CONVERTER; - break; - case DOWN_STREAM_DETAILED_DVI: - link->dpcd_caps.dongle_type = - DISPLAY_DONGLE_DP_DVI_CONVERTER; - break; - case DOWN_STREAM_DETAILED_HDMI: - case DOWN_STREAM_DETAILED_DP_PLUS_PLUS: - /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/ - link->dpcd_caps.dongle_type = - DISPLAY_DONGLE_DP_HDMI_CONVERTER; - - link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type; - if (ds_port.fields.DETAILED_CAPS) { - - union dwnstream_port_caps_byte3_hdmi - hdmi_caps = {.raw = det_caps[3] }; - union dwnstream_port_caps_byte2 - hdmi_color_caps = {.raw = det_caps[2] }; - link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz = - det_caps[1] * 2500; - - link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter = - hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK; - /*YCBCR capability only for HDMI case*/ - if (port_caps->bits.DWN_STRM_PORTX_TYPE - == DOWN_STREAM_DETAILED_HDMI) { - link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through = - hdmi_caps.bits.YCrCr422_PASS_THROUGH; - link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through = - hdmi_caps.bits.YCrCr420_PASS_THROUGH; - link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter = - hdmi_caps.bits.YCrCr422_CONVERSION; - link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter = - hdmi_caps.bits.YCrCr420_CONVERSION; + switch (port_caps->bits.DWN_STRM_PORTX_TYPE) { + /*Handle DP case as DONGLE_NONE*/ + case DOWN_STREAM_DETAILED_DP: + link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; + break; + case DOWN_STREAM_DETAILED_VGA: + link->dpcd_caps.dongle_type = + DISPLAY_DONGLE_DP_VGA_CONVERTER; + break; + case DOWN_STREAM_DETAILED_DVI: + link->dpcd_caps.dongle_type = + DISPLAY_DONGLE_DP_DVI_CONVERTER; + break; + case DOWN_STREAM_DETAILED_HDMI: + case DOWN_STREAM_DETAILED_DP_PLUS_PLUS: + /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/ + link->dpcd_caps.dongle_type = + DISPLAY_DONGLE_DP_HDMI_CONVERTER; + + link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type; + if (ds_port.fields.DETAILED_CAPS) { + + union dwnstream_port_caps_byte3_hdmi + hdmi_caps = {.raw = det_caps[3] }; + union dwnstream_port_caps_byte2 + hdmi_color_caps = {.raw = det_caps[2] }; + link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz = + det_caps[1] * 2500; + + link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter = + hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK; + /*YCBCR capability only for HDMI case*/ + if (port_caps->bits.DWN_STRM_PORTX_TYPE + == DOWN_STREAM_DETAILED_HDMI) { + link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through = + hdmi_caps.bits.YCrCr422_PASS_THROUGH; + link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through = + hdmi_caps.bits.YCrCr420_PASS_THROUGH; + link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter = + hdmi_caps.bits.YCrCr422_CONVERSION; + link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter = + hdmi_caps.bits.YCrCr420_CONVERSION; + } + + link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc = + translate_dpcd_max_bpc( + hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); + + if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0) + link->dpcd_caps.dongle_caps.extendedCapValid = true; } - link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc = - translate_dpcd_max_bpc( - hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); - - if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0) - link->dpcd_caps.dongle_caps.extendedCapValid = true; + break; } - - break; } } @@ -3255,17 +3250,8 @@ static bool retrieve_link_cap(struct dc_link *link) uint32_t read_dpcd_retry_cnt = 3; int i; struct dp_sink_hw_fw_revision dp_hw_fw_revision; - - /* Set default timeout to 3.2ms and read LTTPR capabilities */ - bool ext_timeout_support = link->dc->caps.extended_aux_timeout_support && - !link->dc->config.disable_extended_timeout_support; - - link->is_lttpr_mode_transparent = true; - - if (ext_timeout_support) { - dc_link_aux_configure_timeout(link->ddc, - LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD); - } + bool is_lttpr_present = false; + const uint32_t post_oui_delay = 30; // 30ms memset(dpcd_data, '\0', sizeof(dpcd_data)); memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data)); @@ -3274,6 +3260,13 @@ static bool retrieve_link_cap(struct dc_link *link) memset(&edp_config_cap, '\0', sizeof(union edp_configuration_cap)); + /* if extended timeout is supported in hardware, + * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer + * CTS 4.2.1.1 regression introduced by CTS specs requirement update. + */ + dc_link_aux_try_to_configure_timeout(link->ddc, + LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); + status = core_link_read_dpcd(link, DP_SET_POWER, &dpcd_power_state, sizeof(dpcd_power_state)); @@ -3285,6 +3278,12 @@ static bool retrieve_link_cap(struct dc_link *link) if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) udelay(1000); + dpcd_set_source_specific_data(link); + /* Sink may need to configure internals based on vendor, so allow some + * time before proceeding with possibly vendor specific transactions + */ + msleep(post_oui_delay); + for (i = 0; i < read_dpcd_retry_cnt; i++) { status = core_link_read_dpcd( link, @@ -3300,8 +3299,14 @@ static bool retrieve_link_cap(struct dc_link *link) return false; } - if (ext_timeout_support) { - + if (link->dc->caps.extended_aux_timeout_support && + link->dc->config.allow_lttpr_non_transparent_mode) { + /* By reading LTTPR capability, RX assumes that we will enable + * LTTPR non transparent if LTTPR is present. + * Therefore, only query LTTPR capability when both LTTPR + * extended aux timeout and + * non transparent mode is supported by hardware + */ status = core_link_read_dpcd( link, DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, @@ -3332,20 +3337,21 @@ static bool retrieve_link_cap(struct dc_link *link) lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; - if (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 && + is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 && link->dpcd_caps.lttpr_caps.max_lane_count > 0 && link->dpcd_caps.lttpr_caps.max_lane_count <= 4 && - link->dpcd_caps.lttpr_caps.revision.raw >= 0x14) { - link->is_lttpr_mode_transparent = false; - } else { - /*No lttpr reset timeout to its default value*/ - link->is_lttpr_mode_transparent = true; - dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); - } - - CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: "); + link->dpcd_caps.lttpr_caps.revision.raw >= 0x14); + if (is_lttpr_present) + CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: "); } + /* decide lttpr non transparent mode */ + link->lttpr_non_transparent_mode = is_lttpr_present; + + if (!is_lttpr_present) + dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); + + { union training_aux_rd_interval aux_rd_interval; @@ -3378,7 +3384,7 @@ static bool retrieve_link_cap(struct dc_link *link) link->dpcd_caps.dpcd_rev.raw = dpcd_data[DP_DPCD_REV - DP_DPCD_REV]; - if (link->dpcd_caps.dpcd_rev.raw >= 0x14) { + if (link->dpcd_caps.ext_receiver_cap_field_present) { for (i = 0; i < read_dpcd_retry_cnt; i++) { status = core_link_read_dpcd( link, @@ -3513,8 +3519,8 @@ static bool retrieve_link_cap(struct dc_link *link) status = core_link_read_dpcd( link, DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, - link->dpcd_caps.dsc_caps.dsc_ext_caps.raw, - sizeof(link->dpcd_caps.dsc_caps.dsc_ext_caps.raw)); + link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, + sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw)); } if (!dpcd_read_sink_ext_caps(link)) @@ -4034,9 +4040,23 @@ bool dc_link_dp_set_test_pattern( break; } - if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) - pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable( - pipe_ctx->stream_res.tg); + if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) { + if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) { + union dmub_hw_lock_flags hw_locks = { 0 }; + struct dmub_hw_lock_inst_flags inst_flags = { 0 }; + + hw_locks.bits.lock_dig = 1; + inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst; + + dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv, + true, + &hw_locks, + &inst_flags); + } else + pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable( + pipe_ctx->stream_res.tg); + } + pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); /* update MSA to requested color space */ pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc, @@ -4063,9 +4083,24 @@ bool dc_link_dp_set_test_pattern( CRTC_STATE_VBLANK); pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); - if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) - pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable( - pipe_ctx->stream_res.tg); + + if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) { + if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) { + union dmub_hw_lock_flags hw_locks = { 0 }; + struct dmub_hw_lock_inst_flags inst_flags = { 0 }; + + hw_locks.bits.lock_dig = 1; + inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst; + + dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv, + false, + &hw_locks, + &inst_flags); + } else + pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable( + pipe_ctx->stream_res.tg); + } + /* Set Test Pattern state */ link->test_pattern_enabled = true; } @@ -4255,7 +4290,6 @@ void dp_set_fec_enable(struct dc_link *link, bool enable) void dpcd_set_source_specific_data(struct dc_link *link) { - const uint32_t post_oui_delay = 30; // 30ms uint8_t dspc = 0; enum dc_status ret; @@ -4296,10 +4330,6 @@ void dpcd_set_source_specific_data(struct dc_link *link) link->dc->vendor_signature.data.raw, sizeof(link->dc->vendor_signature.data.raw)); } - - // Sink may need to configure internals based on vendor, so allow some - // time before proceeding with possibly vendor specific transactions - msleep(post_oui_delay); } bool dc_link_set_backlight_level_nits(struct dc_link *link, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 6590f51caefa..dd88eb348dfa 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -14,6 +14,7 @@ #include "dpcd_defs.h" #include "dsc.h" #include "resource.h" +#include "clk_mgr.h" static uint8_t convert_to_count(uint8_t lttpr_repeater_count) { @@ -123,6 +124,11 @@ void dp_enable_link_phy( } } + link->cur_link_settings = *link_settings; + + if (dc->clk_mgr->funcs->notify_link_rate_change) + dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link); + if (dmcu != NULL && dmcu->funcs->lock_phy) dmcu->funcs->lock_phy(dmcu); @@ -141,8 +147,6 @@ void dp_enable_link_phy( if (dmcu != NULL && dmcu->funcs->unlock_phy) dmcu->funcs->unlock_phy(dmcu); - link->cur_link_settings = *link_settings; - dp_receiver_power_ctrl(link, true); } @@ -151,7 +155,8 @@ bool edp_receiver_ready_T9(struct dc_link *link) unsigned int tries = 0; unsigned char sinkstatus = 0; unsigned char edpRev = 0; - enum dc_status result = DC_OK; + enum dc_status result; + result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev)); /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/ @@ -167,7 +172,8 @@ bool edp_receiver_ready_T9(struct dc_link *link) } while (++tries < 50); } - if (link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0) + if (link->local_sink && + link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0) udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off * 1000); return result; @@ -176,7 +182,7 @@ bool edp_receiver_ready_T7(struct dc_link *link) { unsigned char sinkstatus = 0; unsigned char edpRev = 0; - enum dc_status result = DC_OK; + enum dc_status result; /* use absolute time stamp to constrain max T7*/ unsigned long long enter_timestamp = 0; @@ -201,7 +207,8 @@ bool edp_receiver_ready_T7(struct dc_link *link) } while (time_taken_in_ns < 50 * 1000000); //MAx T7 is 50ms } - if (link->local_sink->edid_caps.panel_patch.extra_t7_ms > 0) + if (link->local_sink && + link->local_sink->edid_caps.panel_patch.extra_t7_ms > 0) udelay(link->local_sink->edid_caps.panel_patch.extra_t7_ms * 1000); return result; @@ -231,6 +238,9 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal) /* Clear current link setting.*/ memset(&link->cur_link_settings, 0, sizeof(link->cur_link_settings)); + + if (dc->clk_mgr->funcs->notify_link_rate_change) + dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link); } void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal) @@ -281,7 +291,7 @@ void dp_set_hw_lane_settings( { struct link_encoder *encoder = link->link_enc; - if (!link->is_lttpr_mode_transparent && !is_immediate_downstream(link, offset)) + if (link->lttpr_non_transparent_mode && !is_immediate_downstream(link, offset)) return; /* call Encoder to set lane settings */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 0c5619364e7d..7b5f90ebb133 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -52,6 +52,9 @@ #include "dcn20/dcn20_resource.h" #include "dcn21/dcn21_resource.h" #endif +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#include "../dcn30/dcn30_resource.h" +#endif #define DC_LOGGER_INIT(logger) @@ -107,6 +110,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) case FAMILY_NV: dc_version = DCN_VERSION_2_0; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) + dc_version = DCN_VERSION_3_0; +#endif break; default: dc_version = DCE_VERSION_UNKNOWN; @@ -168,6 +175,11 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, res_pool = dcn21_create_resource_pool(init_data, dc); break; #endif +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + case DCN_VERSION_3_0: + res_pool = dcn30_create_resource_pool(init_data, dc); + break; +#endif default: break; @@ -282,6 +294,16 @@ bool resource_construct( } } +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + for (i = 0; i < caps->num_mpc_3dlut; i++) { + pool->mpc_lut[i] = dc_create_3dlut_func(); + if (pool->mpc_lut[i] == NULL) + DC_ERR("DC: failed to create MPC 3dlut!\n"); + pool->mpc_shaper[i] = dc_create_transfer_func(); + if (pool->mpc_shaper[i] == NULL) + DC_ERR("DC: failed to create MPC shaper!\n"); + } +#endif dc->caps.dynamic_audio = false; if (pool->audio_count < pool->stream_enc_count) { dc->caps.dynamic_audio = true; @@ -377,6 +399,10 @@ bool resource_are_streams_timing_synchronizable( != stream2->timing.v_addressable) return false; + if (stream1->timing.v_front_porch + != stream2->timing.v_front_porch) + return false; + if (stream1->timing.pix_clk_100hz != stream2->timing.pix_clk_100hz) return false; @@ -1136,19 +1162,32 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) /* May need to re-check lb size after this in some obscure scenario */ calculate_inits_and_adj_vp(pipe_ctx); - DC_LOG_SCALER( - "%s: Viewport:\nheight:%d width:%d x:%d " - "y:%d\n dst_rect:\nheight:%d width:%d x:%d " - "y:%d\n", - __func__, - pipe_ctx->plane_res.scl_data.viewport.height, - pipe_ctx->plane_res.scl_data.viewport.width, - pipe_ctx->plane_res.scl_data.viewport.x, - pipe_ctx->plane_res.scl_data.viewport.y, - plane_state->dst_rect.height, - plane_state->dst_rect.width, - plane_state->dst_rect.x, - plane_state->dst_rect.y); + DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n" + "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n", + __func__, + pipe_ctx->pipe_idx, + pipe_ctx->plane_res.scl_data.viewport.height, + pipe_ctx->plane_res.scl_data.viewport.width, + pipe_ctx->plane_res.scl_data.viewport.x, + pipe_ctx->plane_res.scl_data.viewport.y, + pipe_ctx->plane_res.scl_data.recout.height, + pipe_ctx->plane_res.scl_data.recout.width, + pipe_ctx->plane_res.scl_data.recout.x, + pipe_ctx->plane_res.scl_data.recout.y, + pipe_ctx->plane_res.scl_data.h_active, + pipe_ctx->plane_res.scl_data.v_active, + plane_state->src_rect.height, + plane_state->src_rect.width, + plane_state->src_rect.x, + plane_state->src_rect.y, + plane_state->dst_rect.height, + plane_state->dst_rect.width, + plane_state->dst_rect.x, + plane_state->dst_rect.y, + plane_state->clip_rect.height, + plane_state->clip_rect.width, + plane_state->clip_rect.x, + plane_state->clip_rect.y); if (store_h_border_left) restore_border_left_from_dst(pipe_ctx, store_h_border_left); @@ -2049,8 +2088,16 @@ enum dc_status resource_map_pool_resources( } /* Add ABM to the resource if on EDP */ - if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) + if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) { +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + if (pool->abm) + pipe_ctx->stream_res.abm = pool->abm; + else + pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst]; +#else pipe_ctx->stream_res.abm = pool->abm; +#endif + } for (i = 0; i < context->stream_count; i++) if (context->streams[i] == stream) { @@ -2867,6 +2914,10 @@ unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format) case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + case SURFACE_PIXEL_FORMAT_GRPH_RGBE: + case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: +#endif return 32; case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 470c82794f6f..10d69ada88e3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -244,6 +244,25 @@ struct dc_stream_status *dc_stream_get_status( return dc_stream_get_status_from_state(dc->current_state, stream); } +#ifndef TRIM_FSFT +/** + * dc_optimize_timing() - dc to optimize timing + */ +bool dc_optimize_timing( + struct dc_crtc_timing *timing, + unsigned int max_input_rate_in_khz) +{ + //optimization is expected to assing a value to these: + //timing->pix_clk_100hz + //timing->v_front_porch + //timing->v_total + //timing->fast_transport_output_rate_100hz; + timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz; + + return true; +} +#endif + /** * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address @@ -256,6 +275,9 @@ bool dc_stream_set_cursor_attributes( struct dc *dc; struct resource_context *res_ctx; struct pipe_ctx *pipe_to_program = NULL; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + bool reset_idle_optimizations = false; +#endif if (NULL == stream) { dm_error("DC: dc_stream is NULL!\n"); @@ -275,6 +297,15 @@ bool dc_stream_set_cursor_attributes( res_ctx = &dc->current_state->res_ctx; stream->cursor_attributes = *attributes; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + /* disable idle optimizations while updating cursor */ + if (dc->idle_optimizations_allowed) { + dc->hwss.apply_idle_power_optimizations(dc, false); + reset_idle_optimizations = true; + } + +#endif + for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; @@ -294,6 +325,12 @@ bool dc_stream_set_cursor_attributes( if (pipe_to_program) dc->hwss.cursor_lock(dc, pipe_to_program, false); +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + /* re-enable idle optimizations if necessary */ + if (reset_idle_optimizations) + dc->hwss.apply_idle_power_optimizations(dc, true); + +#endif return true; } @@ -305,6 +342,9 @@ bool dc_stream_set_cursor_position( struct dc *dc; struct resource_context *res_ctx; struct pipe_ctx *pipe_to_program = NULL; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + bool reset_idle_optimizations = false; +#endif if (NULL == stream) { dm_error("DC: dc_stream is NULL!\n"); @@ -318,6 +358,16 @@ bool dc_stream_set_cursor_position( dc = stream->ctx->dc; res_ctx = &dc->current_state->res_ctx; +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + + /* disable idle optimizations if enabling cursor */ + if (dc->idle_optimizations_allowed && + !stream->cursor_position.enable && position->enable) { + dc->hwss.apply_idle_power_optimizations(dc, false); + reset_idle_optimizations = true; + } + +#endif stream->cursor_position = *position; for (i = 0; i < MAX_PIPES; i++) { @@ -341,6 +391,12 @@ bool dc_stream_set_cursor_position( if (pipe_to_program) dc->hwss.cursor_lock(dc, pipe_to_program, false); +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) + /* re-enable idle optimizations if necessary */ + if (reset_idle_optimizations) + dc->hwss.apply_idle_power_optimizations(dc, true); + +#endif return true; } @@ -618,6 +674,17 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc, return true; } +enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, + struct dc_state *state, + struct dc_stream_state *stream) +{ + if (dc->res_pool->funcs->add_dsc_to_stream_resource) { + return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream); + } else { + return DC_NO_DSC_RESOURCE; + } +} + void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream) { DC_LOG_DC( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c index 64cf24a9ab08..f2b39ec35c89 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c @@ -47,9 +47,6 @@ int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_c */ memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config)); dc->vm_pa_config.valid = true; - - if (pa_config->is_hvm_enabled == 0) - dc->debug.nv12_iflip_vm_wa = false; } return num_vmids; |