diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc.h | 79 |
1 files changed, 74 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 3ab52d9a82cf..dd995905b0cb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -44,8 +44,10 @@ /* forward declaration */ struct aux_payload; +struct set_config_cmd_payload; +struct dmub_notification; -#define DC_VER "3.2.149" +#define DC_VER "3.2.156" #define MAX_SURFACES 3 #define MAX_PLANES 6 @@ -183,6 +185,9 @@ struct dc_caps { unsigned int cursor_cache_size; struct dc_plane_cap planes[MAX_PLANES]; struct dc_color_caps color; +#if defined(CONFIG_DRM_AMD_DC_DCN) + bool dp_hpo; +#endif bool vbios_lttpr_aware; bool vbios_lttpr_enable; }; @@ -289,7 +294,15 @@ struct dc_cap_funcs { struct link_training_settings; - +#if defined(CONFIG_DRM_AMD_DC_DCN) +union allow_lttpr_non_transparent_mode { + struct { + bool DP1_4A : 1; + bool DP2_0 : 1; + } bits; + unsigned char raw; +}; +#endif /* Structure to hold configuration flags set by dm at dc creation. */ struct dc_config { bool gpu_vm_support; @@ -302,7 +315,11 @@ struct dc_config { bool edp_no_power_sequencing; bool force_enum_edp; bool forced_clocks; +#if defined(CONFIG_DRM_AMD_DC_DCN) + union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; +#else bool allow_lttpr_non_transparent_mode; +#endif bool multi_mon_pp_mclk_switch; bool disable_dmcu; bool enable_4to1MPC; @@ -456,10 +473,39 @@ union mem_low_power_enable_options { bool cm: 1; bool mpc: 1; bool optc: 1; + bool vpg: 1; + bool afmt: 1; + } bits; + uint32_t u32All; +}; + +union root_clock_optimization_options { + struct { + bool dpp: 1; + bool dsc: 1; + bool hdmistream: 1; + bool hdmichar: 1; + bool dpstream: 1; + bool symclk32_se: 1; + bool symclk32_le: 1; + bool symclk_fe: 1; + bool physymclk: 1; + bool dpiasymclk: 1; + uint32_t reserved: 22; } bits; uint32_t u32All; }; +union dpia_debug_options { + struct { + uint32_t disable_dpia:1; + uint32_t force_non_lttpr:1; + uint32_t extend_aux_rd_interval:1; + uint32_t reserved:29; + } bits; + uint32_t raw; +}; + struct dc_debug_data { uint32_t ltFailCount; uint32_t i2cErrorCount; @@ -548,6 +594,7 @@ struct dc_debug_options { enum wm_report_mode pplib_wm_report_mode; unsigned int min_disp_clk_khz; unsigned int min_dpp_clk_khz; + unsigned int min_dram_clk_khz; int sr_exit_time_dpm0_ns; int sr_enter_plus_exit_time_dpm0_ns; int sr_exit_time_ns; @@ -614,19 +661,24 @@ struct dc_debug_options { bool enable_dmcub_surface_flip; bool usbc_combo_phy_reset_wa; bool enable_dram_clock_change_one_display_vactive; +#if defined(CONFIG_DRM_AMD_DC_DCN) + /* TODO - remove once tested */ + bool legacy_dp2_lt; +#endif union mem_low_power_enable_options enable_mem_low_power; + union root_clock_optimization_options root_clock_optimization; bool force_vblank_alignment; /* Enable dmub aux for legacy ddc */ bool enable_dmub_aux_for_legacy_ddc; bool optimize_edp_link_rate; /* eDP ILR */ - /* force enable edp FEC */ - bool force_enable_edp_fec; /* FEC/PSR1 sequence enable delay in 100us */ uint8_t fec_enable_delay_in100us; + bool enable_driver_sequence_debug; #if defined(CONFIG_DRM_AMD_DC_DCN) bool disable_z10; bool enable_sw_cntl_psr; + union dpia_debug_options dpia_debug; #endif }; @@ -1145,7 +1197,14 @@ struct dpcd_caps { struct dpcd_dsc_capabilities dsc_caps; struct dc_lttpr_caps lttpr_caps; struct psr_caps psr_caps; + struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; +#if defined(CONFIG_DRM_AMD_DC_DCN) + union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; + union dp_main_line_channel_coding_cap channel_coding_cap; + union dp_sink_video_fallback_formats fallback_formats; + union dp_fec_capability1 fec_cap1; +#endif }; union dpcd_sink_ext_caps { @@ -1287,6 +1346,8 @@ void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); enum dc_irq_source dc_get_hpd_irq_source_at_index( struct dc *dc, uint32_t link_index); +void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); + /******************************************************************************* * Power Interfaces ******************************************************************************/ @@ -1337,7 +1398,7 @@ void dc_hardware_release(struct dc *dc); bool dc_set_psr_allow_active(struct dc *dc, bool enable); #if defined(CONFIG_DRM_AMD_DC_DCN) -void dc_z10_restore(struct dc *dc); +void dc_z10_restore(const struct dc *dc); void dc_z10_save_init(struct dc *dc); #endif @@ -1347,6 +1408,14 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc, uint32_t link_index, struct aux_payload *payload); +/* Get dc link index from dpia port index */ +uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, + uint8_t dpia_port_index); + +bool dc_process_dmub_set_config_async(struct dc *dc, + uint32_t link_index, + struct set_config_cmd_payload *payload, + struct dmub_notification *notify); /******************************************************************************* * DSC Interfaces ******************************************************************************/ |