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path: root/drivers/gpu/drm/amd/display/dc/dc_types.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc_types.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc_types.h37
1 files changed, 37 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index f236da1c1859..29fe5389f973 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -177,6 +177,7 @@ enum dc_edid_status {
EDID_NO_RESPONSE,
EDID_BAD_CHECKSUM,
EDID_THE_SAME,
+ EDID_FALL_BACK,
};
enum act_return_status {
@@ -255,6 +256,8 @@ struct dc_edid_caps {
uint8_t qs_bit;
uint8_t qy_bit;
+ uint32_t max_tmds_clk_mhz;
+
/*HDMI 2.0 caps*/
bool lte_340mcsc_scramble;
@@ -475,6 +478,19 @@ enum display_content_type {
DISPLAY_CONTENT_TYPE_GAME = 8
};
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+enum cm_gamut_adjust_type {
+ CM_GAMUT_ADJUST_TYPE_BYPASS = 0,
+ CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
+ CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */
+};
+
+struct cm_grph_csc_adjustment {
+ struct fixed31_32 temperature_matrix[12];
+ enum cm_gamut_adjust_type gamut_adjust_type;
+ enum cm_gamut_coef_format gamut_coef_format;
+};
+#endif
/* writeback */
struct dwb_stereo_params {
bool stereo_enabled; /* false: normal mode, true: 3D stereo */
@@ -492,9 +508,21 @@ struct dc_dwb_cnv_params {
unsigned int crop_x; /* cropped window start x value at cnv output */
unsigned int crop_y; /* cropped window start y value at cnv output */
enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+ enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */
+ enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */
+ unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */
+ unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */
+#endif
};
struct dc_dwb_params {
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+ unsigned int dwbscl_black_color; /* must be in FP1.5.10 */
+ unsigned int hdr_mult; /* must be in FP1.6.12 */
+ struct cm_grph_csc_adjustment csc_params;
+ struct dwb_stereo_params stereo_params;
+#endif
struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */
unsigned int dest_width; /* Destination width */
unsigned int dest_height; /* Destination height */
@@ -862,6 +890,15 @@ struct dsc_dec_dpcd_caps {
uint32_t branch_max_line_width;
};
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+enum dc_gpu_mem_alloc_type {
+ DC_MEM_ALLOC_TYPE_GART,
+ DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+ DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER,
+ DC_MEM_ALLOC_TYPE_AGP
+};
+
+#endif
enum dc_psr_version {
DC_PSR_VERSION_1 = 0,
DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,