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path: root/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
index 8a6b2d328467..34fdb386c884 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
@@ -78,6 +78,8 @@ struct dce_dccg {
/* Cache the status of DFS-bypass feature*/
bool dfs_bypass_enabled;
+ /* True if the DFS-bypass feature is enabled and active. */
+ bool dfs_bypass_active;
/* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
* This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
int dfs_bypass_disp_clk;
@@ -88,6 +90,7 @@ struct dce_dccg {
int dprefclk_ss_percentage;
/* DPREFCLK SS percentage Divider (100 or 1000) */
int dprefclk_ss_divider;
+ int dprefclk_khz;
};