diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 60 |
1 files changed, 58 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c index 1ea91e153d3a..4254e7e1a509 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c @@ -87,6 +87,23 @@ void hubbub1_wm_read_state(struct hubbub *hubbub, s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); } +void hubbub1_disable_allow_self_refresh(struct hubbub *hubbub) +{ + REG_UPDATE(DCHUBBUB_ARB_DRAM_STATE_CNTL, + DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, 0); +} + +bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub) +{ + uint32_t enable = 0; + + REG_GET(DCHUBBUB_ARB_DRAM_STATE_CNTL, + DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, &enable); + + return true ? false : enable; +} + + bool hubbub1_verify_allow_pstate_change_high( struct hubbub *hubbub) { @@ -116,7 +133,43 @@ bool hubbub1_verify_allow_pstate_change_high( forced_pstate_allow = false; } - /* RV1: + /* RV2: + * dchubbubdebugind, at: 0xB + * description + * 0: Pipe0 Plane0 Allow Pstate Change + * 1: Pipe0 Plane1 Allow Pstate Change + * 2: Pipe0 Cursor0 Allow Pstate Change + * 3: Pipe0 Cursor1 Allow Pstate Change + * 4: Pipe1 Plane0 Allow Pstate Change + * 5: Pipe1 Plane1 Allow Pstate Change + * 6: Pipe1 Cursor0 Allow Pstate Change + * 7: Pipe1 Cursor1 Allow Pstate Change + * 8: Pipe2 Plane0 Allow Pstate Change + * 9: Pipe2 Plane1 Allow Pstate Change + * 10: Pipe2 Cursor0 Allow Pstate Change + * 11: Pipe2 Cursor1 Allow Pstate Change + * 12: Pipe3 Plane0 Allow Pstate Change + * 13: Pipe3 Plane1 Allow Pstate Change + * 14: Pipe3 Cursor0 Allow Pstate Change + * 15: Pipe3 Cursor1 Allow Pstate Change + * 16: Pipe4 Plane0 Allow Pstate Change + * 17: Pipe4 Plane1 Allow Pstate Change + * 18: Pipe4 Cursor0 Allow Pstate Change + * 19: Pipe4 Cursor1 Allow Pstate Change + * 20: Pipe5 Plane0 Allow Pstate Change + * 21: Pipe5 Plane1 Allow Pstate Change + * 22: Pipe5 Cursor0 Allow Pstate Change + * 23: Pipe5 Cursor1 Allow Pstate Change + * 24: Pipe6 Plane0 Allow Pstate Change + * 25: Pipe6 Plane1 Allow Pstate Change + * 26: Pipe6 Cursor0 Allow Pstate Change + * 27: Pipe6 Cursor1 Allow Pstate Change + * 28: WB0 Allow Pstate Change + * 29: WB1 Allow Pstate Change + * 30: Arbiter's allow_pstate_change + * 31: SOC pstate change request" + * + * RV1: * dchubbubdebugind, at: 0x7 * description "3-0: Pipe0 cursor0 QOS * 7-4: Pipe1 cursor0 QOS @@ -140,7 +193,6 @@ bool hubbub1_verify_allow_pstate_change_high( * 31: SOC pstate change request */ - REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub->debug_test_index_pstate); for (i = 0; i < pstate_wait_timeout_us; i++) { @@ -802,5 +854,9 @@ void hubbub1_construct(struct hubbub *hubbub, hubbub->masks = hubbub_mask; hubbub->debug_test_index_pstate = 0x7; +#if defined(CONFIG_DRM_AMD_DC_DCN1_01) + if (ctx->dce_version == DCN_VERSION_1_01) + hubbub->debug_test_index_pstate = 0xB; +#endif } |