diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c index 4d7588f2ee79..26648ce772da 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c @@ -54,9 +54,9 @@ static void enc32_dp_set_odm_combine( struct stream_encoder *enc, bool odm_combine) { - //struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - //TODO: REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine); + REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, odm_combine ? 1 : 0); } /* setup stream encoder in dvi mode */ @@ -249,6 +249,7 @@ static void enc32_stream_encoder_dp_unblank( const struct encoder_unblank_param *param) { struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + struct dc *dc = enc->ctx->dc; if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { uint32_t n_vid = 0x8000; @@ -257,7 +258,8 @@ static void enc32_stream_encoder_dp_unblank( uint64_t m_vid_l = n_vid; /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ - if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1) { + if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1 + || dc->debug.enable_dp_dig_pixel_rate_div_policy) { /*this logic should be the same in get_pixel_clock_parameters() */ n_multiply = 1; } @@ -389,6 +391,16 @@ static void enc32_stream_encoder_reset_fifo(struct stream_encoder *enc) } } +static void enc32_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + /* The naming of this field is confusing, what it means is the output mode of otg, which + * is the input mode of the dig + */ + REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container == 2 ? 0x1 : 0x0); +} + static const struct stream_encoder_funcs dcn32_str_enc_funcs = { .dp_set_odm_combine = enc32_dp_set_odm_combine, @@ -434,6 +446,8 @@ static const struct stream_encoder_funcs dcn32_str_enc_funcs = { .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, + + .set_input_mode = enc32_set_dig_input_mode, }; void dcn32_dio_stream_encoder_construct( |