diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dsc')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 24 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h | 4 |
3 files changed, 21 insertions, 13 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 4c844cfaa956..c62d0eddc9c6 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -545,6 +545,7 @@ static bool setup_dsc_config( int target_bandwidth_kbps, const struct dc_crtc_timing *timing, int min_slice_height_override, + int max_dsc_target_bpp_limit_override, struct dc_dsc_config *dsc_cfg) { struct dsc_enc_caps dsc_common_caps; @@ -563,7 +564,7 @@ static bool setup_dsc_config( memset(dsc_cfg, 0, sizeof(struct dc_dsc_config)); - dc_dsc_get_policy_for_timing(timing, &policy); + dc_dsc_get_policy_for_timing(timing, max_dsc_target_bpp_limit_override, &policy); pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right; pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; @@ -863,9 +864,9 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc, const uint8_t *dpcd_dsc_basic_da */ bool dc_dsc_compute_bandwidth_range( const struct display_stream_compressor *dsc, - const uint32_t dsc_min_slice_height_override, - const uint32_t min_bpp, - const uint32_t max_bpp, + uint32_t dsc_min_slice_height_override, + uint32_t min_bpp, + uint32_t max_bpp, const struct dsc_dec_dpcd_caps *dsc_sink_caps, const struct dc_crtc_timing *timing, struct dc_dsc_bw_range *range) @@ -882,7 +883,7 @@ bool dc_dsc_compute_bandwidth_range( if (is_dsc_possible) is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, 0, timing, - dsc_min_slice_height_override, &config); + dsc_min_slice_height_override, max_bpp, &config); if (is_dsc_possible) get_dsc_bandwidth_range(min_bpp, max_bpp, &dsc_common_caps, timing, range); @@ -893,7 +894,8 @@ bool dc_dsc_compute_bandwidth_range( bool dc_dsc_compute_config( const struct display_stream_compressor *dsc, const struct dsc_dec_dpcd_caps *dsc_sink_caps, - const uint32_t dsc_min_slice_height_override, + uint32_t dsc_min_slice_height_override, + uint32_t max_target_bpp_limit_override, uint32_t target_bandwidth_kbps, const struct dc_crtc_timing *timing, struct dc_dsc_config *dsc_cfg) @@ -905,11 +907,12 @@ bool dc_dsc_compute_config( is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, target_bandwidth_kbps, - timing, dsc_min_slice_height_override, dsc_cfg); + timing, dsc_min_slice_height_override, + max_target_bpp_limit_override, dsc_cfg); return is_dsc_possible; } -void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, struct dc_dsc_policy *policy) +void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override, struct dc_dsc_policy *policy) { uint32_t bpc = 0; @@ -963,10 +966,15 @@ void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, struct dc default: return; } + /* internal upper limit, default 16 bpp */ if (policy->max_target_bpp > dsc_policy_max_target_bpp_limit) policy->max_target_bpp = dsc_policy_max_target_bpp_limit; + /* apply override */ + if (max_target_bpp_limit_override && policy->max_target_bpp > max_target_bpp_limit_override) + policy->max_target_bpp = max_target_bpp_limit_override; + /* enable DSC when not needed, default false */ if (dsc_policy_enable_dsc_when_not_needed) policy->enable_dsc_when_not_needed = dsc_policy_enable_dsc_when_not_needed; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c index 4da21966ddce..c6a1cd80aeae 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c @@ -51,7 +51,7 @@ static void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc, const struct qp_entry *table = 0L; // alias enum - enum { min = MM_MIN, max = MM_MAX }; + enum { min = DAL_MM_MIN, max = DAL_MM_MAX }; switch (sel) { TABLE_CASE(444, 8, max); TABLE_CASE(444, 8, min); @@ -233,8 +233,8 @@ static void _do_calc_rc_params(struct rc_params *rc, enum colour_mode cm, rc->flatness_max_qp = ((bpc == BPC_8) ? (12) : ((bpc == BPC_10) ? (16) : (20))) - ((minor_version == 1 && cm == CM_444) ? 1 : 0); rc->flatness_det_thresh = 2 << (bpc - 8); - get_qp_set(rc->qp_min, cm, bpc, MM_MIN, bpp); - get_qp_set(rc->qp_max, cm, bpc, MM_MAX, bpp); + get_qp_set(rc->qp_min, cm, bpc, DAL_MM_MIN, bpp); + get_qp_set(rc->qp_max, cm, bpc, DAL_MM_MAX, bpp); if (cm == CM_444 && minor_version == 1) { for (i = 0; i < QP_SET_SIZE; ++i) { rc->qp_min[i] = rc->qp_min[i] > 0 ? rc->qp_min[i] - 1 : 0; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h index 21723fa6561e..8123827840c5 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h @@ -66,8 +66,8 @@ enum bits_per_comp { }; enum max_min { - MM_MIN = 0, - MM_MAX = 1 + DAL_MM_MIN = 0, + DAL_MM_MAX = 1 }; struct qp_entry { |