diff options
Diffstat (limited to 'drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c')
-rw-r--r-- | drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 45 |
1 files changed, 28 insertions, 17 deletions
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c index ed05a30d1139..f5fe540cd536 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c @@ -1261,9 +1261,21 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx, void *value, int *size) { struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); - uint32_t sclk, mclk; + struct amdgpu_device *adev = hwmgr->adev; + uint32_t sclk, mclk, activity_percent; + bool has_gfx_busy; int ret = 0; + /* GetGfxBusy support was added on RV SMU FW 30.85.00 and PCO 4.30.59 */ + if ((adev->apu_flags & AMD_APU_IS_PICASSO) && + (hwmgr->smu_version >= 0x41e3b)) + has_gfx_busy = true; + else if ((adev->apu_flags & AMD_APU_IS_RAVEN) && + (hwmgr->smu_version >= 0x1e5500)) + has_gfx_busy = true; + else + has_gfx_busy = false; + switch (idx) { case AMDGPU_PP_SENSOR_GFX_SCLK: smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &sclk); @@ -1284,8 +1296,21 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx, *(uint32_t *)value = smu10_data->vcn_power_gated ? 0 : 1; *size = 4; break; + case AMDGPU_PP_SENSOR_GPU_LOAD: + if (!has_gfx_busy) + ret = -EOPNOTSUPP; + else { + ret = smum_send_msg_to_smc(hwmgr, + PPSMC_MSG_GetGfxBusy, + &activity_percent); + if (!ret) + *((uint32_t *)value) = min(activity_percent, (u32)100); + else + ret = -EIO; + } + break; default: - ret = -EINVAL; + ret = -EOPNOTSUPP; break; } @@ -1487,7 +1512,7 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr, } if (!smu10_data->fine_grain_enabled) { - pr_err("pp_od_clk_voltage is not accessible if power_dpm_force_perfomance_level is not in manual mode!\n"); + pr_err("pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n"); return -EINVAL; } @@ -1526,20 +1551,6 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr, smu10_data->gfx_actual_soft_min_freq = min_freq; smu10_data->gfx_actual_soft_max_freq = max_freq; - - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetHardMinGfxClk, - min_freq, - NULL); - if (ret) - return ret; - - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_SetSoftMaxGfxClk, - max_freq, - NULL); - if (ret) - return ret; } else if (type == PP_OD_COMMIT_DPM_TABLE) { if (size != 0) { pr_err("Input parameter number not correct\n"); |