diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index bfb39bce3b04..d3de4df2b682 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -196,16 +196,19 @@ #define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val) #define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx)) #define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx)) +#define C20_PHY_TX_RATE REG_GENMASK(2, 0) #define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx)) #define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx)) #define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx)) #define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx)) #define C20_MPLLA_FRACEN REG_BIT(14) +#define C20_FB_CLK_DIV4_EN REG_BIT(13) #define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8) #define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx)) #define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx)) #define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13) #define C20_MPLLB_FRACEN REG_BIT(13) +#define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10) #define C20_MULTIPLIER_MASK REG_GENMASK(11, 0) #define C20_PHY_USE_MPLLB REG_BIT(7) |