diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dpll.c')
-rw-r--r-- | drivers/gpu/drm/i915/display/intel_dpll.c | 328 |
1 files changed, 192 insertions, 136 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 3038655377ea..49274d632716 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -369,38 +369,68 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock) return clock->dot; } -static int i9xx_pll_refclk(struct drm_device *dev, - const struct intel_crtc_state *pipe_config) +static int i9xx_pll_refclk(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(dev); - u32 dpll = pipe_config->dpll_hw_state.dpll; + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; - if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) - return dev_priv->display.vbt.lvds_ssc_freq; - else if (HAS_PCH_SPLIT(dev_priv)) + if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) + return i915->display.vbt.lvds_ssc_freq; + else if (HAS_PCH_SPLIT(i915)) return 120000; - else if (DISPLAY_VER(dev_priv) != 2) + else if (DISPLAY_VER(i915) != 2) return 96000; else return 48000; } +void i9xx_dpll_get_hw_state(struct intel_crtc *crtc, + struct intel_dpll_hw_state *dpll_hw_state) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; + + if (DISPLAY_VER(dev_priv) >= 4) { + u32 tmp; + + /* No way to read it out on pipes B and C */ + if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) + tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; + else + tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); + + hw_state->dpll_md = tmp; + } + + hw_state->dpll = intel_de_read(dev_priv, DPLL(crtc->pipe)); + + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { + hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe)); + hw_state->fp1 = intel_de_read(dev_priv, FP1(crtc->pipe)); + } else { + /* Mask out read-only status bits. */ + hw_state->dpll &= ~(DPLL_LOCK_VLV | + DPLL_PORTC_READY_MASK | + DPLL_PORTB_READY_MASK); + } +} + /* Returns the clock of the currently programmed mode of the given pipe. */ -void i9xx_crtc_clock_get(struct intel_crtc *crtc, - struct intel_crtc_state *pipe_config) +void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); - u32 dpll = pipe_config->dpll_hw_state.dpll; + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; + u32 dpll = hw_state->dpll; u32 fp; struct dpll clock; int port_clock; - int refclk = i9xx_pll_refclk(dev, pipe_config); + int refclk = i9xx_pll_refclk(crtc_state); if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) - fp = pipe_config->dpll_hw_state.fp0; + fp = hw_state->fp0; else - fp = pipe_config->dpll_hw_state.fp1; + fp = hw_state->fp1; clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; if (IS_PINEVIEW(dev_priv)) { @@ -475,21 +505,21 @@ void i9xx_crtc_clock_get(struct intel_crtc *crtc, * port_clock to compute adjusted_mode.crtc_clock in the * encoder's get_config() function. */ - pipe_config->port_clock = port_clock; + crtc_state->port_clock = port_clock; } -void vlv_crtc_clock_get(struct intel_crtc *crtc, - struct intel_crtc_state *pipe_config) +void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; struct dpll clock; u32 mdiv; int refclk = 100000; /* In case of DSI, DPLL will not be used */ - if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) + if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) return; vlv_dpio_get(dev_priv); @@ -502,22 +532,22 @@ void vlv_crtc_clock_get(struct intel_crtc *crtc, clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; - pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); + crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock); } -void chv_crtc_clock_get(struct intel_crtc *crtc, - struct intel_crtc_state *pipe_config) +void chv_crtc_clock_get(struct intel_crtc_state *crtc_state) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum dpio_channel port = vlv_pipe_to_channel(crtc->pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; struct dpll clock; u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; int refclk = 100000; /* In case of DSI, DPLL will not be used */ - if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) + if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) return; vlv_dpio_get(dev_priv); @@ -536,7 +566,7 @@ void chv_crtc_clock_get(struct intel_crtc *crtc, clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; - pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); + crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock); } /* @@ -958,37 +988,20 @@ static u32 pnv_dpll_compute_fp(const struct dpll *dpll) return (1 << dpll->n) << 16 | dpll->m2; } -static void i9xx_update_pll_dividers(struct intel_crtc_state *crtc_state, - const struct dpll *clock, - const struct dpll *reduced_clock) +static u32 i965_dpll_md(const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - u32 fp, fp2; - - if (IS_PINEVIEW(dev_priv)) { - fp = pnv_dpll_compute_fp(clock); - fp2 = pnv_dpll_compute_fp(reduced_clock); - } else { - fp = i9xx_dpll_compute_fp(clock); - fp2 = i9xx_dpll_compute_fp(reduced_clock); - } - - crtc_state->dpll_hw_state.fp0 = fp; - crtc_state->dpll_hw_state.fp1 = fp2; + return (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; } -static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, - const struct dpll *clock, - const struct dpll *reduced_clock) +static u32 i9xx_dpll(const struct intel_crtc_state *crtc_state, + const struct dpll *clock, + const struct dpll *reduced_clock) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dpll; - i9xx_update_pll_dividers(crtc_state, clock, reduced_clock); - - dpll = DPLL_VGA_MODE_DIS; + dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) dpll |= DPLLB_MODE_LVDS; @@ -1047,27 +1060,40 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, else dpll |= PLL_REF_INPUT_DREFCLK; - dpll |= DPLL_VCO_ENABLE; - crtc_state->dpll_hw_state.dpll = dpll; - - if (DISPLAY_VER(dev_priv) >= 4) { - u32 dpll_md = (crtc_state->pixel_multiplier - 1) - << DPLL_MD_UDI_MULTIPLIER_SHIFT; - crtc_state->dpll_hw_state.dpll_md = dpll_md; - } + return dpll; } -static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state, +static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, const struct dpll *clock, const struct dpll *reduced_clock) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - u32 dpll; + struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; - i9xx_update_pll_dividers(crtc_state, clock, reduced_clock); + if (IS_PINEVIEW(dev_priv)) { + hw_state->fp0 = pnv_dpll_compute_fp(clock); + hw_state->fp1 = pnv_dpll_compute_fp(reduced_clock); + } else { + hw_state->fp0 = i9xx_dpll_compute_fp(clock); + hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock); + } + + hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock); - dpll = DPLL_VGA_MODE_DIS; + if (DISPLAY_VER(dev_priv) >= 4) + hw_state->dpll_md = i965_dpll_md(crtc_state); +} + +static u32 i8xx_dpll(const struct intel_crtc_state *crtc_state, + const struct dpll *clock, + const struct dpll *reduced_clock) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + u32 dpll; + + dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; @@ -1104,8 +1130,19 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state, else dpll |= PLL_REF_INPUT_DREFCLK; - dpll |= DPLL_VCO_ENABLE; - crtc_state->dpll_hw_state.dpll = dpll; + return dpll; +} + +static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state, + const struct dpll *clock, + const struct dpll *reduced_clock) +{ + struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; + + hw_state->fp0 = i9xx_dpll_compute_fp(clock); + hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock); + + hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock); } static int hsw_crtc_compute_clock(struct intel_atomic_state *state, @@ -1185,62 +1222,54 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state, return ret; /* TODO: Do the readback via intel_compute_shared_dplls() */ - crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->cx0pll_state); + crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); return 0; } +static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && + ((intel_panel_use_ssc(i915) && i915->display.vbt.lvds_ssc_freq == 100000) || + (HAS_PCH_IBX(i915) && intel_is_dual_link_lvds(i915)))) + return 25; + + if (crtc_state->sdvo_tv_clock) + return 20; + + return 21; +} + static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) { return dpll->m < factor * dpll->n; } -static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state, - const struct dpll *clock, - const struct dpll *reduced_clock) +static u32 ilk_dpll_compute_fp(const struct dpll *clock, int factor) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - u32 fp, fp2; - int factor; - - /* Enable autotuning of the PLL clock (if permissible) */ - factor = 21; - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { - if ((intel_panel_use_ssc(dev_priv) && - dev_priv->display.vbt.lvds_ssc_freq == 100000) || - (HAS_PCH_IBX(dev_priv) && - intel_is_dual_link_lvds(dev_priv))) - factor = 25; - } else if (crtc_state->sdvo_tv_clock) { - factor = 20; - } + u32 fp; fp = i9xx_dpll_compute_fp(clock); if (ilk_needs_fb_cb_tune(clock, factor)) fp |= FP_CB_TUNE; - fp2 = i9xx_dpll_compute_fp(reduced_clock); - if (ilk_needs_fb_cb_tune(reduced_clock, factor)) - fp2 |= FP_CB_TUNE; - - crtc_state->dpll_hw_state.fp0 = fp; - crtc_state->dpll_hw_state.fp1 = fp2; + return fp; } -static void ilk_compute_dpll(struct intel_crtc_state *crtc_state, - const struct dpll *clock, - const struct dpll *reduced_clock) +static u32 ilk_dpll(const struct intel_crtc_state *crtc_state, + const struct dpll *clock, + const struct dpll *reduced_clock) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dpll; - ilk_update_pll_dividers(crtc_state, clock, reduced_clock); - - dpll = 0; + dpll = DPLL_VCO_ENABLE; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) dpll |= DPLLB_MODE_LVDS; @@ -1302,9 +1331,20 @@ static void ilk_compute_dpll(struct intel_crtc_state *crtc_state, else dpll |= PLL_REF_INPUT_DREFCLK; - dpll |= DPLL_VCO_ENABLE; + return dpll; +} - crtc_state->dpll_hw_state.dpll = dpll; +static void ilk_compute_dpll(struct intel_crtc_state *crtc_state, + const struct dpll *clock, + const struct dpll *reduced_clock) +{ + struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; + int factor = ilk_fb_cb_factor(crtc_state); + + hw_state->fp0 = ilk_dpll_compute_fp(clock, factor); + hw_state->fp1 = ilk_dpll_compute_fp(reduced_clock, factor); + + hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock); } static int ilk_crtc_compute_clock(struct intel_atomic_state *state, @@ -1377,39 +1417,56 @@ static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state, return intel_reserve_shared_dplls(state, crtc, NULL); } -void vlv_compute_dpll(struct intel_crtc_state *crtc_state) +static u32 vlv_dpll(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + u32 dpll; - crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | + dpll = DPLL_INTEGRATED_REF_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; + if (crtc->pipe != PIPE_A) - crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; + dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; /* DPLL not used with DSI, but still need the rest set up */ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) - crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | - DPLL_EXT_BUFFER_ENABLE_VLV; + dpll |= DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV; - crtc_state->dpll_hw_state.dpll_md = - (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; + return dpll; } -void chv_compute_dpll(struct intel_crtc_state *crtc_state) +void vlv_compute_dpll(struct intel_crtc_state *crtc_state) +{ + struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; + + hw_state->dpll = vlv_dpll(crtc_state); + hw_state->dpll_md = i965_dpll_md(crtc_state); +} + +static u32 chv_dpll(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + u32 dpll; - crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | + dpll = DPLL_SSC_REF_CLK_CHV | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; + if (crtc->pipe != PIPE_A) - crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; + dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; /* DPLL not used with DSI, but still need the rest set up */ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) - crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; + dpll |= DPLL_VCO_ENABLE; + + return dpll; +} + +void chv_compute_dpll(struct intel_crtc_state *crtc_state) +{ + struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; - crtc_state->dpll_hw_state.dpll_md = - (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; + hw_state->dpll = chv_dpll(crtc_state); + hw_state->dpll_md = i965_dpll_md(crtc_state); } static int chv_crtc_compute_clock(struct intel_atomic_state *state, @@ -1765,7 +1822,7 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - u32 dpll = crtc_state->dpll_hw_state.dpll; + const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; int i; @@ -1775,36 +1832,35 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) if (i9xx_has_pps(dev_priv)) assert_pps_unlocked(dev_priv, pipe); - intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0); - intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1); + intel_de_write(dev_priv, FP0(pipe), hw_state->fp0); + intel_de_write(dev_priv, FP1(pipe), hw_state->fp1); /* * Apparently we need to have VGA mode enabled prior to changing * the P1/P2 dividers. Otherwise the DPLL will keep using the old * dividers, even though the register value does change. */ - intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); - intel_de_write(dev_priv, DPLL(pipe), dpll); + intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll & ~DPLL_VGA_MODE_DIS); + intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); /* Wait for the clocks to stabilize. */ intel_de_posting_read(dev_priv, DPLL(pipe)); udelay(150); if (DISPLAY_VER(dev_priv) >= 4) { - intel_de_write(dev_priv, DPLL_MD(pipe), - crtc_state->dpll_hw_state.dpll_md); + intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md); } else { /* The pixel multiplier can only be updated once the * DPLL is enabled and the clocks are stable. * * So write it again. */ - intel_de_write(dev_priv, DPLL(pipe), dpll); + intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); } /* We do this three times for luck */ for (i = 0; i < 3; i++) { - intel_de_write(dev_priv, DPLL(pipe), dpll); + intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); intel_de_posting_read(dev_priv, DPLL(pipe)); udelay(150); /* wait for warmup */ } @@ -1934,9 +1990,10 @@ static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; - intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); + intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); intel_de_posting_read(dev_priv, DPLL(pipe)); udelay(150); @@ -1948,6 +2005,7 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); @@ -1957,16 +2015,14 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state) /* Enable Refclk */ intel_de_write(dev_priv, DPLL(pipe), - crtc_state->dpll_hw_state.dpll & - ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); + hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); - if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { + if (hw_state->dpll & DPLL_VCO_ENABLE) { vlv_prepare_pll(crtc_state); _vlv_enable_pll(crtc_state); } - intel_de_write(dev_priv, DPLL_MD(pipe), - crtc_state->dpll_hw_state.dpll_md); + intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md); intel_de_posting_read(dev_priv, DPLL_MD(pipe)); } @@ -2069,6 +2125,7 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; enum dpio_channel port = vlv_pipe_to_channel(pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); @@ -2089,7 +2146,7 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) udelay(1); /* Enable PLL */ - intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); + intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); /* Check PLL is locked */ if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) @@ -2100,6 +2157,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); @@ -2109,9 +2167,9 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) /* Enable Refclk and SSC */ intel_de_write(dev_priv, DPLL(pipe), - crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); + hw_state->dpll & ~DPLL_VCO_ENABLE); - if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { + if (hw_state->dpll & DPLL_VCO_ENABLE) { chv_prepare_pll(crtc_state); _chv_enable_pll(crtc_state); } @@ -2124,10 +2182,9 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) * the value from DPLLBMD to either pipe B or C. */ intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); - intel_de_write(dev_priv, DPLL_MD(PIPE_B), - crtc_state->dpll_hw_state.dpll_md); + intel_de_write(dev_priv, DPLL_MD(PIPE_B), hw_state->dpll_md); intel_de_write(dev_priv, CBR4_VLV, 0); - dev_priv->display.state.chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md; + dev_priv->display.state.chv_dpll_md[pipe] = hw_state->dpll_md; /* * DPLLB VGA mode also seems to cause problems. @@ -2137,8 +2194,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); } else { - intel_de_write(dev_priv, DPLL_MD(pipe), - crtc_state->dpll_hw_state.dpll_md); + intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md); intel_de_posting_read(dev_priv, DPLL_MD(pipe)); } } |