diff options
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 98 |
1 files changed, 43 insertions, 55 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 71584cd56fd7..b860784ade72 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. */ @@ -48,6 +48,8 @@ enum { * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results * in a failure + * @DPU_MDP_VSYNC_SEL Enables vsync source selection via MDP_VSYNC_SEL register + * (moved into INTF block since DPU 5.0.0) * @DPU_MDP_MAX Maximum value */ @@ -59,12 +61,12 @@ enum { DPU_MDP_UBWC_1_5, DPU_MDP_AUDIO_SELECT, DPU_MDP_PERIPH_0_REMOVED, + DPU_MDP_VSYNC_SEL, DPU_MDP_MAX }; /** * SSPP sub-blocks/features - * @DPU_SSPP_SRC Src and fetch part of the pipes, * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support * @DPU_SSPP_SCALER_QSEED3LITE, QSEED3 Lite alogorithm support @@ -85,8 +87,7 @@ enum { * @DPU_SSPP_MAX maximum value */ enum { - DPU_SSPP_SRC = 0x1, - DPU_SSPP_SCALER_QSEED2, + DPU_SSPP_SCALER_QSEED2 = 0x1, DPU_SSPP_SCALER_QSEED3, DPU_SSPP_SCALER_QSEED3LITE, DPU_SSPP_SCALER_QSEED4, @@ -127,13 +128,9 @@ enum { /** * DSPP sub-blocks * @DPU_DSPP_PCC Panel color correction block - * @DPU_DSPP_GC Gamma correction block - * @DPU_DSPP_IGC Inverse gamma correction block */ enum { DPU_DSPP_PCC = 0x1, - DPU_DSPP_GC, - DPU_DSPP_IGC, DPU_DSPP_MAX }; @@ -143,7 +140,8 @@ enum { * @DPU_PINGPONG_TE2 Additional tear check block for split pipes * @DPU_PINGPONG_SPLIT PP block supports split fifo * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo - * @DPU_PINGPONG_DITHER, Dither blocks + * @DPU_PINGPONG_DITHER Dither blocks + * @DPU_PINGPONG_DSC PP block supports DSC * @DPU_PINGPONG_MAX */ enum { @@ -152,6 +150,7 @@ enum { DPU_PINGPONG_SPLIT, DPU_PINGPONG_SLAVE, DPU_PINGPONG_DITHER, + DPU_PINGPONG_DSC, DPU_PINGPONG_MAX }; @@ -182,6 +181,7 @@ enum { * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate * than video timing * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register + * @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register * @DPU_INTF_MAX */ enum { @@ -189,6 +189,7 @@ enum { DPU_INTF_TE, DPU_DATA_HCTL_EN, DPU_INTF_STATUS_SUPPORTED, + DPU_INTF_DATA_COMPRESS, DPU_INTF_MAX }; @@ -241,12 +242,18 @@ enum { }; /** - * DSC features + * DSC sub-blocks/features * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets * the pixel output from this DSC. + * @DPU_DSC_HW_REV_1_2 DSC block supports DSC 1.1 and 1.2 + * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN encoding + * @DPU_DSC_MAX */ enum { DPU_DSC_OUTPUT_CTRL = 0x1, + DPU_DSC_HW_REV_1_2, + DPU_DSC_NATIVE_42x_EN, + DPU_DSC_MAX }; /** @@ -279,14 +286,6 @@ enum { u32 len /** - * struct dpu_src_blk: SSPP part of the source pipes - * @info: HW register and features supported by this sub-blk - */ -struct dpu_src_blk { - DPU_HW_SUBBLK_INFO; -}; - -/** * struct dpu_scaler_blk: Scaler information * @info: HW register and features supported by this sub-blk * @version: qseed block revision @@ -311,6 +310,14 @@ struct dpu_pp_blk { }; /** + * struct dpu_dsc_blk - DSC Encoder sub-blk information + * @info: HW register and features supported by this sub-blk + */ +struct dpu_dsc_blk { + DPU_HW_SUBBLK_INFO; +}; + +/** * enum dpu_qos_lut_usage - define QoS LUT use cases */ enum dpu_qos_lut_usage { @@ -385,20 +392,13 @@ struct dpu_caps { /** * struct dpu_sspp_sub_blks : SSPP sub-blocks * common: Pointer to common configurations shared by sub blocks - * @creq_vblank: creq priority during vertical blanking - * @danger_vblank: danger priority during vertical blanking * @maxdwnscale: max downscale ratio supported(without DECIMATION) * @maxupscale: maxupscale ratio supported * @smart_dma_priority: hw priority of rect1 of multirect pipe * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps * @qseed_ver: qseed version - * @src_blk: * @scaler_blk: * @csc_blk: - * @hsic: - * @memcolor: - * @pcc_blk: - * @igc_blk: * @format_list: Pointer to list of supported formats * @num_formats: Number of supported formats * @virt_format_list: Pointer to list of supported formats for virtual planes @@ -406,20 +406,13 @@ struct dpu_caps { * @dpu_rotation_cfg: inline rotation configuration */ struct dpu_sspp_sub_blks { - u32 creq_vblank; - u32 danger_vblank; u32 maxdwnscale; u32 maxupscale; u32 smart_dma_priority; u32 max_per_pipe_bw; u32 qseed_ver; - struct dpu_src_blk src_blk; struct dpu_scaler_blk scaler_blk; struct dpu_pp_blk csc_blk; - struct dpu_pp_blk hsic_blk; - struct dpu_pp_blk memcolor_blk; - struct dpu_pp_blk pcc_blk; - struct dpu_pp_blk igc_blk; const u32 *format_list; u32 num_formats; @@ -433,22 +426,18 @@ struct dpu_sspp_sub_blks { * @maxwidth: Max pixel width supported by this mixer * @maxblendstages: Max number of blend-stages supported * @blendstage_base: Blend-stage register base offset - * @gc: gamma correction block */ struct dpu_lm_sub_blks { u32 maxwidth; u32 maxblendstages; u32 blendstage_base[MAX_BLOCKS]; - struct dpu_pp_blk gc; }; /** * struct dpu_dspp_sub_blks: Information of DSPP block - * @gc : gamma correction block * @pcc: pixel color correction block */ struct dpu_dspp_sub_blks { - struct dpu_pp_blk gc; struct dpu_pp_blk pcc; }; @@ -459,6 +448,16 @@ struct dpu_pingpong_sub_blks { }; /** + * struct dpu_dsc_sub_blks - DSC sub-blks + * @enc: DSC encoder sub-block + * @ctl: DSC controller sub-block + */ +struct dpu_dsc_sub_blks { + struct dpu_dsc_blk enc; + struct dpu_dsc_blk ctl; +}; + +/** * dpu_clk_ctrl_type - Defines top level clock control signals */ enum dpu_clk_ctrl_type { @@ -554,7 +553,7 @@ struct dpu_sspp_cfg { * @base register offset of this block * @features bit mask identifying sub-blocks/features * @sblk: LM Sub-blocks information - * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported + * @pingpong: ID of connected PingPong, PINGPONG_NONE if unsupported * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL */ struct dpu_lm_cfg { @@ -612,10 +611,13 @@ struct dpu_merge_3d_cfg { * struct dpu_dsc_cfg - information of DSC blocks * @id enum identifying this block * @base register offset of this block + * @len: length of hardware block * @features bit mask identifying sub-blocks/features + * @sblk: sub-blocks information */ struct dpu_dsc_cfg { DPU_HW_BLK_INFO; + const struct dpu_dsc_sub_blks *sblk; }; /** @@ -628,6 +630,7 @@ struct dpu_dsc_cfg { * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch * @intr_underrun: index for INTF underrun interrupt * @intr_vsync: index for INTF VSYNC interrupt + * @intr_tear_rd_ptr: Index for INTF TEAR_RD_PTR interrupt */ struct dpu_intf_cfg { DPU_HW_BLK_INFO; @@ -636,6 +639,7 @@ struct dpu_intf_cfg { u32 prog_fetch_lines_worst_case; s32 intr_underrun; s32 intr_vsync; + s32 intr_tear_rd_ptr; }; /** @@ -720,21 +724,6 @@ struct dpu_vbif_cfg { u32 memtype_count; u32 memtype[MAX_XIN_COUNT]; }; -/** - * struct dpu_reg_dma_cfg - information of lut dma blocks - * @id enum identifying this block - * @base register offset of this block - * @features bit mask identifying sub-blocks/features - * @version version of lutdma hw block - * @trigger_sel_off offset to trigger select registers of lutdma - */ -struct dpu_reg_dma_cfg { - DPU_HW_BLK_INFO; - u32 version; - u32 trigger_sel_off; - u32 xin_id; - enum dpu_clk_ctrl_type clk_ctrl; -}; /** * Define CDP use cases @@ -850,9 +839,6 @@ struct dpu_mdss_cfg { u32 wb_count; const struct dpu_wb_cfg *wb; - u32 reg_dma_count; - const struct dpu_reg_dma_cfg *dma_cfg; - u32 ad_count; u32 dspp_count; @@ -875,7 +861,9 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; extern const struct dpu_mdss_cfg dpu_sm8250_cfg; extern const struct dpu_mdss_cfg dpu_sc7180_cfg; extern const struct dpu_mdss_cfg dpu_sm6115_cfg; +extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; +extern const struct dpu_mdss_cfg dpu_sm6375_cfg; extern const struct dpu_mdss_cfg dpu_sm8350_cfg; extern const struct dpu_mdss_cfg dpu_sc7280_cfg; extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; |